pci-dra7xx.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
  4. *
  5. * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Kishon Vijay Abraham I <kishon@ti.com>
  8. */
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_pci.h>
  20. #include <linux/pci.h>
  21. #include <linux/phy/phy.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/resource.h>
  25. #include <linux/types.h>
  26. #include <linux/mfd/syscon.h>
  27. #include <linux/regmap.h>
  28. #include "pcie-designware.h"
  29. /* PCIe controller wrapper DRA7XX configuration registers */
  30. #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
  31. #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
  32. #define ERR_SYS BIT(0)
  33. #define ERR_FATAL BIT(1)
  34. #define ERR_NONFATAL BIT(2)
  35. #define ERR_COR BIT(3)
  36. #define ERR_AXI BIT(4)
  37. #define ERR_ECRC BIT(5)
  38. #define PME_TURN_OFF BIT(8)
  39. #define PME_TO_ACK BIT(9)
  40. #define PM_PME BIT(10)
  41. #define LINK_REQ_RST BIT(11)
  42. #define LINK_UP_EVT BIT(12)
  43. #define CFG_BME_EVT BIT(13)
  44. #define CFG_MSE_EVT BIT(14)
  45. #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
  46. ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
  47. LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
  48. #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
  49. #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
  50. #define INTA BIT(0)
  51. #define INTB BIT(1)
  52. #define INTC BIT(2)
  53. #define INTD BIT(3)
  54. #define MSI BIT(4)
  55. #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
  56. #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
  57. #define DEVICE_TYPE_EP 0x0
  58. #define DEVICE_TYPE_LEG_EP 0x1
  59. #define DEVICE_TYPE_RC 0x4
  60. #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
  61. #define LTSSM_EN 0x1
  62. #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
  63. #define LINK_UP BIT(16)
  64. #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
  65. #define EXP_CAP_ID_OFFSET 0x70
  66. #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
  67. #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
  68. #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
  69. #define MSI_REQ_GRANT BIT(0)
  70. #define MSI_VECTOR_SHIFT 7
  71. struct dra7xx_pcie {
  72. struct dw_pcie *pci;
  73. void __iomem *base; /* DT ti_conf */
  74. int phy_count; /* DT phy-names count */
  75. struct phy **phy;
  76. int link_gen;
  77. struct irq_domain *irq_domain;
  78. enum dw_pcie_device_mode mode;
  79. };
  80. struct dra7xx_pcie_of_data {
  81. enum dw_pcie_device_mode mode;
  82. };
  83. #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
  84. static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
  85. {
  86. return readl(pcie->base + offset);
  87. }
  88. static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
  89. u32 value)
  90. {
  91. writel(value, pcie->base + offset);
  92. }
  93. static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
  94. {
  95. return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
  96. }
  97. static int dra7xx_pcie_link_up(struct dw_pcie *pci)
  98. {
  99. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  100. u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
  101. return !!(reg & LINK_UP);
  102. }
  103. static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
  104. {
  105. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  106. u32 reg;
  107. reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
  108. reg &= ~LTSSM_EN;
  109. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
  110. }
  111. static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
  112. {
  113. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  114. struct device *dev = pci->dev;
  115. u32 reg;
  116. u32 exp_cap_off = EXP_CAP_ID_OFFSET;
  117. if (dw_pcie_link_up(pci)) {
  118. dev_err(dev, "link is already up\n");
  119. return 0;
  120. }
  121. if (dra7xx->link_gen == 1) {
  122. dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
  123. 4, &reg);
  124. if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
  125. reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
  126. reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
  127. dw_pcie_write(pci->dbi_base + exp_cap_off +
  128. PCI_EXP_LNKCAP, 4, reg);
  129. }
  130. dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
  131. 2, &reg);
  132. if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
  133. reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
  134. reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
  135. dw_pcie_write(pci->dbi_base + exp_cap_off +
  136. PCI_EXP_LNKCTL2, 2, reg);
  137. }
  138. }
  139. reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
  140. reg |= LTSSM_EN;
  141. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
  142. return 0;
  143. }
  144. static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
  145. {
  146. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
  147. LEG_EP_INTERRUPTS | MSI);
  148. dra7xx_pcie_writel(dra7xx,
  149. PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
  150. MSI | LEG_EP_INTERRUPTS);
  151. }
  152. static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
  153. {
  154. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
  155. INTERRUPTS);
  156. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
  157. INTERRUPTS);
  158. }
  159. static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
  160. {
  161. dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
  162. dra7xx_pcie_enable_msi_interrupts(dra7xx);
  163. }
  164. static int dra7xx_pcie_host_init(struct pcie_port *pp)
  165. {
  166. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  167. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  168. dw_pcie_setup_rc(pp);
  169. dra7xx_pcie_establish_link(pci);
  170. dw_pcie_wait_for_link(pci);
  171. dw_pcie_msi_init(pp);
  172. dra7xx_pcie_enable_interrupts(dra7xx);
  173. return 0;
  174. }
  175. static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
  176. .host_init = dra7xx_pcie_host_init,
  177. };
  178. static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
  179. irq_hw_number_t hwirq)
  180. {
  181. irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
  182. irq_set_chip_data(irq, domain->host_data);
  183. return 0;
  184. }
  185. static const struct irq_domain_ops intx_domain_ops = {
  186. .map = dra7xx_pcie_intx_map,
  187. .xlate = pci_irqd_intx_xlate,
  188. };
  189. static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
  190. {
  191. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  192. struct device *dev = pci->dev;
  193. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  194. struct device_node *node = dev->of_node;
  195. struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
  196. if (!pcie_intc_node) {
  197. dev_err(dev, "No PCIe Intc node found\n");
  198. return -ENODEV;
  199. }
  200. dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
  201. &intx_domain_ops, pp);
  202. if (!dra7xx->irq_domain) {
  203. dev_err(dev, "Failed to get a INTx IRQ domain\n");
  204. return -ENODEV;
  205. }
  206. return 0;
  207. }
  208. static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
  209. {
  210. struct dra7xx_pcie *dra7xx = arg;
  211. struct dw_pcie *pci = dra7xx->pci;
  212. struct pcie_port *pp = &pci->pp;
  213. unsigned long reg;
  214. u32 virq, bit;
  215. reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
  216. switch (reg) {
  217. case MSI:
  218. dw_handle_msi_irq(pp);
  219. break;
  220. case INTA:
  221. case INTB:
  222. case INTC:
  223. case INTD:
  224. for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
  225. virq = irq_find_mapping(dra7xx->irq_domain, bit);
  226. if (virq)
  227. generic_handle_irq(virq);
  228. }
  229. break;
  230. }
  231. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
  232. return IRQ_HANDLED;
  233. }
  234. static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
  235. {
  236. struct dra7xx_pcie *dra7xx = arg;
  237. struct dw_pcie *pci = dra7xx->pci;
  238. struct device *dev = pci->dev;
  239. struct dw_pcie_ep *ep = &pci->ep;
  240. u32 reg;
  241. reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
  242. if (reg & ERR_SYS)
  243. dev_dbg(dev, "System Error\n");
  244. if (reg & ERR_FATAL)
  245. dev_dbg(dev, "Fatal Error\n");
  246. if (reg & ERR_NONFATAL)
  247. dev_dbg(dev, "Non Fatal Error\n");
  248. if (reg & ERR_COR)
  249. dev_dbg(dev, "Correctable Error\n");
  250. if (reg & ERR_AXI)
  251. dev_dbg(dev, "AXI tag lookup fatal Error\n");
  252. if (reg & ERR_ECRC)
  253. dev_dbg(dev, "ECRC Error\n");
  254. if (reg & PME_TURN_OFF)
  255. dev_dbg(dev,
  256. "Power Management Event Turn-Off message received\n");
  257. if (reg & PME_TO_ACK)
  258. dev_dbg(dev,
  259. "Power Management Turn-Off Ack message received\n");
  260. if (reg & PM_PME)
  261. dev_dbg(dev, "PM Power Management Event message received\n");
  262. if (reg & LINK_REQ_RST)
  263. dev_dbg(dev, "Link Request Reset\n");
  264. if (reg & LINK_UP_EVT) {
  265. if (dra7xx->mode == DW_PCIE_EP_TYPE)
  266. dw_pcie_ep_linkup(ep);
  267. dev_dbg(dev, "Link-up state change\n");
  268. }
  269. if (reg & CFG_BME_EVT)
  270. dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
  271. if (reg & CFG_MSE_EVT)
  272. dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
  273. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
  274. return IRQ_HANDLED;
  275. }
  276. static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
  277. {
  278. struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  279. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  280. enum pci_barno bar;
  281. for (bar = BAR_0; bar <= BAR_5; bar++)
  282. dw_pcie_ep_reset_bar(pci, bar);
  283. dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
  284. }
  285. static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
  286. {
  287. dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
  288. mdelay(1);
  289. dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
  290. }
  291. static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
  292. u8 interrupt_num)
  293. {
  294. u32 reg;
  295. reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
  296. reg |= MSI_REQ_GRANT;
  297. dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
  298. }
  299. static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
  300. enum pci_epc_irq_type type, u8 interrupt_num)
  301. {
  302. struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  303. struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  304. switch (type) {
  305. case PCI_EPC_IRQ_LEGACY:
  306. dra7xx_pcie_raise_legacy_irq(dra7xx);
  307. break;
  308. case PCI_EPC_IRQ_MSI:
  309. dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
  310. break;
  311. default:
  312. dev_err(pci->dev, "UNKNOWN IRQ type\n");
  313. }
  314. return 0;
  315. }
  316. static struct dw_pcie_ep_ops pcie_ep_ops = {
  317. .ep_init = dra7xx_pcie_ep_init,
  318. .raise_irq = dra7xx_pcie_raise_irq,
  319. };
  320. static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
  321. struct platform_device *pdev)
  322. {
  323. int ret;
  324. struct dw_pcie_ep *ep;
  325. struct resource *res;
  326. struct device *dev = &pdev->dev;
  327. struct dw_pcie *pci = dra7xx->pci;
  328. ep = &pci->ep;
  329. ep->ops = &pcie_ep_ops;
  330. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
  331. pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
  332. if (!pci->dbi_base)
  333. return -ENOMEM;
  334. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
  335. pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
  336. if (!pci->dbi_base2)
  337. return -ENOMEM;
  338. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
  339. if (!res)
  340. return -EINVAL;
  341. ep->phys_base = res->start;
  342. ep->addr_size = resource_size(res);
  343. ret = dw_pcie_ep_init(ep);
  344. if (ret) {
  345. dev_err(dev, "failed to initialize endpoint\n");
  346. return ret;
  347. }
  348. return 0;
  349. }
  350. static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
  351. struct platform_device *pdev)
  352. {
  353. int ret;
  354. struct dw_pcie *pci = dra7xx->pci;
  355. struct pcie_port *pp = &pci->pp;
  356. struct device *dev = pci->dev;
  357. struct resource *res;
  358. pp->irq = platform_get_irq(pdev, 1);
  359. if (pp->irq < 0) {
  360. dev_err(dev, "missing IRQ resource\n");
  361. return pp->irq;
  362. }
  363. ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
  364. IRQF_SHARED | IRQF_NO_THREAD,
  365. "dra7-pcie-msi", dra7xx);
  366. if (ret) {
  367. dev_err(dev, "failed to request irq\n");
  368. return ret;
  369. }
  370. ret = dra7xx_pcie_init_irq_domain(pp);
  371. if (ret < 0)
  372. return ret;
  373. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
  374. pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
  375. if (!pci->dbi_base)
  376. return -ENOMEM;
  377. pp->ops = &dra7xx_pcie_host_ops;
  378. ret = dw_pcie_host_init(pp);
  379. if (ret) {
  380. dev_err(dev, "failed to initialize host\n");
  381. return ret;
  382. }
  383. return 0;
  384. }
  385. static const struct dw_pcie_ops dw_pcie_ops = {
  386. .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
  387. .start_link = dra7xx_pcie_establish_link,
  388. .stop_link = dra7xx_pcie_stop_link,
  389. .link_up = dra7xx_pcie_link_up,
  390. };
  391. static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
  392. {
  393. int phy_count = dra7xx->phy_count;
  394. while (phy_count--) {
  395. phy_power_off(dra7xx->phy[phy_count]);
  396. phy_exit(dra7xx->phy[phy_count]);
  397. }
  398. }
  399. static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
  400. {
  401. int phy_count = dra7xx->phy_count;
  402. int ret;
  403. int i;
  404. for (i = 0; i < phy_count; i++) {
  405. ret = phy_init(dra7xx->phy[i]);
  406. if (ret < 0)
  407. goto err_phy;
  408. ret = phy_power_on(dra7xx->phy[i]);
  409. if (ret < 0) {
  410. phy_exit(dra7xx->phy[i]);
  411. goto err_phy;
  412. }
  413. }
  414. return 0;
  415. err_phy:
  416. while (--i >= 0) {
  417. phy_power_off(dra7xx->phy[i]);
  418. phy_exit(dra7xx->phy[i]);
  419. }
  420. return ret;
  421. }
  422. static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
  423. .mode = DW_PCIE_RC_TYPE,
  424. };
  425. static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
  426. .mode = DW_PCIE_EP_TYPE,
  427. };
  428. static const struct of_device_id of_dra7xx_pcie_match[] = {
  429. {
  430. .compatible = "ti,dra7-pcie",
  431. .data = &dra7xx_pcie_rc_of_data,
  432. },
  433. {
  434. .compatible = "ti,dra7-pcie-ep",
  435. .data = &dra7xx_pcie_ep_of_data,
  436. },
  437. {},
  438. };
  439. /*
  440. * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
  441. * @dra7xx: the dra7xx device where the workaround should be applied
  442. *
  443. * Access to the PCIe slave port that are not 32-bit aligned will result
  444. * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
  445. * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
  446. * 0x3.
  447. *
  448. * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
  449. */
  450. static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
  451. {
  452. int ret;
  453. struct device_node *np = dev->of_node;
  454. struct of_phandle_args args;
  455. struct regmap *regmap;
  456. regmap = syscon_regmap_lookup_by_phandle(np,
  457. "ti,syscon-unaligned-access");
  458. if (IS_ERR(regmap)) {
  459. dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
  460. return -EINVAL;
  461. }
  462. ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
  463. 2, 0, &args);
  464. if (ret) {
  465. dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
  466. return ret;
  467. }
  468. ret = regmap_update_bits(regmap, args.args[0], args.args[1],
  469. args.args[1]);
  470. if (ret)
  471. dev_err(dev, "failed to enable unaligned access\n");
  472. of_node_put(args.np);
  473. return ret;
  474. }
  475. static int __init dra7xx_pcie_probe(struct platform_device *pdev)
  476. {
  477. u32 reg;
  478. int ret;
  479. int irq;
  480. int i;
  481. int phy_count;
  482. struct phy **phy;
  483. struct device_link **link;
  484. void __iomem *base;
  485. struct resource *res;
  486. struct dw_pcie *pci;
  487. struct dra7xx_pcie *dra7xx;
  488. struct device *dev = &pdev->dev;
  489. struct device_node *np = dev->of_node;
  490. char name[10];
  491. struct gpio_desc *reset;
  492. const struct of_device_id *match;
  493. const struct dra7xx_pcie_of_data *data;
  494. enum dw_pcie_device_mode mode;
  495. match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
  496. if (!match)
  497. return -EINVAL;
  498. data = (struct dra7xx_pcie_of_data *)match->data;
  499. mode = (enum dw_pcie_device_mode)data->mode;
  500. dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
  501. if (!dra7xx)
  502. return -ENOMEM;
  503. pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
  504. if (!pci)
  505. return -ENOMEM;
  506. pci->dev = dev;
  507. pci->ops = &dw_pcie_ops;
  508. irq = platform_get_irq(pdev, 0);
  509. if (irq < 0) {
  510. dev_err(dev, "missing IRQ resource: %d\n", irq);
  511. return irq;
  512. }
  513. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
  514. base = devm_ioremap_nocache(dev, res->start, resource_size(res));
  515. if (!base)
  516. return -ENOMEM;
  517. phy_count = of_property_count_strings(np, "phy-names");
  518. if (phy_count < 0) {
  519. dev_err(dev, "unable to find the strings\n");
  520. return phy_count;
  521. }
  522. phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
  523. if (!phy)
  524. return -ENOMEM;
  525. link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
  526. if (!link)
  527. return -ENOMEM;
  528. for (i = 0; i < phy_count; i++) {
  529. snprintf(name, sizeof(name), "pcie-phy%d", i);
  530. phy[i] = devm_phy_get(dev, name);
  531. if (IS_ERR(phy[i]))
  532. return PTR_ERR(phy[i]);
  533. link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
  534. if (!link[i]) {
  535. ret = -EINVAL;
  536. goto err_link;
  537. }
  538. }
  539. dra7xx->base = base;
  540. dra7xx->phy = phy;
  541. dra7xx->pci = pci;
  542. dra7xx->phy_count = phy_count;
  543. ret = dra7xx_pcie_enable_phy(dra7xx);
  544. if (ret) {
  545. dev_err(dev, "failed to enable phy\n");
  546. return ret;
  547. }
  548. platform_set_drvdata(pdev, dra7xx);
  549. pm_runtime_enable(dev);
  550. ret = pm_runtime_get_sync(dev);
  551. if (ret < 0) {
  552. dev_err(dev, "pm_runtime_get_sync failed\n");
  553. goto err_get_sync;
  554. }
  555. reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
  556. if (IS_ERR(reset)) {
  557. ret = PTR_ERR(reset);
  558. dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
  559. goto err_gpio;
  560. }
  561. reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
  562. reg &= ~LTSSM_EN;
  563. dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
  564. dra7xx->link_gen = of_pci_get_max_link_speed(np);
  565. if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
  566. dra7xx->link_gen = 2;
  567. switch (mode) {
  568. case DW_PCIE_RC_TYPE:
  569. if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
  570. ret = -ENODEV;
  571. goto err_gpio;
  572. }
  573. dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
  574. DEVICE_TYPE_RC);
  575. ret = dra7xx_add_pcie_port(dra7xx, pdev);
  576. if (ret < 0)
  577. goto err_gpio;
  578. break;
  579. case DW_PCIE_EP_TYPE:
  580. if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
  581. ret = -ENODEV;
  582. goto err_gpio;
  583. }
  584. dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
  585. DEVICE_TYPE_EP);
  586. ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
  587. if (ret)
  588. goto err_gpio;
  589. ret = dra7xx_add_pcie_ep(dra7xx, pdev);
  590. if (ret < 0)
  591. goto err_gpio;
  592. break;
  593. default:
  594. dev_err(dev, "INVALID device type %d\n", mode);
  595. }
  596. dra7xx->mode = mode;
  597. ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
  598. IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
  599. if (ret) {
  600. dev_err(dev, "failed to request irq\n");
  601. goto err_gpio;
  602. }
  603. return 0;
  604. err_gpio:
  605. pm_runtime_put(dev);
  606. err_get_sync:
  607. pm_runtime_disable(dev);
  608. dra7xx_pcie_disable_phy(dra7xx);
  609. err_link:
  610. while (--i >= 0)
  611. device_link_del(link[i]);
  612. return ret;
  613. }
  614. #ifdef CONFIG_PM_SLEEP
  615. static int dra7xx_pcie_suspend(struct device *dev)
  616. {
  617. struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
  618. struct dw_pcie *pci = dra7xx->pci;
  619. u32 val;
  620. if (dra7xx->mode != DW_PCIE_RC_TYPE)
  621. return 0;
  622. /* clear MSE */
  623. val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
  624. val &= ~PCI_COMMAND_MEMORY;
  625. dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
  626. return 0;
  627. }
  628. static int dra7xx_pcie_resume(struct device *dev)
  629. {
  630. struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
  631. struct dw_pcie *pci = dra7xx->pci;
  632. u32 val;
  633. if (dra7xx->mode != DW_PCIE_RC_TYPE)
  634. return 0;
  635. /* set MSE */
  636. val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
  637. val |= PCI_COMMAND_MEMORY;
  638. dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
  639. return 0;
  640. }
  641. static int dra7xx_pcie_suspend_noirq(struct device *dev)
  642. {
  643. struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
  644. dra7xx_pcie_disable_phy(dra7xx);
  645. return 0;
  646. }
  647. static int dra7xx_pcie_resume_noirq(struct device *dev)
  648. {
  649. struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
  650. int ret;
  651. ret = dra7xx_pcie_enable_phy(dra7xx);
  652. if (ret) {
  653. dev_err(dev, "failed to enable phy\n");
  654. return ret;
  655. }
  656. return 0;
  657. }
  658. #endif
  659. static void dra7xx_pcie_shutdown(struct platform_device *pdev)
  660. {
  661. struct device *dev = &pdev->dev;
  662. struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
  663. int ret;
  664. dra7xx_pcie_stop_link(dra7xx->pci);
  665. ret = pm_runtime_put_sync(dev);
  666. if (ret < 0)
  667. dev_dbg(dev, "pm_runtime_put_sync failed\n");
  668. pm_runtime_disable(dev);
  669. dra7xx_pcie_disable_phy(dra7xx);
  670. }
  671. static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
  672. SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
  673. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
  674. dra7xx_pcie_resume_noirq)
  675. };
  676. static struct platform_driver dra7xx_pcie_driver = {
  677. .driver = {
  678. .name = "dra7-pcie",
  679. .of_match_table = of_dra7xx_pcie_match,
  680. .suppress_bind_attrs = true,
  681. .pm = &dra7xx_pcie_pm_ops,
  682. },
  683. .shutdown = dra7xx_pcie_shutdown,
  684. };
  685. builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);