mt76x2_eeprom.h 5.0 KB

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  1. /*
  2. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef __MT76x2_EEPROM_H
  17. #define __MT76x2_EEPROM_H
  18. #include "mt76x2.h"
  19. enum mt76x2_eeprom_field {
  20. MT_EE_CHIP_ID = 0x000,
  21. MT_EE_VERSION = 0x002,
  22. MT_EE_MAC_ADDR = 0x004,
  23. MT_EE_PCI_ID = 0x00A,
  24. MT_EE_NIC_CONF_0 = 0x034,
  25. MT_EE_NIC_CONF_1 = 0x036,
  26. MT_EE_NIC_CONF_2 = 0x042,
  27. MT_EE_XTAL_TRIM_1 = 0x03a,
  28. MT_EE_XTAL_TRIM_2 = 0x09e,
  29. MT_EE_LNA_GAIN = 0x044,
  30. MT_EE_RSSI_OFFSET_2G_0 = 0x046,
  31. MT_EE_RSSI_OFFSET_2G_1 = 0x048,
  32. MT_EE_RSSI_OFFSET_5G_0 = 0x04a,
  33. MT_EE_RSSI_OFFSET_5G_1 = 0x04c,
  34. MT_EE_TX_POWER_DELTA_BW40 = 0x050,
  35. MT_EE_TX_POWER_DELTA_BW80 = 0x052,
  36. MT_EE_TX_POWER_EXT_PA_5G = 0x054,
  37. MT_EE_TX_POWER_0_START_2G = 0x056,
  38. MT_EE_TX_POWER_1_START_2G = 0x05c,
  39. /* used as byte arrays */
  40. #define MT_TX_POWER_GROUP_SIZE_5G 5
  41. #define MT_TX_POWER_GROUPS_5G 6
  42. MT_EE_TX_POWER_0_START_5G = 0x062,
  43. MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074,
  44. MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076,
  45. MT_EE_TX_POWER_1_START_5G = 0x080,
  46. MT_EE_TX_POWER_CCK = 0x0a0,
  47. MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2,
  48. MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4,
  49. MT_EE_TX_POWER_OFDM_5G_6M = 0x0b2,
  50. MT_EE_TX_POWER_OFDM_5G_24M = 0x0b4,
  51. MT_EE_TX_POWER_HT_MCS0 = 0x0a6,
  52. MT_EE_TX_POWER_HT_MCS4 = 0x0a8,
  53. MT_EE_TX_POWER_HT_MCS8 = 0x0aa,
  54. MT_EE_TX_POWER_HT_MCS12 = 0x0ac,
  55. MT_EE_TX_POWER_VHT_MCS0 = 0x0ba,
  56. MT_EE_TX_POWER_VHT_MCS4 = 0x0bc,
  57. MT_EE_TX_POWER_VHT_MCS8 = 0x0be,
  58. MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x0f2,
  59. MT_EE_RF_TEMP_COMP_SLOPE_2G = 0x0f4,
  60. MT_EE_RF_2G_TSSI_OFF_TXPOWER = 0x0f6,
  61. MT_EE_RF_2G_RX_HIGH_GAIN = 0x0f8,
  62. MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN = 0x0fa,
  63. MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN = 0x0fc,
  64. MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN = 0x0fe,
  65. MT_EE_BT_RCAL_RESULT = 0x138,
  66. MT_EE_BT_VCDL_CALIBRATION = 0x13c,
  67. MT_EE_BT_PMUCFG = 0x13e,
  68. __MT_EE_MAX
  69. };
  70. #define MT_EE_NIC_CONF_0_PA_INT_2G BIT(8)
  71. #define MT_EE_NIC_CONF_0_PA_INT_5G BIT(9)
  72. #define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)
  73. #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)
  74. #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)
  75. #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)
  76. #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)
  77. #define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0)
  78. #define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4)
  79. #define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8)
  80. #define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)
  81. #define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11)
  82. #define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
  83. enum mt76x2_board_type {
  84. BOARD_TYPE_2GHZ = 1,
  85. BOARD_TYPE_5GHZ = 2,
  86. };
  87. enum mt76x2_cal_channel_group {
  88. MT_CH_5G_JAPAN,
  89. MT_CH_5G_UNII_1,
  90. MT_CH_5G_UNII_2,
  91. MT_CH_5G_UNII_2E_1,
  92. MT_CH_5G_UNII_2E_2,
  93. MT_CH_5G_UNII_3,
  94. __MT_CH_MAX
  95. };
  96. struct mt76x2_tx_power_info {
  97. u8 target_power;
  98. s8 delta_bw40;
  99. s8 delta_bw80;
  100. struct {
  101. s8 tssi_slope;
  102. s8 tssi_offset;
  103. s8 target_power;
  104. s8 delta;
  105. } chain[MT_MAX_CHAINS];
  106. };
  107. struct mt76x2_temp_comp {
  108. u8 temp_25_ref;
  109. int lower_bound; /* J */
  110. int upper_bound; /* J */
  111. unsigned int high_slope; /* J / dB */
  112. unsigned int low_slope; /* J / dB */
  113. };
  114. static inline int
  115. mt76x2_eeprom_get(struct mt76x2_dev *dev, enum mt76x2_eeprom_field field)
  116. {
  117. if ((field & 1) || field >= __MT_EE_MAX)
  118. return -1;
  119. return get_unaligned_le16(dev->mt76.eeprom.data + field);
  120. }
  121. void mt76x2_get_rate_power(struct mt76x2_dev *dev, struct mt76_rate_power *t,
  122. struct ieee80211_channel *chan);
  123. int mt76x2_get_max_rate_power(struct mt76_rate_power *r);
  124. void mt76x2_get_power_info(struct mt76x2_dev *dev,
  125. struct mt76x2_tx_power_info *t,
  126. struct ieee80211_channel *chan);
  127. int mt76x2_get_temp_comp(struct mt76x2_dev *dev, struct mt76x2_temp_comp *t);
  128. bool mt76x2_ext_pa_enabled(struct mt76x2_dev *dev, enum nl80211_band band);
  129. void mt76x2_read_rx_gain(struct mt76x2_dev *dev);
  130. static inline bool
  131. mt76x2_temp_tx_alc_enabled(struct mt76x2_dev *dev)
  132. {
  133. return mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1) &
  134. MT_EE_NIC_CONF_1_TEMP_TX_ALC;
  135. }
  136. static inline bool
  137. mt76x2_tssi_enabled(struct mt76x2_dev *dev)
  138. {
  139. return !mt76x2_temp_tx_alc_enabled(dev) &&
  140. (mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1) &
  141. MT_EE_NIC_CONF_1_TX_ALC_EN);
  142. }
  143. static inline bool
  144. mt76x2_has_ext_lna(struct mt76x2_dev *dev)
  145. {
  146. u32 val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1);
  147. if (dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ)
  148. return val & MT_EE_NIC_CONF_1_LNA_EXT_2G;
  149. else
  150. return val & MT_EE_NIC_CONF_1_LNA_EXT_5G;
  151. }
  152. #endif