trans-gen2.c 11 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2017 Intel Deutschland GmbH
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of version 2 of the GNU General Public License as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * BSD LICENSE
  20. *
  21. * Copyright(c) 2017 Intel Deutschland GmbH
  22. * All rights reserved.
  23. *
  24. * Redistribution and use in source and binary forms, with or without
  25. * modification, are permitted provided that the following conditions
  26. * are met:
  27. *
  28. * * Redistributions of source code must retain the above copyright
  29. * notice, this list of conditions and the following disclaimer.
  30. * * Redistributions in binary form must reproduce the above copyright
  31. * notice, this list of conditions and the following disclaimer in
  32. * the documentation and/or other materials provided with the
  33. * distribution.
  34. * * Neither the name Intel Corporation nor the names of its
  35. * contributors may be used to endorse or promote products derived
  36. * from this software without specific prior written permission.
  37. *
  38. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  39. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  40. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  41. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  42. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  43. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  44. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  45. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  46. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  47. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  48. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  49. *
  50. *****************************************************************************/
  51. #include "iwl-trans.h"
  52. #include "iwl-prph.h"
  53. #include "iwl-context-info.h"
  54. #include "internal.h"
  55. /*
  56. * Start up NIC's basic functionality after it has been reset
  57. * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
  58. * NOTE: This does not load uCode nor start the embedded processor
  59. */
  60. static int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
  61. {
  62. int ret = 0;
  63. IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
  64. /*
  65. * Use "set_bit" below rather than "write", to preserve any hardware
  66. * bits already set by default after reset.
  67. */
  68. /*
  69. * Disable L0s without affecting L1;
  70. * don't wait for ICH L0s (ICH bug W/A)
  71. */
  72. iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
  73. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  74. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  75. iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  76. /*
  77. * Enable HAP INTA (interrupt from management bus) to
  78. * wake device's PCI Express link L1a -> L0s
  79. */
  80. iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
  81. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  82. iwl_pcie_apm_config(trans);
  83. /*
  84. * Set "initialization complete" bit to move adapter from
  85. * D0U* --> D0A* (powered-up active) state.
  86. */
  87. iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  88. /*
  89. * Wait for clock stabilization; once stabilized, access to
  90. * device-internal resources is supported, e.g. iwl_write_prph()
  91. * and accesses to uCode SRAM.
  92. */
  93. ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
  94. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  95. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  96. if (ret < 0) {
  97. IWL_DEBUG_INFO(trans, "Failed to init the card\n");
  98. return ret;
  99. }
  100. set_bit(STATUS_DEVICE_ENABLED, &trans->status);
  101. return 0;
  102. }
  103. static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
  104. {
  105. IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
  106. if (op_mode_leave) {
  107. if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
  108. iwl_pcie_gen2_apm_init(trans);
  109. /* inform ME that we are leaving */
  110. iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
  111. CSR_RESET_LINK_PWR_MGMT_DISABLED);
  112. iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
  113. CSR_HW_IF_CONFIG_REG_PREPARE |
  114. CSR_HW_IF_CONFIG_REG_ENABLE_PME);
  115. mdelay(1);
  116. iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
  117. CSR_RESET_LINK_PWR_MGMT_DISABLED);
  118. mdelay(5);
  119. }
  120. clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
  121. /* Stop device's DMA activity */
  122. iwl_pcie_apm_stop_master(trans);
  123. iwl_trans_sw_reset(trans);
  124. /*
  125. * Clear "initialization complete" bit to move adapter from
  126. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  127. */
  128. iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  129. }
  130. void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
  131. {
  132. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  133. lockdep_assert_held(&trans_pcie->mutex);
  134. if (trans_pcie->is_down)
  135. return;
  136. trans_pcie->is_down = true;
  137. /* Stop dbgc before stopping device */
  138. iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
  139. udelay(100);
  140. iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
  141. /* tell the device to stop sending interrupts */
  142. iwl_disable_interrupts(trans);
  143. /* device going down, Stop using ICT table */
  144. iwl_pcie_disable_ict(trans);
  145. /*
  146. * If a HW restart happens during firmware loading,
  147. * then the firmware loading might call this function
  148. * and later it might be called again due to the
  149. * restart. So don't process again if the device is
  150. * already dead.
  151. */
  152. if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
  153. IWL_DEBUG_INFO(trans,
  154. "DEVICE_ENABLED bit was set and is now cleared\n");
  155. iwl_pcie_gen2_tx_stop(trans);
  156. iwl_pcie_rx_stop(trans);
  157. }
  158. iwl_pcie_ctxt_info_free_paging(trans);
  159. iwl_pcie_ctxt_info_free(trans);
  160. /* Make sure (redundant) we've released our request to stay awake */
  161. iwl_clear_bit(trans, CSR_GP_CNTRL,
  162. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  163. /* Stop the device, and put it in low power state */
  164. iwl_pcie_gen2_apm_stop(trans, false);
  165. iwl_trans_sw_reset(trans);
  166. /*
  167. * Upon stop, the IVAR table gets erased, so msi-x won't
  168. * work. This causes a bug in RF-KILL flows, since the interrupt
  169. * that enables radio won't fire on the correct irq, and the
  170. * driver won't be able to handle the interrupt.
  171. * Configure the IVAR table again after reset.
  172. */
  173. iwl_pcie_conf_msix_hw(trans_pcie);
  174. /*
  175. * Upon stop, the APM issues an interrupt if HW RF kill is set.
  176. * This is a bug in certain verions of the hardware.
  177. * Certain devices also keep sending HW RF kill interrupt all
  178. * the time, unless the interrupt is ACKed even if the interrupt
  179. * should be masked. Re-ACK all the interrupts here.
  180. */
  181. iwl_disable_interrupts(trans);
  182. /* clear all status bits */
  183. clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
  184. clear_bit(STATUS_INT_ENABLED, &trans->status);
  185. clear_bit(STATUS_TPOWER_PMI, &trans->status);
  186. /*
  187. * Even if we stop the HW, we still want the RF kill
  188. * interrupt
  189. */
  190. iwl_enable_rfkill_int(trans);
  191. /* re-take ownership to prevent other users from stealing the device */
  192. iwl_pcie_prepare_card_hw(trans);
  193. }
  194. void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
  195. {
  196. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  197. bool was_in_rfkill;
  198. mutex_lock(&trans_pcie->mutex);
  199. trans_pcie->opmode_down = true;
  200. was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
  201. _iwl_trans_pcie_gen2_stop_device(trans, low_power);
  202. iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
  203. mutex_unlock(&trans_pcie->mutex);
  204. }
  205. static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
  206. {
  207. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  208. /* TODO: most of the logic can be removed in A0 - but not in Z0 */
  209. spin_lock(&trans_pcie->irq_lock);
  210. iwl_pcie_gen2_apm_init(trans);
  211. spin_unlock(&trans_pcie->irq_lock);
  212. iwl_op_mode_nic_config(trans->op_mode);
  213. /* Allocate the RX queue, or reset if it is already allocated */
  214. if (iwl_pcie_gen2_rx_init(trans))
  215. return -ENOMEM;
  216. /* Allocate or reset and init all Tx and Command queues */
  217. if (iwl_pcie_gen2_tx_init(trans))
  218. return -ENOMEM;
  219. /* enable shadow regs in HW */
  220. iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
  221. IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
  222. return 0;
  223. }
  224. void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
  225. {
  226. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  227. iwl_pcie_reset_ict(trans);
  228. /* make sure all queue are not stopped/used */
  229. memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
  230. memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
  231. /* now that we got alive we can free the fw image & the context info.
  232. * paging memory cannot be freed included since FW will still use it
  233. */
  234. iwl_pcie_ctxt_info_free(trans);
  235. }
  236. int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
  237. const struct fw_img *fw, bool run_in_rfkill)
  238. {
  239. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  240. bool hw_rfkill;
  241. int ret;
  242. /* This may fail if AMT took ownership of the device */
  243. if (iwl_pcie_prepare_card_hw(trans)) {
  244. IWL_WARN(trans, "Exit HW not ready\n");
  245. ret = -EIO;
  246. goto out;
  247. }
  248. iwl_enable_rfkill_int(trans);
  249. iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
  250. /*
  251. * We enabled the RF-Kill interrupt and the handler may very
  252. * well be running. Disable the interrupts to make sure no other
  253. * interrupt can be fired.
  254. */
  255. iwl_disable_interrupts(trans);
  256. /* Make sure it finished running */
  257. iwl_pcie_synchronize_irqs(trans);
  258. mutex_lock(&trans_pcie->mutex);
  259. /* If platform's RF_KILL switch is NOT set to KILL */
  260. hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
  261. if (hw_rfkill && !run_in_rfkill) {
  262. ret = -ERFKILL;
  263. goto out;
  264. }
  265. /* Someone called stop_device, don't try to start_fw */
  266. if (trans_pcie->is_down) {
  267. IWL_WARN(trans,
  268. "Can't start_fw since the HW hasn't been started\n");
  269. ret = -EIO;
  270. goto out;
  271. }
  272. /* make sure rfkill handshake bits are cleared */
  273. iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  274. iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
  275. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  276. /* clear (again), then enable host interrupts */
  277. iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
  278. ret = iwl_pcie_gen2_nic_init(trans);
  279. if (ret) {
  280. IWL_ERR(trans, "Unable to init nic\n");
  281. goto out;
  282. }
  283. ret = iwl_pcie_ctxt_info_init(trans, fw);
  284. if (ret)
  285. goto out;
  286. /* re-check RF-Kill state since we may have missed the interrupt */
  287. hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
  288. if (hw_rfkill && !run_in_rfkill)
  289. ret = -ERFKILL;
  290. out:
  291. mutex_unlock(&trans_pcie->mutex);
  292. return ret;
  293. }