iwl-nvm-parse.c 31 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37. * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  38. * All rights reserved.
  39. *
  40. * Redistribution and use in source and binary forms, with or without
  41. * modification, are permitted provided that the following conditions
  42. * are met:
  43. *
  44. * * Redistributions of source code must retain the above copyright
  45. * notice, this list of conditions and the following disclaimer.
  46. * * Redistributions in binary form must reproduce the above copyright
  47. * notice, this list of conditions and the following disclaimer in
  48. * the documentation and/or other materials provided with the
  49. * distribution.
  50. * * Neither the name Intel Corporation nor the names of its
  51. * contributors may be used to endorse or promote products derived
  52. * from this software without specific prior written permission.
  53. *
  54. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  59. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  60. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65. *****************************************************************************/
  66. #include <linux/types.h>
  67. #include <linux/slab.h>
  68. #include <linux/export.h>
  69. #include <linux/etherdevice.h>
  70. #include <linux/pci.h>
  71. #include "iwl-drv.h"
  72. #include "iwl-modparams.h"
  73. #include "iwl-nvm-parse.h"
  74. #include "iwl-prph.h"
  75. #include "iwl-io.h"
  76. #include "iwl-csr.h"
  77. #include "fw/acpi.h"
  78. #include "fw/api/nvm-reg.h"
  79. /* NVM offsets (in words) definitions */
  80. enum nvm_offsets {
  81. /* NVM HW-Section offset (in words) definitions */
  82. SUBSYSTEM_ID = 0x0A,
  83. HW_ADDR = 0x15,
  84. /* NVM SW-Section offset (in words) definitions */
  85. NVM_SW_SECTION = 0x1C0,
  86. NVM_VERSION = 0,
  87. RADIO_CFG = 1,
  88. SKU = 2,
  89. N_HW_ADDRS = 3,
  90. NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  91. /* NVM calibration section offset (in words) definitions */
  92. NVM_CALIB_SECTION = 0x2B8,
  93. XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
  94. /* NVM REGULATORY -Section offset (in words) definitions */
  95. NVM_CHANNELS_SDP = 0,
  96. };
  97. enum ext_nvm_offsets {
  98. /* NVM HW-Section offset (in words) definitions */
  99. MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
  100. /* NVM SW-Section offset (in words) definitions */
  101. NVM_VERSION_EXT_NVM = 0,
  102. RADIO_CFG_FAMILY_EXT_NVM = 0,
  103. SKU_FAMILY_8000 = 2,
  104. N_HW_ADDRS_FAMILY_8000 = 3,
  105. /* NVM REGULATORY -Section offset (in words) definitions */
  106. NVM_CHANNELS_EXTENDED = 0,
  107. NVM_LAR_OFFSET_OLD = 0x4C7,
  108. NVM_LAR_OFFSET = 0x507,
  109. NVM_LAR_ENABLED = 0x7,
  110. };
  111. /* SKU Capabilities (actual values from NVM definition) */
  112. enum nvm_sku_bits {
  113. NVM_SKU_CAP_BAND_24GHZ = BIT(0),
  114. NVM_SKU_CAP_BAND_52GHZ = BIT(1),
  115. NVM_SKU_CAP_11N_ENABLE = BIT(2),
  116. NVM_SKU_CAP_11AC_ENABLE = BIT(3),
  117. NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
  118. };
  119. /*
  120. * These are the channel numbers in the order that they are stored in the NVM
  121. */
  122. static const u8 iwl_nvm_channels[] = {
  123. /* 2.4 GHz */
  124. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  125. /* 5 GHz */
  126. 36, 40, 44 , 48, 52, 56, 60, 64,
  127. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  128. 149, 153, 157, 161, 165
  129. };
  130. static const u8 iwl_ext_nvm_channels[] = {
  131. /* 2.4 GHz */
  132. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  133. /* 5 GHz */
  134. 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  135. 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  136. 149, 153, 157, 161, 165, 169, 173, 177, 181
  137. };
  138. #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
  139. #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
  140. #define NUM_2GHZ_CHANNELS 14
  141. #define NUM_2GHZ_CHANNELS_EXT 14
  142. #define FIRST_2GHZ_HT_MINUS 5
  143. #define LAST_2GHZ_HT_PLUS 9
  144. #define LAST_5GHZ_HT 165
  145. #define LAST_5GHZ_HT_FAMILY_8000 181
  146. #define N_HW_ADDR_MASK 0xF
  147. /* rate data (static) */
  148. static struct ieee80211_rate iwl_cfg80211_rates[] = {
  149. { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
  150. { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
  151. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  152. { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
  153. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  154. { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
  155. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  156. { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
  157. { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
  158. { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
  159. { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
  160. { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
  161. { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
  162. { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
  163. { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
  164. };
  165. #define RATES_24_OFFS 0
  166. #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
  167. #define RATES_52_OFFS 4
  168. #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
  169. /**
  170. * enum iwl_nvm_channel_flags - channel flags in NVM
  171. * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
  172. * @NVM_CHANNEL_IBSS: usable as an IBSS channel
  173. * @NVM_CHANNEL_ACTIVE: active scanning allowed
  174. * @NVM_CHANNEL_RADAR: radar detection required
  175. * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
  176. * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
  177. * on same channel on 2.4 or same UNII band on 5.2
  178. * @NVM_CHANNEL_UNIFORM: uniform spreading required
  179. * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
  180. * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
  181. * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
  182. * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
  183. * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
  184. */
  185. enum iwl_nvm_channel_flags {
  186. NVM_CHANNEL_VALID = BIT(0),
  187. NVM_CHANNEL_IBSS = BIT(1),
  188. NVM_CHANNEL_ACTIVE = BIT(3),
  189. NVM_CHANNEL_RADAR = BIT(4),
  190. NVM_CHANNEL_INDOOR_ONLY = BIT(5),
  191. NVM_CHANNEL_GO_CONCURRENT = BIT(6),
  192. NVM_CHANNEL_UNIFORM = BIT(7),
  193. NVM_CHANNEL_20MHZ = BIT(8),
  194. NVM_CHANNEL_40MHZ = BIT(9),
  195. NVM_CHANNEL_80MHZ = BIT(10),
  196. NVM_CHANNEL_160MHZ = BIT(11),
  197. NVM_CHANNEL_DC_HIGH = BIT(12),
  198. };
  199. static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
  200. int chan, u16 flags)
  201. {
  202. #define CHECK_AND_PRINT_I(x) \
  203. ((flags & NVM_CHANNEL_##x) ? " " #x : "")
  204. if (!(flags & NVM_CHANNEL_VALID)) {
  205. IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
  206. chan, flags);
  207. return;
  208. }
  209. /* Note: already can print up to 101 characters, 110 is the limit! */
  210. IWL_DEBUG_DEV(dev, level,
  211. "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
  212. chan, flags,
  213. CHECK_AND_PRINT_I(VALID),
  214. CHECK_AND_PRINT_I(IBSS),
  215. CHECK_AND_PRINT_I(ACTIVE),
  216. CHECK_AND_PRINT_I(RADAR),
  217. CHECK_AND_PRINT_I(INDOOR_ONLY),
  218. CHECK_AND_PRINT_I(GO_CONCURRENT),
  219. CHECK_AND_PRINT_I(UNIFORM),
  220. CHECK_AND_PRINT_I(20MHZ),
  221. CHECK_AND_PRINT_I(40MHZ),
  222. CHECK_AND_PRINT_I(80MHZ),
  223. CHECK_AND_PRINT_I(160MHZ),
  224. CHECK_AND_PRINT_I(DC_HIGH));
  225. #undef CHECK_AND_PRINT_I
  226. }
  227. static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
  228. u16 nvm_flags, const struct iwl_cfg *cfg)
  229. {
  230. u32 flags = IEEE80211_CHAN_NO_HT40;
  231. u32 last_5ghz_ht = LAST_5GHZ_HT;
  232. if (cfg->nvm_type == IWL_NVM_EXT)
  233. last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
  234. if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
  235. if (ch_num <= LAST_2GHZ_HT_PLUS)
  236. flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  237. if (ch_num >= FIRST_2GHZ_HT_MINUS)
  238. flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  239. } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
  240. if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
  241. flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  242. else
  243. flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  244. }
  245. if (!(nvm_flags & NVM_CHANNEL_80MHZ))
  246. flags |= IEEE80211_CHAN_NO_80MHZ;
  247. if (!(nvm_flags & NVM_CHANNEL_160MHZ))
  248. flags |= IEEE80211_CHAN_NO_160MHZ;
  249. if (!(nvm_flags & NVM_CHANNEL_IBSS))
  250. flags |= IEEE80211_CHAN_NO_IR;
  251. if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
  252. flags |= IEEE80211_CHAN_NO_IR;
  253. if (nvm_flags & NVM_CHANNEL_RADAR)
  254. flags |= IEEE80211_CHAN_RADAR;
  255. if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
  256. flags |= IEEE80211_CHAN_INDOOR_ONLY;
  257. /* Set the GO concurrent flag only in case that NO_IR is set.
  258. * Otherwise it is meaningless
  259. */
  260. if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  261. (flags & IEEE80211_CHAN_NO_IR))
  262. flags |= IEEE80211_CHAN_IR_CONCURRENT;
  263. return flags;
  264. }
  265. static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
  266. struct iwl_nvm_data *data,
  267. const __le16 * const nvm_ch_flags,
  268. bool lar_supported, bool no_wide_in_5ghz)
  269. {
  270. int ch_idx;
  271. int n_channels = 0;
  272. struct ieee80211_channel *channel;
  273. u16 ch_flags;
  274. int num_of_ch, num_2ghz_channels;
  275. const u8 *nvm_chan;
  276. if (cfg->nvm_type != IWL_NVM_EXT) {
  277. num_of_ch = IWL_NVM_NUM_CHANNELS;
  278. nvm_chan = &iwl_nvm_channels[0];
  279. num_2ghz_channels = NUM_2GHZ_CHANNELS;
  280. } else {
  281. num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
  282. nvm_chan = &iwl_ext_nvm_channels[0];
  283. num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT;
  284. }
  285. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  286. bool is_5ghz = (ch_idx >= num_2ghz_channels);
  287. ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
  288. if (is_5ghz && !data->sku_cap_band_52GHz_enable)
  289. continue;
  290. /* workaround to disable wide channels in 5GHz */
  291. if (no_wide_in_5ghz && is_5ghz) {
  292. ch_flags &= ~(NVM_CHANNEL_40MHZ |
  293. NVM_CHANNEL_80MHZ |
  294. NVM_CHANNEL_160MHZ);
  295. }
  296. if (ch_flags & NVM_CHANNEL_160MHZ)
  297. data->vht160_supported = true;
  298. if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
  299. /*
  300. * Channels might become valid later if lar is
  301. * supported, hence we still want to add them to
  302. * the list of supported channels to cfg80211.
  303. */
  304. iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
  305. nvm_chan[ch_idx], ch_flags);
  306. continue;
  307. }
  308. channel = &data->channels[n_channels];
  309. n_channels++;
  310. channel->hw_value = nvm_chan[ch_idx];
  311. channel->band = is_5ghz ?
  312. NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
  313. channel->center_freq =
  314. ieee80211_channel_to_frequency(
  315. channel->hw_value, channel->band);
  316. /* Initialize regulatory-based run-time data */
  317. /*
  318. * Default value - highest tx power value. max_power
  319. * is not used in mvm, and is used for backwards compatibility
  320. */
  321. channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
  322. /* don't put limitations in case we're using LAR */
  323. if (!lar_supported)
  324. channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
  325. ch_idx, is_5ghz,
  326. ch_flags, cfg);
  327. else
  328. channel->flags = 0;
  329. iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
  330. channel->hw_value, ch_flags);
  331. IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
  332. channel->hw_value, channel->max_power);
  333. }
  334. return n_channels;
  335. }
  336. static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
  337. struct iwl_nvm_data *data,
  338. struct ieee80211_sta_vht_cap *vht_cap,
  339. u8 tx_chains, u8 rx_chains)
  340. {
  341. int num_rx_ants = num_of_ant(rx_chains);
  342. int num_tx_ants = num_of_ant(tx_chains);
  343. unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
  344. IEEE80211_VHT_MAX_AMPDU_1024K);
  345. vht_cap->vht_supported = true;
  346. vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
  347. IEEE80211_VHT_CAP_RXSTBC_1 |
  348. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
  349. 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
  350. max_ampdu_exponent <<
  351. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
  352. if (data->vht160_supported)
  353. vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
  354. IEEE80211_VHT_CAP_SHORT_GI_160;
  355. if (cfg->vht_mu_mimo_supported)
  356. vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
  357. if (cfg->ht_params->ldpc)
  358. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  359. if (data->sku_cap_mimo_disabled) {
  360. num_rx_ants = 1;
  361. num_tx_ants = 1;
  362. }
  363. if (num_tx_ants > 1)
  364. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  365. else
  366. vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
  367. switch (iwlwifi_mod_params.amsdu_size) {
  368. case IWL_AMSDU_DEF:
  369. if (cfg->mq_rx_supported)
  370. vht_cap->cap |=
  371. IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
  372. else
  373. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
  374. break;
  375. case IWL_AMSDU_4K:
  376. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
  377. break;
  378. case IWL_AMSDU_8K:
  379. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
  380. break;
  381. case IWL_AMSDU_12K:
  382. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
  383. break;
  384. default:
  385. break;
  386. }
  387. vht_cap->vht_mcs.rx_mcs_map =
  388. cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
  389. IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
  390. IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
  391. IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
  392. IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
  393. IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
  394. IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
  395. IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
  396. if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
  397. vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
  398. /* this works because NOT_SUPPORTED == 3 */
  399. vht_cap->vht_mcs.rx_mcs_map |=
  400. cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
  401. }
  402. vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
  403. }
  404. void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
  405. struct iwl_nvm_data *data, const __le16 *nvm_ch_flags,
  406. u8 tx_chains, u8 rx_chains, bool lar_supported,
  407. bool no_wide_in_5ghz)
  408. {
  409. int n_channels;
  410. int n_used = 0;
  411. struct ieee80211_supported_band *sband;
  412. n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
  413. lar_supported, no_wide_in_5ghz);
  414. sband = &data->bands[NL80211_BAND_2GHZ];
  415. sband->band = NL80211_BAND_2GHZ;
  416. sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
  417. sband->n_bitrates = N_RATES_24;
  418. n_used += iwl_init_sband_channels(data, sband, n_channels,
  419. NL80211_BAND_2GHZ);
  420. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ,
  421. tx_chains, rx_chains);
  422. sband = &data->bands[NL80211_BAND_5GHZ];
  423. sband->band = NL80211_BAND_5GHZ;
  424. sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
  425. sband->n_bitrates = N_RATES_52;
  426. n_used += iwl_init_sband_channels(data, sband, n_channels,
  427. NL80211_BAND_5GHZ);
  428. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ,
  429. tx_chains, rx_chains);
  430. if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
  431. iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
  432. tx_chains, rx_chains);
  433. if (n_channels != n_used)
  434. IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
  435. n_used, n_channels);
  436. }
  437. IWL_EXPORT_SYMBOL(iwl_init_sbands);
  438. static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
  439. const __le16 *phy_sku)
  440. {
  441. if (cfg->nvm_type != IWL_NVM_EXT)
  442. return le16_to_cpup(nvm_sw + SKU);
  443. return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
  444. }
  445. static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
  446. {
  447. if (cfg->nvm_type != IWL_NVM_EXT)
  448. return le16_to_cpup(nvm_sw + NVM_VERSION);
  449. else
  450. return le32_to_cpup((__le32 *)(nvm_sw +
  451. NVM_VERSION_EXT_NVM));
  452. }
  453. static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
  454. const __le16 *phy_sku)
  455. {
  456. if (cfg->nvm_type != IWL_NVM_EXT)
  457. return le16_to_cpup(nvm_sw + RADIO_CFG);
  458. return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
  459. }
  460. static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
  461. {
  462. int n_hw_addr;
  463. if (cfg->nvm_type != IWL_NVM_EXT)
  464. return le16_to_cpup(nvm_sw + N_HW_ADDRS);
  465. n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
  466. return n_hw_addr & N_HW_ADDR_MASK;
  467. }
  468. static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
  469. struct iwl_nvm_data *data,
  470. u32 radio_cfg)
  471. {
  472. if (cfg->nvm_type != IWL_NVM_EXT) {
  473. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
  474. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
  475. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
  476. data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
  477. return;
  478. }
  479. /* set the radio configuration for family 8000 */
  480. data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
  481. data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
  482. data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
  483. data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
  484. data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
  485. data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
  486. }
  487. static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
  488. {
  489. const u8 *hw_addr;
  490. hw_addr = (const u8 *)&mac_addr0;
  491. dest[0] = hw_addr[3];
  492. dest[1] = hw_addr[2];
  493. dest[2] = hw_addr[1];
  494. dest[3] = hw_addr[0];
  495. hw_addr = (const u8 *)&mac_addr1;
  496. dest[4] = hw_addr[1];
  497. dest[5] = hw_addr[0];
  498. }
  499. void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
  500. struct iwl_nvm_data *data)
  501. {
  502. __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
  503. __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
  504. iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
  505. /*
  506. * If the OEM fused a valid address, use it instead of the one in the
  507. * OTP
  508. */
  509. if (is_valid_ether_addr(data->hw_addr))
  510. return;
  511. mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
  512. mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
  513. iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
  514. }
  515. IWL_EXPORT_SYMBOL(iwl_set_hw_address_from_csr);
  516. static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
  517. const struct iwl_cfg *cfg,
  518. struct iwl_nvm_data *data,
  519. const __le16 *mac_override,
  520. const __be16 *nvm_hw)
  521. {
  522. const u8 *hw_addr;
  523. if (mac_override) {
  524. static const u8 reserved_mac[] = {
  525. 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
  526. };
  527. hw_addr = (const u8 *)(mac_override +
  528. MAC_ADDRESS_OVERRIDE_EXT_NVM);
  529. /*
  530. * Store the MAC address from MAO section.
  531. * No byte swapping is required in MAO section
  532. */
  533. memcpy(data->hw_addr, hw_addr, ETH_ALEN);
  534. /*
  535. * Force the use of the OTP MAC address in case of reserved MAC
  536. * address in the NVM, or if address is given but invalid.
  537. */
  538. if (is_valid_ether_addr(data->hw_addr) &&
  539. memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
  540. return;
  541. IWL_ERR(trans,
  542. "mac address from nvm override section is not valid\n");
  543. }
  544. if (nvm_hw) {
  545. /* read the mac address from WFMP registers */
  546. __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
  547. WFMP_MAC_ADDR_0));
  548. __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
  549. WFMP_MAC_ADDR_1));
  550. iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
  551. return;
  552. }
  553. IWL_ERR(trans, "mac address is not found\n");
  554. }
  555. static int iwl_set_hw_address(struct iwl_trans *trans,
  556. const struct iwl_cfg *cfg,
  557. struct iwl_nvm_data *data, const __be16 *nvm_hw,
  558. const __le16 *mac_override)
  559. {
  560. if (cfg->mac_addr_from_csr) {
  561. iwl_set_hw_address_from_csr(trans, data);
  562. } else if (cfg->nvm_type != IWL_NVM_EXT) {
  563. const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
  564. /* The byte order is little endian 16 bit, meaning 214365 */
  565. data->hw_addr[0] = hw_addr[1];
  566. data->hw_addr[1] = hw_addr[0];
  567. data->hw_addr[2] = hw_addr[3];
  568. data->hw_addr[3] = hw_addr[2];
  569. data->hw_addr[4] = hw_addr[5];
  570. data->hw_addr[5] = hw_addr[4];
  571. } else {
  572. iwl_set_hw_address_family_8000(trans, cfg, data,
  573. mac_override, nvm_hw);
  574. }
  575. if (!is_valid_ether_addr(data->hw_addr)) {
  576. IWL_ERR(trans, "no valid mac address was found\n");
  577. return -EINVAL;
  578. }
  579. IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
  580. return 0;
  581. }
  582. static bool
  583. iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg,
  584. const __be16 *nvm_hw)
  585. {
  586. /*
  587. * Workaround a bug in Indonesia SKUs where the regulatory in
  588. * some 7000-family OTPs erroneously allow wide channels in
  589. * 5GHz. To check for Indonesia, we take the SKU value from
  590. * bits 1-4 in the subsystem ID and check if it is either 5 or
  591. * 9. In those cases, we need to force-disable wide channels
  592. * in 5GHz otherwise the FW will throw a sysassert when we try
  593. * to use them.
  594. */
  595. if (cfg->device_family == IWL_DEVICE_FAMILY_7000) {
  596. /*
  597. * Unlike the other sections in the NVM, the hw
  598. * section uses big-endian.
  599. */
  600. u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
  601. u8 sku = (subsystem_id & 0x1e) >> 1;
  602. if (sku == 5 || sku == 9) {
  603. IWL_DEBUG_EEPROM(dev,
  604. "disabling wide channels in 5GHz (0x%0x %d)\n",
  605. subsystem_id, sku);
  606. return true;
  607. }
  608. }
  609. return false;
  610. }
  611. struct iwl_nvm_data *
  612. iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
  613. const __be16 *nvm_hw, const __le16 *nvm_sw,
  614. const __le16 *nvm_calib, const __le16 *regulatory,
  615. const __le16 *mac_override, const __le16 *phy_sku,
  616. u8 tx_chains, u8 rx_chains, bool lar_fw_supported)
  617. {
  618. struct device *dev = trans->dev;
  619. struct iwl_nvm_data *data;
  620. bool lar_enabled;
  621. bool no_wide_in_5ghz = iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw);
  622. u32 sku, radio_cfg;
  623. u16 lar_config;
  624. const __le16 *ch_section;
  625. if (cfg->nvm_type != IWL_NVM_EXT)
  626. data = kzalloc(sizeof(*data) +
  627. sizeof(struct ieee80211_channel) *
  628. IWL_NVM_NUM_CHANNELS,
  629. GFP_KERNEL);
  630. else
  631. data = kzalloc(sizeof(*data) +
  632. sizeof(struct ieee80211_channel) *
  633. IWL_NVM_NUM_CHANNELS_EXT,
  634. GFP_KERNEL);
  635. if (!data)
  636. return NULL;
  637. data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
  638. radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
  639. iwl_set_radio_cfg(cfg, data, radio_cfg);
  640. if (data->valid_tx_ant)
  641. tx_chains &= data->valid_tx_ant;
  642. if (data->valid_rx_ant)
  643. rx_chains &= data->valid_rx_ant;
  644. sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
  645. data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
  646. data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
  647. data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
  648. if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
  649. data->sku_cap_11n_enable = false;
  650. data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
  651. (sku & NVM_SKU_CAP_11AC_ENABLE);
  652. data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
  653. data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
  654. if (cfg->nvm_type != IWL_NVM_EXT) {
  655. /* Checking for required sections */
  656. if (!nvm_calib) {
  657. IWL_ERR(trans,
  658. "Can't parse empty Calib NVM sections\n");
  659. kfree(data);
  660. return NULL;
  661. }
  662. ch_section = cfg->nvm_type == IWL_NVM_SDP ?
  663. &regulatory[NVM_CHANNELS_SDP] :
  664. &nvm_sw[NVM_CHANNELS];
  665. /* in family 8000 Xtal calibration values moved to OTP */
  666. data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
  667. data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
  668. lar_enabled = true;
  669. } else {
  670. u16 lar_offset = data->nvm_version < 0xE39 ?
  671. NVM_LAR_OFFSET_OLD :
  672. NVM_LAR_OFFSET;
  673. lar_config = le16_to_cpup(regulatory + lar_offset);
  674. data->lar_enabled = !!(lar_config &
  675. NVM_LAR_ENABLED);
  676. lar_enabled = data->lar_enabled;
  677. ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
  678. }
  679. /* If no valid mac address was found - bail out */
  680. if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
  681. kfree(data);
  682. return NULL;
  683. }
  684. iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains,
  685. lar_fw_supported && lar_enabled, no_wide_in_5ghz);
  686. data->calib_version = 255;
  687. return data;
  688. }
  689. IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
  690. static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
  691. int ch_idx, u16 nvm_flags,
  692. const struct iwl_cfg *cfg)
  693. {
  694. u32 flags = NL80211_RRF_NO_HT40;
  695. u32 last_5ghz_ht = LAST_5GHZ_HT;
  696. if (cfg->nvm_type == IWL_NVM_EXT)
  697. last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
  698. if (ch_idx < NUM_2GHZ_CHANNELS &&
  699. (nvm_flags & NVM_CHANNEL_40MHZ)) {
  700. if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
  701. flags &= ~NL80211_RRF_NO_HT40PLUS;
  702. if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
  703. flags &= ~NL80211_RRF_NO_HT40MINUS;
  704. } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
  705. (nvm_flags & NVM_CHANNEL_40MHZ)) {
  706. if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
  707. flags &= ~NL80211_RRF_NO_HT40PLUS;
  708. else
  709. flags &= ~NL80211_RRF_NO_HT40MINUS;
  710. }
  711. if (!(nvm_flags & NVM_CHANNEL_80MHZ))
  712. flags |= NL80211_RRF_NO_80MHZ;
  713. if (!(nvm_flags & NVM_CHANNEL_160MHZ))
  714. flags |= NL80211_RRF_NO_160MHZ;
  715. if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
  716. flags |= NL80211_RRF_NO_IR;
  717. if (nvm_flags & NVM_CHANNEL_RADAR)
  718. flags |= NL80211_RRF_DFS;
  719. if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
  720. flags |= NL80211_RRF_NO_OUTDOOR;
  721. /* Set the GO concurrent flag only in case that NO_IR is set.
  722. * Otherwise it is meaningless
  723. */
  724. if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  725. (flags & NL80211_RRF_NO_IR))
  726. flags |= NL80211_RRF_GO_CONCURRENT;
  727. return flags;
  728. }
  729. struct regdb_ptrs {
  730. struct ieee80211_wmm_rule *rule;
  731. u32 token;
  732. };
  733. struct ieee80211_regdomain *
  734. iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
  735. int num_of_ch, __le32 *channels, u16 fw_mcc,
  736. u16 geo_info)
  737. {
  738. int ch_idx;
  739. u16 ch_flags;
  740. u32 reg_rule_flags, prev_reg_rule_flags = 0;
  741. const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ?
  742. iwl_ext_nvm_channels : iwl_nvm_channels;
  743. struct ieee80211_regdomain *regd, *copy_rd;
  744. int size_of_regd, regd_to_copy, wmms_to_copy;
  745. int size_of_wmms = 0;
  746. struct ieee80211_reg_rule *rule;
  747. struct ieee80211_wmm_rule *wmm_rule, *d_wmm, *s_wmm;
  748. struct regdb_ptrs *regdb_ptrs;
  749. enum nl80211_band band;
  750. int center_freq, prev_center_freq = 0;
  751. int valid_rules = 0, n_wmms = 0;
  752. int i;
  753. bool new_rule;
  754. int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ?
  755. IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS;
  756. if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
  757. return ERR_PTR(-EINVAL);
  758. if (WARN_ON(num_of_ch > max_num_ch))
  759. num_of_ch = max_num_ch;
  760. IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
  761. num_of_ch);
  762. /* build a regdomain rule for every valid channel */
  763. size_of_regd =
  764. sizeof(struct ieee80211_regdomain) +
  765. num_of_ch * sizeof(struct ieee80211_reg_rule);
  766. if (geo_info & GEO_WMM_ETSI_5GHZ_INFO)
  767. size_of_wmms =
  768. num_of_ch * sizeof(struct ieee80211_wmm_rule);
  769. regd = kzalloc(size_of_regd + size_of_wmms, GFP_KERNEL);
  770. if (!regd)
  771. return ERR_PTR(-ENOMEM);
  772. regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL);
  773. if (!regdb_ptrs) {
  774. copy_rd = ERR_PTR(-ENOMEM);
  775. goto out;
  776. }
  777. /* set alpha2 from FW. */
  778. regd->alpha2[0] = fw_mcc >> 8;
  779. regd->alpha2[1] = fw_mcc & 0xff;
  780. wmm_rule = (struct ieee80211_wmm_rule *)((u8 *)regd + size_of_regd);
  781. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  782. ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
  783. band = (ch_idx < NUM_2GHZ_CHANNELS) ?
  784. NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  785. center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
  786. band);
  787. new_rule = false;
  788. if (!(ch_flags & NVM_CHANNEL_VALID)) {
  789. iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
  790. nvm_chan[ch_idx], ch_flags);
  791. continue;
  792. }
  793. reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
  794. ch_flags, cfg);
  795. /* we can't continue the same rule */
  796. if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
  797. center_freq - prev_center_freq > 20) {
  798. valid_rules++;
  799. new_rule = true;
  800. }
  801. rule = &regd->reg_rules[valid_rules - 1];
  802. if (new_rule)
  803. rule->freq_range.start_freq_khz =
  804. MHZ_TO_KHZ(center_freq - 10);
  805. rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
  806. /* this doesn't matter - not used by FW */
  807. rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
  808. rule->power_rule.max_eirp =
  809. DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
  810. rule->flags = reg_rule_flags;
  811. /* rely on auto-calculation to merge BW of contiguous chans */
  812. rule->flags |= NL80211_RRF_AUTO_BW;
  813. rule->freq_range.max_bandwidth_khz = 0;
  814. prev_center_freq = center_freq;
  815. prev_reg_rule_flags = reg_rule_flags;
  816. iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
  817. nvm_chan[ch_idx], ch_flags);
  818. if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
  819. band == NL80211_BAND_2GHZ)
  820. continue;
  821. if (!reg_query_regdb_wmm(regd->alpha2, center_freq,
  822. &regdb_ptrs[n_wmms].token, wmm_rule)) {
  823. /* Add only new rules */
  824. for (i = 0; i < n_wmms; i++) {
  825. if (regdb_ptrs[i].token ==
  826. regdb_ptrs[n_wmms].token) {
  827. rule->wmm_rule = regdb_ptrs[i].rule;
  828. break;
  829. }
  830. }
  831. if (i == n_wmms) {
  832. rule->wmm_rule = wmm_rule;
  833. regdb_ptrs[n_wmms++].rule = wmm_rule;
  834. wmm_rule++;
  835. }
  836. }
  837. }
  838. regd->n_reg_rules = valid_rules;
  839. regd->n_wmm_rules = n_wmms;
  840. /*
  841. * Narrow down regdom for unused regulatory rules to prevent hole
  842. * between reg rules to wmm rules.
  843. */
  844. regd_to_copy = sizeof(struct ieee80211_regdomain) +
  845. valid_rules * sizeof(struct ieee80211_reg_rule);
  846. wmms_to_copy = sizeof(struct ieee80211_wmm_rule) * n_wmms;
  847. copy_rd = kzalloc(regd_to_copy + wmms_to_copy, GFP_KERNEL);
  848. if (!copy_rd) {
  849. copy_rd = ERR_PTR(-ENOMEM);
  850. goto out;
  851. }
  852. memcpy(copy_rd, regd, regd_to_copy);
  853. memcpy((u8 *)copy_rd + regd_to_copy, (u8 *)regd + size_of_regd,
  854. wmms_to_copy);
  855. d_wmm = (struct ieee80211_wmm_rule *)((u8 *)copy_rd + regd_to_copy);
  856. s_wmm = (struct ieee80211_wmm_rule *)((u8 *)regd + size_of_regd);
  857. for (i = 0; i < regd->n_reg_rules; i++) {
  858. if (!regd->reg_rules[i].wmm_rule)
  859. continue;
  860. copy_rd->reg_rules[i].wmm_rule = d_wmm +
  861. (regd->reg_rules[i].wmm_rule - s_wmm) /
  862. sizeof(struct ieee80211_wmm_rule);
  863. }
  864. out:
  865. kfree(regdb_ptrs);
  866. kfree(regd);
  867. return copy_rd;
  868. }
  869. IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);