sdio.c 118 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/atomic.h>
  18. #include <linux/kernel.h>
  19. #include <linux/kthread.h>
  20. #include <linux/printk.h>
  21. #include <linux/pci_ids.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/sched/signal.h>
  25. #include <linux/mmc/sdio.h>
  26. #include <linux/mmc/sdio_ids.h>
  27. #include <linux/mmc/sdio_func.h>
  28. #include <linux/mmc/card.h>
  29. #include <linux/semaphore.h>
  30. #include <linux/firmware.h>
  31. #include <linux/module.h>
  32. #include <linux/bcma/bcma.h>
  33. #include <linux/debugfs.h>
  34. #include <linux/vmalloc.h>
  35. #include <asm/unaligned.h>
  36. #include <defs.h>
  37. #include <brcmu_wifi.h>
  38. #include <brcmu_utils.h>
  39. #include <brcm_hw_ids.h>
  40. #include <soc.h>
  41. #include "sdio.h"
  42. #include "chip.h"
  43. #include "firmware.h"
  44. #include "core.h"
  45. #include "common.h"
  46. #include "bcdc.h"
  47. #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
  48. #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
  49. #ifdef DEBUG
  50. #define BRCMF_TRAP_INFO_SIZE 80
  51. #define CBUF_LEN (128)
  52. /* Device console log buffer state */
  53. #define CONSOLE_BUFFER_MAX 2024
  54. struct rte_log_le {
  55. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  56. __le32 buf_size;
  57. __le32 idx;
  58. char *_buf_compat; /* Redundant pointer for backward compat. */
  59. };
  60. struct rte_console {
  61. /* Virtual UART
  62. * When there is no UART (e.g. Quickturn),
  63. * the host should write a complete
  64. * input line directly into cbuf and then write
  65. * the length into vcons_in.
  66. * This may also be used when there is a real UART
  67. * (at risk of conflicting with
  68. * the real UART). vcons_out is currently unused.
  69. */
  70. uint vcons_in;
  71. uint vcons_out;
  72. /* Output (logging) buffer
  73. * Console output is written to a ring buffer log_buf at index log_idx.
  74. * The host may read the output when it sees log_idx advance.
  75. * Output will be lost if the output wraps around faster than the host
  76. * polls.
  77. */
  78. struct rte_log_le log_le;
  79. /* Console input line buffer
  80. * Characters are read one at a time into cbuf
  81. * until <CR> is received, then
  82. * the buffer is processed as a command line.
  83. * Also used for virtual UART.
  84. */
  85. uint cbuf_idx;
  86. char cbuf[CBUF_LEN];
  87. };
  88. #endif /* DEBUG */
  89. #include <chipcommon.h>
  90. #include "bus.h"
  91. #include "debug.h"
  92. #include "tracepoint.h"
  93. #define TXQLEN 2048 /* bulk tx queue length */
  94. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  95. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  96. #define PRIOMASK 7
  97. #define TXRETRIES 2 /* # of retries for tx frames */
  98. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  99. one scheduling */
  100. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  101. one scheduling */
  102. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  103. #define MEMBLOCK 2048 /* Block size used for downloading
  104. of dongle image */
  105. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  106. biggest possible glom */
  107. #define BRCMF_FIRSTREAD (1 << 6)
  108. #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
  109. /* SBSDIO_DEVICE_CTL */
  110. /* 1: device will assert busy signal when receiving CMD53 */
  111. #define SBSDIO_DEVCTL_SETBUSY 0x01
  112. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  113. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  114. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  115. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  116. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  117. * sdio bus power cycle to clear (rev 9) */
  118. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  119. /* Force SD->SB reset mapping (rev 11) */
  120. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  121. /* Determined by CoreControl bit */
  122. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  123. /* Force backplane reset */
  124. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  125. /* Force no backplane reset */
  126. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  127. /* direct(mapped) cis space */
  128. /* MAPPED common CIS address */
  129. #define SBSDIO_CIS_BASE_COMMON 0x1000
  130. /* maximum bytes in one CIS */
  131. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  132. /* cis offset addr is < 17 bits */
  133. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  134. /* manfid tuple length, include tuple, link bytes */
  135. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  136. #define SD_REG(field) \
  137. (offsetof(struct sdpcmd_regs, field))
  138. /* SDIO function 1 register CHIPCLKCSR */
  139. /* Force ALP request to backplane */
  140. #define SBSDIO_FORCE_ALP 0x01
  141. /* Force HT request to backplane */
  142. #define SBSDIO_FORCE_HT 0x02
  143. /* Force ILP request to backplane */
  144. #define SBSDIO_FORCE_ILP 0x04
  145. /* Make ALP ready (power up xtal) */
  146. #define SBSDIO_ALP_AVAIL_REQ 0x08
  147. /* Make HT ready (power up PLL) */
  148. #define SBSDIO_HT_AVAIL_REQ 0x10
  149. /* Squelch clock requests from HW */
  150. #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
  151. /* Status: ALP is ready */
  152. #define SBSDIO_ALP_AVAIL 0x40
  153. /* Status: HT is ready */
  154. #define SBSDIO_HT_AVAIL 0x80
  155. #define SBSDIO_CSR_MASK 0x1F
  156. #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
  157. #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
  158. #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
  159. #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
  160. #define SBSDIO_CLKAV(regval, alponly) \
  161. (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
  162. /* intstatus */
  163. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  164. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  165. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  166. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  167. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  168. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  169. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  170. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  171. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  172. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  173. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  174. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  175. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  176. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  177. #define I_PC (1 << 10) /* descriptor error */
  178. #define I_PD (1 << 11) /* data error */
  179. #define I_DE (1 << 12) /* Descriptor protocol Error */
  180. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  181. #define I_RO (1 << 14) /* Receive fifo Overflow */
  182. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  183. #define I_RI (1 << 16) /* Receive Interrupt */
  184. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  185. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  186. #define I_XI (1 << 24) /* Transmit Interrupt */
  187. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  188. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  189. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  190. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  191. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  192. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  193. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  194. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  195. #define I_DMA (I_RI | I_XI | I_ERRORS)
  196. /* corecontrol */
  197. #define CC_CISRDY (1 << 0) /* CIS Ready */
  198. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  199. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  200. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  201. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  202. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  203. /* SDA_FRAMECTRL */
  204. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  205. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  206. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  207. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  208. /*
  209. * Software allocation of To SB Mailbox resources
  210. */
  211. /* tosbmailbox bits corresponding to intstatus bits */
  212. #define SMB_NAK (1 << 0) /* Frame NAK */
  213. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  214. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  215. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  216. /* tosbmailboxdata */
  217. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  218. /*
  219. * Software allocation of To Host Mailbox resources
  220. */
  221. /* intstatus bits */
  222. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  223. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  224. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  225. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  226. /* tohostmailboxdata */
  227. #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */
  228. #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */
  229. #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */
  230. #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */
  231. #define HMB_DATA_FWHALT 0x0010 /* firmware halted */
  232. #define HMB_DATA_FCDATA_MASK 0xff000000
  233. #define HMB_DATA_FCDATA_SHIFT 24
  234. #define HMB_DATA_VERSION_MASK 0x00ff0000
  235. #define HMB_DATA_VERSION_SHIFT 16
  236. /*
  237. * Software-defined protocol header
  238. */
  239. /* Current protocol version */
  240. #define SDPCM_PROT_VERSION 4
  241. /*
  242. * Shared structure between dongle and the host.
  243. * The structure contains pointers to trap or assert information.
  244. */
  245. #define SDPCM_SHARED_VERSION 0x0003
  246. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  247. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  248. #define SDPCM_SHARED_ASSERT 0x0200
  249. #define SDPCM_SHARED_TRAP 0x0400
  250. /* Space for header read, limit for data packets */
  251. #define MAX_HDR_READ (1 << 6)
  252. #define MAX_RX_DATASZ 2048
  253. /* Bump up limit on waiting for HT to account for first startup;
  254. * if the image is doing a CRC calculation before programming the PMU
  255. * for HT availability, it could take a couple hundred ms more, so
  256. * max out at a 1 second (1000000us).
  257. */
  258. #undef PMU_MAX_TRANSITION_DLY
  259. #define PMU_MAX_TRANSITION_DLY 1000000
  260. /* Value for ChipClockCSR during initial setup */
  261. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  262. SBSDIO_ALP_AVAIL_REQ)
  263. /* Flags for SDH calls */
  264. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  265. #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
  266. * when idle
  267. */
  268. #define BRCMF_IDLE_INTERVAL 1
  269. #define KSO_WAIT_US 50
  270. #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
  271. #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
  272. /*
  273. * Conversion of 802.1D priority to precedence level
  274. */
  275. static uint prio2prec(u32 prio)
  276. {
  277. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  278. (prio^2) : prio;
  279. }
  280. #ifdef DEBUG
  281. /* Device console log buffer state */
  282. struct brcmf_console {
  283. uint count; /* Poll interval msec counter */
  284. uint log_addr; /* Log struct address (fixed) */
  285. struct rte_log_le log_le; /* Log struct (host copy) */
  286. uint bufsize; /* Size of log buffer */
  287. u8 *buf; /* Log buffer (host copy) */
  288. uint last; /* Last buffer read index */
  289. };
  290. struct brcmf_trap_info {
  291. __le32 type;
  292. __le32 epc;
  293. __le32 cpsr;
  294. __le32 spsr;
  295. __le32 r0; /* a1 */
  296. __le32 r1; /* a2 */
  297. __le32 r2; /* a3 */
  298. __le32 r3; /* a4 */
  299. __le32 r4; /* v1 */
  300. __le32 r5; /* v2 */
  301. __le32 r6; /* v3 */
  302. __le32 r7; /* v4 */
  303. __le32 r8; /* v5 */
  304. __le32 r9; /* sb/v6 */
  305. __le32 r10; /* sl/v7 */
  306. __le32 r11; /* fp/v8 */
  307. __le32 r12; /* ip */
  308. __le32 r13; /* sp */
  309. __le32 r14; /* lr */
  310. __le32 pc; /* r15 */
  311. };
  312. #endif /* DEBUG */
  313. struct sdpcm_shared {
  314. u32 flags;
  315. u32 trap_addr;
  316. u32 assert_exp_addr;
  317. u32 assert_file_addr;
  318. u32 assert_line;
  319. u32 console_addr; /* Address of struct rte_console */
  320. u32 msgtrace_addr;
  321. u8 tag[32];
  322. u32 brpt_addr;
  323. };
  324. struct sdpcm_shared_le {
  325. __le32 flags;
  326. __le32 trap_addr;
  327. __le32 assert_exp_addr;
  328. __le32 assert_file_addr;
  329. __le32 assert_line;
  330. __le32 console_addr; /* Address of struct rte_console */
  331. __le32 msgtrace_addr;
  332. u8 tag[32];
  333. __le32 brpt_addr;
  334. };
  335. /* dongle SDIO bus specific header info */
  336. struct brcmf_sdio_hdrinfo {
  337. u8 seq_num;
  338. u8 channel;
  339. u16 len;
  340. u16 len_left;
  341. u16 len_nxtfrm;
  342. u8 dat_offset;
  343. bool lastfrm;
  344. u16 tail_pad;
  345. };
  346. /*
  347. * hold counter variables
  348. */
  349. struct brcmf_sdio_count {
  350. uint intrcount; /* Count of device interrupt callbacks */
  351. uint lastintrs; /* Count as of last watchdog timer */
  352. uint pollcnt; /* Count of active polls */
  353. uint regfails; /* Count of R_REG failures */
  354. uint tx_sderrs; /* Count of tx attempts with sd errors */
  355. uint fcqueued; /* Tx packets that got queued */
  356. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  357. uint rx_toolong; /* Receive frames too long to receive */
  358. uint rxc_errors; /* SDIO errors when reading control frames */
  359. uint rx_hdrfail; /* SDIO errors on header reads */
  360. uint rx_badhdr; /* Bad received headers (roosync?) */
  361. uint rx_badseq; /* Mismatched rx sequence number */
  362. uint fc_rcvd; /* Number of flow-control events received */
  363. uint fc_xoff; /* Number which turned on flow-control */
  364. uint fc_xon; /* Number which turned off flow-control */
  365. uint rxglomfail; /* Failed deglom attempts */
  366. uint rxglomframes; /* Number of glom frames (superframes) */
  367. uint rxglompkts; /* Number of packets from glom frames */
  368. uint f2rxhdrs; /* Number of header reads */
  369. uint f2rxdata; /* Number of frame data reads */
  370. uint f2txdata; /* Number of f2 frame writes */
  371. uint f1regdata; /* Number of f1 register accesses */
  372. uint tickcnt; /* Number of watchdog been schedule */
  373. ulong tx_ctlerrs; /* Err of sending ctrl frames */
  374. ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
  375. ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
  376. ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
  377. ulong rx_readahead_cnt; /* packets where header read-ahead was used */
  378. };
  379. /* misc chip info needed by some of the routines */
  380. /* Private data for SDIO bus interaction */
  381. struct brcmf_sdio {
  382. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  383. struct brcmf_chip *ci; /* Chip info struct */
  384. struct brcmf_core *sdio_core; /* sdio core info struct */
  385. u32 hostintmask; /* Copy of Host Interrupt Mask */
  386. atomic_t intstatus; /* Intstatus bits (events) pending */
  387. atomic_t fcstate; /* State of dongle flow-control */
  388. uint blocksize; /* Block size of SDIO transfers */
  389. uint roundup; /* Max roundup limit */
  390. struct pktq txq; /* Queue length used for flow-control */
  391. u8 flowcontrol; /* per prio flow control bitmask */
  392. u8 tx_seq; /* Transmit sequence number (next) */
  393. u8 tx_max; /* Maximum transmit sequence allowed */
  394. u8 *hdrbuf; /* buffer for handling rx frame */
  395. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  396. u8 rx_seq; /* Receive sequence number (expected) */
  397. struct brcmf_sdio_hdrinfo cur_read;
  398. /* info of current read frame */
  399. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  400. bool rxpending; /* Data frame pending in dongle */
  401. uint rxbound; /* Rx frames to read before resched */
  402. uint txbound; /* Tx frames to send before resched */
  403. uint txminmax;
  404. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  405. struct sk_buff_head glom; /* Packet list for glommed superframe */
  406. u8 *rxbuf; /* Buffer for receiving control packets */
  407. uint rxblen; /* Allocated length of rxbuf */
  408. u8 *rxctl; /* Aligned pointer into rxbuf */
  409. u8 *rxctl_orig; /* pointer for freeing rxctl */
  410. uint rxlen; /* Length of valid data in buffer */
  411. spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
  412. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  413. bool intr; /* Use interrupts */
  414. bool poll; /* Use polling */
  415. atomic_t ipend; /* Device interrupt is pending */
  416. uint spurious; /* Count of spurious interrupts */
  417. uint pollrate; /* Ticks between device polls */
  418. uint polltick; /* Tick counter */
  419. #ifdef DEBUG
  420. uint console_interval;
  421. struct brcmf_console console; /* Console output polling support */
  422. uint console_addr; /* Console address from shared struct */
  423. #endif /* DEBUG */
  424. uint clkstate; /* State of sd and backplane clock(s) */
  425. s32 idletime; /* Control for activity timeout */
  426. s32 idlecount; /* Activity timeout counter */
  427. s32 idleclock; /* How to set bus driver when idle */
  428. bool rxflow_mode; /* Rx flow control mode */
  429. bool rxflow; /* Is rx flow control on */
  430. bool alp_only; /* Don't use HT clock (ALP only) */
  431. u8 *ctrl_frame_buf;
  432. u16 ctrl_frame_len;
  433. bool ctrl_frame_stat;
  434. int ctrl_frame_err;
  435. spinlock_t txq_lock; /* protect bus->txq */
  436. wait_queue_head_t ctrl_wait;
  437. wait_queue_head_t dcmd_resp_wait;
  438. struct timer_list timer;
  439. struct completion watchdog_wait;
  440. struct task_struct *watchdog_tsk;
  441. bool wd_active;
  442. struct workqueue_struct *brcmf_wq;
  443. struct work_struct datawork;
  444. bool dpc_triggered;
  445. bool dpc_running;
  446. bool txoff; /* Transmit flow-controlled */
  447. struct brcmf_sdio_count sdcnt;
  448. bool sr_enabled; /* SaveRestore enabled */
  449. bool sleeping;
  450. u8 tx_hdrlen; /* sdio bus header length for tx packet */
  451. bool txglom; /* host tx glomming enable flag */
  452. u16 head_align; /* buffer pointer alignment */
  453. u16 sgentry_align; /* scatter-gather buffer alignment */
  454. };
  455. /* clkstate */
  456. #define CLK_NONE 0
  457. #define CLK_SDONLY 1
  458. #define CLK_PENDING 2
  459. #define CLK_AVAIL 3
  460. #ifdef DEBUG
  461. static int qcount[NUMPRIO];
  462. #endif /* DEBUG */
  463. #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  464. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  465. /* Limit on rounding up frames */
  466. static const uint max_roundup = 512;
  467. #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
  468. #define ALIGNMENT 8
  469. #else
  470. #define ALIGNMENT 4
  471. #endif
  472. enum brcmf_sdio_frmtype {
  473. BRCMF_SDIO_FT_NORMAL,
  474. BRCMF_SDIO_FT_SUPER,
  475. BRCMF_SDIO_FT_SUB,
  476. };
  477. #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
  478. /* SDIO Pad drive strength to select value mappings */
  479. struct sdiod_drive_str {
  480. u8 strength; /* Pad Drive Strength in mA */
  481. u8 sel; /* Chip-specific select value */
  482. };
  483. /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
  484. static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
  485. {32, 0x6},
  486. {26, 0x7},
  487. {22, 0x4},
  488. {16, 0x5},
  489. {12, 0x2},
  490. {8, 0x3},
  491. {4, 0x0},
  492. {0, 0x1}
  493. };
  494. /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
  495. static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
  496. {6, 0x7},
  497. {5, 0x6},
  498. {4, 0x5},
  499. {3, 0x4},
  500. {2, 0x2},
  501. {1, 0x1},
  502. {0, 0x0}
  503. };
  504. /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
  505. static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
  506. {3, 0x3},
  507. {2, 0x2},
  508. {1, 0x1},
  509. {0, 0x0} };
  510. /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
  511. static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
  512. {16, 0x7},
  513. {12, 0x5},
  514. {8, 0x3},
  515. {4, 0x1}
  516. };
  517. BRCMF_FW_DEF(43143, "brcmfmac43143-sdio");
  518. BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio");
  519. BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio");
  520. BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio");
  521. BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
  522. BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
  523. BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
  524. BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
  525. BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
  526. BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
  527. BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
  528. BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
  529. /* Note the names are not postfixed with a1 for backward compatibility */
  530. BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio");
  531. BRCMF_FW_DEF(43455, "brcmfmac43455-sdio");
  532. BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
  533. BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
  534. BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
  535. static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
  536. BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
  537. BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
  538. BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
  539. BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
  540. BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
  541. BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
  542. BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
  543. BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
  544. BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
  545. BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
  546. BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
  547. BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
  548. BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
  549. BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1),
  550. BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
  551. BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
  552. BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  553. BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373)
  554. };
  555. static void pkt_align(struct sk_buff *p, int len, int align)
  556. {
  557. uint datalign;
  558. datalign = (unsigned long)(p->data);
  559. datalign = roundup(datalign, (align)) - datalign;
  560. if (datalign)
  561. skb_pull(p, datalign);
  562. __skb_trim(p, len);
  563. }
  564. /* To check if there's window offered */
  565. static bool data_ok(struct brcmf_sdio *bus)
  566. {
  567. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  568. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  569. }
  570. static int
  571. brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
  572. {
  573. u8 wr_val = 0, rd_val, cmp_val, bmask;
  574. int err = 0;
  575. int err_cnt = 0;
  576. int try_cnt = 0;
  577. brcmf_dbg(TRACE, "Enter: on=%d\n", on);
  578. wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
  579. /* 1st KSO write goes to AOS wake up core if device is asleep */
  580. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
  581. if (on) {
  582. /* device WAKEUP through KSO:
  583. * write bit 0 & read back until
  584. * both bits 0 (kso bit) & 1 (dev on status) are set
  585. */
  586. cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
  587. SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
  588. bmask = cmp_val;
  589. usleep_range(2000, 3000);
  590. } else {
  591. /* Put device to sleep, turn off KSO */
  592. cmp_val = 0;
  593. /* only check for bit0, bit1(dev on status) may not
  594. * get cleared right away
  595. */
  596. bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
  597. }
  598. do {
  599. /* reliable KSO bit set/clr:
  600. * the sdiod sleep write access is synced to PMU 32khz clk
  601. * just one write attempt may fail,
  602. * read it back until it matches written value
  603. */
  604. rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  605. &err);
  606. if (!err) {
  607. if ((rd_val & bmask) == cmp_val)
  608. break;
  609. err_cnt = 0;
  610. }
  611. /* bail out upon subsequent access errors */
  612. if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
  613. break;
  614. udelay(KSO_WAIT_US);
  615. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val,
  616. &err);
  617. } while (try_cnt++ < MAX_KSO_ATTEMPTS);
  618. if (try_cnt > 2)
  619. brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
  620. rd_val, err);
  621. if (try_cnt > MAX_KSO_ATTEMPTS)
  622. brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
  623. return err;
  624. }
  625. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  626. /* Turn backplane clock on or off */
  627. static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
  628. {
  629. int err;
  630. u8 clkctl, clkreq, devctl;
  631. unsigned long timeout;
  632. brcmf_dbg(SDIO, "Enter\n");
  633. clkctl = 0;
  634. if (bus->sr_enabled) {
  635. bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
  636. return 0;
  637. }
  638. if (on) {
  639. /* Request HT Avail */
  640. clkreq =
  641. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  642. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  643. clkreq, &err);
  644. if (err) {
  645. brcmf_err("HT Avail request error: %d\n", err);
  646. return -EBADE;
  647. }
  648. /* Check current status */
  649. clkctl = brcmf_sdiod_readb(bus->sdiodev,
  650. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  651. if (err) {
  652. brcmf_err("HT Avail read error: %d\n", err);
  653. return -EBADE;
  654. }
  655. /* Go to pending and await interrupt if appropriate */
  656. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  657. /* Allow only clock-available interrupt */
  658. devctl = brcmf_sdiod_readb(bus->sdiodev,
  659. SBSDIO_DEVICE_CTL, &err);
  660. if (err) {
  661. brcmf_err("Devctl error setting CA: %d\n", err);
  662. return -EBADE;
  663. }
  664. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  665. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  666. devctl, &err);
  667. brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
  668. bus->clkstate = CLK_PENDING;
  669. return 0;
  670. } else if (bus->clkstate == CLK_PENDING) {
  671. /* Cancel CA-only interrupt filter */
  672. devctl = brcmf_sdiod_readb(bus->sdiodev,
  673. SBSDIO_DEVICE_CTL, &err);
  674. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  675. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  676. devctl, &err);
  677. }
  678. /* Otherwise, wait here (polling) for HT Avail */
  679. timeout = jiffies +
  680. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  681. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  682. clkctl = brcmf_sdiod_readb(bus->sdiodev,
  683. SBSDIO_FUNC1_CHIPCLKCSR,
  684. &err);
  685. if (time_after(jiffies, timeout))
  686. break;
  687. else
  688. usleep_range(5000, 10000);
  689. }
  690. if (err) {
  691. brcmf_err("HT Avail request error: %d\n", err);
  692. return -EBADE;
  693. }
  694. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  695. brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
  696. PMU_MAX_TRANSITION_DLY, clkctl);
  697. return -EBADE;
  698. }
  699. /* Mark clock available */
  700. bus->clkstate = CLK_AVAIL;
  701. brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
  702. #if defined(DEBUG)
  703. if (!bus->alp_only) {
  704. if (SBSDIO_ALPONLY(clkctl))
  705. brcmf_err("HT Clock should be on\n");
  706. }
  707. #endif /* defined (DEBUG) */
  708. } else {
  709. clkreq = 0;
  710. if (bus->clkstate == CLK_PENDING) {
  711. /* Cancel CA-only interrupt filter */
  712. devctl = brcmf_sdiod_readb(bus->sdiodev,
  713. SBSDIO_DEVICE_CTL, &err);
  714. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  715. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  716. devctl, &err);
  717. }
  718. bus->clkstate = CLK_SDONLY;
  719. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  720. clkreq, &err);
  721. brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
  722. if (err) {
  723. brcmf_err("Failed access turning clock off: %d\n",
  724. err);
  725. return -EBADE;
  726. }
  727. }
  728. return 0;
  729. }
  730. /* Change idle/active SD state */
  731. static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
  732. {
  733. brcmf_dbg(SDIO, "Enter\n");
  734. if (on)
  735. bus->clkstate = CLK_SDONLY;
  736. else
  737. bus->clkstate = CLK_NONE;
  738. return 0;
  739. }
  740. /* Transition SD and backplane clock readiness */
  741. static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
  742. {
  743. #ifdef DEBUG
  744. uint oldstate = bus->clkstate;
  745. #endif /* DEBUG */
  746. brcmf_dbg(SDIO, "Enter\n");
  747. /* Early exit if we're already there */
  748. if (bus->clkstate == target)
  749. return 0;
  750. switch (target) {
  751. case CLK_AVAIL:
  752. /* Make sure SD clock is available */
  753. if (bus->clkstate == CLK_NONE)
  754. brcmf_sdio_sdclk(bus, true);
  755. /* Now request HT Avail on the backplane */
  756. brcmf_sdio_htclk(bus, true, pendok);
  757. break;
  758. case CLK_SDONLY:
  759. /* Remove HT request, or bring up SD clock */
  760. if (bus->clkstate == CLK_NONE)
  761. brcmf_sdio_sdclk(bus, true);
  762. else if (bus->clkstate == CLK_AVAIL)
  763. brcmf_sdio_htclk(bus, false, false);
  764. else
  765. brcmf_err("request for %d -> %d\n",
  766. bus->clkstate, target);
  767. break;
  768. case CLK_NONE:
  769. /* Make sure to remove HT request */
  770. if (bus->clkstate == CLK_AVAIL)
  771. brcmf_sdio_htclk(bus, false, false);
  772. /* Now remove the SD clock */
  773. brcmf_sdio_sdclk(bus, false);
  774. break;
  775. }
  776. #ifdef DEBUG
  777. brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
  778. #endif /* DEBUG */
  779. return 0;
  780. }
  781. static int
  782. brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
  783. {
  784. int err = 0;
  785. u8 clkcsr;
  786. brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
  787. (sleep ? "SLEEP" : "WAKE"),
  788. (bus->sleeping ? "SLEEP" : "WAKE"));
  789. /* If SR is enabled control bus state with KSO */
  790. if (bus->sr_enabled) {
  791. /* Done if we're already in the requested state */
  792. if (sleep == bus->sleeping)
  793. goto end;
  794. /* Going to sleep */
  795. if (sleep) {
  796. clkcsr = brcmf_sdiod_readb(bus->sdiodev,
  797. SBSDIO_FUNC1_CHIPCLKCSR,
  798. &err);
  799. if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
  800. brcmf_dbg(SDIO, "no clock, set ALP\n");
  801. brcmf_sdiod_writeb(bus->sdiodev,
  802. SBSDIO_FUNC1_CHIPCLKCSR,
  803. SBSDIO_ALP_AVAIL_REQ, &err);
  804. }
  805. err = brcmf_sdio_kso_control(bus, false);
  806. } else {
  807. err = brcmf_sdio_kso_control(bus, true);
  808. }
  809. if (err) {
  810. brcmf_err("error while changing bus sleep state %d\n",
  811. err);
  812. goto done;
  813. }
  814. }
  815. end:
  816. /* control clocks */
  817. if (sleep) {
  818. if (!bus->sr_enabled)
  819. brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
  820. } else {
  821. brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
  822. brcmf_sdio_wd_timer(bus, true);
  823. }
  824. bus->sleeping = sleep;
  825. brcmf_dbg(SDIO, "new state %s\n",
  826. (sleep ? "SLEEP" : "WAKE"));
  827. done:
  828. brcmf_dbg(SDIO, "Exit: err=%d\n", err);
  829. return err;
  830. }
  831. #ifdef DEBUG
  832. static inline bool brcmf_sdio_valid_shared_address(u32 addr)
  833. {
  834. return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
  835. }
  836. static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
  837. struct sdpcm_shared *sh)
  838. {
  839. u32 addr = 0;
  840. int rv;
  841. u32 shaddr = 0;
  842. struct sdpcm_shared_le sh_le;
  843. __le32 addr_le;
  844. sdio_claim_host(bus->sdiodev->func1);
  845. brcmf_sdio_bus_sleep(bus, false, false);
  846. /*
  847. * Read last word in socram to determine
  848. * address of sdpcm_shared structure
  849. */
  850. shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
  851. if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
  852. shaddr -= bus->ci->srsize;
  853. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
  854. (u8 *)&addr_le, 4);
  855. if (rv < 0)
  856. goto fail;
  857. /*
  858. * Check if addr is valid.
  859. * NVRAM length at the end of memory should have been overwritten.
  860. */
  861. addr = le32_to_cpu(addr_le);
  862. if (!brcmf_sdio_valid_shared_address(addr)) {
  863. brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
  864. rv = -EINVAL;
  865. goto fail;
  866. }
  867. brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
  868. /* Read hndrte_shared structure */
  869. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
  870. sizeof(struct sdpcm_shared_le));
  871. if (rv < 0)
  872. goto fail;
  873. sdio_release_host(bus->sdiodev->func1);
  874. /* Endianness */
  875. sh->flags = le32_to_cpu(sh_le.flags);
  876. sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
  877. sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
  878. sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
  879. sh->assert_line = le32_to_cpu(sh_le.assert_line);
  880. sh->console_addr = le32_to_cpu(sh_le.console_addr);
  881. sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
  882. if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
  883. brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
  884. SDPCM_SHARED_VERSION,
  885. sh->flags & SDPCM_SHARED_VERSION_MASK);
  886. return -EPROTO;
  887. }
  888. return 0;
  889. fail:
  890. brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
  891. rv, addr);
  892. sdio_release_host(bus->sdiodev->func1);
  893. return rv;
  894. }
  895. static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
  896. {
  897. struct sdpcm_shared sh;
  898. if (brcmf_sdio_readshared(bus, &sh) == 0)
  899. bus->console_addr = sh.console_addr;
  900. }
  901. #else
  902. static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
  903. {
  904. }
  905. #endif /* DEBUG */
  906. static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
  907. {
  908. struct brcmf_sdio_dev *sdiod = bus->sdiodev;
  909. struct brcmf_core *core = bus->sdio_core;
  910. u32 intstatus = 0;
  911. u32 hmb_data;
  912. u8 fcbits;
  913. int ret;
  914. brcmf_dbg(SDIO, "Enter\n");
  915. /* Read mailbox data and ack that we did so */
  916. hmb_data = brcmf_sdiod_readl(sdiod,
  917. core->base + SD_REG(tohostmailboxdata),
  918. &ret);
  919. if (!ret)
  920. brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
  921. SMB_INT_ACK, &ret);
  922. bus->sdcnt.f1regdata += 2;
  923. /* dongle indicates the firmware has halted/crashed */
  924. if (hmb_data & HMB_DATA_FWHALT)
  925. brcmf_err("mailbox indicates firmware halted\n");
  926. /* Dongle recomposed rx frames, accept them again */
  927. if (hmb_data & HMB_DATA_NAKHANDLED) {
  928. brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
  929. bus->rx_seq);
  930. if (!bus->rxskip)
  931. brcmf_err("unexpected NAKHANDLED!\n");
  932. bus->rxskip = false;
  933. intstatus |= I_HMB_FRAME_IND;
  934. }
  935. /*
  936. * DEVREADY does not occur with gSPI.
  937. */
  938. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  939. bus->sdpcm_ver =
  940. (hmb_data & HMB_DATA_VERSION_MASK) >>
  941. HMB_DATA_VERSION_SHIFT;
  942. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  943. brcmf_err("Version mismatch, dongle reports %d, "
  944. "expecting %d\n",
  945. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  946. else
  947. brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
  948. bus->sdpcm_ver);
  949. /*
  950. * Retrieve console state address now that firmware should have
  951. * updated it.
  952. */
  953. brcmf_sdio_get_console_addr(bus);
  954. }
  955. /*
  956. * Flow Control has been moved into the RX headers and this out of band
  957. * method isn't used any more.
  958. * remaining backward compatible with older dongles.
  959. */
  960. if (hmb_data & HMB_DATA_FC) {
  961. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  962. HMB_DATA_FCDATA_SHIFT;
  963. if (fcbits & ~bus->flowcontrol)
  964. bus->sdcnt.fc_xoff++;
  965. if (bus->flowcontrol & ~fcbits)
  966. bus->sdcnt.fc_xon++;
  967. bus->sdcnt.fc_rcvd++;
  968. bus->flowcontrol = fcbits;
  969. }
  970. /* Shouldn't be any others */
  971. if (hmb_data & ~(HMB_DATA_DEVREADY |
  972. HMB_DATA_NAKHANDLED |
  973. HMB_DATA_FC |
  974. HMB_DATA_FWREADY |
  975. HMB_DATA_FWHALT |
  976. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  977. brcmf_err("Unknown mailbox data content: 0x%02x\n",
  978. hmb_data);
  979. return intstatus;
  980. }
  981. static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
  982. {
  983. struct brcmf_sdio_dev *sdiod = bus->sdiodev;
  984. struct brcmf_core *core = bus->sdio_core;
  985. uint retries = 0;
  986. u16 lastrbc;
  987. u8 hi, lo;
  988. int err;
  989. brcmf_err("%sterminate frame%s\n",
  990. abort ? "abort command, " : "",
  991. rtx ? ", send NAK" : "");
  992. if (abort)
  993. brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2);
  994. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
  995. &err);
  996. bus->sdcnt.f1regdata++;
  997. /* Wait until the packet has been flushed (device/FIFO stable) */
  998. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  999. hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI,
  1000. &err);
  1001. lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO,
  1002. &err);
  1003. bus->sdcnt.f1regdata += 2;
  1004. if ((hi == 0) && (lo == 0))
  1005. break;
  1006. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  1007. brcmf_err("count growing: last 0x%04x now 0x%04x\n",
  1008. lastrbc, (hi << 8) + lo);
  1009. }
  1010. lastrbc = (hi << 8) + lo;
  1011. }
  1012. if (!retries)
  1013. brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
  1014. else
  1015. brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
  1016. if (rtx) {
  1017. bus->sdcnt.rxrtx++;
  1018. brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
  1019. SMB_NAK, &err);
  1020. bus->sdcnt.f1regdata++;
  1021. if (err == 0)
  1022. bus->rxskip = true;
  1023. }
  1024. /* Clear partial in any case */
  1025. bus->cur_read.len = 0;
  1026. }
  1027. static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
  1028. {
  1029. struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
  1030. u8 i, hi, lo;
  1031. /* On failure, abort the command and terminate the frame */
  1032. brcmf_err("sdio error, abort command and terminate frame\n");
  1033. bus->sdcnt.tx_sderrs++;
  1034. brcmf_sdiod_abort(sdiodev, sdiodev->func2);
  1035. brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
  1036. bus->sdcnt.f1regdata++;
  1037. for (i = 0; i < 3; i++) {
  1038. hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
  1039. lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
  1040. bus->sdcnt.f1regdata += 2;
  1041. if ((hi == 0) && (lo == 0))
  1042. break;
  1043. }
  1044. }
  1045. /* return total length of buffer chain */
  1046. static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
  1047. {
  1048. struct sk_buff *p;
  1049. uint total;
  1050. total = 0;
  1051. skb_queue_walk(&bus->glom, p)
  1052. total += p->len;
  1053. return total;
  1054. }
  1055. static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
  1056. {
  1057. struct sk_buff *cur, *next;
  1058. skb_queue_walk_safe(&bus->glom, cur, next) {
  1059. skb_unlink(cur, &bus->glom);
  1060. brcmu_pkt_buf_free_skb(cur);
  1061. }
  1062. }
  1063. /**
  1064. * brcmfmac sdio bus specific header
  1065. * This is the lowest layer header wrapped on the packets transmitted between
  1066. * host and WiFi dongle which contains information needed for SDIO core and
  1067. * firmware
  1068. *
  1069. * It consists of 3 parts: hardware header, hardware extension header and
  1070. * software header
  1071. * hardware header (frame tag) - 4 bytes
  1072. * Byte 0~1: Frame length
  1073. * Byte 2~3: Checksum, bit-wise inverse of frame length
  1074. * hardware extension header - 8 bytes
  1075. * Tx glom mode only, N/A for Rx or normal Tx
  1076. * Byte 0~1: Packet length excluding hw frame tag
  1077. * Byte 2: Reserved
  1078. * Byte 3: Frame flags, bit 0: last frame indication
  1079. * Byte 4~5: Reserved
  1080. * Byte 6~7: Tail padding length
  1081. * software header - 8 bytes
  1082. * Byte 0: Rx/Tx sequence number
  1083. * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
  1084. * Byte 2: Length of next data frame, reserved for Tx
  1085. * Byte 3: Data offset
  1086. * Byte 4: Flow control bits, reserved for Tx
  1087. * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
  1088. * Byte 6~7: Reserved
  1089. */
  1090. #define SDPCM_HWHDR_LEN 4
  1091. #define SDPCM_HWEXT_LEN 8
  1092. #define SDPCM_SWHDR_LEN 8
  1093. #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
  1094. /* software header */
  1095. #define SDPCM_SEQ_MASK 0x000000ff
  1096. #define SDPCM_SEQ_WRAP 256
  1097. #define SDPCM_CHANNEL_MASK 0x00000f00
  1098. #define SDPCM_CHANNEL_SHIFT 8
  1099. #define SDPCM_CONTROL_CHANNEL 0 /* Control */
  1100. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
  1101. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
  1102. #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
  1103. #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
  1104. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  1105. #define SDPCM_NEXTLEN_MASK 0x00ff0000
  1106. #define SDPCM_NEXTLEN_SHIFT 16
  1107. #define SDPCM_DOFFSET_MASK 0xff000000
  1108. #define SDPCM_DOFFSET_SHIFT 24
  1109. #define SDPCM_FCMASK_MASK 0x000000ff
  1110. #define SDPCM_WINDOW_MASK 0x0000ff00
  1111. #define SDPCM_WINDOW_SHIFT 8
  1112. static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
  1113. {
  1114. u32 hdrvalue;
  1115. hdrvalue = *(u32 *)swheader;
  1116. return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
  1117. }
  1118. static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
  1119. {
  1120. u32 hdrvalue;
  1121. u8 ret;
  1122. hdrvalue = *(u32 *)swheader;
  1123. ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
  1124. return (ret == SDPCM_EVENT_CHANNEL);
  1125. }
  1126. static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
  1127. struct brcmf_sdio_hdrinfo *rd,
  1128. enum brcmf_sdio_frmtype type)
  1129. {
  1130. u16 len, checksum;
  1131. u8 rx_seq, fc, tx_seq_max;
  1132. u32 swheader;
  1133. trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
  1134. /* hw header */
  1135. len = get_unaligned_le16(header);
  1136. checksum = get_unaligned_le16(header + sizeof(u16));
  1137. /* All zero means no more to read */
  1138. if (!(len | checksum)) {
  1139. bus->rxpending = false;
  1140. return -ENODATA;
  1141. }
  1142. if ((u16)(~(len ^ checksum))) {
  1143. brcmf_err("HW header checksum error\n");
  1144. bus->sdcnt.rx_badhdr++;
  1145. brcmf_sdio_rxfail(bus, false, false);
  1146. return -EIO;
  1147. }
  1148. if (len < SDPCM_HDRLEN) {
  1149. brcmf_err("HW header length error\n");
  1150. return -EPROTO;
  1151. }
  1152. if (type == BRCMF_SDIO_FT_SUPER &&
  1153. (roundup(len, bus->blocksize) != rd->len)) {
  1154. brcmf_err("HW superframe header length error\n");
  1155. return -EPROTO;
  1156. }
  1157. if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
  1158. brcmf_err("HW subframe header length error\n");
  1159. return -EPROTO;
  1160. }
  1161. rd->len = len;
  1162. /* software header */
  1163. header += SDPCM_HWHDR_LEN;
  1164. swheader = le32_to_cpu(*(__le32 *)header);
  1165. if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
  1166. brcmf_err("Glom descriptor found in superframe head\n");
  1167. rd->len = 0;
  1168. return -EINVAL;
  1169. }
  1170. rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
  1171. rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
  1172. if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
  1173. type != BRCMF_SDIO_FT_SUPER) {
  1174. brcmf_err("HW header length too long\n");
  1175. bus->sdcnt.rx_toolong++;
  1176. brcmf_sdio_rxfail(bus, false, false);
  1177. rd->len = 0;
  1178. return -EPROTO;
  1179. }
  1180. if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
  1181. brcmf_err("Wrong channel for superframe\n");
  1182. rd->len = 0;
  1183. return -EINVAL;
  1184. }
  1185. if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
  1186. rd->channel != SDPCM_EVENT_CHANNEL) {
  1187. brcmf_err("Wrong channel for subframe\n");
  1188. rd->len = 0;
  1189. return -EINVAL;
  1190. }
  1191. rd->dat_offset = brcmf_sdio_getdatoffset(header);
  1192. if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
  1193. brcmf_err("seq %d: bad data offset\n", rx_seq);
  1194. bus->sdcnt.rx_badhdr++;
  1195. brcmf_sdio_rxfail(bus, false, false);
  1196. rd->len = 0;
  1197. return -ENXIO;
  1198. }
  1199. if (rd->seq_num != rx_seq) {
  1200. brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
  1201. bus->sdcnt.rx_badseq++;
  1202. rd->seq_num = rx_seq;
  1203. }
  1204. /* no need to check the reset for subframe */
  1205. if (type == BRCMF_SDIO_FT_SUB)
  1206. return 0;
  1207. rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
  1208. if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
  1209. /* only warm for NON glom packet */
  1210. if (rd->channel != SDPCM_GLOM_CHANNEL)
  1211. brcmf_err("seq %d: next length error\n", rx_seq);
  1212. rd->len_nxtfrm = 0;
  1213. }
  1214. swheader = le32_to_cpu(*(__le32 *)(header + 4));
  1215. fc = swheader & SDPCM_FCMASK_MASK;
  1216. if (bus->flowcontrol != fc) {
  1217. if (~bus->flowcontrol & fc)
  1218. bus->sdcnt.fc_xoff++;
  1219. if (bus->flowcontrol & ~fc)
  1220. bus->sdcnt.fc_xon++;
  1221. bus->sdcnt.fc_rcvd++;
  1222. bus->flowcontrol = fc;
  1223. }
  1224. tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
  1225. if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
  1226. brcmf_err("seq %d: max tx seq number error\n", rx_seq);
  1227. tx_seq_max = bus->tx_seq + 2;
  1228. }
  1229. bus->tx_max = tx_seq_max;
  1230. return 0;
  1231. }
  1232. static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
  1233. {
  1234. *(__le16 *)header = cpu_to_le16(frm_length);
  1235. *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
  1236. }
  1237. static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
  1238. struct brcmf_sdio_hdrinfo *hd_info)
  1239. {
  1240. u32 hdrval;
  1241. u8 hdr_offset;
  1242. brcmf_sdio_update_hwhdr(header, hd_info->len);
  1243. hdr_offset = SDPCM_HWHDR_LEN;
  1244. if (bus->txglom) {
  1245. hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
  1246. *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
  1247. hdrval = (u16)hd_info->tail_pad << 16;
  1248. *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
  1249. hdr_offset += SDPCM_HWEXT_LEN;
  1250. }
  1251. hdrval = hd_info->seq_num;
  1252. hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
  1253. SDPCM_CHANNEL_MASK;
  1254. hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
  1255. SDPCM_DOFFSET_MASK;
  1256. *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
  1257. *(((__le32 *)(header + hdr_offset)) + 1) = 0;
  1258. trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
  1259. }
  1260. static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
  1261. {
  1262. u16 dlen, totlen;
  1263. u8 *dptr, num = 0;
  1264. u16 sublen;
  1265. struct sk_buff *pfirst, *pnext;
  1266. int errcode;
  1267. u8 doff, sfdoff;
  1268. struct brcmf_sdio_hdrinfo rd_new;
  1269. /* If packets, issue read(s) and send up packet chain */
  1270. /* Return sequence numbers consumed? */
  1271. brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
  1272. bus->glomd, skb_peek(&bus->glom));
  1273. /* If there's a descriptor, generate the packet chain */
  1274. if (bus->glomd) {
  1275. pfirst = pnext = NULL;
  1276. dlen = (u16) (bus->glomd->len);
  1277. dptr = bus->glomd->data;
  1278. if (!dlen || (dlen & 1)) {
  1279. brcmf_err("bad glomd len(%d), ignore descriptor\n",
  1280. dlen);
  1281. dlen = 0;
  1282. }
  1283. for (totlen = num = 0; dlen; num++) {
  1284. /* Get (and move past) next length */
  1285. sublen = get_unaligned_le16(dptr);
  1286. dlen -= sizeof(u16);
  1287. dptr += sizeof(u16);
  1288. if ((sublen < SDPCM_HDRLEN) ||
  1289. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  1290. brcmf_err("descriptor len %d bad: %d\n",
  1291. num, sublen);
  1292. pnext = NULL;
  1293. break;
  1294. }
  1295. if (sublen % bus->sgentry_align) {
  1296. brcmf_err("sublen %d not multiple of %d\n",
  1297. sublen, bus->sgentry_align);
  1298. }
  1299. totlen += sublen;
  1300. /* For last frame, adjust read len so total
  1301. is a block multiple */
  1302. if (!dlen) {
  1303. sublen +=
  1304. (roundup(totlen, bus->blocksize) - totlen);
  1305. totlen = roundup(totlen, bus->blocksize);
  1306. }
  1307. /* Allocate/chain packet for next subframe */
  1308. pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
  1309. if (pnext == NULL) {
  1310. brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
  1311. num, sublen);
  1312. break;
  1313. }
  1314. skb_queue_tail(&bus->glom, pnext);
  1315. /* Adhere to start alignment requirements */
  1316. pkt_align(pnext, sublen, bus->sgentry_align);
  1317. }
  1318. /* If all allocations succeeded, save packet chain
  1319. in bus structure */
  1320. if (pnext) {
  1321. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  1322. totlen, num);
  1323. if (BRCMF_GLOM_ON() && bus->cur_read.len &&
  1324. totlen != bus->cur_read.len) {
  1325. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  1326. bus->cur_read.len, totlen, rxseq);
  1327. }
  1328. pfirst = pnext = NULL;
  1329. } else {
  1330. brcmf_sdio_free_glom(bus);
  1331. num = 0;
  1332. }
  1333. /* Done with descriptor packet */
  1334. brcmu_pkt_buf_free_skb(bus->glomd);
  1335. bus->glomd = NULL;
  1336. bus->cur_read.len = 0;
  1337. }
  1338. /* Ok -- either we just generated a packet chain,
  1339. or had one from before */
  1340. if (!skb_queue_empty(&bus->glom)) {
  1341. if (BRCMF_GLOM_ON()) {
  1342. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1343. skb_queue_walk(&bus->glom, pnext) {
  1344. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1345. pnext, (u8 *) (pnext->data),
  1346. pnext->len, pnext->len);
  1347. }
  1348. }
  1349. pfirst = skb_peek(&bus->glom);
  1350. dlen = (u16) brcmf_sdio_glom_len(bus);
  1351. /* Do an SDIO read for the superframe. Configurable iovar to
  1352. * read directly into the chained packet, or allocate a large
  1353. * packet and and copy into the chain.
  1354. */
  1355. sdio_claim_host(bus->sdiodev->func1);
  1356. errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
  1357. &bus->glom, dlen);
  1358. sdio_release_host(bus->sdiodev->func1);
  1359. bus->sdcnt.f2rxdata++;
  1360. /* On failure, kill the superframe */
  1361. if (errcode < 0) {
  1362. brcmf_err("glom read of %d bytes failed: %d\n",
  1363. dlen, errcode);
  1364. sdio_claim_host(bus->sdiodev->func1);
  1365. brcmf_sdio_rxfail(bus, true, false);
  1366. bus->sdcnt.rxglomfail++;
  1367. brcmf_sdio_free_glom(bus);
  1368. sdio_release_host(bus->sdiodev->func1);
  1369. return 0;
  1370. }
  1371. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1372. pfirst->data, min_t(int, pfirst->len, 48),
  1373. "SUPERFRAME:\n");
  1374. rd_new.seq_num = rxseq;
  1375. rd_new.len = dlen;
  1376. sdio_claim_host(bus->sdiodev->func1);
  1377. errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
  1378. BRCMF_SDIO_FT_SUPER);
  1379. sdio_release_host(bus->sdiodev->func1);
  1380. bus->cur_read.len = rd_new.len_nxtfrm << 4;
  1381. /* Remove superframe header, remember offset */
  1382. skb_pull(pfirst, rd_new.dat_offset);
  1383. sfdoff = rd_new.dat_offset;
  1384. num = 0;
  1385. /* Validate all the subframe headers */
  1386. skb_queue_walk(&bus->glom, pnext) {
  1387. /* leave when invalid subframe is found */
  1388. if (errcode)
  1389. break;
  1390. rd_new.len = pnext->len;
  1391. rd_new.seq_num = rxseq++;
  1392. sdio_claim_host(bus->sdiodev->func1);
  1393. errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
  1394. BRCMF_SDIO_FT_SUB);
  1395. sdio_release_host(bus->sdiodev->func1);
  1396. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1397. pnext->data, 32, "subframe:\n");
  1398. num++;
  1399. }
  1400. if (errcode) {
  1401. /* Terminate frame on error */
  1402. sdio_claim_host(bus->sdiodev->func1);
  1403. brcmf_sdio_rxfail(bus, true, false);
  1404. bus->sdcnt.rxglomfail++;
  1405. brcmf_sdio_free_glom(bus);
  1406. sdio_release_host(bus->sdiodev->func1);
  1407. bus->cur_read.len = 0;
  1408. return 0;
  1409. }
  1410. /* Basic SD framing looks ok - process each packet (header) */
  1411. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1412. dptr = (u8 *) (pfirst->data);
  1413. sublen = get_unaligned_le16(dptr);
  1414. doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
  1415. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
  1416. dptr, pfirst->len,
  1417. "Rx Subframe Data:\n");
  1418. __skb_trim(pfirst, sublen);
  1419. skb_pull(pfirst, doff);
  1420. if (pfirst->len == 0) {
  1421. skb_unlink(pfirst, &bus->glom);
  1422. brcmu_pkt_buf_free_skb(pfirst);
  1423. continue;
  1424. }
  1425. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1426. pfirst->data,
  1427. min_t(int, pfirst->len, 32),
  1428. "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1429. bus->glom.qlen, pfirst, pfirst->data,
  1430. pfirst->len, pfirst->next,
  1431. pfirst->prev);
  1432. skb_unlink(pfirst, &bus->glom);
  1433. if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
  1434. brcmf_rx_event(bus->sdiodev->dev, pfirst);
  1435. else
  1436. brcmf_rx_frame(bus->sdiodev->dev, pfirst,
  1437. false);
  1438. bus->sdcnt.rxglompkts++;
  1439. }
  1440. bus->sdcnt.rxglomframes++;
  1441. }
  1442. return num;
  1443. }
  1444. static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
  1445. bool *pending)
  1446. {
  1447. DECLARE_WAITQUEUE(wait, current);
  1448. int timeout = DCMD_RESP_TIMEOUT;
  1449. /* Wait until control frame is available */
  1450. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1451. set_current_state(TASK_INTERRUPTIBLE);
  1452. while (!(*condition) && (!signal_pending(current) && timeout))
  1453. timeout = schedule_timeout(timeout);
  1454. if (signal_pending(current))
  1455. *pending = true;
  1456. set_current_state(TASK_RUNNING);
  1457. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1458. return timeout;
  1459. }
  1460. static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
  1461. {
  1462. wake_up_interruptible(&bus->dcmd_resp_wait);
  1463. return 0;
  1464. }
  1465. static void
  1466. brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
  1467. {
  1468. uint rdlen, pad;
  1469. u8 *buf = NULL, *rbuf;
  1470. int sdret;
  1471. brcmf_dbg(SDIO, "Enter\n");
  1472. if (bus->rxblen)
  1473. buf = vzalloc(bus->rxblen);
  1474. if (!buf)
  1475. goto done;
  1476. rbuf = bus->rxbuf;
  1477. pad = ((unsigned long)rbuf % bus->head_align);
  1478. if (pad)
  1479. rbuf += (bus->head_align - pad);
  1480. /* Copy the already-read portion over */
  1481. memcpy(buf, hdr, BRCMF_FIRSTREAD);
  1482. if (len <= BRCMF_FIRSTREAD)
  1483. goto gotpkt;
  1484. /* Raise rdlen to next SDIO block to avoid tail command */
  1485. rdlen = len - BRCMF_FIRSTREAD;
  1486. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1487. pad = bus->blocksize - (rdlen % bus->blocksize);
  1488. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1489. ((len + pad) < bus->sdiodev->bus_if->maxctl))
  1490. rdlen += pad;
  1491. } else if (rdlen % bus->head_align) {
  1492. rdlen += bus->head_align - (rdlen % bus->head_align);
  1493. }
  1494. /* Drop if the read is too big or it exceeds our maximum */
  1495. if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
  1496. brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
  1497. rdlen, bus->sdiodev->bus_if->maxctl);
  1498. brcmf_sdio_rxfail(bus, false, false);
  1499. goto done;
  1500. }
  1501. if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
  1502. brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1503. len, len - doff, bus->sdiodev->bus_if->maxctl);
  1504. bus->sdcnt.rx_toolong++;
  1505. brcmf_sdio_rxfail(bus, false, false);
  1506. goto done;
  1507. }
  1508. /* Read remain of frame body */
  1509. sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
  1510. bus->sdcnt.f2rxdata++;
  1511. /* Control frame failures need retransmission */
  1512. if (sdret < 0) {
  1513. brcmf_err("read %d control bytes failed: %d\n",
  1514. rdlen, sdret);
  1515. bus->sdcnt.rxc_errors++;
  1516. brcmf_sdio_rxfail(bus, true, true);
  1517. goto done;
  1518. } else
  1519. memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
  1520. gotpkt:
  1521. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
  1522. buf, len, "RxCtrl:\n");
  1523. /* Point to valid data and indicate its length */
  1524. spin_lock_bh(&bus->rxctl_lock);
  1525. if (bus->rxctl) {
  1526. brcmf_err("last control frame is being processed.\n");
  1527. spin_unlock_bh(&bus->rxctl_lock);
  1528. vfree(buf);
  1529. goto done;
  1530. }
  1531. bus->rxctl = buf + doff;
  1532. bus->rxctl_orig = buf;
  1533. bus->rxlen = len - doff;
  1534. spin_unlock_bh(&bus->rxctl_lock);
  1535. done:
  1536. /* Awake any waiters */
  1537. brcmf_sdio_dcmd_resp_wake(bus);
  1538. }
  1539. /* Pad read to blocksize for efficiency */
  1540. static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
  1541. {
  1542. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1543. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1544. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1545. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1546. *rdlen += *pad;
  1547. } else if (*rdlen % bus->head_align) {
  1548. *rdlen += bus->head_align - (*rdlen % bus->head_align);
  1549. }
  1550. }
  1551. static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
  1552. {
  1553. struct sk_buff *pkt; /* Packet for event or data frames */
  1554. u16 pad; /* Number of pad bytes to read */
  1555. uint rxleft = 0; /* Remaining number of frames allowed */
  1556. int ret; /* Return code from calls */
  1557. uint rxcount = 0; /* Total frames read */
  1558. struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
  1559. u8 head_read = 0;
  1560. brcmf_dbg(SDIO, "Enter\n");
  1561. /* Not finished unless we encounter no more frames indication */
  1562. bus->rxpending = true;
  1563. for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
  1564. !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
  1565. rd->seq_num++, rxleft--) {
  1566. /* Handle glomming separately */
  1567. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1568. u8 cnt;
  1569. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1570. bus->glomd, skb_peek(&bus->glom));
  1571. cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
  1572. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1573. rd->seq_num += cnt - 1;
  1574. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1575. continue;
  1576. }
  1577. rd->len_left = rd->len;
  1578. /* read header first for unknow frame length */
  1579. sdio_claim_host(bus->sdiodev->func1);
  1580. if (!rd->len) {
  1581. ret = brcmf_sdiod_recv_buf(bus->sdiodev,
  1582. bus->rxhdr, BRCMF_FIRSTREAD);
  1583. bus->sdcnt.f2rxhdrs++;
  1584. if (ret < 0) {
  1585. brcmf_err("RXHEADER FAILED: %d\n",
  1586. ret);
  1587. bus->sdcnt.rx_hdrfail++;
  1588. brcmf_sdio_rxfail(bus, true, true);
  1589. sdio_release_host(bus->sdiodev->func1);
  1590. continue;
  1591. }
  1592. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
  1593. bus->rxhdr, SDPCM_HDRLEN,
  1594. "RxHdr:\n");
  1595. if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
  1596. BRCMF_SDIO_FT_NORMAL)) {
  1597. sdio_release_host(bus->sdiodev->func1);
  1598. if (!bus->rxpending)
  1599. break;
  1600. else
  1601. continue;
  1602. }
  1603. if (rd->channel == SDPCM_CONTROL_CHANNEL) {
  1604. brcmf_sdio_read_control(bus, bus->rxhdr,
  1605. rd->len,
  1606. rd->dat_offset);
  1607. /* prepare the descriptor for the next read */
  1608. rd->len = rd->len_nxtfrm << 4;
  1609. rd->len_nxtfrm = 0;
  1610. /* treat all packet as event if we don't know */
  1611. rd->channel = SDPCM_EVENT_CHANNEL;
  1612. sdio_release_host(bus->sdiodev->func1);
  1613. continue;
  1614. }
  1615. rd->len_left = rd->len > BRCMF_FIRSTREAD ?
  1616. rd->len - BRCMF_FIRSTREAD : 0;
  1617. head_read = BRCMF_FIRSTREAD;
  1618. }
  1619. brcmf_sdio_pad(bus, &pad, &rd->len_left);
  1620. pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
  1621. bus->head_align);
  1622. if (!pkt) {
  1623. /* Give up on data, request rtx of events */
  1624. brcmf_err("brcmu_pkt_buf_get_skb failed\n");
  1625. brcmf_sdio_rxfail(bus, false,
  1626. RETRYCHAN(rd->channel));
  1627. sdio_release_host(bus->sdiodev->func1);
  1628. continue;
  1629. }
  1630. skb_pull(pkt, head_read);
  1631. pkt_align(pkt, rd->len_left, bus->head_align);
  1632. ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
  1633. bus->sdcnt.f2rxdata++;
  1634. sdio_release_host(bus->sdiodev->func1);
  1635. if (ret < 0) {
  1636. brcmf_err("read %d bytes from channel %d failed: %d\n",
  1637. rd->len, rd->channel, ret);
  1638. brcmu_pkt_buf_free_skb(pkt);
  1639. sdio_claim_host(bus->sdiodev->func1);
  1640. brcmf_sdio_rxfail(bus, true,
  1641. RETRYCHAN(rd->channel));
  1642. sdio_release_host(bus->sdiodev->func1);
  1643. continue;
  1644. }
  1645. if (head_read) {
  1646. skb_push(pkt, head_read);
  1647. memcpy(pkt->data, bus->rxhdr, head_read);
  1648. head_read = 0;
  1649. } else {
  1650. memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
  1651. rd_new.seq_num = rd->seq_num;
  1652. sdio_claim_host(bus->sdiodev->func1);
  1653. if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
  1654. BRCMF_SDIO_FT_NORMAL)) {
  1655. rd->len = 0;
  1656. brcmu_pkt_buf_free_skb(pkt);
  1657. }
  1658. bus->sdcnt.rx_readahead_cnt++;
  1659. if (rd->len != roundup(rd_new.len, 16)) {
  1660. brcmf_err("frame length mismatch:read %d, should be %d\n",
  1661. rd->len,
  1662. roundup(rd_new.len, 16) >> 4);
  1663. rd->len = 0;
  1664. brcmf_sdio_rxfail(bus, true, true);
  1665. sdio_release_host(bus->sdiodev->func1);
  1666. brcmu_pkt_buf_free_skb(pkt);
  1667. continue;
  1668. }
  1669. sdio_release_host(bus->sdiodev->func1);
  1670. rd->len_nxtfrm = rd_new.len_nxtfrm;
  1671. rd->channel = rd_new.channel;
  1672. rd->dat_offset = rd_new.dat_offset;
  1673. brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
  1674. BRCMF_DATA_ON()) &&
  1675. BRCMF_HDRS_ON(),
  1676. bus->rxhdr, SDPCM_HDRLEN,
  1677. "RxHdr:\n");
  1678. if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
  1679. brcmf_err("readahead on control packet %d?\n",
  1680. rd_new.seq_num);
  1681. /* Force retry w/normal header read */
  1682. rd->len = 0;
  1683. sdio_claim_host(bus->sdiodev->func1);
  1684. brcmf_sdio_rxfail(bus, false, true);
  1685. sdio_release_host(bus->sdiodev->func1);
  1686. brcmu_pkt_buf_free_skb(pkt);
  1687. continue;
  1688. }
  1689. }
  1690. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
  1691. pkt->data, rd->len, "Rx Data:\n");
  1692. /* Save superframe descriptor and allocate packet frame */
  1693. if (rd->channel == SDPCM_GLOM_CHANNEL) {
  1694. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
  1695. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1696. rd->len);
  1697. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1698. pkt->data, rd->len,
  1699. "Glom Data:\n");
  1700. __skb_trim(pkt, rd->len);
  1701. skb_pull(pkt, SDPCM_HDRLEN);
  1702. bus->glomd = pkt;
  1703. } else {
  1704. brcmf_err("%s: glom superframe w/o "
  1705. "descriptor!\n", __func__);
  1706. sdio_claim_host(bus->sdiodev->func1);
  1707. brcmf_sdio_rxfail(bus, false, false);
  1708. sdio_release_host(bus->sdiodev->func1);
  1709. }
  1710. /* prepare the descriptor for the next read */
  1711. rd->len = rd->len_nxtfrm << 4;
  1712. rd->len_nxtfrm = 0;
  1713. /* treat all packet as event if we don't know */
  1714. rd->channel = SDPCM_EVENT_CHANNEL;
  1715. continue;
  1716. }
  1717. /* Fill in packet len and prio, deliver upward */
  1718. __skb_trim(pkt, rd->len);
  1719. skb_pull(pkt, rd->dat_offset);
  1720. if (pkt->len == 0)
  1721. brcmu_pkt_buf_free_skb(pkt);
  1722. else if (rd->channel == SDPCM_EVENT_CHANNEL)
  1723. brcmf_rx_event(bus->sdiodev->dev, pkt);
  1724. else
  1725. brcmf_rx_frame(bus->sdiodev->dev, pkt,
  1726. false);
  1727. /* prepare the descriptor for the next read */
  1728. rd->len = rd->len_nxtfrm << 4;
  1729. rd->len_nxtfrm = 0;
  1730. /* treat all packet as event if we don't know */
  1731. rd->channel = SDPCM_EVENT_CHANNEL;
  1732. }
  1733. rxcount = maxframes - rxleft;
  1734. /* Message if we hit the limit */
  1735. if (!rxleft)
  1736. brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
  1737. else
  1738. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1739. /* Back off rxseq if awaiting rtx, update rx_seq */
  1740. if (bus->rxskip)
  1741. rd->seq_num--;
  1742. bus->rx_seq = rd->seq_num;
  1743. return rxcount;
  1744. }
  1745. static void
  1746. brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
  1747. {
  1748. wake_up_interruptible(&bus->ctrl_wait);
  1749. return;
  1750. }
  1751. static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
  1752. {
  1753. struct brcmf_bus_stats *stats;
  1754. u16 head_pad;
  1755. u8 *dat_buf;
  1756. dat_buf = (u8 *)(pkt->data);
  1757. /* Check head padding */
  1758. head_pad = ((unsigned long)dat_buf % bus->head_align);
  1759. if (head_pad) {
  1760. if (skb_headroom(pkt) < head_pad) {
  1761. stats = &bus->sdiodev->bus_if->stats;
  1762. atomic_inc(&stats->pktcowed);
  1763. if (skb_cow_head(pkt, head_pad)) {
  1764. atomic_inc(&stats->pktcow_failed);
  1765. return -ENOMEM;
  1766. }
  1767. head_pad = 0;
  1768. }
  1769. skb_push(pkt, head_pad);
  1770. dat_buf = (u8 *)(pkt->data);
  1771. }
  1772. memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
  1773. return head_pad;
  1774. }
  1775. /*
  1776. * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
  1777. * bus layer usage.
  1778. */
  1779. /* flag marking a dummy skb added for DMA alignment requirement */
  1780. #define ALIGN_SKB_FLAG 0x8000
  1781. /* bit mask of data length chopped from the previous packet */
  1782. #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
  1783. static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
  1784. struct sk_buff_head *pktq,
  1785. struct sk_buff *pkt, u16 total_len)
  1786. {
  1787. struct brcmf_sdio_dev *sdiodev;
  1788. struct sk_buff *pkt_pad;
  1789. u16 tail_pad, tail_chop, chain_pad;
  1790. unsigned int blksize;
  1791. bool lastfrm;
  1792. int ntail, ret;
  1793. sdiodev = bus->sdiodev;
  1794. blksize = sdiodev->func2->cur_blksize;
  1795. /* sg entry alignment should be a divisor of block size */
  1796. WARN_ON(blksize % bus->sgentry_align);
  1797. /* Check tail padding */
  1798. lastfrm = skb_queue_is_last(pktq, pkt);
  1799. tail_pad = 0;
  1800. tail_chop = pkt->len % bus->sgentry_align;
  1801. if (tail_chop)
  1802. tail_pad = bus->sgentry_align - tail_chop;
  1803. chain_pad = (total_len + tail_pad) % blksize;
  1804. if (lastfrm && chain_pad)
  1805. tail_pad += blksize - chain_pad;
  1806. if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
  1807. pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
  1808. bus->head_align);
  1809. if (pkt_pad == NULL)
  1810. return -ENOMEM;
  1811. ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
  1812. if (unlikely(ret < 0)) {
  1813. kfree_skb(pkt_pad);
  1814. return ret;
  1815. }
  1816. memcpy(pkt_pad->data,
  1817. pkt->data + pkt->len - tail_chop,
  1818. tail_chop);
  1819. *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
  1820. skb_trim(pkt, pkt->len - tail_chop);
  1821. skb_trim(pkt_pad, tail_pad + tail_chop);
  1822. __skb_queue_after(pktq, pkt, pkt_pad);
  1823. } else {
  1824. ntail = pkt->data_len + tail_pad -
  1825. (pkt->end - pkt->tail);
  1826. if (skb_cloned(pkt) || ntail > 0)
  1827. if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
  1828. return -ENOMEM;
  1829. if (skb_linearize(pkt))
  1830. return -ENOMEM;
  1831. __skb_put(pkt, tail_pad);
  1832. }
  1833. return tail_pad;
  1834. }
  1835. /**
  1836. * brcmf_sdio_txpkt_prep - packet preparation for transmit
  1837. * @bus: brcmf_sdio structure pointer
  1838. * @pktq: packet list pointer
  1839. * @chan: virtual channel to transmit the packet
  1840. *
  1841. * Processes to be applied to the packet
  1842. * - Align data buffer pointer
  1843. * - Align data buffer length
  1844. * - Prepare header
  1845. * Return: negative value if there is error
  1846. */
  1847. static int
  1848. brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
  1849. uint chan)
  1850. {
  1851. u16 head_pad, total_len;
  1852. struct sk_buff *pkt_next;
  1853. u8 txseq;
  1854. int ret;
  1855. struct brcmf_sdio_hdrinfo hd_info = {0};
  1856. txseq = bus->tx_seq;
  1857. total_len = 0;
  1858. skb_queue_walk(pktq, pkt_next) {
  1859. /* alignment packet inserted in previous
  1860. * loop cycle can be skipped as it is
  1861. * already properly aligned and does not
  1862. * need an sdpcm header.
  1863. */
  1864. if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
  1865. continue;
  1866. /* align packet data pointer */
  1867. ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
  1868. if (ret < 0)
  1869. return ret;
  1870. head_pad = (u16)ret;
  1871. if (head_pad)
  1872. memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
  1873. total_len += pkt_next->len;
  1874. hd_info.len = pkt_next->len;
  1875. hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
  1876. if (bus->txglom && pktq->qlen > 1) {
  1877. ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
  1878. pkt_next, total_len);
  1879. if (ret < 0)
  1880. return ret;
  1881. hd_info.tail_pad = (u16)ret;
  1882. total_len += (u16)ret;
  1883. }
  1884. hd_info.channel = chan;
  1885. hd_info.dat_offset = head_pad + bus->tx_hdrlen;
  1886. hd_info.seq_num = txseq++;
  1887. /* Now fill the header */
  1888. brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
  1889. if (BRCMF_BYTES_ON() &&
  1890. ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
  1891. (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
  1892. brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
  1893. "Tx Frame:\n");
  1894. else if (BRCMF_HDRS_ON())
  1895. brcmf_dbg_hex_dump(true, pkt_next->data,
  1896. head_pad + bus->tx_hdrlen,
  1897. "Tx Header:\n");
  1898. }
  1899. /* Hardware length tag of the first packet should be total
  1900. * length of the chain (including padding)
  1901. */
  1902. if (bus->txglom)
  1903. brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
  1904. return 0;
  1905. }
  1906. /**
  1907. * brcmf_sdio_txpkt_postp - packet post processing for transmit
  1908. * @bus: brcmf_sdio structure pointer
  1909. * @pktq: packet list pointer
  1910. *
  1911. * Processes to be applied to the packet
  1912. * - Remove head padding
  1913. * - Remove tail padding
  1914. */
  1915. static void
  1916. brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
  1917. {
  1918. u8 *hdr;
  1919. u32 dat_offset;
  1920. u16 tail_pad;
  1921. u16 dummy_flags, chop_len;
  1922. struct sk_buff *pkt_next, *tmp, *pkt_prev;
  1923. skb_queue_walk_safe(pktq, pkt_next, tmp) {
  1924. dummy_flags = *(u16 *)(pkt_next->cb);
  1925. if (dummy_flags & ALIGN_SKB_FLAG) {
  1926. chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
  1927. if (chop_len) {
  1928. pkt_prev = pkt_next->prev;
  1929. skb_put(pkt_prev, chop_len);
  1930. }
  1931. __skb_unlink(pkt_next, pktq);
  1932. brcmu_pkt_buf_free_skb(pkt_next);
  1933. } else {
  1934. hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
  1935. dat_offset = le32_to_cpu(*(__le32 *)hdr);
  1936. dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
  1937. SDPCM_DOFFSET_SHIFT;
  1938. skb_pull(pkt_next, dat_offset);
  1939. if (bus->txglom) {
  1940. tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
  1941. skb_trim(pkt_next, pkt_next->len - tail_pad);
  1942. }
  1943. }
  1944. }
  1945. }
  1946. /* Writes a HW/SW header into the packet and sends it. */
  1947. /* Assumes: (a) header space already there, (b) caller holds lock */
  1948. static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
  1949. uint chan)
  1950. {
  1951. int ret;
  1952. struct sk_buff *pkt_next, *tmp;
  1953. brcmf_dbg(TRACE, "Enter\n");
  1954. ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
  1955. if (ret)
  1956. goto done;
  1957. sdio_claim_host(bus->sdiodev->func1);
  1958. ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
  1959. bus->sdcnt.f2txdata++;
  1960. if (ret < 0)
  1961. brcmf_sdio_txfail(bus);
  1962. sdio_release_host(bus->sdiodev->func1);
  1963. done:
  1964. brcmf_sdio_txpkt_postp(bus, pktq);
  1965. if (ret == 0)
  1966. bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
  1967. skb_queue_walk_safe(pktq, pkt_next, tmp) {
  1968. __skb_unlink(pkt_next, pktq);
  1969. brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next,
  1970. ret == 0);
  1971. }
  1972. return ret;
  1973. }
  1974. static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
  1975. {
  1976. struct sk_buff *pkt;
  1977. struct sk_buff_head pktq;
  1978. u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
  1979. u32 intstatus = 0;
  1980. int ret = 0, prec_out, i;
  1981. uint cnt = 0;
  1982. u8 tx_prec_map, pkt_num;
  1983. brcmf_dbg(TRACE, "Enter\n");
  1984. tx_prec_map = ~bus->flowcontrol;
  1985. /* Send frames until the limit or some other event */
  1986. for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
  1987. pkt_num = 1;
  1988. if (bus->txglom)
  1989. pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
  1990. bus->sdiodev->txglomsz);
  1991. pkt_num = min_t(u32, pkt_num,
  1992. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
  1993. __skb_queue_head_init(&pktq);
  1994. spin_lock_bh(&bus->txq_lock);
  1995. for (i = 0; i < pkt_num; i++) {
  1996. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
  1997. &prec_out);
  1998. if (pkt == NULL)
  1999. break;
  2000. __skb_queue_tail(&pktq, pkt);
  2001. }
  2002. spin_unlock_bh(&bus->txq_lock);
  2003. if (i == 0)
  2004. break;
  2005. ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
  2006. cnt += i;
  2007. /* In poll mode, need to check for other events */
  2008. if (!bus->intr) {
  2009. /* Check device status, signal pending interrupt */
  2010. sdio_claim_host(bus->sdiodev->func1);
  2011. intstatus = brcmf_sdiod_readl(bus->sdiodev,
  2012. intstat_addr, &ret);
  2013. sdio_release_host(bus->sdiodev->func1);
  2014. bus->sdcnt.f2txdata++;
  2015. if (ret != 0)
  2016. break;
  2017. if (intstatus & bus->hostintmask)
  2018. atomic_set(&bus->ipend, 1);
  2019. }
  2020. }
  2021. /* Deflow-control stack if needed */
  2022. if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
  2023. bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
  2024. bus->txoff = false;
  2025. brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false);
  2026. }
  2027. return cnt;
  2028. }
  2029. static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
  2030. {
  2031. u8 doff;
  2032. u16 pad;
  2033. uint retries = 0;
  2034. struct brcmf_sdio_hdrinfo hd_info = {0};
  2035. int ret;
  2036. brcmf_dbg(SDIO, "Enter\n");
  2037. /* Back the pointer to make room for bus header */
  2038. frame -= bus->tx_hdrlen;
  2039. len += bus->tx_hdrlen;
  2040. /* Add alignment padding (optional for ctl frames) */
  2041. doff = ((unsigned long)frame % bus->head_align);
  2042. if (doff) {
  2043. frame -= doff;
  2044. len += doff;
  2045. memset(frame + bus->tx_hdrlen, 0, doff);
  2046. }
  2047. /* Round send length to next SDIO block */
  2048. pad = 0;
  2049. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2050. pad = bus->blocksize - (len % bus->blocksize);
  2051. if ((pad > bus->roundup) || (pad >= bus->blocksize))
  2052. pad = 0;
  2053. } else if (len % bus->head_align) {
  2054. pad = bus->head_align - (len % bus->head_align);
  2055. }
  2056. len += pad;
  2057. hd_info.len = len - pad;
  2058. hd_info.channel = SDPCM_CONTROL_CHANNEL;
  2059. hd_info.dat_offset = doff + bus->tx_hdrlen;
  2060. hd_info.seq_num = bus->tx_seq;
  2061. hd_info.lastfrm = true;
  2062. hd_info.tail_pad = pad;
  2063. brcmf_sdio_hdpack(bus, frame, &hd_info);
  2064. if (bus->txglom)
  2065. brcmf_sdio_update_hwhdr(frame, len);
  2066. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
  2067. frame, len, "Tx Frame:\n");
  2068. brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
  2069. BRCMF_HDRS_ON(),
  2070. frame, min_t(u16, len, 16), "TxHdr:\n");
  2071. do {
  2072. ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
  2073. if (ret < 0)
  2074. brcmf_sdio_txfail(bus);
  2075. else
  2076. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
  2077. } while (ret < 0 && retries++ < TXRETRIES);
  2078. return ret;
  2079. }
  2080. static void brcmf_sdio_bus_stop(struct device *dev)
  2081. {
  2082. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2083. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2084. struct brcmf_sdio *bus = sdiodev->bus;
  2085. struct brcmf_core *core = bus->sdio_core;
  2086. u32 local_hostintmask;
  2087. u8 saveclk;
  2088. int err;
  2089. brcmf_dbg(TRACE, "Enter\n");
  2090. if (bus->watchdog_tsk) {
  2091. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  2092. kthread_stop(bus->watchdog_tsk);
  2093. bus->watchdog_tsk = NULL;
  2094. }
  2095. if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
  2096. sdio_claim_host(sdiodev->func1);
  2097. /* Enable clock for device interrupts */
  2098. brcmf_sdio_bus_sleep(bus, false, false);
  2099. /* Disable and clear interrupts at the chip level also */
  2100. brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask),
  2101. 0, NULL);
  2102. local_hostintmask = bus->hostintmask;
  2103. bus->hostintmask = 0;
  2104. /* Force backplane clocks to assure F2 interrupt propagates */
  2105. saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  2106. &err);
  2107. if (!err)
  2108. brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  2109. (saveclk | SBSDIO_FORCE_HT), &err);
  2110. if (err)
  2111. brcmf_err("Failed to force clock for F2: err %d\n",
  2112. err);
  2113. /* Turn off the bus (F2), free any pending packets */
  2114. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  2115. sdio_disable_func(sdiodev->func2);
  2116. /* Clear any pending interrupts now that F2 is disabled */
  2117. brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus),
  2118. local_hostintmask, NULL);
  2119. sdio_release_host(sdiodev->func1);
  2120. }
  2121. /* Clear the data packet queues */
  2122. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  2123. /* Clear any held glomming stuff */
  2124. brcmu_pkt_buf_free_skb(bus->glomd);
  2125. brcmf_sdio_free_glom(bus);
  2126. /* Clear rx control and wake any waiters */
  2127. spin_lock_bh(&bus->rxctl_lock);
  2128. bus->rxlen = 0;
  2129. spin_unlock_bh(&bus->rxctl_lock);
  2130. brcmf_sdio_dcmd_resp_wake(bus);
  2131. /* Reset some F2 state stuff */
  2132. bus->rxskip = false;
  2133. bus->tx_seq = bus->rx_seq = 0;
  2134. }
  2135. static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
  2136. {
  2137. struct brcmf_sdio_dev *sdiodev;
  2138. unsigned long flags;
  2139. sdiodev = bus->sdiodev;
  2140. if (sdiodev->oob_irq_requested) {
  2141. spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
  2142. if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
  2143. enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
  2144. sdiodev->irq_en = true;
  2145. }
  2146. spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
  2147. }
  2148. }
  2149. static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
  2150. {
  2151. struct brcmf_core *core = bus->sdio_core;
  2152. u32 addr;
  2153. unsigned long val;
  2154. int ret;
  2155. addr = core->base + SD_REG(intstatus);
  2156. val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret);
  2157. bus->sdcnt.f1regdata++;
  2158. if (ret != 0)
  2159. return ret;
  2160. val &= bus->hostintmask;
  2161. atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
  2162. /* Clear interrupts */
  2163. if (val) {
  2164. brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret);
  2165. bus->sdcnt.f1regdata++;
  2166. atomic_or(val, &bus->intstatus);
  2167. }
  2168. return ret;
  2169. }
  2170. static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
  2171. {
  2172. struct brcmf_sdio_dev *sdiod = bus->sdiodev;
  2173. u32 newstatus = 0;
  2174. u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
  2175. unsigned long intstatus;
  2176. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  2177. uint framecnt; /* Temporary counter of tx/rx frames */
  2178. int err = 0;
  2179. brcmf_dbg(SDIO, "Enter\n");
  2180. sdio_claim_host(bus->sdiodev->func1);
  2181. /* If waiting for HTAVAIL, check status */
  2182. if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
  2183. u8 clkctl, devctl = 0;
  2184. #ifdef DEBUG
  2185. /* Check for inconsistent device control */
  2186. devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  2187. &err);
  2188. #endif /* DEBUG */
  2189. /* Read CSR, if clock on switch to AVAIL, else ignore */
  2190. clkctl = brcmf_sdiod_readb(bus->sdiodev,
  2191. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2192. brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  2193. devctl, clkctl);
  2194. if (SBSDIO_HTAV(clkctl)) {
  2195. devctl = brcmf_sdiod_readb(bus->sdiodev,
  2196. SBSDIO_DEVICE_CTL, &err);
  2197. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  2198. brcmf_sdiod_writeb(bus->sdiodev,
  2199. SBSDIO_DEVICE_CTL, devctl, &err);
  2200. bus->clkstate = CLK_AVAIL;
  2201. }
  2202. }
  2203. /* Make sure backplane clock is on */
  2204. brcmf_sdio_bus_sleep(bus, false, true);
  2205. /* Pending interrupt indicates new device status */
  2206. if (atomic_read(&bus->ipend) > 0) {
  2207. atomic_set(&bus->ipend, 0);
  2208. err = brcmf_sdio_intr_rstatus(bus);
  2209. }
  2210. /* Start with leftover status bits */
  2211. intstatus = atomic_xchg(&bus->intstatus, 0);
  2212. /* Handle flow-control change: read new state in case our ack
  2213. * crossed another change interrupt. If change still set, assume
  2214. * FC ON for safety, let next loop through do the debounce.
  2215. */
  2216. if (intstatus & I_HMB_FC_CHANGE) {
  2217. intstatus &= ~I_HMB_FC_CHANGE;
  2218. brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err);
  2219. newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err);
  2220. bus->sdcnt.f1regdata += 2;
  2221. atomic_set(&bus->fcstate,
  2222. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
  2223. intstatus |= (newstatus & bus->hostintmask);
  2224. }
  2225. /* Handle host mailbox indication */
  2226. if (intstatus & I_HMB_HOST_INT) {
  2227. intstatus &= ~I_HMB_HOST_INT;
  2228. intstatus |= brcmf_sdio_hostmail(bus);
  2229. }
  2230. sdio_release_host(bus->sdiodev->func1);
  2231. /* Generally don't ask for these, can get CRC errors... */
  2232. if (intstatus & I_WR_OOSYNC) {
  2233. brcmf_err("Dongle reports WR_OOSYNC\n");
  2234. intstatus &= ~I_WR_OOSYNC;
  2235. }
  2236. if (intstatus & I_RD_OOSYNC) {
  2237. brcmf_err("Dongle reports RD_OOSYNC\n");
  2238. intstatus &= ~I_RD_OOSYNC;
  2239. }
  2240. if (intstatus & I_SBINT) {
  2241. brcmf_err("Dongle reports SBINT\n");
  2242. intstatus &= ~I_SBINT;
  2243. }
  2244. /* Would be active due to wake-wlan in gSPI */
  2245. if (intstatus & I_CHIPACTIVE) {
  2246. brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n");
  2247. intstatus &= ~I_CHIPACTIVE;
  2248. }
  2249. /* Ignore frame indications if rxskip is set */
  2250. if (bus->rxskip)
  2251. intstatus &= ~I_HMB_FRAME_IND;
  2252. /* On frame indication, read available frames */
  2253. if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
  2254. brcmf_sdio_readframes(bus, bus->rxbound);
  2255. if (!bus->rxpending)
  2256. intstatus &= ~I_HMB_FRAME_IND;
  2257. }
  2258. /* Keep still-pending events for next scheduling */
  2259. if (intstatus)
  2260. atomic_or(intstatus, &bus->intstatus);
  2261. brcmf_sdio_clrintr(bus);
  2262. if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
  2263. data_ok(bus)) {
  2264. sdio_claim_host(bus->sdiodev->func1);
  2265. if (bus->ctrl_frame_stat) {
  2266. err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
  2267. bus->ctrl_frame_len);
  2268. bus->ctrl_frame_err = err;
  2269. wmb();
  2270. bus->ctrl_frame_stat = false;
  2271. }
  2272. sdio_release_host(bus->sdiodev->func1);
  2273. brcmf_sdio_wait_event_wakeup(bus);
  2274. }
  2275. /* Send queued frames (limit 1 if rx may still be pending) */
  2276. if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
  2277. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
  2278. data_ok(bus)) {
  2279. framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
  2280. txlimit;
  2281. brcmf_sdio_sendfromq(bus, framecnt);
  2282. }
  2283. if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
  2284. brcmf_err("failed backplane access over SDIO, halting operation\n");
  2285. atomic_set(&bus->intstatus, 0);
  2286. if (bus->ctrl_frame_stat) {
  2287. sdio_claim_host(bus->sdiodev->func1);
  2288. if (bus->ctrl_frame_stat) {
  2289. bus->ctrl_frame_err = -ENODEV;
  2290. wmb();
  2291. bus->ctrl_frame_stat = false;
  2292. brcmf_sdio_wait_event_wakeup(bus);
  2293. }
  2294. sdio_release_host(bus->sdiodev->func1);
  2295. }
  2296. } else if (atomic_read(&bus->intstatus) ||
  2297. atomic_read(&bus->ipend) > 0 ||
  2298. (!atomic_read(&bus->fcstate) &&
  2299. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
  2300. data_ok(bus))) {
  2301. bus->dpc_triggered = true;
  2302. }
  2303. }
  2304. static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
  2305. {
  2306. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2307. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2308. struct brcmf_sdio *bus = sdiodev->bus;
  2309. return &bus->txq;
  2310. }
  2311. static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
  2312. {
  2313. struct sk_buff *p;
  2314. int eprec = -1; /* precedence to evict from */
  2315. /* Fast case, precedence queue is not full and we are also not
  2316. * exceeding total queue length
  2317. */
  2318. if (!pktq_pfull(q, prec) && !pktq_full(q)) {
  2319. brcmu_pktq_penq(q, prec, pkt);
  2320. return true;
  2321. }
  2322. /* Determine precedence from which to evict packet, if any */
  2323. if (pktq_pfull(q, prec)) {
  2324. eprec = prec;
  2325. } else if (pktq_full(q)) {
  2326. p = brcmu_pktq_peek_tail(q, &eprec);
  2327. if (eprec > prec)
  2328. return false;
  2329. }
  2330. /* Evict if needed */
  2331. if (eprec >= 0) {
  2332. /* Detect queueing to unconfigured precedence */
  2333. if (eprec == prec)
  2334. return false; /* refuse newer (incoming) packet */
  2335. /* Evict packet according to discard policy */
  2336. p = brcmu_pktq_pdeq_tail(q, eprec);
  2337. if (p == NULL)
  2338. brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
  2339. brcmu_pkt_buf_free_skb(p);
  2340. }
  2341. /* Enqueue */
  2342. p = brcmu_pktq_penq(q, prec, pkt);
  2343. if (p == NULL)
  2344. brcmf_err("brcmu_pktq_penq() failed\n");
  2345. return p != NULL;
  2346. }
  2347. static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
  2348. {
  2349. int ret = -EBADE;
  2350. uint prec;
  2351. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2352. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2353. struct brcmf_sdio *bus = sdiodev->bus;
  2354. brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
  2355. if (sdiodev->state != BRCMF_SDIOD_DATA)
  2356. return -EIO;
  2357. /* Add space for the header */
  2358. skb_push(pkt, bus->tx_hdrlen);
  2359. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2360. prec = prio2prec((pkt->priority & PRIOMASK));
  2361. /* Check for existing queue, current flow-control,
  2362. pending event, or pending clock */
  2363. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2364. bus->sdcnt.fcqueued++;
  2365. /* Priority based enq */
  2366. spin_lock_bh(&bus->txq_lock);
  2367. /* reset bus_flags in packet cb */
  2368. *(u16 *)(pkt->cb) = 0;
  2369. if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
  2370. skb_pull(pkt, bus->tx_hdrlen);
  2371. brcmf_err("out of bus->txq !!!\n");
  2372. ret = -ENOSR;
  2373. } else {
  2374. ret = 0;
  2375. }
  2376. if (pktq_len(&bus->txq) >= TXHI) {
  2377. bus->txoff = true;
  2378. brcmf_proto_bcdc_txflowblock(dev, true);
  2379. }
  2380. spin_unlock_bh(&bus->txq_lock);
  2381. #ifdef DEBUG
  2382. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2383. qcount[prec] = pktq_plen(&bus->txq, prec);
  2384. #endif
  2385. brcmf_sdio_trigger_dpc(bus);
  2386. return ret;
  2387. }
  2388. #ifdef DEBUG
  2389. #define CONSOLE_LINE_MAX 192
  2390. static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
  2391. {
  2392. struct brcmf_console *c = &bus->console;
  2393. u8 line[CONSOLE_LINE_MAX], ch;
  2394. u32 n, idx, addr;
  2395. int rv;
  2396. /* Don't do anything until FWREADY updates console address */
  2397. if (bus->console_addr == 0)
  2398. return 0;
  2399. /* Read console log struct */
  2400. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2401. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
  2402. sizeof(c->log_le));
  2403. if (rv < 0)
  2404. return rv;
  2405. /* Allocate console buffer (one time only) */
  2406. if (c->buf == NULL) {
  2407. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2408. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2409. if (c->buf == NULL)
  2410. return -ENOMEM;
  2411. }
  2412. idx = le32_to_cpu(c->log_le.idx);
  2413. /* Protect against corrupt value */
  2414. if (idx > c->bufsize)
  2415. return -EBADE;
  2416. /* Skip reading the console buffer if the index pointer
  2417. has not moved */
  2418. if (idx == c->last)
  2419. return 0;
  2420. /* Read the console buffer */
  2421. addr = le32_to_cpu(c->log_le.buf);
  2422. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
  2423. if (rv < 0)
  2424. return rv;
  2425. while (c->last != idx) {
  2426. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2427. if (c->last == idx) {
  2428. /* This would output a partial line.
  2429. * Instead, back up
  2430. * the buffer pointer and output this
  2431. * line next time around.
  2432. */
  2433. if (c->last >= n)
  2434. c->last -= n;
  2435. else
  2436. c->last = c->bufsize - n;
  2437. goto break2;
  2438. }
  2439. ch = c->buf[c->last];
  2440. c->last = (c->last + 1) % c->bufsize;
  2441. if (ch == '\n')
  2442. break;
  2443. line[n] = ch;
  2444. }
  2445. if (n > 0) {
  2446. if (line[n - 1] == '\r')
  2447. n--;
  2448. line[n] = 0;
  2449. pr_debug("CONSOLE: %s\n", line);
  2450. }
  2451. }
  2452. break2:
  2453. return 0;
  2454. }
  2455. #endif /* DEBUG */
  2456. static int
  2457. brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
  2458. {
  2459. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2460. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2461. struct brcmf_sdio *bus = sdiodev->bus;
  2462. int ret;
  2463. brcmf_dbg(TRACE, "Enter\n");
  2464. if (sdiodev->state != BRCMF_SDIOD_DATA)
  2465. return -EIO;
  2466. /* Send from dpc */
  2467. bus->ctrl_frame_buf = msg;
  2468. bus->ctrl_frame_len = msglen;
  2469. wmb();
  2470. bus->ctrl_frame_stat = true;
  2471. brcmf_sdio_trigger_dpc(bus);
  2472. wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
  2473. CTL_DONE_TIMEOUT);
  2474. ret = 0;
  2475. if (bus->ctrl_frame_stat) {
  2476. sdio_claim_host(bus->sdiodev->func1);
  2477. if (bus->ctrl_frame_stat) {
  2478. brcmf_dbg(SDIO, "ctrl_frame timeout\n");
  2479. bus->ctrl_frame_stat = false;
  2480. ret = -ETIMEDOUT;
  2481. }
  2482. sdio_release_host(bus->sdiodev->func1);
  2483. }
  2484. if (!ret) {
  2485. brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
  2486. bus->ctrl_frame_err);
  2487. rmb();
  2488. ret = bus->ctrl_frame_err;
  2489. }
  2490. if (ret)
  2491. bus->sdcnt.tx_ctlerrs++;
  2492. else
  2493. bus->sdcnt.tx_ctlpkts++;
  2494. return ret;
  2495. }
  2496. #ifdef DEBUG
  2497. static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
  2498. struct sdpcm_shared *sh)
  2499. {
  2500. u32 addr, console_ptr, console_size, console_index;
  2501. char *conbuf = NULL;
  2502. __le32 sh_val;
  2503. int rv;
  2504. /* obtain console information from device memory */
  2505. addr = sh->console_addr + offsetof(struct rte_console, log_le);
  2506. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
  2507. (u8 *)&sh_val, sizeof(u32));
  2508. if (rv < 0)
  2509. return rv;
  2510. console_ptr = le32_to_cpu(sh_val);
  2511. addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
  2512. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
  2513. (u8 *)&sh_val, sizeof(u32));
  2514. if (rv < 0)
  2515. return rv;
  2516. console_size = le32_to_cpu(sh_val);
  2517. addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
  2518. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
  2519. (u8 *)&sh_val, sizeof(u32));
  2520. if (rv < 0)
  2521. return rv;
  2522. console_index = le32_to_cpu(sh_val);
  2523. /* allocate buffer for console data */
  2524. if (console_size <= CONSOLE_BUFFER_MAX)
  2525. conbuf = vzalloc(console_size+1);
  2526. if (!conbuf)
  2527. return -ENOMEM;
  2528. /* obtain the console data from device */
  2529. conbuf[console_size] = '\0';
  2530. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
  2531. console_size);
  2532. if (rv < 0)
  2533. goto done;
  2534. rv = seq_write(seq, conbuf + console_index,
  2535. console_size - console_index);
  2536. if (rv < 0)
  2537. goto done;
  2538. if (console_index > 0)
  2539. rv = seq_write(seq, conbuf, console_index - 1);
  2540. done:
  2541. vfree(conbuf);
  2542. return rv;
  2543. }
  2544. static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
  2545. struct sdpcm_shared *sh)
  2546. {
  2547. int error;
  2548. struct brcmf_trap_info tr;
  2549. if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
  2550. brcmf_dbg(INFO, "no trap in firmware\n");
  2551. return 0;
  2552. }
  2553. error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
  2554. sizeof(struct brcmf_trap_info));
  2555. if (error < 0)
  2556. return error;
  2557. seq_printf(seq,
  2558. "dongle trap info: type 0x%x @ epc 0x%08x\n"
  2559. " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
  2560. " lr 0x%08x pc 0x%08x offset 0x%x\n"
  2561. " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
  2562. " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
  2563. le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
  2564. le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
  2565. le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
  2566. le32_to_cpu(tr.pc), sh->trap_addr,
  2567. le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
  2568. le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
  2569. le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
  2570. le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
  2571. return 0;
  2572. }
  2573. static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
  2574. struct sdpcm_shared *sh)
  2575. {
  2576. int error = 0;
  2577. char file[80] = "?";
  2578. char expr[80] = "<???>";
  2579. if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
  2580. brcmf_dbg(INFO, "firmware not built with -assert\n");
  2581. return 0;
  2582. } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
  2583. brcmf_dbg(INFO, "no assert in dongle\n");
  2584. return 0;
  2585. }
  2586. sdio_claim_host(bus->sdiodev->func1);
  2587. if (sh->assert_file_addr != 0) {
  2588. error = brcmf_sdiod_ramrw(bus->sdiodev, false,
  2589. sh->assert_file_addr, (u8 *)file, 80);
  2590. if (error < 0)
  2591. return error;
  2592. }
  2593. if (sh->assert_exp_addr != 0) {
  2594. error = brcmf_sdiod_ramrw(bus->sdiodev, false,
  2595. sh->assert_exp_addr, (u8 *)expr, 80);
  2596. if (error < 0)
  2597. return error;
  2598. }
  2599. sdio_release_host(bus->sdiodev->func1);
  2600. seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
  2601. file, sh->assert_line, expr);
  2602. return 0;
  2603. }
  2604. static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
  2605. {
  2606. int error;
  2607. struct sdpcm_shared sh;
  2608. error = brcmf_sdio_readshared(bus, &sh);
  2609. if (error < 0)
  2610. return error;
  2611. if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
  2612. brcmf_dbg(INFO, "firmware not built with -assert\n");
  2613. else if (sh.flags & SDPCM_SHARED_ASSERT)
  2614. brcmf_err("assertion in dongle\n");
  2615. if (sh.flags & SDPCM_SHARED_TRAP)
  2616. brcmf_err("firmware trap in dongle\n");
  2617. return 0;
  2618. }
  2619. static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
  2620. {
  2621. int error = 0;
  2622. struct sdpcm_shared sh;
  2623. error = brcmf_sdio_readshared(bus, &sh);
  2624. if (error < 0)
  2625. goto done;
  2626. error = brcmf_sdio_assert_info(seq, bus, &sh);
  2627. if (error < 0)
  2628. goto done;
  2629. error = brcmf_sdio_trap_info(seq, bus, &sh);
  2630. if (error < 0)
  2631. goto done;
  2632. error = brcmf_sdio_dump_console(seq, bus, &sh);
  2633. done:
  2634. return error;
  2635. }
  2636. static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
  2637. {
  2638. struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
  2639. struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
  2640. return brcmf_sdio_died_dump(seq, bus);
  2641. }
  2642. static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
  2643. {
  2644. struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
  2645. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2646. struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
  2647. seq_printf(seq,
  2648. "intrcount: %u\nlastintrs: %u\n"
  2649. "pollcnt: %u\nregfails: %u\n"
  2650. "tx_sderrs: %u\nfcqueued: %u\n"
  2651. "rxrtx: %u\nrx_toolong: %u\n"
  2652. "rxc_errors: %u\nrx_hdrfail: %u\n"
  2653. "rx_badhdr: %u\nrx_badseq: %u\n"
  2654. "fc_rcvd: %u\nfc_xoff: %u\n"
  2655. "fc_xon: %u\nrxglomfail: %u\n"
  2656. "rxglomframes: %u\nrxglompkts: %u\n"
  2657. "f2rxhdrs: %u\nf2rxdata: %u\n"
  2658. "f2txdata: %u\nf1regdata: %u\n"
  2659. "tickcnt: %u\ntx_ctlerrs: %lu\n"
  2660. "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
  2661. "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
  2662. sdcnt->intrcount, sdcnt->lastintrs,
  2663. sdcnt->pollcnt, sdcnt->regfails,
  2664. sdcnt->tx_sderrs, sdcnt->fcqueued,
  2665. sdcnt->rxrtx, sdcnt->rx_toolong,
  2666. sdcnt->rxc_errors, sdcnt->rx_hdrfail,
  2667. sdcnt->rx_badhdr, sdcnt->rx_badseq,
  2668. sdcnt->fc_rcvd, sdcnt->fc_xoff,
  2669. sdcnt->fc_xon, sdcnt->rxglomfail,
  2670. sdcnt->rxglomframes, sdcnt->rxglompkts,
  2671. sdcnt->f2rxhdrs, sdcnt->f2rxdata,
  2672. sdcnt->f2txdata, sdcnt->f1regdata,
  2673. sdcnt->tickcnt, sdcnt->tx_ctlerrs,
  2674. sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
  2675. sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
  2676. return 0;
  2677. }
  2678. static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
  2679. {
  2680. struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
  2681. struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
  2682. if (IS_ERR_OR_NULL(dentry))
  2683. return;
  2684. bus->console_interval = BRCMF_CONSOLE;
  2685. brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
  2686. brcmf_debugfs_add_entry(drvr, "counters",
  2687. brcmf_debugfs_sdio_count_read);
  2688. debugfs_create_u32("console_interval", 0644, dentry,
  2689. &bus->console_interval);
  2690. }
  2691. #else
  2692. static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
  2693. {
  2694. return 0;
  2695. }
  2696. static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
  2697. {
  2698. }
  2699. #endif /* DEBUG */
  2700. static int
  2701. brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
  2702. {
  2703. int timeleft;
  2704. uint rxlen = 0;
  2705. bool pending;
  2706. u8 *buf;
  2707. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2708. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2709. struct brcmf_sdio *bus = sdiodev->bus;
  2710. brcmf_dbg(TRACE, "Enter\n");
  2711. if (sdiodev->state != BRCMF_SDIOD_DATA)
  2712. return -EIO;
  2713. /* Wait until control frame is available */
  2714. timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2715. spin_lock_bh(&bus->rxctl_lock);
  2716. rxlen = bus->rxlen;
  2717. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2718. bus->rxctl = NULL;
  2719. buf = bus->rxctl_orig;
  2720. bus->rxctl_orig = NULL;
  2721. bus->rxlen = 0;
  2722. spin_unlock_bh(&bus->rxctl_lock);
  2723. vfree(buf);
  2724. if (rxlen) {
  2725. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2726. rxlen, msglen);
  2727. } else if (timeleft == 0) {
  2728. brcmf_err("resumed on timeout\n");
  2729. brcmf_sdio_checkdied(bus);
  2730. } else if (pending) {
  2731. brcmf_dbg(CTL, "cancelled\n");
  2732. return -ERESTARTSYS;
  2733. } else {
  2734. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2735. brcmf_sdio_checkdied(bus);
  2736. }
  2737. if (rxlen)
  2738. bus->sdcnt.rx_ctlpkts++;
  2739. else
  2740. bus->sdcnt.rx_ctlerrs++;
  2741. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2742. }
  2743. #ifdef DEBUG
  2744. static bool
  2745. brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
  2746. u8 *ram_data, uint ram_sz)
  2747. {
  2748. char *ram_cmp;
  2749. int err;
  2750. bool ret = true;
  2751. int address;
  2752. int offset;
  2753. int len;
  2754. /* read back and verify */
  2755. brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
  2756. ram_sz);
  2757. ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
  2758. /* do not proceed while no memory but */
  2759. if (!ram_cmp)
  2760. return true;
  2761. address = ram_addr;
  2762. offset = 0;
  2763. while (offset < ram_sz) {
  2764. len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
  2765. ram_sz - offset;
  2766. err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
  2767. if (err) {
  2768. brcmf_err("error %d on reading %d membytes at 0x%08x\n",
  2769. err, len, address);
  2770. ret = false;
  2771. break;
  2772. } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
  2773. brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
  2774. offset, len);
  2775. ret = false;
  2776. break;
  2777. }
  2778. offset += len;
  2779. address += len;
  2780. }
  2781. kfree(ram_cmp);
  2782. return ret;
  2783. }
  2784. #else /* DEBUG */
  2785. static bool
  2786. brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
  2787. u8 *ram_data, uint ram_sz)
  2788. {
  2789. return true;
  2790. }
  2791. #endif /* DEBUG */
  2792. static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
  2793. const struct firmware *fw)
  2794. {
  2795. int err;
  2796. brcmf_dbg(TRACE, "Enter\n");
  2797. err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
  2798. (u8 *)fw->data, fw->size);
  2799. if (err)
  2800. brcmf_err("error %d on writing %d membytes at 0x%08x\n",
  2801. err, (int)fw->size, bus->ci->rambase);
  2802. else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
  2803. (u8 *)fw->data, fw->size))
  2804. err = -EIO;
  2805. return err;
  2806. }
  2807. static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
  2808. void *vars, u32 varsz)
  2809. {
  2810. int address;
  2811. int err;
  2812. brcmf_dbg(TRACE, "Enter\n");
  2813. address = bus->ci->ramsize - varsz + bus->ci->rambase;
  2814. err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
  2815. if (err)
  2816. brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
  2817. err, varsz, address);
  2818. else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
  2819. err = -EIO;
  2820. return err;
  2821. }
  2822. static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
  2823. const struct firmware *fw,
  2824. void *nvram, u32 nvlen)
  2825. {
  2826. int bcmerror;
  2827. u32 rstvec;
  2828. sdio_claim_host(bus->sdiodev->func1);
  2829. brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
  2830. rstvec = get_unaligned_le32(fw->data);
  2831. brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
  2832. bcmerror = brcmf_sdio_download_code_file(bus, fw);
  2833. release_firmware(fw);
  2834. if (bcmerror) {
  2835. brcmf_err("dongle image file download failed\n");
  2836. brcmf_fw_nvram_free(nvram);
  2837. goto err;
  2838. }
  2839. bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
  2840. brcmf_fw_nvram_free(nvram);
  2841. if (bcmerror) {
  2842. brcmf_err("dongle nvram file download failed\n");
  2843. goto err;
  2844. }
  2845. /* Take arm out of reset */
  2846. if (!brcmf_chip_set_active(bus->ci, rstvec)) {
  2847. brcmf_err("error getting out of ARM core reset\n");
  2848. goto err;
  2849. }
  2850. err:
  2851. brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
  2852. sdio_release_host(bus->sdiodev->func1);
  2853. return bcmerror;
  2854. }
  2855. static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
  2856. {
  2857. int err = 0;
  2858. u8 val;
  2859. brcmf_dbg(TRACE, "Enter\n");
  2860. val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
  2861. if (err) {
  2862. brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
  2863. return;
  2864. }
  2865. val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
  2866. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
  2867. if (err) {
  2868. brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
  2869. return;
  2870. }
  2871. /* Add CMD14 Support */
  2872. brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
  2873. (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
  2874. SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
  2875. &err);
  2876. if (err) {
  2877. brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
  2878. return;
  2879. }
  2880. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  2881. SBSDIO_FORCE_HT, &err);
  2882. if (err) {
  2883. brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
  2884. return;
  2885. }
  2886. /* set flag */
  2887. bus->sr_enabled = true;
  2888. brcmf_dbg(INFO, "SR enabled\n");
  2889. }
  2890. /* enable KSO bit */
  2891. static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
  2892. {
  2893. struct brcmf_core *core = bus->sdio_core;
  2894. u8 val;
  2895. int err = 0;
  2896. brcmf_dbg(TRACE, "Enter\n");
  2897. /* KSO bit added in SDIO core rev 12 */
  2898. if (core->rev < 12)
  2899. return 0;
  2900. val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
  2901. if (err) {
  2902. brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
  2903. return err;
  2904. }
  2905. if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
  2906. val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
  2907. SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
  2908. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  2909. val, &err);
  2910. if (err) {
  2911. brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
  2912. return err;
  2913. }
  2914. }
  2915. return 0;
  2916. }
  2917. static int brcmf_sdio_bus_preinit(struct device *dev)
  2918. {
  2919. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2920. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2921. struct brcmf_sdio *bus = sdiodev->bus;
  2922. struct brcmf_core *core = bus->sdio_core;
  2923. uint pad_size;
  2924. u32 value;
  2925. int err;
  2926. /* maxctl provided by common layer */
  2927. if (WARN_ON(!bus_if->maxctl))
  2928. return -EINVAL;
  2929. /* Allocate control receive buffer */
  2930. bus_if->maxctl += bus->roundup;
  2931. value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT);
  2932. value += bus->head_align;
  2933. bus->rxbuf = kmalloc(value, GFP_ATOMIC);
  2934. if (bus->rxbuf)
  2935. bus->rxblen = value;
  2936. brcmf_sdio_debugfs_create(bus);
  2937. /* the commands below use the terms tx and rx from
  2938. * a device perspective, ie. bus:txglom affects the
  2939. * bus transfers from device to host.
  2940. */
  2941. if (core->rev < 12) {
  2942. /* for sdio core rev < 12, disable txgloming */
  2943. value = 0;
  2944. err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
  2945. sizeof(u32));
  2946. } else {
  2947. /* otherwise, set txglomalign */
  2948. value = sdiodev->settings->bus.sdio.sd_sgentry_align;
  2949. /* SDIO ADMA requires at least 32 bit alignment */
  2950. value = max_t(u32, value, ALIGNMENT);
  2951. err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
  2952. sizeof(u32));
  2953. }
  2954. if (err < 0)
  2955. goto done;
  2956. bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
  2957. if (sdiodev->sg_support) {
  2958. bus->txglom = false;
  2959. value = 1;
  2960. pad_size = bus->sdiodev->func2->cur_blksize << 1;
  2961. err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
  2962. &value, sizeof(u32));
  2963. if (err < 0) {
  2964. /* bus:rxglom is allowed to fail */
  2965. err = 0;
  2966. } else {
  2967. bus->txglom = true;
  2968. bus->tx_hdrlen += SDPCM_HWEXT_LEN;
  2969. }
  2970. }
  2971. brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
  2972. done:
  2973. return err;
  2974. }
  2975. static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
  2976. {
  2977. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2978. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2979. struct brcmf_sdio *bus = sdiodev->bus;
  2980. return bus->ci->ramsize - bus->ci->srsize;
  2981. }
  2982. static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
  2983. size_t mem_size)
  2984. {
  2985. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2986. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2987. struct brcmf_sdio *bus = sdiodev->bus;
  2988. int err;
  2989. int address;
  2990. int offset;
  2991. int len;
  2992. brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
  2993. mem_size);
  2994. address = bus->ci->rambase;
  2995. offset = err = 0;
  2996. sdio_claim_host(sdiodev->func1);
  2997. while (offset < mem_size) {
  2998. len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
  2999. mem_size - offset;
  3000. err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
  3001. if (err) {
  3002. brcmf_err("error %d on reading %d membytes at 0x%08x\n",
  3003. err, len, address);
  3004. goto done;
  3005. }
  3006. data += len;
  3007. offset += len;
  3008. address += len;
  3009. }
  3010. done:
  3011. sdio_release_host(sdiodev->func1);
  3012. return err;
  3013. }
  3014. void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
  3015. {
  3016. if (!bus->dpc_triggered) {
  3017. bus->dpc_triggered = true;
  3018. queue_work(bus->brcmf_wq, &bus->datawork);
  3019. }
  3020. }
  3021. void brcmf_sdio_isr(struct brcmf_sdio *bus)
  3022. {
  3023. brcmf_dbg(TRACE, "Enter\n");
  3024. if (!bus) {
  3025. brcmf_err("bus is null pointer, exiting\n");
  3026. return;
  3027. }
  3028. /* Count the interrupt call */
  3029. bus->sdcnt.intrcount++;
  3030. if (in_interrupt())
  3031. atomic_set(&bus->ipend, 1);
  3032. else
  3033. if (brcmf_sdio_intr_rstatus(bus)) {
  3034. brcmf_err("failed backplane access\n");
  3035. }
  3036. /* Disable additional interrupts (is this needed now)? */
  3037. if (!bus->intr)
  3038. brcmf_err("isr w/o interrupt configured!\n");
  3039. bus->dpc_triggered = true;
  3040. queue_work(bus->brcmf_wq, &bus->datawork);
  3041. }
  3042. static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
  3043. {
  3044. brcmf_dbg(TIMER, "Enter\n");
  3045. /* Poll period: check device if appropriate. */
  3046. if (!bus->sr_enabled &&
  3047. bus->poll && (++bus->polltick >= bus->pollrate)) {
  3048. u32 intstatus = 0;
  3049. /* Reset poll tick */
  3050. bus->polltick = 0;
  3051. /* Check device if no interrupts */
  3052. if (!bus->intr ||
  3053. (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
  3054. if (!bus->dpc_triggered) {
  3055. u8 devpend;
  3056. sdio_claim_host(bus->sdiodev->func1);
  3057. devpend = brcmf_sdiod_func0_rb(bus->sdiodev,
  3058. SDIO_CCCR_INTx, NULL);
  3059. sdio_release_host(bus->sdiodev->func1);
  3060. intstatus = devpend & (INTR_STATUS_FUNC1 |
  3061. INTR_STATUS_FUNC2);
  3062. }
  3063. /* If there is something, make like the ISR and
  3064. schedule the DPC */
  3065. if (intstatus) {
  3066. bus->sdcnt.pollcnt++;
  3067. atomic_set(&bus->ipend, 1);
  3068. bus->dpc_triggered = true;
  3069. queue_work(bus->brcmf_wq, &bus->datawork);
  3070. }
  3071. }
  3072. /* Update interrupt tracking */
  3073. bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
  3074. }
  3075. #ifdef DEBUG
  3076. /* Poll for console output periodically */
  3077. if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
  3078. bus->console_interval != 0) {
  3079. bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
  3080. if (bus->console.count >= bus->console_interval) {
  3081. bus->console.count -= bus->console_interval;
  3082. sdio_claim_host(bus->sdiodev->func1);
  3083. /* Make sure backplane clock is on */
  3084. brcmf_sdio_bus_sleep(bus, false, false);
  3085. if (brcmf_sdio_readconsole(bus) < 0)
  3086. /* stop on error */
  3087. bus->console_interval = 0;
  3088. sdio_release_host(bus->sdiodev->func1);
  3089. }
  3090. }
  3091. #endif /* DEBUG */
  3092. /* On idle timeout clear activity flag and/or turn off clock */
  3093. if (!bus->dpc_triggered) {
  3094. rmb();
  3095. if ((!bus->dpc_running) && (bus->idletime > 0) &&
  3096. (bus->clkstate == CLK_AVAIL)) {
  3097. bus->idlecount++;
  3098. if (bus->idlecount > bus->idletime) {
  3099. brcmf_dbg(SDIO, "idle\n");
  3100. sdio_claim_host(bus->sdiodev->func1);
  3101. brcmf_sdio_wd_timer(bus, false);
  3102. bus->idlecount = 0;
  3103. brcmf_sdio_bus_sleep(bus, true, false);
  3104. sdio_release_host(bus->sdiodev->func1);
  3105. }
  3106. } else {
  3107. bus->idlecount = 0;
  3108. }
  3109. } else {
  3110. bus->idlecount = 0;
  3111. }
  3112. }
  3113. static void brcmf_sdio_dataworker(struct work_struct *work)
  3114. {
  3115. struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
  3116. datawork);
  3117. bus->dpc_running = true;
  3118. wmb();
  3119. while (READ_ONCE(bus->dpc_triggered)) {
  3120. bus->dpc_triggered = false;
  3121. brcmf_sdio_dpc(bus);
  3122. bus->idlecount = 0;
  3123. }
  3124. bus->dpc_running = false;
  3125. if (brcmf_sdiod_freezing(bus->sdiodev)) {
  3126. brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
  3127. brcmf_sdiod_try_freeze(bus->sdiodev);
  3128. brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
  3129. }
  3130. }
  3131. static void
  3132. brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
  3133. struct brcmf_chip *ci, u32 drivestrength)
  3134. {
  3135. const struct sdiod_drive_str *str_tab = NULL;
  3136. u32 str_mask;
  3137. u32 str_shift;
  3138. u32 i;
  3139. u32 drivestrength_sel = 0;
  3140. u32 cc_data_temp;
  3141. u32 addr;
  3142. if (!(ci->cc_caps & CC_CAP_PMU))
  3143. return;
  3144. switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
  3145. case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
  3146. str_tab = sdiod_drvstr_tab1_1v8;
  3147. str_mask = 0x00003800;
  3148. str_shift = 11;
  3149. break;
  3150. case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
  3151. str_tab = sdiod_drvstr_tab6_1v8;
  3152. str_mask = 0x00001800;
  3153. str_shift = 11;
  3154. break;
  3155. case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
  3156. /* note: 43143 does not support tristate */
  3157. i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
  3158. if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
  3159. str_tab = sdiod_drvstr_tab2_3v3;
  3160. str_mask = 0x00000007;
  3161. str_shift = 0;
  3162. } else
  3163. brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
  3164. ci->name, drivestrength);
  3165. break;
  3166. case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
  3167. str_tab = sdiod_drive_strength_tab5_1v8;
  3168. str_mask = 0x00003800;
  3169. str_shift = 11;
  3170. break;
  3171. default:
  3172. brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
  3173. ci->name, ci->chiprev, ci->pmurev);
  3174. break;
  3175. }
  3176. if (str_tab != NULL) {
  3177. struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
  3178. for (i = 0; str_tab[i].strength != 0; i++) {
  3179. if (drivestrength >= str_tab[i].strength) {
  3180. drivestrength_sel = str_tab[i].sel;
  3181. break;
  3182. }
  3183. }
  3184. addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
  3185. brcmf_sdiod_writel(sdiodev, addr, 1, NULL);
  3186. cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL);
  3187. cc_data_temp &= ~str_mask;
  3188. drivestrength_sel <<= str_shift;
  3189. cc_data_temp |= drivestrength_sel;
  3190. brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL);
  3191. brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
  3192. str_tab[i].strength, drivestrength, cc_data_temp);
  3193. }
  3194. }
  3195. static int brcmf_sdio_buscoreprep(void *ctx)
  3196. {
  3197. struct brcmf_sdio_dev *sdiodev = ctx;
  3198. int err = 0;
  3199. u8 clkval, clkset;
  3200. /* Try forcing SDIO core to do ALPAvail request only */
  3201. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
  3202. brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  3203. if (err) {
  3204. brcmf_err("error writing for HT off\n");
  3205. return err;
  3206. }
  3207. /* If register supported, wait for ALPAvail and then force ALP */
  3208. /* This may take up to 15 milliseconds */
  3209. clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
  3210. if ((clkval & ~SBSDIO_AVBITS) != clkset) {
  3211. brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
  3212. clkset, clkval);
  3213. return -EACCES;
  3214. }
  3215. SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  3216. NULL)),
  3217. !SBSDIO_ALPAV(clkval)),
  3218. PMU_MAX_TRANSITION_DLY);
  3219. if (!SBSDIO_ALPAV(clkval)) {
  3220. brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
  3221. clkval);
  3222. return -EBUSY;
  3223. }
  3224. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
  3225. brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  3226. udelay(65);
  3227. /* Also, disable the extra SDIO pull-ups */
  3228. brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
  3229. return 0;
  3230. }
  3231. static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
  3232. u32 rstvec)
  3233. {
  3234. struct brcmf_sdio_dev *sdiodev = ctx;
  3235. struct brcmf_core *core = sdiodev->bus->sdio_core;
  3236. u32 reg_addr;
  3237. /* clear all interrupts */
  3238. reg_addr = core->base + SD_REG(intstatus);
  3239. brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
  3240. if (rstvec)
  3241. /* Write reset vector to address 0 */
  3242. brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
  3243. sizeof(rstvec));
  3244. }
  3245. static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
  3246. {
  3247. struct brcmf_sdio_dev *sdiodev = ctx;
  3248. u32 val, rev;
  3249. val = brcmf_sdiod_readl(sdiodev, addr, NULL);
  3250. /*
  3251. * this is a bit of special handling if reading the chipcommon chipid
  3252. * register. The 4339 is a next-gen of the 4335. It uses the same
  3253. * SDIO device id as 4335 and the chipid register returns 4335 as well.
  3254. * It can be identified as 4339 by looking at the chip revision. It
  3255. * is corrected here so the chip.c module has the right info.
  3256. */
  3257. if (addr == CORE_CC_REG(SI_ENUM_BASE, chipid) &&
  3258. (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 ||
  3259. sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) {
  3260. rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
  3261. if (rev >= 2) {
  3262. val &= ~CID_ID_MASK;
  3263. val |= BRCM_CC_4339_CHIP_ID;
  3264. }
  3265. }
  3266. return val;
  3267. }
  3268. static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
  3269. {
  3270. struct brcmf_sdio_dev *sdiodev = ctx;
  3271. brcmf_sdiod_writel(sdiodev, addr, val, NULL);
  3272. }
  3273. static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
  3274. .prepare = brcmf_sdio_buscoreprep,
  3275. .activate = brcmf_sdio_buscore_activate,
  3276. .read32 = brcmf_sdio_buscore_read32,
  3277. .write32 = brcmf_sdio_buscore_write32,
  3278. };
  3279. static bool
  3280. brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
  3281. {
  3282. struct brcmf_sdio_dev *sdiodev;
  3283. u8 clkctl = 0;
  3284. int err = 0;
  3285. int reg_addr;
  3286. u32 reg_val;
  3287. u32 drivestrength;
  3288. sdiodev = bus->sdiodev;
  3289. sdio_claim_host(sdiodev->func1);
  3290. pr_debug("F1 signature read @0x18000000=0x%4x\n",
  3291. brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL));
  3292. /*
  3293. * Force PLL off until brcmf_chip_attach()
  3294. * programs PLL control regs
  3295. */
  3296. brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1,
  3297. &err);
  3298. if (!err)
  3299. clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  3300. &err);
  3301. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3302. brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3303. err, BRCMF_INIT_CLKCTL1, clkctl);
  3304. goto fail;
  3305. }
  3306. bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
  3307. if (IS_ERR(bus->ci)) {
  3308. brcmf_err("brcmf_chip_attach failed!\n");
  3309. bus->ci = NULL;
  3310. goto fail;
  3311. }
  3312. /* Pick up the SDIO core info struct from chip.c */
  3313. bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  3314. if (!bus->sdio_core)
  3315. goto fail;
  3316. /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */
  3317. sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON);
  3318. if (!sdiodev->cc_core)
  3319. goto fail;
  3320. sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
  3321. BRCMF_BUSTYPE_SDIO,
  3322. bus->ci->chip,
  3323. bus->ci->chiprev);
  3324. if (!sdiodev->settings) {
  3325. brcmf_err("Failed to get device parameters\n");
  3326. goto fail;
  3327. }
  3328. /* platform specific configuration:
  3329. * alignments must be at least 4 bytes for ADMA
  3330. */
  3331. bus->head_align = ALIGNMENT;
  3332. bus->sgentry_align = ALIGNMENT;
  3333. if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
  3334. bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
  3335. if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
  3336. bus->sgentry_align =
  3337. sdiodev->settings->bus.sdio.sd_sgentry_align;
  3338. /* allocate scatter-gather table. sg support
  3339. * will be disabled upon allocation failure.
  3340. */
  3341. brcmf_sdiod_sgtable_alloc(sdiodev);
  3342. #ifdef CONFIG_PM_SLEEP
  3343. /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
  3344. * is true or when platform data OOB irq is true).
  3345. */
  3346. if ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) &&
  3347. ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) ||
  3348. (sdiodev->settings->bus.sdio.oob_irq_supported)))
  3349. sdiodev->bus_if->wowl_supported = true;
  3350. #endif
  3351. if (brcmf_sdio_kso_init(bus)) {
  3352. brcmf_err("error enabling KSO\n");
  3353. goto fail;
  3354. }
  3355. if (sdiodev->settings->bus.sdio.drive_strength)
  3356. drivestrength = sdiodev->settings->bus.sdio.drive_strength;
  3357. else
  3358. drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
  3359. brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
  3360. /* Set card control so an SDIO card reset does a WLAN backplane reset */
  3361. reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
  3362. if (err)
  3363. goto fail;
  3364. reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
  3365. brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
  3366. if (err)
  3367. goto fail;
  3368. /* set PMUControl so a backplane reset does PMU state reload */
  3369. reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
  3370. reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err);
  3371. if (err)
  3372. goto fail;
  3373. reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
  3374. brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err);
  3375. if (err)
  3376. goto fail;
  3377. sdio_release_host(sdiodev->func1);
  3378. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3379. /* allocate header buffer */
  3380. bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
  3381. if (!bus->hdrbuf)
  3382. return false;
  3383. /* Locate an appropriately-aligned portion of hdrbuf */
  3384. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3385. bus->head_align);
  3386. /* Set the poll and/or interrupt flags */
  3387. bus->intr = true;
  3388. bus->poll = false;
  3389. if (bus->poll)
  3390. bus->pollrate = 1;
  3391. return true;
  3392. fail:
  3393. sdio_release_host(sdiodev->func1);
  3394. return false;
  3395. }
  3396. static int
  3397. brcmf_sdio_watchdog_thread(void *data)
  3398. {
  3399. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3400. int wait;
  3401. allow_signal(SIGTERM);
  3402. /* Run until signal received */
  3403. brcmf_sdiod_freezer_count(bus->sdiodev);
  3404. while (1) {
  3405. if (kthread_should_stop())
  3406. break;
  3407. brcmf_sdiod_freezer_uncount(bus->sdiodev);
  3408. wait = wait_for_completion_interruptible(&bus->watchdog_wait);
  3409. brcmf_sdiod_freezer_count(bus->sdiodev);
  3410. brcmf_sdiod_try_freeze(bus->sdiodev);
  3411. if (!wait) {
  3412. brcmf_sdio_bus_watchdog(bus);
  3413. /* Count the tick for reference */
  3414. bus->sdcnt.tickcnt++;
  3415. reinit_completion(&bus->watchdog_wait);
  3416. } else
  3417. break;
  3418. }
  3419. return 0;
  3420. }
  3421. static void
  3422. brcmf_sdio_watchdog(struct timer_list *t)
  3423. {
  3424. struct brcmf_sdio *bus = from_timer(bus, t, timer);
  3425. if (bus->watchdog_tsk) {
  3426. complete(&bus->watchdog_wait);
  3427. /* Reschedule the watchdog */
  3428. if (bus->wd_active)
  3429. mod_timer(&bus->timer,
  3430. jiffies + BRCMF_WD_POLL);
  3431. }
  3432. }
  3433. static
  3434. int brcmf_sdio_get_fwname(struct device *dev, const char *ext, u8 *fw_name)
  3435. {
  3436. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  3437. struct brcmf_fw_request *fwreq;
  3438. struct brcmf_fw_name fwnames[] = {
  3439. { ext, fw_name },
  3440. };
  3441. fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev,
  3442. brcmf_sdio_fwnames,
  3443. ARRAY_SIZE(brcmf_sdio_fwnames),
  3444. fwnames, ARRAY_SIZE(fwnames));
  3445. if (!fwreq)
  3446. return -ENOMEM;
  3447. kfree(fwreq);
  3448. return 0;
  3449. }
  3450. static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
  3451. .stop = brcmf_sdio_bus_stop,
  3452. .preinit = brcmf_sdio_bus_preinit,
  3453. .txdata = brcmf_sdio_bus_txdata,
  3454. .txctl = brcmf_sdio_bus_txctl,
  3455. .rxctl = brcmf_sdio_bus_rxctl,
  3456. .gettxq = brcmf_sdio_bus_gettxq,
  3457. .wowl_config = brcmf_sdio_wowl_config,
  3458. .get_ramsize = brcmf_sdio_bus_get_ramsize,
  3459. .get_memdump = brcmf_sdio_bus_get_memdump,
  3460. .get_fwname = brcmf_sdio_get_fwname,
  3461. };
  3462. #define BRCMF_SDIO_FW_CODE 0
  3463. #define BRCMF_SDIO_FW_NVRAM 1
  3464. static void brcmf_sdio_firmware_callback(struct device *dev, int err,
  3465. struct brcmf_fw_request *fwreq)
  3466. {
  3467. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  3468. struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio;
  3469. struct brcmf_sdio *bus = sdiod->bus;
  3470. struct brcmf_core *core = bus->sdio_core;
  3471. const struct firmware *code;
  3472. void *nvram;
  3473. u32 nvram_len;
  3474. u8 saveclk;
  3475. brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
  3476. if (err)
  3477. goto fail;
  3478. code = fwreq->items[BRCMF_SDIO_FW_CODE].binary;
  3479. nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data;
  3480. nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len;
  3481. kfree(fwreq);
  3482. /* try to download image and nvram to the dongle */
  3483. bus->alp_only = true;
  3484. err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
  3485. if (err)
  3486. goto fail;
  3487. bus->alp_only = false;
  3488. /* Start the watchdog timer */
  3489. bus->sdcnt.tickcnt = 0;
  3490. brcmf_sdio_wd_timer(bus, true);
  3491. sdio_claim_host(sdiod->func1);
  3492. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  3493. brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
  3494. if (bus->clkstate != CLK_AVAIL)
  3495. goto release;
  3496. /* Force clocks on backplane to be sure F2 interrupt propagates */
  3497. saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3498. if (!err) {
  3499. brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
  3500. (saveclk | SBSDIO_FORCE_HT), &err);
  3501. }
  3502. if (err) {
  3503. brcmf_err("Failed to force clock for F2: err %d\n", err);
  3504. goto release;
  3505. }
  3506. /* Enable function 2 (frame transfers) */
  3507. brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata),
  3508. SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL);
  3509. err = sdio_enable_func(sdiod->func2);
  3510. brcmf_dbg(INFO, "enable F2: err=%d\n", err);
  3511. /* If F2 successfully enabled, set core and enable interrupts */
  3512. if (!err) {
  3513. /* Set up the interrupt mask and enable interrupts */
  3514. bus->hostintmask = HOSTINTMASK;
  3515. brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask),
  3516. bus->hostintmask, NULL);
  3517. brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 8, &err);
  3518. } else {
  3519. /* Disable F2 again */
  3520. sdio_disable_func(sdiod->func2);
  3521. goto release;
  3522. }
  3523. if (brcmf_chip_sr_capable(bus->ci)) {
  3524. brcmf_sdio_sr_init(bus);
  3525. } else {
  3526. /* Restore previous clock setting */
  3527. brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
  3528. saveclk, &err);
  3529. }
  3530. if (err == 0) {
  3531. /* Allow full data communication using DPC from now on. */
  3532. brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
  3533. err = brcmf_sdiod_intr_register(sdiod);
  3534. if (err != 0)
  3535. brcmf_err("intr register failed:%d\n", err);
  3536. }
  3537. /* If we didn't come up, turn off backplane clock */
  3538. if (err != 0)
  3539. brcmf_sdio_clkctl(bus, CLK_NONE, false);
  3540. sdio_release_host(sdiod->func1);
  3541. /* Assign bus interface call back */
  3542. sdiod->bus_if->dev = sdiod->dev;
  3543. sdiod->bus_if->ops = &brcmf_sdio_bus_ops;
  3544. sdiod->bus_if->chip = bus->ci->chip;
  3545. sdiod->bus_if->chiprev = bus->ci->chiprev;
  3546. /* Attach to the common layer, reserve hdr space */
  3547. err = brcmf_attach(sdiod->dev, sdiod->settings);
  3548. if (err != 0) {
  3549. brcmf_err("brcmf_attach failed\n");
  3550. goto fail;
  3551. }
  3552. /* ready */
  3553. return;
  3554. release:
  3555. sdio_release_host(sdiod->func1);
  3556. fail:
  3557. brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
  3558. device_release_driver(&sdiod->func2->dev);
  3559. device_release_driver(dev);
  3560. }
  3561. static struct brcmf_fw_request *
  3562. brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus)
  3563. {
  3564. struct brcmf_fw_request *fwreq;
  3565. struct brcmf_fw_name fwnames[] = {
  3566. { ".bin", bus->sdiodev->fw_name },
  3567. { ".txt", bus->sdiodev->nvram_name },
  3568. };
  3569. fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev,
  3570. brcmf_sdio_fwnames,
  3571. ARRAY_SIZE(brcmf_sdio_fwnames),
  3572. fwnames, ARRAY_SIZE(fwnames));
  3573. if (!fwreq)
  3574. return NULL;
  3575. fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
  3576. fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
  3577. return fwreq;
  3578. }
  3579. struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
  3580. {
  3581. int ret;
  3582. struct brcmf_sdio *bus;
  3583. struct workqueue_struct *wq;
  3584. struct brcmf_fw_request *fwreq;
  3585. brcmf_dbg(TRACE, "Enter\n");
  3586. /* Allocate private bus interface state */
  3587. bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
  3588. if (!bus)
  3589. goto fail;
  3590. bus->sdiodev = sdiodev;
  3591. sdiodev->bus = bus;
  3592. skb_queue_head_init(&bus->glom);
  3593. bus->txbound = BRCMF_TXBOUND;
  3594. bus->rxbound = BRCMF_RXBOUND;
  3595. bus->txminmax = BRCMF_TXMINMAX;
  3596. bus->tx_seq = SDPCM_SEQ_WRAP - 1;
  3597. /* single-threaded workqueue */
  3598. wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
  3599. dev_name(&sdiodev->func1->dev));
  3600. if (!wq) {
  3601. brcmf_err("insufficient memory to create txworkqueue\n");
  3602. goto fail;
  3603. }
  3604. brcmf_sdiod_freezer_count(sdiodev);
  3605. INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
  3606. bus->brcmf_wq = wq;
  3607. /* attempt to attach to the dongle */
  3608. if (!(brcmf_sdio_probe_attach(bus))) {
  3609. brcmf_err("brcmf_sdio_probe_attach failed\n");
  3610. goto fail;
  3611. }
  3612. spin_lock_init(&bus->rxctl_lock);
  3613. spin_lock_init(&bus->txq_lock);
  3614. init_waitqueue_head(&bus->ctrl_wait);
  3615. init_waitqueue_head(&bus->dcmd_resp_wait);
  3616. /* Set up the watchdog timer */
  3617. timer_setup(&bus->timer, brcmf_sdio_watchdog, 0);
  3618. /* Initialize watchdog thread */
  3619. init_completion(&bus->watchdog_wait);
  3620. bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
  3621. bus, "brcmf_wdog/%s",
  3622. dev_name(&sdiodev->func1->dev));
  3623. if (IS_ERR(bus->watchdog_tsk)) {
  3624. pr_warn("brcmf_watchdog thread failed to start\n");
  3625. bus->watchdog_tsk = NULL;
  3626. }
  3627. /* Initialize DPC thread */
  3628. bus->dpc_triggered = false;
  3629. bus->dpc_running = false;
  3630. /* default sdio bus header length for tx packet */
  3631. bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
  3632. /* Query the F2 block size, set roundup accordingly */
  3633. bus->blocksize = bus->sdiodev->func2->cur_blksize;
  3634. bus->roundup = min(max_roundup, bus->blocksize);
  3635. sdio_claim_host(bus->sdiodev->func1);
  3636. /* Disable F2 to clear any intermediate frame state on the dongle */
  3637. sdio_disable_func(bus->sdiodev->func2);
  3638. bus->rxflow = false;
  3639. /* Done with backplane-dependent accesses, can drop clock... */
  3640. brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3641. sdio_release_host(bus->sdiodev->func1);
  3642. /* ...and initialize clock/power states */
  3643. bus->clkstate = CLK_SDONLY;
  3644. bus->idletime = BRCMF_IDLE_INTERVAL;
  3645. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3646. /* SR state */
  3647. bus->sr_enabled = false;
  3648. brcmf_dbg(INFO, "completed!!\n");
  3649. fwreq = brcmf_sdio_prepare_fw_request(bus);
  3650. if (!fwreq) {
  3651. ret = -ENOMEM;
  3652. goto fail;
  3653. }
  3654. ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq,
  3655. brcmf_sdio_firmware_callback);
  3656. if (ret != 0) {
  3657. brcmf_err("async firmware request failed: %d\n", ret);
  3658. kfree(fwreq);
  3659. goto fail;
  3660. }
  3661. return bus;
  3662. fail:
  3663. brcmf_sdio_remove(bus);
  3664. return NULL;
  3665. }
  3666. /* Detach and free everything */
  3667. void brcmf_sdio_remove(struct brcmf_sdio *bus)
  3668. {
  3669. brcmf_dbg(TRACE, "Enter\n");
  3670. if (bus) {
  3671. /* De-register interrupt handler */
  3672. brcmf_sdiod_intr_unregister(bus->sdiodev);
  3673. brcmf_detach(bus->sdiodev->dev);
  3674. cancel_work_sync(&bus->datawork);
  3675. if (bus->brcmf_wq)
  3676. destroy_workqueue(bus->brcmf_wq);
  3677. if (bus->ci) {
  3678. if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
  3679. sdio_claim_host(bus->sdiodev->func1);
  3680. brcmf_sdio_wd_timer(bus, false);
  3681. brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
  3682. /* Leave the device in state where it is
  3683. * 'passive'. This is done by resetting all
  3684. * necessary cores.
  3685. */
  3686. msleep(20);
  3687. brcmf_chip_set_passive(bus->ci);
  3688. brcmf_sdio_clkctl(bus, CLK_NONE, false);
  3689. sdio_release_host(bus->sdiodev->func1);
  3690. }
  3691. brcmf_chip_detach(bus->ci);
  3692. }
  3693. if (bus->sdiodev->settings)
  3694. brcmf_release_module_param(bus->sdiodev->settings);
  3695. kfree(bus->rxbuf);
  3696. kfree(bus->hdrbuf);
  3697. kfree(bus);
  3698. }
  3699. brcmf_dbg(TRACE, "Disconnected\n");
  3700. }
  3701. void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
  3702. {
  3703. /* Totally stop the timer */
  3704. if (!active && bus->wd_active) {
  3705. del_timer_sync(&bus->timer);
  3706. bus->wd_active = false;
  3707. return;
  3708. }
  3709. /* don't start the wd until fw is loaded */
  3710. if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
  3711. return;
  3712. if (active) {
  3713. if (!bus->wd_active) {
  3714. /* Create timer again when watchdog period is
  3715. dynamically changed or in the first instance
  3716. */
  3717. bus->timer.expires = jiffies + BRCMF_WD_POLL;
  3718. add_timer(&bus->timer);
  3719. bus->wd_active = true;
  3720. } else {
  3721. /* Re arm the timer, at last watchdog period */
  3722. mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
  3723. }
  3724. }
  3725. }
  3726. int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
  3727. {
  3728. int ret;
  3729. sdio_claim_host(bus->sdiodev->func1);
  3730. ret = brcmf_sdio_bus_sleep(bus, sleep, false);
  3731. sdio_release_host(bus->sdiodev->func1);
  3732. return ret;
  3733. }