nfp_asm.c 8.6 KB

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  1. /*
  2. * Copyright (C) 2016-2017 Netronome Systems, Inc.
  3. *
  4. * This software is dual licensed under the GNU General License Version 2,
  5. * June 1991 as shown in the file COPYING in the top-level directory of this
  6. * source tree or the BSD 2-Clause License provided below. You have the
  7. * option to license this software under the complete terms of either license.
  8. *
  9. * The BSD 2-Clause License:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * 1. Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * 2. Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/bitops.h>
  34. #include <linux/errno.h>
  35. #include <linux/kernel.h>
  36. #include <linux/string.h>
  37. #include <linux/types.h>
  38. #include "nfp_asm.h"
  39. const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE] = {
  40. [CMD_TGT_WRITE8_SWAP] = { 0x02, 0x42 },
  41. [CMD_TGT_WRITE32_SWAP] = { 0x02, 0x5f },
  42. [CMD_TGT_READ8] = { 0x01, 0x43 },
  43. [CMD_TGT_READ32] = { 0x00, 0x5c },
  44. [CMD_TGT_READ32_LE] = { 0x01, 0x5c },
  45. [CMD_TGT_READ32_SWAP] = { 0x02, 0x5c },
  46. [CMD_TGT_READ_LE] = { 0x01, 0x40 },
  47. [CMD_TGT_READ_SWAP_LE] = { 0x03, 0x40 },
  48. [CMD_TGT_ADD] = { 0x00, 0x47 },
  49. [CMD_TGT_ADD_IMM] = { 0x02, 0x47 },
  50. };
  51. static bool unreg_is_imm(u16 reg)
  52. {
  53. return (reg & UR_REG_IMM) == UR_REG_IMM;
  54. }
  55. u16 br_get_offset(u64 instr)
  56. {
  57. u16 addr_lo, addr_hi;
  58. addr_lo = FIELD_GET(OP_BR_ADDR_LO, instr);
  59. addr_hi = FIELD_GET(OP_BR_ADDR_HI, instr);
  60. return (addr_hi * ((OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)) + 1)) |
  61. addr_lo;
  62. }
  63. void br_set_offset(u64 *instr, u16 offset)
  64. {
  65. u16 addr_lo, addr_hi;
  66. addr_lo = offset & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO));
  67. addr_hi = offset != addr_lo;
  68. *instr &= ~(OP_BR_ADDR_HI | OP_BR_ADDR_LO);
  69. *instr |= FIELD_PREP(OP_BR_ADDR_HI, addr_hi);
  70. *instr |= FIELD_PREP(OP_BR_ADDR_LO, addr_lo);
  71. }
  72. void br_add_offset(u64 *instr, u16 offset)
  73. {
  74. u16 addr;
  75. addr = br_get_offset(*instr);
  76. br_set_offset(instr, addr + offset);
  77. }
  78. static bool immed_can_modify(u64 instr)
  79. {
  80. if (FIELD_GET(OP_IMMED_INV, instr) ||
  81. FIELD_GET(OP_IMMED_SHIFT, instr) ||
  82. FIELD_GET(OP_IMMED_WIDTH, instr) != IMMED_WIDTH_ALL) {
  83. pr_err("Can't decode/encode immed!\n");
  84. return false;
  85. }
  86. return true;
  87. }
  88. u16 immed_get_value(u64 instr)
  89. {
  90. u16 reg;
  91. if (!immed_can_modify(instr))
  92. return 0;
  93. reg = FIELD_GET(OP_IMMED_A_SRC, instr);
  94. if (!unreg_is_imm(reg))
  95. reg = FIELD_GET(OP_IMMED_B_SRC, instr);
  96. return (reg & 0xff) | FIELD_GET(OP_IMMED_IMM, instr) << 8;
  97. }
  98. void immed_set_value(u64 *instr, u16 immed)
  99. {
  100. if (!immed_can_modify(*instr))
  101. return;
  102. if (unreg_is_imm(FIELD_GET(OP_IMMED_A_SRC, *instr))) {
  103. *instr &= ~FIELD_PREP(OP_IMMED_A_SRC, 0xff);
  104. *instr |= FIELD_PREP(OP_IMMED_A_SRC, immed & 0xff);
  105. } else {
  106. *instr &= ~FIELD_PREP(OP_IMMED_B_SRC, 0xff);
  107. *instr |= FIELD_PREP(OP_IMMED_B_SRC, immed & 0xff);
  108. }
  109. *instr &= ~OP_IMMED_IMM;
  110. *instr |= FIELD_PREP(OP_IMMED_IMM, immed >> 8);
  111. }
  112. void immed_add_value(u64 *instr, u16 offset)
  113. {
  114. u16 val;
  115. if (!immed_can_modify(*instr))
  116. return;
  117. val = immed_get_value(*instr);
  118. immed_set_value(instr, val + offset);
  119. }
  120. static u16 nfp_swreg_to_unreg(swreg reg, bool is_dst)
  121. {
  122. bool lm_id, lm_dec = false;
  123. u16 val = swreg_value(reg);
  124. switch (swreg_type(reg)) {
  125. case NN_REG_GPR_A:
  126. case NN_REG_GPR_B:
  127. case NN_REG_GPR_BOTH:
  128. return val;
  129. case NN_REG_NNR:
  130. return UR_REG_NN | val;
  131. case NN_REG_XFER:
  132. return UR_REG_XFR | val;
  133. case NN_REG_LMEM:
  134. lm_id = swreg_lm_idx(reg);
  135. switch (swreg_lm_mode(reg)) {
  136. case NN_LM_MOD_NONE:
  137. if (val & ~UR_REG_LM_IDX_MAX) {
  138. pr_err("LM offset too large\n");
  139. return 0;
  140. }
  141. return UR_REG_LM | FIELD_PREP(UR_REG_LM_IDX, lm_id) |
  142. val;
  143. case NN_LM_MOD_DEC:
  144. lm_dec = true;
  145. /* fall through */
  146. case NN_LM_MOD_INC:
  147. if (val) {
  148. pr_err("LM offset in inc/dev mode\n");
  149. return 0;
  150. }
  151. return UR_REG_LM | UR_REG_LM_POST_MOD |
  152. FIELD_PREP(UR_REG_LM_IDX, lm_id) |
  153. FIELD_PREP(UR_REG_LM_POST_MOD_DEC, lm_dec);
  154. default:
  155. pr_err("bad LM mode for unrestricted operands %d\n",
  156. swreg_lm_mode(reg));
  157. return 0;
  158. }
  159. case NN_REG_IMM:
  160. if (val & ~0xff) {
  161. pr_err("immediate too large\n");
  162. return 0;
  163. }
  164. return UR_REG_IMM_encode(val);
  165. case NN_REG_NONE:
  166. return is_dst ? UR_REG_NO_DST : REG_NONE;
  167. }
  168. pr_err("unrecognized reg encoding %08x\n", reg);
  169. return 0;
  170. }
  171. int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
  172. struct nfp_insn_ur_regs *reg)
  173. {
  174. memset(reg, 0, sizeof(*reg));
  175. /* Decode destination */
  176. if (swreg_type(dst) == NN_REG_IMM)
  177. return -EFAULT;
  178. if (swreg_type(dst) == NN_REG_GPR_B)
  179. reg->dst_ab = ALU_DST_B;
  180. if (swreg_type(dst) == NN_REG_GPR_BOTH)
  181. reg->wr_both = true;
  182. reg->dst = nfp_swreg_to_unreg(dst, true);
  183. /* Decode source operands */
  184. if (swreg_type(lreg) == swreg_type(rreg) &&
  185. swreg_type(lreg) != NN_REG_NONE)
  186. return -EFAULT;
  187. if (swreg_type(lreg) == NN_REG_GPR_B ||
  188. swreg_type(rreg) == NN_REG_GPR_A) {
  189. reg->areg = nfp_swreg_to_unreg(rreg, false);
  190. reg->breg = nfp_swreg_to_unreg(lreg, false);
  191. reg->swap = true;
  192. } else {
  193. reg->areg = nfp_swreg_to_unreg(lreg, false);
  194. reg->breg = nfp_swreg_to_unreg(rreg, false);
  195. }
  196. reg->dst_lmextn = swreg_lmextn(dst);
  197. reg->src_lmextn = swreg_lmextn(lreg) | swreg_lmextn(rreg);
  198. return 0;
  199. }
  200. static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8)
  201. {
  202. u16 val = swreg_value(reg);
  203. bool lm_id;
  204. switch (swreg_type(reg)) {
  205. case NN_REG_GPR_A:
  206. case NN_REG_GPR_B:
  207. case NN_REG_GPR_BOTH:
  208. return val;
  209. case NN_REG_XFER:
  210. return RE_REG_XFR | val;
  211. case NN_REG_LMEM:
  212. lm_id = swreg_lm_idx(reg);
  213. if (swreg_lm_mode(reg) != NN_LM_MOD_NONE) {
  214. pr_err("bad LM mode for restricted operands %d\n",
  215. swreg_lm_mode(reg));
  216. return 0;
  217. }
  218. if (val & ~RE_REG_LM_IDX_MAX) {
  219. pr_err("LM offset too large\n");
  220. return 0;
  221. }
  222. return RE_REG_LM | FIELD_PREP(RE_REG_LM_IDX, lm_id) | val;
  223. case NN_REG_IMM:
  224. if (val & ~(0x7f | has_imm8 << 7)) {
  225. pr_err("immediate too large\n");
  226. return 0;
  227. }
  228. *i8 = val & 0x80;
  229. return RE_REG_IMM_encode(val & 0x7f);
  230. case NN_REG_NONE:
  231. return is_dst ? RE_REG_NO_DST : REG_NONE;
  232. case NN_REG_NNR:
  233. pr_err("NNRs used with restricted encoding\n");
  234. return 0;
  235. }
  236. pr_err("unrecognized reg encoding\n");
  237. return 0;
  238. }
  239. int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
  240. struct nfp_insn_re_regs *reg, bool has_imm8)
  241. {
  242. memset(reg, 0, sizeof(*reg));
  243. /* Decode destination */
  244. if (swreg_type(dst) == NN_REG_IMM)
  245. return -EFAULT;
  246. if (swreg_type(dst) == NN_REG_GPR_B)
  247. reg->dst_ab = ALU_DST_B;
  248. if (swreg_type(dst) == NN_REG_GPR_BOTH)
  249. reg->wr_both = true;
  250. reg->dst = nfp_swreg_to_rereg(dst, true, false, NULL);
  251. /* Decode source operands */
  252. if (swreg_type(lreg) == swreg_type(rreg) &&
  253. swreg_type(lreg) != NN_REG_NONE)
  254. return -EFAULT;
  255. if (swreg_type(lreg) == NN_REG_GPR_B ||
  256. swreg_type(rreg) == NN_REG_GPR_A) {
  257. reg->areg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
  258. reg->breg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
  259. reg->swap = true;
  260. } else {
  261. reg->areg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
  262. reg->breg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
  263. }
  264. reg->dst_lmextn = swreg_lmextn(dst);
  265. reg->src_lmextn = swreg_lmextn(lreg) | swreg_lmextn(rreg);
  266. return 0;
  267. }
  268. #define NFP_USTORE_ECC_POLY_WORDS 7
  269. #define NFP_USTORE_OP_BITS 45
  270. static const u64 nfp_ustore_ecc_polynomials[NFP_USTORE_ECC_POLY_WORDS] = {
  271. 0x0ff800007fffULL,
  272. 0x11f801ff801fULL,
  273. 0x1e387e0781e1ULL,
  274. 0x17cb8e388e22ULL,
  275. 0x1af5b2c93244ULL,
  276. 0x1f56d5525488ULL,
  277. 0x0daf69a46910ULL,
  278. };
  279. static bool parity(u64 value)
  280. {
  281. return hweight64(value) & 1;
  282. }
  283. int nfp_ustore_check_valid_no_ecc(u64 insn)
  284. {
  285. if (insn & ~GENMASK_ULL(NFP_USTORE_OP_BITS, 0))
  286. return -EINVAL;
  287. return 0;
  288. }
  289. u64 nfp_ustore_calc_ecc_insn(u64 insn)
  290. {
  291. u8 ecc = 0;
  292. int i;
  293. for (i = 0; i < NFP_USTORE_ECC_POLY_WORDS; i++)
  294. ecc |= parity(nfp_ustore_ecc_polynomials[i] & insn) << i;
  295. return insn | (u64)ecc << NFP_USTORE_OP_BITS;
  296. }