bnxt_dcb.c 16 KB

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  1. /* Broadcom NetXtreme-C/E network driver.
  2. *
  3. * Copyright (c) 2014-2016 Broadcom Corporation
  4. * Copyright (c) 2016-2017 Broadcom Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/netdevice.h>
  11. #include <linux/types.h>
  12. #include <linux/errno.h>
  13. #include <linux/rtnetlink.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/pci.h>
  16. #include <linux/etherdevice.h>
  17. #include <rdma/ib_verbs.h>
  18. #include "bnxt_hsi.h"
  19. #include "bnxt.h"
  20. #include "bnxt_dcb.h"
  21. #ifdef CONFIG_BNXT_DCB
  22. static int bnxt_hwrm_queue_pri2cos_cfg(struct bnxt *bp, struct ieee_ets *ets)
  23. {
  24. struct hwrm_queue_pri2cos_cfg_input req = {0};
  25. int rc = 0, i;
  26. u8 *pri2cos;
  27. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PRI2COS_CFG, -1, -1);
  28. req.flags = cpu_to_le32(QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR |
  29. QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN);
  30. pri2cos = &req.pri0_cos_queue_id;
  31. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  32. req.enables |= cpu_to_le32(
  33. QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID << i);
  34. pri2cos[i] = bp->q_info[ets->prio_tc[i]].queue_id;
  35. }
  36. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  37. return rc;
  38. }
  39. static int bnxt_hwrm_queue_pri2cos_qcfg(struct bnxt *bp, struct ieee_ets *ets)
  40. {
  41. struct hwrm_queue_pri2cos_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
  42. struct hwrm_queue_pri2cos_qcfg_input req = {0};
  43. int rc = 0;
  44. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
  45. req.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
  46. mutex_lock(&bp->hwrm_cmd_lock);
  47. rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  48. if (!rc) {
  49. u8 *pri2cos = &resp->pri0_cos_queue_id;
  50. int i, j;
  51. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  52. u8 queue_id = pri2cos[i];
  53. for (j = 0; j < bp->max_tc; j++) {
  54. if (bp->q_info[j].queue_id == queue_id) {
  55. ets->prio_tc[i] = j;
  56. break;
  57. }
  58. }
  59. }
  60. }
  61. mutex_unlock(&bp->hwrm_cmd_lock);
  62. return rc;
  63. }
  64. static int bnxt_hwrm_queue_cos2bw_cfg(struct bnxt *bp, struct ieee_ets *ets,
  65. u8 max_tc)
  66. {
  67. struct hwrm_queue_cos2bw_cfg_input req = {0};
  68. struct bnxt_cos2bw_cfg cos2bw;
  69. int rc = 0, i;
  70. void *data;
  71. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_COS2BW_CFG, -1, -1);
  72. data = &req.unused_0;
  73. for (i = 0; i < max_tc; i++, data += sizeof(cos2bw) - 4) {
  74. req.enables |= cpu_to_le32(
  75. QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID << i);
  76. memset(&cos2bw, 0, sizeof(cos2bw));
  77. cos2bw.queue_id = bp->q_info[i].queue_id;
  78. if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_STRICT) {
  79. cos2bw.tsa =
  80. QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP;
  81. cos2bw.pri_lvl = i;
  82. } else {
  83. cos2bw.tsa =
  84. QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS;
  85. cos2bw.bw_weight = ets->tc_tx_bw[i];
  86. /* older firmware requires min_bw to be set to the
  87. * same weight value in percent.
  88. */
  89. cos2bw.min_bw =
  90. cpu_to_le32((ets->tc_tx_bw[i] * 100) |
  91. BW_VALUE_UNIT_PERCENT1_100);
  92. }
  93. memcpy(data, &cos2bw.queue_id, sizeof(cos2bw) - 4);
  94. if (i == 0) {
  95. req.queue_id0 = cos2bw.queue_id;
  96. req.unused_0 = 0;
  97. }
  98. }
  99. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  100. return rc;
  101. }
  102. static int bnxt_hwrm_queue_cos2bw_qcfg(struct bnxt *bp, struct ieee_ets *ets)
  103. {
  104. struct hwrm_queue_cos2bw_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
  105. struct hwrm_queue_cos2bw_qcfg_input req = {0};
  106. struct bnxt_cos2bw_cfg cos2bw;
  107. void *data;
  108. int rc, i;
  109. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_COS2BW_QCFG, -1, -1);
  110. mutex_lock(&bp->hwrm_cmd_lock);
  111. rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  112. if (rc) {
  113. mutex_unlock(&bp->hwrm_cmd_lock);
  114. return rc;
  115. }
  116. data = &resp->queue_id0 + offsetof(struct bnxt_cos2bw_cfg, queue_id);
  117. for (i = 0; i < bp->max_tc; i++, data += sizeof(cos2bw) - 4) {
  118. int j;
  119. memcpy(&cos2bw.queue_id, data, sizeof(cos2bw) - 4);
  120. if (i == 0)
  121. cos2bw.queue_id = resp->queue_id0;
  122. for (j = 0; j < bp->max_tc; j++) {
  123. if (bp->q_info[j].queue_id != cos2bw.queue_id)
  124. continue;
  125. if (cos2bw.tsa ==
  126. QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP) {
  127. ets->tc_tsa[j] = IEEE_8021QAZ_TSA_STRICT;
  128. } else {
  129. ets->tc_tsa[j] = IEEE_8021QAZ_TSA_ETS;
  130. ets->tc_tx_bw[j] = cos2bw.bw_weight;
  131. }
  132. }
  133. }
  134. mutex_unlock(&bp->hwrm_cmd_lock);
  135. return 0;
  136. }
  137. static int bnxt_hwrm_queue_cfg(struct bnxt *bp, unsigned int lltc_mask)
  138. {
  139. struct hwrm_queue_cfg_input req = {0};
  140. int i;
  141. if (netif_running(bp->dev))
  142. bnxt_tx_disable(bp);
  143. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_CFG, -1, -1);
  144. req.flags = cpu_to_le32(QUEUE_CFG_REQ_FLAGS_PATH_BIDIR);
  145. req.enables = cpu_to_le32(QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE);
  146. /* Configure lossless queues to lossy first */
  147. req.service_profile = QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY;
  148. for (i = 0; i < bp->max_tc; i++) {
  149. if (BNXT_LLQ(bp->q_info[i].queue_profile)) {
  150. req.queue_id = cpu_to_le32(bp->q_info[i].queue_id);
  151. hwrm_send_message(bp, &req, sizeof(req),
  152. HWRM_CMD_TIMEOUT);
  153. bp->q_info[i].queue_profile =
  154. QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY;
  155. }
  156. }
  157. /* Now configure desired queues to lossless */
  158. req.service_profile = QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS;
  159. for (i = 0; i < bp->max_tc; i++) {
  160. if (lltc_mask & (1 << i)) {
  161. req.queue_id = cpu_to_le32(bp->q_info[i].queue_id);
  162. hwrm_send_message(bp, &req, sizeof(req),
  163. HWRM_CMD_TIMEOUT);
  164. bp->q_info[i].queue_profile =
  165. QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS;
  166. }
  167. }
  168. if (netif_running(bp->dev))
  169. bnxt_tx_enable(bp);
  170. return 0;
  171. }
  172. static int bnxt_hwrm_queue_pfc_cfg(struct bnxt *bp, struct ieee_pfc *pfc)
  173. {
  174. struct hwrm_queue_pfcenable_cfg_input req = {0};
  175. struct ieee_ets *my_ets = bp->ieee_ets;
  176. unsigned int tc_mask = 0, pri_mask = 0;
  177. u8 i, pri, lltc_count = 0;
  178. bool need_q_recfg = false;
  179. int rc;
  180. if (!my_ets)
  181. return -EINVAL;
  182. for (i = 0; i < bp->max_tc; i++) {
  183. for (pri = 0; pri < IEEE_8021QAZ_MAX_TCS; pri++) {
  184. if ((pfc->pfc_en & (1 << pri)) &&
  185. (my_ets->prio_tc[pri] == i)) {
  186. pri_mask |= 1 << pri;
  187. tc_mask |= 1 << i;
  188. }
  189. }
  190. if (tc_mask & (1 << i))
  191. lltc_count++;
  192. }
  193. if (lltc_count > bp->max_lltc)
  194. return -EINVAL;
  195. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PFCENABLE_CFG, -1, -1);
  196. req.flags = cpu_to_le32(pri_mask);
  197. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  198. if (rc)
  199. return rc;
  200. for (i = 0; i < bp->max_tc; i++) {
  201. if (tc_mask & (1 << i)) {
  202. if (!BNXT_LLQ(bp->q_info[i].queue_profile))
  203. need_q_recfg = true;
  204. }
  205. }
  206. if (need_q_recfg)
  207. rc = bnxt_hwrm_queue_cfg(bp, tc_mask);
  208. return rc;
  209. }
  210. static int bnxt_hwrm_queue_pfc_qcfg(struct bnxt *bp, struct ieee_pfc *pfc)
  211. {
  212. struct hwrm_queue_pfcenable_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
  213. struct hwrm_queue_pfcenable_qcfg_input req = {0};
  214. u8 pri_mask;
  215. int rc;
  216. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PFCENABLE_QCFG, -1, -1);
  217. mutex_lock(&bp->hwrm_cmd_lock);
  218. rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  219. if (rc) {
  220. mutex_unlock(&bp->hwrm_cmd_lock);
  221. return rc;
  222. }
  223. pri_mask = le32_to_cpu(resp->flags);
  224. pfc->pfc_en = pri_mask;
  225. mutex_unlock(&bp->hwrm_cmd_lock);
  226. return 0;
  227. }
  228. static int bnxt_hwrm_set_dcbx_app(struct bnxt *bp, struct dcb_app *app,
  229. bool add)
  230. {
  231. struct hwrm_fw_set_structured_data_input set = {0};
  232. struct hwrm_fw_get_structured_data_input get = {0};
  233. struct hwrm_struct_data_dcbx_app *fw_app;
  234. struct hwrm_struct_hdr *data;
  235. dma_addr_t mapping;
  236. size_t data_len;
  237. int rc, n, i;
  238. if (bp->hwrm_spec_code < 0x10601)
  239. return 0;
  240. n = IEEE_8021QAZ_MAX_TCS;
  241. data_len = sizeof(*data) + sizeof(*fw_app) * n;
  242. data = dma_zalloc_coherent(&bp->pdev->dev, data_len, &mapping,
  243. GFP_KERNEL);
  244. if (!data)
  245. return -ENOMEM;
  246. bnxt_hwrm_cmd_hdr_init(bp, &get, HWRM_FW_GET_STRUCTURED_DATA, -1, -1);
  247. get.dest_data_addr = cpu_to_le64(mapping);
  248. get.structure_id = cpu_to_le16(STRUCT_HDR_STRUCT_ID_DCBX_APP);
  249. get.subtype = cpu_to_le16(HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL);
  250. get.count = 0;
  251. rc = hwrm_send_message(bp, &get, sizeof(get), HWRM_CMD_TIMEOUT);
  252. if (rc)
  253. goto set_app_exit;
  254. fw_app = (struct hwrm_struct_data_dcbx_app *)(data + 1);
  255. if (data->struct_id != cpu_to_le16(STRUCT_HDR_STRUCT_ID_DCBX_APP)) {
  256. rc = -ENODEV;
  257. goto set_app_exit;
  258. }
  259. n = data->count;
  260. for (i = 0; i < n; i++, fw_app++) {
  261. if (fw_app->protocol_id == cpu_to_be16(app->protocol) &&
  262. fw_app->protocol_selector == app->selector &&
  263. fw_app->priority == app->priority) {
  264. if (add)
  265. goto set_app_exit;
  266. else
  267. break;
  268. }
  269. }
  270. if (add) {
  271. /* append */
  272. n++;
  273. fw_app->protocol_id = cpu_to_be16(app->protocol);
  274. fw_app->protocol_selector = app->selector;
  275. fw_app->priority = app->priority;
  276. fw_app->valid = 1;
  277. } else {
  278. size_t len = 0;
  279. /* not found, nothing to delete */
  280. if (n == i)
  281. goto set_app_exit;
  282. len = (n - 1 - i) * sizeof(*fw_app);
  283. if (len)
  284. memmove(fw_app, fw_app + 1, len);
  285. n--;
  286. memset(fw_app + n, 0, sizeof(*fw_app));
  287. }
  288. data->count = n;
  289. data->len = cpu_to_le16(sizeof(*fw_app) * n);
  290. data->subtype = cpu_to_le16(HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL);
  291. bnxt_hwrm_cmd_hdr_init(bp, &set, HWRM_FW_SET_STRUCTURED_DATA, -1, -1);
  292. set.src_data_addr = cpu_to_le64(mapping);
  293. set.data_len = cpu_to_le16(sizeof(*data) + sizeof(*fw_app) * n);
  294. set.hdr_cnt = 1;
  295. rc = hwrm_send_message(bp, &set, sizeof(set), HWRM_CMD_TIMEOUT);
  296. if (rc)
  297. rc = -EIO;
  298. set_app_exit:
  299. dma_free_coherent(&bp->pdev->dev, data_len, data, mapping);
  300. return rc;
  301. }
  302. static int bnxt_ets_validate(struct bnxt *bp, struct ieee_ets *ets, u8 *tc)
  303. {
  304. int total_ets_bw = 0;
  305. u8 max_tc = 0;
  306. int i;
  307. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  308. if (ets->prio_tc[i] > bp->max_tc) {
  309. netdev_err(bp->dev, "priority to TC mapping exceeds TC count %d\n",
  310. ets->prio_tc[i]);
  311. return -EINVAL;
  312. }
  313. if (ets->prio_tc[i] > max_tc)
  314. max_tc = ets->prio_tc[i];
  315. if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) && i > bp->max_tc)
  316. return -EINVAL;
  317. switch (ets->tc_tsa[i]) {
  318. case IEEE_8021QAZ_TSA_STRICT:
  319. break;
  320. case IEEE_8021QAZ_TSA_ETS:
  321. total_ets_bw += ets->tc_tx_bw[i];
  322. break;
  323. default:
  324. return -ENOTSUPP;
  325. }
  326. }
  327. if (total_ets_bw > 100)
  328. return -EINVAL;
  329. *tc = max_tc + 1;
  330. return 0;
  331. }
  332. static int bnxt_dcbnl_ieee_getets(struct net_device *dev, struct ieee_ets *ets)
  333. {
  334. struct bnxt *bp = netdev_priv(dev);
  335. struct ieee_ets *my_ets = bp->ieee_ets;
  336. ets->ets_cap = bp->max_tc;
  337. if (!my_ets) {
  338. int rc;
  339. if (bp->dcbx_cap & DCB_CAP_DCBX_HOST)
  340. return 0;
  341. my_ets = kzalloc(sizeof(*my_ets), GFP_KERNEL);
  342. if (!my_ets)
  343. return 0;
  344. rc = bnxt_hwrm_queue_cos2bw_qcfg(bp, my_ets);
  345. if (rc)
  346. return 0;
  347. rc = bnxt_hwrm_queue_pri2cos_qcfg(bp, my_ets);
  348. if (rc)
  349. return 0;
  350. }
  351. ets->cbs = my_ets->cbs;
  352. memcpy(ets->tc_tx_bw, my_ets->tc_tx_bw, sizeof(ets->tc_tx_bw));
  353. memcpy(ets->tc_rx_bw, my_ets->tc_rx_bw, sizeof(ets->tc_rx_bw));
  354. memcpy(ets->tc_tsa, my_ets->tc_tsa, sizeof(ets->tc_tsa));
  355. memcpy(ets->prio_tc, my_ets->prio_tc, sizeof(ets->prio_tc));
  356. return 0;
  357. }
  358. static int bnxt_dcbnl_ieee_setets(struct net_device *dev, struct ieee_ets *ets)
  359. {
  360. struct bnxt *bp = netdev_priv(dev);
  361. struct ieee_ets *my_ets = bp->ieee_ets;
  362. u8 max_tc = 0;
  363. int rc, i;
  364. if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
  365. !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))
  366. return -EINVAL;
  367. rc = bnxt_ets_validate(bp, ets, &max_tc);
  368. if (!rc) {
  369. if (!my_ets) {
  370. my_ets = kzalloc(sizeof(*my_ets), GFP_KERNEL);
  371. if (!my_ets)
  372. return -ENOMEM;
  373. /* initialize PRI2TC mappings to invalid value */
  374. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
  375. my_ets->prio_tc[i] = IEEE_8021QAZ_MAX_TCS;
  376. bp->ieee_ets = my_ets;
  377. }
  378. rc = bnxt_setup_mq_tc(dev, max_tc);
  379. if (rc)
  380. return rc;
  381. rc = bnxt_hwrm_queue_cos2bw_cfg(bp, ets, max_tc);
  382. if (rc)
  383. return rc;
  384. rc = bnxt_hwrm_queue_pri2cos_cfg(bp, ets);
  385. if (rc)
  386. return rc;
  387. memcpy(my_ets, ets, sizeof(*my_ets));
  388. }
  389. return rc;
  390. }
  391. static int bnxt_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc)
  392. {
  393. struct bnxt *bp = netdev_priv(dev);
  394. __le64 *stats = (__le64 *)bp->hw_rx_port_stats;
  395. struct ieee_pfc *my_pfc = bp->ieee_pfc;
  396. long rx_off, tx_off;
  397. int i, rc;
  398. pfc->pfc_cap = bp->max_lltc;
  399. if (!my_pfc) {
  400. if (bp->dcbx_cap & DCB_CAP_DCBX_HOST)
  401. return 0;
  402. my_pfc = kzalloc(sizeof(*my_pfc), GFP_KERNEL);
  403. if (!my_pfc)
  404. return 0;
  405. bp->ieee_pfc = my_pfc;
  406. rc = bnxt_hwrm_queue_pfc_qcfg(bp, my_pfc);
  407. if (rc)
  408. return 0;
  409. }
  410. pfc->pfc_en = my_pfc->pfc_en;
  411. pfc->mbc = my_pfc->mbc;
  412. pfc->delay = my_pfc->delay;
  413. if (!stats)
  414. return 0;
  415. rx_off = BNXT_RX_STATS_OFFSET(rx_pfc_ena_frames_pri0);
  416. tx_off = BNXT_TX_STATS_OFFSET(tx_pfc_ena_frames_pri0);
  417. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++, rx_off++, tx_off++) {
  418. pfc->requests[i] = le64_to_cpu(*(stats + tx_off));
  419. pfc->indications[i] = le64_to_cpu(*(stats + rx_off));
  420. }
  421. return 0;
  422. }
  423. static int bnxt_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)
  424. {
  425. struct bnxt *bp = netdev_priv(dev);
  426. struct ieee_pfc *my_pfc = bp->ieee_pfc;
  427. int rc;
  428. if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
  429. !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))
  430. return -EINVAL;
  431. if (!my_pfc) {
  432. my_pfc = kzalloc(sizeof(*my_pfc), GFP_KERNEL);
  433. if (!my_pfc)
  434. return -ENOMEM;
  435. bp->ieee_pfc = my_pfc;
  436. }
  437. rc = bnxt_hwrm_queue_pfc_cfg(bp, pfc);
  438. if (!rc)
  439. memcpy(my_pfc, pfc, sizeof(*my_pfc));
  440. return rc;
  441. }
  442. static int bnxt_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
  443. {
  444. struct bnxt *bp = netdev_priv(dev);
  445. int rc = -EINVAL;
  446. if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
  447. !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))
  448. return -EINVAL;
  449. rc = dcb_ieee_setapp(dev, app);
  450. if (rc)
  451. return rc;
  452. if ((app->selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE &&
  453. app->protocol == ETH_P_IBOE) ||
  454. (app->selector == IEEE_8021QAZ_APP_SEL_DGRAM &&
  455. app->protocol == ROCE_V2_UDP_DPORT))
  456. rc = bnxt_hwrm_set_dcbx_app(bp, app, true);
  457. return rc;
  458. }
  459. static int bnxt_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
  460. {
  461. struct bnxt *bp = netdev_priv(dev);
  462. int rc;
  463. if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
  464. !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))
  465. return -EINVAL;
  466. rc = dcb_ieee_delapp(dev, app);
  467. if (rc)
  468. return rc;
  469. if ((app->selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE &&
  470. app->protocol == ETH_P_IBOE) ||
  471. (app->selector == IEEE_8021QAZ_APP_SEL_DGRAM &&
  472. app->protocol == ROCE_V2_UDP_DPORT))
  473. rc = bnxt_hwrm_set_dcbx_app(bp, app, false);
  474. return rc;
  475. }
  476. static u8 bnxt_dcbnl_getdcbx(struct net_device *dev)
  477. {
  478. struct bnxt *bp = netdev_priv(dev);
  479. return bp->dcbx_cap;
  480. }
  481. static u8 bnxt_dcbnl_setdcbx(struct net_device *dev, u8 mode)
  482. {
  483. struct bnxt *bp = netdev_priv(dev);
  484. /* All firmware DCBX settings are set in NVRAM */
  485. if (bp->dcbx_cap & DCB_CAP_DCBX_LLD_MANAGED)
  486. return 1;
  487. if (mode & DCB_CAP_DCBX_HOST) {
  488. if (BNXT_VF(bp) || (bp->flags & BNXT_FLAG_FW_LLDP_AGENT))
  489. return 1;
  490. /* only support IEEE */
  491. if ((mode & DCB_CAP_DCBX_VER_CEE) ||
  492. !(mode & DCB_CAP_DCBX_VER_IEEE))
  493. return 1;
  494. }
  495. if (mode == bp->dcbx_cap)
  496. return 0;
  497. bp->dcbx_cap = mode;
  498. return 0;
  499. }
  500. static const struct dcbnl_rtnl_ops dcbnl_ops = {
  501. .ieee_getets = bnxt_dcbnl_ieee_getets,
  502. .ieee_setets = bnxt_dcbnl_ieee_setets,
  503. .ieee_getpfc = bnxt_dcbnl_ieee_getpfc,
  504. .ieee_setpfc = bnxt_dcbnl_ieee_setpfc,
  505. .ieee_setapp = bnxt_dcbnl_ieee_setapp,
  506. .ieee_delapp = bnxt_dcbnl_ieee_delapp,
  507. .getdcbx = bnxt_dcbnl_getdcbx,
  508. .setdcbx = bnxt_dcbnl_setdcbx,
  509. };
  510. void bnxt_dcb_init(struct bnxt *bp)
  511. {
  512. if (bp->hwrm_spec_code < 0x10501)
  513. return;
  514. bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE;
  515. if (BNXT_PF(bp) && !(bp->flags & BNXT_FLAG_FW_LLDP_AGENT))
  516. bp->dcbx_cap |= DCB_CAP_DCBX_HOST;
  517. else if (bp->flags & BNXT_FLAG_FW_DCBX_AGENT)
  518. bp->dcbx_cap |= DCB_CAP_DCBX_LLD_MANAGED;
  519. bp->dev->dcbnl_ops = &dcbnl_ops;
  520. }
  521. void bnxt_dcb_free(struct bnxt *bp)
  522. {
  523. kfree(bp->ieee_pfc);
  524. kfree(bp->ieee_ets);
  525. bp->ieee_pfc = NULL;
  526. bp->ieee_ets = NULL;
  527. }
  528. #else
  529. void bnxt_dcb_init(struct bnxt *bp)
  530. {
  531. }
  532. void bnxt_dcb_free(struct bnxt *bp)
  533. {
  534. }
  535. #endif