atl1e_main.c 69 KB

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  1. /*
  2. * Copyright(c) 2007 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1e.h"
  22. #define DRV_VERSION "1.0.0.7-NAPI"
  23. char atl1e_driver_name[] = "ATL1E";
  24. char atl1e_driver_version[] = DRV_VERSION;
  25. #define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
  26. /*
  27. * atl1e_pci_tbl - PCI Device ID Table
  28. *
  29. * Wildcard entries (PCI_ANY_ID) should come last
  30. * Last entry must be all 0s
  31. *
  32. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  33. * Class, Class Mask, private data (not used) }
  34. */
  35. static const struct pci_device_id atl1e_pci_tbl[] = {
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1066)},
  38. /* required last entry */
  39. { 0 }
  40. };
  41. MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
  42. MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
  43. MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
  44. MODULE_LICENSE("GPL");
  45. MODULE_VERSION(DRV_VERSION);
  46. static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
  47. static const u16
  48. atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
  49. {
  50. {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
  51. {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
  52. {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
  53. {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
  54. };
  55. static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
  56. {
  57. REG_RXF0_BASE_ADDR_HI,
  58. REG_RXF1_BASE_ADDR_HI,
  59. REG_RXF2_BASE_ADDR_HI,
  60. REG_RXF3_BASE_ADDR_HI
  61. };
  62. static const u16
  63. atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
  64. {
  65. {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
  66. {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
  67. {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
  68. {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
  69. };
  70. static const u16
  71. atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
  72. {
  73. {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
  74. {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
  75. {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
  76. {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
  77. };
  78. static const u16 atl1e_pay_load_size[] = {
  79. 128, 256, 512, 1024, 2048, 4096,
  80. };
  81. /**
  82. * atl1e_irq_enable - Enable default interrupt generation settings
  83. * @adapter: board private structure
  84. */
  85. static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
  86. {
  87. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  88. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  89. AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
  90. AT_WRITE_FLUSH(&adapter->hw);
  91. }
  92. }
  93. /**
  94. * atl1e_irq_disable - Mask off interrupt generation on the NIC
  95. * @adapter: board private structure
  96. */
  97. static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
  98. {
  99. atomic_inc(&adapter->irq_sem);
  100. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  101. AT_WRITE_FLUSH(&adapter->hw);
  102. synchronize_irq(adapter->pdev->irq);
  103. }
  104. /**
  105. * atl1e_irq_reset - reset interrupt confiure on the NIC
  106. * @adapter: board private structure
  107. */
  108. static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
  109. {
  110. atomic_set(&adapter->irq_sem, 0);
  111. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  112. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  113. AT_WRITE_FLUSH(&adapter->hw);
  114. }
  115. /**
  116. * atl1e_phy_config - Timer Call-back
  117. * @data: pointer to netdev cast into an unsigned long
  118. */
  119. static void atl1e_phy_config(struct timer_list *t)
  120. {
  121. struct atl1e_adapter *adapter = from_timer(adapter, t,
  122. phy_config_timer);
  123. struct atl1e_hw *hw = &adapter->hw;
  124. unsigned long flags;
  125. spin_lock_irqsave(&adapter->mdio_lock, flags);
  126. atl1e_restart_autoneg(hw);
  127. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  128. }
  129. void atl1e_reinit_locked(struct atl1e_adapter *adapter)
  130. {
  131. WARN_ON(in_interrupt());
  132. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  133. msleep(1);
  134. atl1e_down(adapter);
  135. atl1e_up(adapter);
  136. clear_bit(__AT_RESETTING, &adapter->flags);
  137. }
  138. static void atl1e_reset_task(struct work_struct *work)
  139. {
  140. struct atl1e_adapter *adapter;
  141. adapter = container_of(work, struct atl1e_adapter, reset_task);
  142. atl1e_reinit_locked(adapter);
  143. }
  144. static int atl1e_check_link(struct atl1e_adapter *adapter)
  145. {
  146. struct atl1e_hw *hw = &adapter->hw;
  147. struct net_device *netdev = adapter->netdev;
  148. int err = 0;
  149. u16 speed, duplex, phy_data;
  150. /* MII_BMSR must read twice */
  151. atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
  152. atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
  153. if ((phy_data & BMSR_LSTATUS) == 0) {
  154. /* link down */
  155. if (netif_carrier_ok(netdev)) { /* old link state: Up */
  156. u32 value;
  157. /* disable rx */
  158. value = AT_READ_REG(hw, REG_MAC_CTRL);
  159. value &= ~MAC_CTRL_RX_EN;
  160. AT_WRITE_REG(hw, REG_MAC_CTRL, value);
  161. adapter->link_speed = SPEED_0;
  162. netif_carrier_off(netdev);
  163. netif_stop_queue(netdev);
  164. }
  165. } else {
  166. /* Link Up */
  167. err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
  168. if (unlikely(err))
  169. return err;
  170. /* link result is our setting */
  171. if (adapter->link_speed != speed ||
  172. adapter->link_duplex != duplex) {
  173. adapter->link_speed = speed;
  174. adapter->link_duplex = duplex;
  175. atl1e_setup_mac_ctrl(adapter);
  176. netdev_info(netdev,
  177. "NIC Link is Up <%d Mbps %s Duplex>\n",
  178. adapter->link_speed,
  179. adapter->link_duplex == FULL_DUPLEX ?
  180. "Full" : "Half");
  181. }
  182. if (!netif_carrier_ok(netdev)) {
  183. /* Link down -> Up */
  184. netif_carrier_on(netdev);
  185. netif_wake_queue(netdev);
  186. }
  187. }
  188. return 0;
  189. }
  190. /**
  191. * atl1e_link_chg_task - deal with link change event Out of interrupt context
  192. * @netdev: network interface device structure
  193. */
  194. static void atl1e_link_chg_task(struct work_struct *work)
  195. {
  196. struct atl1e_adapter *adapter;
  197. unsigned long flags;
  198. adapter = container_of(work, struct atl1e_adapter, link_chg_task);
  199. spin_lock_irqsave(&adapter->mdio_lock, flags);
  200. atl1e_check_link(adapter);
  201. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  202. }
  203. static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
  204. {
  205. struct net_device *netdev = adapter->netdev;
  206. u16 phy_data = 0;
  207. u16 link_up = 0;
  208. spin_lock(&adapter->mdio_lock);
  209. atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  210. atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  211. spin_unlock(&adapter->mdio_lock);
  212. link_up = phy_data & BMSR_LSTATUS;
  213. /* notify upper layer link down ASAP */
  214. if (!link_up) {
  215. if (netif_carrier_ok(netdev)) {
  216. /* old link state: Up */
  217. netdev_info(netdev, "NIC Link is Down\n");
  218. adapter->link_speed = SPEED_0;
  219. netif_stop_queue(netdev);
  220. }
  221. }
  222. schedule_work(&adapter->link_chg_task);
  223. }
  224. static void atl1e_del_timer(struct atl1e_adapter *adapter)
  225. {
  226. del_timer_sync(&adapter->phy_config_timer);
  227. }
  228. static void atl1e_cancel_work(struct atl1e_adapter *adapter)
  229. {
  230. cancel_work_sync(&adapter->reset_task);
  231. cancel_work_sync(&adapter->link_chg_task);
  232. }
  233. /**
  234. * atl1e_tx_timeout - Respond to a Tx Hang
  235. * @netdev: network interface device structure
  236. */
  237. static void atl1e_tx_timeout(struct net_device *netdev)
  238. {
  239. struct atl1e_adapter *adapter = netdev_priv(netdev);
  240. /* Do the reset outside of interrupt context */
  241. schedule_work(&adapter->reset_task);
  242. }
  243. /**
  244. * atl1e_set_multi - Multicast and Promiscuous mode set
  245. * @netdev: network interface device structure
  246. *
  247. * The set_multi entry point is called whenever the multicast address
  248. * list or the network interface flags are updated. This routine is
  249. * responsible for configuring the hardware for proper multicast,
  250. * promiscuous mode, and all-multi behavior.
  251. */
  252. static void atl1e_set_multi(struct net_device *netdev)
  253. {
  254. struct atl1e_adapter *adapter = netdev_priv(netdev);
  255. struct atl1e_hw *hw = &adapter->hw;
  256. struct netdev_hw_addr *ha;
  257. u32 mac_ctrl_data = 0;
  258. u32 hash_value;
  259. /* Check for Promiscuous and All Multicast modes */
  260. mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
  261. if (netdev->flags & IFF_PROMISC) {
  262. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  263. } else if (netdev->flags & IFF_ALLMULTI) {
  264. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  265. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  266. } else {
  267. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  268. }
  269. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  270. /* clear the old settings from the multicast hash table */
  271. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  272. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  273. /* comoute mc addresses' hash value ,and put it into hash table */
  274. netdev_for_each_mc_addr(ha, netdev) {
  275. hash_value = atl1e_hash_mc_addr(hw, ha->addr);
  276. atl1e_hash_set(hw, hash_value);
  277. }
  278. }
  279. static void __atl1e_rx_mode(netdev_features_t features, u32 *mac_ctrl_data)
  280. {
  281. if (features & NETIF_F_RXALL) {
  282. /* enable RX of ALL frames */
  283. *mac_ctrl_data |= MAC_CTRL_DBG;
  284. } else {
  285. /* disable RX of ALL frames */
  286. *mac_ctrl_data &= ~MAC_CTRL_DBG;
  287. }
  288. }
  289. static void atl1e_rx_mode(struct net_device *netdev,
  290. netdev_features_t features)
  291. {
  292. struct atl1e_adapter *adapter = netdev_priv(netdev);
  293. u32 mac_ctrl_data = 0;
  294. netdev_dbg(adapter->netdev, "%s\n", __func__);
  295. atl1e_irq_disable(adapter);
  296. mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
  297. __atl1e_rx_mode(features, &mac_ctrl_data);
  298. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  299. atl1e_irq_enable(adapter);
  300. }
  301. static void __atl1e_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  302. {
  303. if (features & NETIF_F_HW_VLAN_CTAG_RX) {
  304. /* enable VLAN tag insert/strip */
  305. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  306. } else {
  307. /* disable VLAN tag insert/strip */
  308. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  309. }
  310. }
  311. static void atl1e_vlan_mode(struct net_device *netdev,
  312. netdev_features_t features)
  313. {
  314. struct atl1e_adapter *adapter = netdev_priv(netdev);
  315. u32 mac_ctrl_data = 0;
  316. netdev_dbg(adapter->netdev, "%s\n", __func__);
  317. atl1e_irq_disable(adapter);
  318. mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
  319. __atl1e_vlan_mode(features, &mac_ctrl_data);
  320. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  321. atl1e_irq_enable(adapter);
  322. }
  323. static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
  324. {
  325. netdev_dbg(adapter->netdev, "%s\n", __func__);
  326. atl1e_vlan_mode(adapter->netdev, adapter->netdev->features);
  327. }
  328. /**
  329. * atl1e_set_mac - Change the Ethernet Address of the NIC
  330. * @netdev: network interface device structure
  331. * @p: pointer to an address structure
  332. *
  333. * Returns 0 on success, negative on failure
  334. */
  335. static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
  336. {
  337. struct atl1e_adapter *adapter = netdev_priv(netdev);
  338. struct sockaddr *addr = p;
  339. if (!is_valid_ether_addr(addr->sa_data))
  340. return -EADDRNOTAVAIL;
  341. if (netif_running(netdev))
  342. return -EBUSY;
  343. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  344. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  345. atl1e_hw_set_mac_addr(&adapter->hw);
  346. return 0;
  347. }
  348. static netdev_features_t atl1e_fix_features(struct net_device *netdev,
  349. netdev_features_t features)
  350. {
  351. /*
  352. * Since there is no support for separate rx/tx vlan accel
  353. * enable/disable make sure tx flag is always in same state as rx.
  354. */
  355. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  356. features |= NETIF_F_HW_VLAN_CTAG_TX;
  357. else
  358. features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  359. return features;
  360. }
  361. static int atl1e_set_features(struct net_device *netdev,
  362. netdev_features_t features)
  363. {
  364. netdev_features_t changed = netdev->features ^ features;
  365. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  366. atl1e_vlan_mode(netdev, features);
  367. if (changed & NETIF_F_RXALL)
  368. atl1e_rx_mode(netdev, features);
  369. return 0;
  370. }
  371. /**
  372. * atl1e_change_mtu - Change the Maximum Transfer Unit
  373. * @netdev: network interface device structure
  374. * @new_mtu: new value for maximum frame size
  375. *
  376. * Returns 0 on success, negative on failure
  377. */
  378. static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
  379. {
  380. struct atl1e_adapter *adapter = netdev_priv(netdev);
  381. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  382. /* set MTU */
  383. if (netif_running(netdev)) {
  384. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  385. msleep(1);
  386. netdev->mtu = new_mtu;
  387. adapter->hw.max_frame_size = new_mtu;
  388. adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
  389. atl1e_down(adapter);
  390. atl1e_up(adapter);
  391. clear_bit(__AT_RESETTING, &adapter->flags);
  392. }
  393. return 0;
  394. }
  395. /*
  396. * caller should hold mdio_lock
  397. */
  398. static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  399. {
  400. struct atl1e_adapter *adapter = netdev_priv(netdev);
  401. u16 result;
  402. atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
  403. return result;
  404. }
  405. static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
  406. int reg_num, int val)
  407. {
  408. struct atl1e_adapter *adapter = netdev_priv(netdev);
  409. atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
  410. }
  411. static int atl1e_mii_ioctl(struct net_device *netdev,
  412. struct ifreq *ifr, int cmd)
  413. {
  414. struct atl1e_adapter *adapter = netdev_priv(netdev);
  415. struct mii_ioctl_data *data = if_mii(ifr);
  416. unsigned long flags;
  417. int retval = 0;
  418. if (!netif_running(netdev))
  419. return -EINVAL;
  420. spin_lock_irqsave(&adapter->mdio_lock, flags);
  421. switch (cmd) {
  422. case SIOCGMIIPHY:
  423. data->phy_id = 0;
  424. break;
  425. case SIOCGMIIREG:
  426. if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  427. &data->val_out)) {
  428. retval = -EIO;
  429. goto out;
  430. }
  431. break;
  432. case SIOCSMIIREG:
  433. if (data->reg_num & ~(0x1F)) {
  434. retval = -EFAULT;
  435. goto out;
  436. }
  437. netdev_dbg(adapter->netdev, "<atl1e_mii_ioctl> write %x %x\n",
  438. data->reg_num, data->val_in);
  439. if (atl1e_write_phy_reg(&adapter->hw,
  440. data->reg_num, data->val_in)) {
  441. retval = -EIO;
  442. goto out;
  443. }
  444. break;
  445. default:
  446. retval = -EOPNOTSUPP;
  447. break;
  448. }
  449. out:
  450. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  451. return retval;
  452. }
  453. static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  454. {
  455. switch (cmd) {
  456. case SIOCGMIIPHY:
  457. case SIOCGMIIREG:
  458. case SIOCSMIIREG:
  459. return atl1e_mii_ioctl(netdev, ifr, cmd);
  460. default:
  461. return -EOPNOTSUPP;
  462. }
  463. }
  464. static void atl1e_setup_pcicmd(struct pci_dev *pdev)
  465. {
  466. u16 cmd;
  467. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  468. cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
  469. cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  470. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  471. /*
  472. * some motherboards BIOS(PXE/EFI) driver may set PME
  473. * while they transfer control to OS (Windows/Linux)
  474. * so we should clear this bit before NIC work normally
  475. */
  476. pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
  477. msleep(1);
  478. }
  479. /**
  480. * atl1e_alloc_queues - Allocate memory for all rings
  481. * @adapter: board private structure to initialize
  482. *
  483. */
  484. static int atl1e_alloc_queues(struct atl1e_adapter *adapter)
  485. {
  486. return 0;
  487. }
  488. /**
  489. * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
  490. * @adapter: board private structure to initialize
  491. *
  492. * atl1e_sw_init initializes the Adapter private data structure.
  493. * Fields are initialized based on PCI device information and
  494. * OS network device settings (MTU size).
  495. */
  496. static int atl1e_sw_init(struct atl1e_adapter *adapter)
  497. {
  498. struct atl1e_hw *hw = &adapter->hw;
  499. struct pci_dev *pdev = adapter->pdev;
  500. u32 phy_status_data = 0;
  501. adapter->wol = 0;
  502. adapter->link_speed = SPEED_0; /* hardware init */
  503. adapter->link_duplex = FULL_DUPLEX;
  504. adapter->num_rx_queues = 1;
  505. /* PCI config space info */
  506. hw->vendor_id = pdev->vendor;
  507. hw->device_id = pdev->device;
  508. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  509. hw->subsystem_id = pdev->subsystem_device;
  510. hw->revision_id = pdev->revision;
  511. pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
  512. phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
  513. /* nic type */
  514. if (hw->revision_id >= 0xF0) {
  515. hw->nic_type = athr_l2e_revB;
  516. } else {
  517. if (phy_status_data & PHY_STATUS_100M)
  518. hw->nic_type = athr_l1e;
  519. else
  520. hw->nic_type = athr_l2e_revA;
  521. }
  522. phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
  523. if (phy_status_data & PHY_STATUS_EMI_CA)
  524. hw->emi_ca = true;
  525. else
  526. hw->emi_ca = false;
  527. hw->phy_configured = false;
  528. hw->preamble_len = 7;
  529. hw->max_frame_size = adapter->netdev->mtu;
  530. hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
  531. VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
  532. hw->rrs_type = atl1e_rrs_disable;
  533. hw->indirect_tab = 0;
  534. hw->base_cpu = 0;
  535. /* need confirm */
  536. hw->ict = 50000; /* 100ms */
  537. hw->smb_timer = 200000; /* 200ms */
  538. hw->tpd_burst = 5;
  539. hw->rrd_thresh = 1;
  540. hw->tpd_thresh = adapter->tx_ring.count / 2;
  541. hw->rx_count_down = 4; /* 2us resolution */
  542. hw->tx_count_down = hw->imt * 4 / 3;
  543. hw->dmar_block = atl1e_dma_req_1024;
  544. hw->dmaw_block = atl1e_dma_req_1024;
  545. hw->dmar_dly_cnt = 15;
  546. hw->dmaw_dly_cnt = 4;
  547. if (atl1e_alloc_queues(adapter)) {
  548. netdev_err(adapter->netdev, "Unable to allocate memory for queues\n");
  549. return -ENOMEM;
  550. }
  551. atomic_set(&adapter->irq_sem, 1);
  552. spin_lock_init(&adapter->mdio_lock);
  553. set_bit(__AT_DOWN, &adapter->flags);
  554. return 0;
  555. }
  556. /**
  557. * atl1e_clean_tx_ring - Free Tx-skb
  558. * @adapter: board private structure
  559. */
  560. static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
  561. {
  562. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  563. struct atl1e_tx_buffer *tx_buffer = NULL;
  564. struct pci_dev *pdev = adapter->pdev;
  565. u16 index, ring_count;
  566. if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
  567. return;
  568. ring_count = tx_ring->count;
  569. /* first unmmap dma */
  570. for (index = 0; index < ring_count; index++) {
  571. tx_buffer = &tx_ring->tx_buffer[index];
  572. if (tx_buffer->dma) {
  573. if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
  574. pci_unmap_single(pdev, tx_buffer->dma,
  575. tx_buffer->length, PCI_DMA_TODEVICE);
  576. else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
  577. pci_unmap_page(pdev, tx_buffer->dma,
  578. tx_buffer->length, PCI_DMA_TODEVICE);
  579. tx_buffer->dma = 0;
  580. }
  581. }
  582. /* second free skb */
  583. for (index = 0; index < ring_count; index++) {
  584. tx_buffer = &tx_ring->tx_buffer[index];
  585. if (tx_buffer->skb) {
  586. dev_kfree_skb_any(tx_buffer->skb);
  587. tx_buffer->skb = NULL;
  588. }
  589. }
  590. /* Zero out Tx-buffers */
  591. memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
  592. ring_count);
  593. memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
  594. ring_count);
  595. }
  596. /**
  597. * atl1e_clean_rx_ring - Free rx-reservation skbs
  598. * @adapter: board private structure
  599. */
  600. static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
  601. {
  602. struct atl1e_rx_ring *rx_ring =
  603. &adapter->rx_ring;
  604. struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
  605. u16 i, j;
  606. if (adapter->ring_vir_addr == NULL)
  607. return;
  608. /* Zero out the descriptor ring */
  609. for (i = 0; i < adapter->num_rx_queues; i++) {
  610. for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
  611. if (rx_page_desc[i].rx_page[j].addr != NULL) {
  612. memset(rx_page_desc[i].rx_page[j].addr, 0,
  613. rx_ring->real_page_size);
  614. }
  615. }
  616. }
  617. }
  618. static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
  619. {
  620. *ring_size = ((u32)(adapter->tx_ring.count *
  621. sizeof(struct atl1e_tpd_desc) + 7
  622. /* tx ring, qword align */
  623. + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
  624. adapter->num_rx_queues + 31
  625. /* rx ring, 32 bytes align */
  626. + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
  627. sizeof(u32) + 3));
  628. /* tx, rx cmd, dword align */
  629. }
  630. static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
  631. {
  632. struct atl1e_rx_ring *rx_ring = NULL;
  633. rx_ring = &adapter->rx_ring;
  634. rx_ring->real_page_size = adapter->rx_ring.page_size
  635. + adapter->hw.max_frame_size
  636. + ETH_HLEN + VLAN_HLEN
  637. + ETH_FCS_LEN;
  638. rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
  639. atl1e_cal_ring_size(adapter, &adapter->ring_size);
  640. adapter->ring_vir_addr = NULL;
  641. adapter->rx_ring.desc = NULL;
  642. rwlock_init(&adapter->tx_ring.tx_lock);
  643. }
  644. /*
  645. * Read / Write Ptr Initialize:
  646. */
  647. static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
  648. {
  649. struct atl1e_tx_ring *tx_ring = NULL;
  650. struct atl1e_rx_ring *rx_ring = NULL;
  651. struct atl1e_rx_page_desc *rx_page_desc = NULL;
  652. int i, j;
  653. tx_ring = &adapter->tx_ring;
  654. rx_ring = &adapter->rx_ring;
  655. rx_page_desc = rx_ring->rx_page_desc;
  656. tx_ring->next_to_use = 0;
  657. atomic_set(&tx_ring->next_to_clean, 0);
  658. for (i = 0; i < adapter->num_rx_queues; i++) {
  659. rx_page_desc[i].rx_using = 0;
  660. rx_page_desc[i].rx_nxseq = 0;
  661. for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
  662. *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
  663. rx_page_desc[i].rx_page[j].read_offset = 0;
  664. }
  665. }
  666. }
  667. /**
  668. * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
  669. * @adapter: board private structure
  670. *
  671. * Free all transmit software resources
  672. */
  673. static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
  674. {
  675. struct pci_dev *pdev = adapter->pdev;
  676. atl1e_clean_tx_ring(adapter);
  677. atl1e_clean_rx_ring(adapter);
  678. if (adapter->ring_vir_addr) {
  679. pci_free_consistent(pdev, adapter->ring_size,
  680. adapter->ring_vir_addr, adapter->ring_dma);
  681. adapter->ring_vir_addr = NULL;
  682. }
  683. if (adapter->tx_ring.tx_buffer) {
  684. kfree(adapter->tx_ring.tx_buffer);
  685. adapter->tx_ring.tx_buffer = NULL;
  686. }
  687. }
  688. /**
  689. * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
  690. * @adapter: board private structure
  691. *
  692. * Return 0 on success, negative on failure
  693. */
  694. static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
  695. {
  696. struct pci_dev *pdev = adapter->pdev;
  697. struct atl1e_tx_ring *tx_ring;
  698. struct atl1e_rx_ring *rx_ring;
  699. struct atl1e_rx_page_desc *rx_page_desc;
  700. int size, i, j;
  701. u32 offset = 0;
  702. int err = 0;
  703. if (adapter->ring_vir_addr != NULL)
  704. return 0; /* alloced already */
  705. tx_ring = &adapter->tx_ring;
  706. rx_ring = &adapter->rx_ring;
  707. /* real ring DMA buffer */
  708. size = adapter->ring_size;
  709. adapter->ring_vir_addr = pci_zalloc_consistent(pdev, adapter->ring_size,
  710. &adapter->ring_dma);
  711. if (adapter->ring_vir_addr == NULL) {
  712. netdev_err(adapter->netdev,
  713. "pci_alloc_consistent failed, size = D%d\n", size);
  714. return -ENOMEM;
  715. }
  716. rx_page_desc = rx_ring->rx_page_desc;
  717. /* Init TPD Ring */
  718. tx_ring->dma = roundup(adapter->ring_dma, 8);
  719. offset = tx_ring->dma - adapter->ring_dma;
  720. tx_ring->desc = adapter->ring_vir_addr + offset;
  721. size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
  722. tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
  723. if (tx_ring->tx_buffer == NULL) {
  724. err = -ENOMEM;
  725. goto failed;
  726. }
  727. /* Init RXF-Pages */
  728. offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
  729. offset = roundup(offset, 32);
  730. for (i = 0; i < adapter->num_rx_queues; i++) {
  731. for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
  732. rx_page_desc[i].rx_page[j].dma =
  733. adapter->ring_dma + offset;
  734. rx_page_desc[i].rx_page[j].addr =
  735. adapter->ring_vir_addr + offset;
  736. offset += rx_ring->real_page_size;
  737. }
  738. }
  739. /* Init CMB dma address */
  740. tx_ring->cmb_dma = adapter->ring_dma + offset;
  741. tx_ring->cmb = adapter->ring_vir_addr + offset;
  742. offset += sizeof(u32);
  743. for (i = 0; i < adapter->num_rx_queues; i++) {
  744. for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
  745. rx_page_desc[i].rx_page[j].write_offset_dma =
  746. adapter->ring_dma + offset;
  747. rx_page_desc[i].rx_page[j].write_offset_addr =
  748. adapter->ring_vir_addr + offset;
  749. offset += sizeof(u32);
  750. }
  751. }
  752. if (unlikely(offset > adapter->ring_size)) {
  753. netdev_err(adapter->netdev, "offset(%d) > ring size(%d) !!\n",
  754. offset, adapter->ring_size);
  755. err = -1;
  756. goto failed;
  757. }
  758. return 0;
  759. failed:
  760. if (adapter->ring_vir_addr != NULL) {
  761. pci_free_consistent(pdev, adapter->ring_size,
  762. adapter->ring_vir_addr, adapter->ring_dma);
  763. adapter->ring_vir_addr = NULL;
  764. }
  765. return err;
  766. }
  767. static inline void atl1e_configure_des_ring(struct atl1e_adapter *adapter)
  768. {
  769. struct atl1e_hw *hw = &adapter->hw;
  770. struct atl1e_rx_ring *rx_ring = &adapter->rx_ring;
  771. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  772. struct atl1e_rx_page_desc *rx_page_desc = NULL;
  773. int i, j;
  774. AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
  775. (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
  776. AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
  777. (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
  778. AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
  779. AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
  780. (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
  781. rx_page_desc = rx_ring->rx_page_desc;
  782. /* RXF Page Physical address / Page Length */
  783. for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
  784. AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
  785. (u32)((adapter->ring_dma &
  786. AT_DMA_HI_ADDR_MASK) >> 32));
  787. for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
  788. u32 page_phy_addr;
  789. u32 offset_phy_addr;
  790. page_phy_addr = rx_page_desc[i].rx_page[j].dma;
  791. offset_phy_addr =
  792. rx_page_desc[i].rx_page[j].write_offset_dma;
  793. AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
  794. page_phy_addr & AT_DMA_LO_ADDR_MASK);
  795. AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
  796. offset_phy_addr & AT_DMA_LO_ADDR_MASK);
  797. AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
  798. }
  799. }
  800. /* Page Length */
  801. AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
  802. /* Load all of base address above */
  803. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  804. }
  805. static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
  806. {
  807. struct atl1e_hw *hw = &adapter->hw;
  808. u32 dev_ctrl_data = 0;
  809. u32 max_pay_load = 0;
  810. u32 jumbo_thresh = 0;
  811. u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
  812. /* configure TXQ param */
  813. if (hw->nic_type != athr_l2e_revB) {
  814. extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
  815. if (hw->max_frame_size <= 1500) {
  816. jumbo_thresh = hw->max_frame_size + extra_size;
  817. } else if (hw->max_frame_size < 6*1024) {
  818. jumbo_thresh =
  819. (hw->max_frame_size + extra_size) * 2 / 3;
  820. } else {
  821. jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
  822. }
  823. AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
  824. }
  825. dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
  826. max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
  827. DEVICE_CTRL_MAX_PAYLOAD_MASK;
  828. hw->dmaw_block = min_t(u32, max_pay_load, hw->dmaw_block);
  829. max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
  830. DEVICE_CTRL_MAX_RREQ_SZ_MASK;
  831. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  832. if (hw->nic_type != athr_l2e_revB)
  833. AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
  834. atl1e_pay_load_size[hw->dmar_block]);
  835. /* enable TXQ */
  836. AT_WRITE_REGW(hw, REG_TXQ_CTRL,
  837. (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
  838. << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
  839. | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
  840. }
  841. static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
  842. {
  843. struct atl1e_hw *hw = &adapter->hw;
  844. u32 rxf_len = 0;
  845. u32 rxf_low = 0;
  846. u32 rxf_high = 0;
  847. u32 rxf_thresh_data = 0;
  848. u32 rxq_ctrl_data = 0;
  849. if (hw->nic_type != athr_l2e_revB) {
  850. AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
  851. (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
  852. RXQ_JMBOSZ_TH_SHIFT |
  853. (1 & RXQ_JMBO_LKAH_MASK) <<
  854. RXQ_JMBO_LKAH_SHIFT));
  855. rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
  856. rxf_high = rxf_len * 4 / 5;
  857. rxf_low = rxf_len / 5;
  858. rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
  859. << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
  860. ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
  861. << RXQ_RXF_PAUSE_TH_LO_SHIFT);
  862. AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
  863. }
  864. /* RRS */
  865. AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
  866. AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
  867. if (hw->rrs_type & atl1e_rrs_ipv4)
  868. rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
  869. if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
  870. rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
  871. if (hw->rrs_type & atl1e_rrs_ipv6)
  872. rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
  873. if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
  874. rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
  875. if (hw->rrs_type != atl1e_rrs_disable)
  876. rxq_ctrl_data |=
  877. (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
  878. rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
  879. RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
  880. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  881. }
  882. static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
  883. {
  884. struct atl1e_hw *hw = &adapter->hw;
  885. u32 dma_ctrl_data = 0;
  886. dma_ctrl_data = DMA_CTRL_RXCMB_EN;
  887. dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
  888. << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
  889. dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
  890. << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
  891. dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
  892. dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
  893. << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
  894. dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
  895. << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
  896. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  897. }
  898. static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
  899. {
  900. u32 value;
  901. struct atl1e_hw *hw = &adapter->hw;
  902. struct net_device *netdev = adapter->netdev;
  903. /* Config MAC CTRL Register */
  904. value = MAC_CTRL_TX_EN |
  905. MAC_CTRL_RX_EN ;
  906. if (FULL_DUPLEX == adapter->link_duplex)
  907. value |= MAC_CTRL_DUPLX;
  908. value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
  909. MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
  910. MAC_CTRL_SPEED_SHIFT);
  911. value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
  912. value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
  913. value |= (((u32)adapter->hw.preamble_len &
  914. MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
  915. __atl1e_vlan_mode(netdev->features, &value);
  916. value |= MAC_CTRL_BC_EN;
  917. if (netdev->flags & IFF_PROMISC)
  918. value |= MAC_CTRL_PROMIS_EN;
  919. if (netdev->flags & IFF_ALLMULTI)
  920. value |= MAC_CTRL_MC_ALL_EN;
  921. if (netdev->features & NETIF_F_RXALL)
  922. value |= MAC_CTRL_DBG;
  923. AT_WRITE_REG(hw, REG_MAC_CTRL, value);
  924. }
  925. /**
  926. * atl1e_configure - Configure Transmit&Receive Unit after Reset
  927. * @adapter: board private structure
  928. *
  929. * Configure the Tx /Rx unit of the MAC after a reset.
  930. */
  931. static int atl1e_configure(struct atl1e_adapter *adapter)
  932. {
  933. struct atl1e_hw *hw = &adapter->hw;
  934. u32 intr_status_data = 0;
  935. /* clear interrupt status */
  936. AT_WRITE_REG(hw, REG_ISR, ~0);
  937. /* 1. set MAC Address */
  938. atl1e_hw_set_mac_addr(hw);
  939. /* 2. Init the Multicast HASH table done by set_muti */
  940. /* 3. Clear any WOL status */
  941. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  942. /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
  943. * TPD Ring/SMB/RXF0 Page CMBs, they use the same
  944. * High 32bits memory */
  945. atl1e_configure_des_ring(adapter);
  946. /* 5. set Interrupt Moderator Timer */
  947. AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
  948. AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
  949. AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
  950. MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
  951. /* 6. rx/tx threshold to trig interrupt */
  952. AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
  953. AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
  954. AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
  955. AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
  956. /* 7. set Interrupt Clear Timer */
  957. AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
  958. /* 8. set MTU */
  959. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  960. VLAN_HLEN + ETH_FCS_LEN);
  961. /* 9. config TXQ early tx threshold */
  962. atl1e_configure_tx(adapter);
  963. /* 10. config RXQ */
  964. atl1e_configure_rx(adapter);
  965. /* 11. config DMA Engine */
  966. atl1e_configure_dma(adapter);
  967. /* 12. smb timer to trig interrupt */
  968. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
  969. intr_status_data = AT_READ_REG(hw, REG_ISR);
  970. if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
  971. netdev_err(adapter->netdev,
  972. "atl1e_configure failed, PCIE phy link down\n");
  973. return -1;
  974. }
  975. AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
  976. return 0;
  977. }
  978. /**
  979. * atl1e_get_stats - Get System Network Statistics
  980. * @netdev: network interface device structure
  981. *
  982. * Returns the address of the device statistics structure.
  983. * The statistics are actually updated from the timer callback.
  984. */
  985. static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
  986. {
  987. struct atl1e_adapter *adapter = netdev_priv(netdev);
  988. struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
  989. struct net_device_stats *net_stats = &netdev->stats;
  990. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  991. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  992. net_stats->multicast = hw_stats->rx_mcast;
  993. net_stats->collisions = hw_stats->tx_1_col +
  994. hw_stats->tx_2_col +
  995. hw_stats->tx_late_col +
  996. hw_stats->tx_abort_col;
  997. net_stats->rx_errors = hw_stats->rx_frag +
  998. hw_stats->rx_fcs_err +
  999. hw_stats->rx_len_err +
  1000. hw_stats->rx_sz_ov +
  1001. hw_stats->rx_rrd_ov +
  1002. hw_stats->rx_align_err +
  1003. hw_stats->rx_rxf_ov;
  1004. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1005. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1006. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1007. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1008. net_stats->rx_dropped = hw_stats->rx_rrd_ov;
  1009. net_stats->tx_errors = hw_stats->tx_late_col +
  1010. hw_stats->tx_abort_col +
  1011. hw_stats->tx_underrun +
  1012. hw_stats->tx_trunc;
  1013. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1014. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1015. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1016. net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
  1017. net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
  1018. return net_stats;
  1019. }
  1020. static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
  1021. {
  1022. u16 hw_reg_addr = 0;
  1023. unsigned long *stats_item = NULL;
  1024. /* update rx status */
  1025. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1026. stats_item = &adapter->hw_stats.rx_ok;
  1027. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1028. *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
  1029. stats_item++;
  1030. hw_reg_addr += 4;
  1031. }
  1032. /* update tx status */
  1033. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1034. stats_item = &adapter->hw_stats.tx_ok;
  1035. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1036. *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
  1037. stats_item++;
  1038. hw_reg_addr += 4;
  1039. }
  1040. }
  1041. static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
  1042. {
  1043. u16 phy_data;
  1044. spin_lock(&adapter->mdio_lock);
  1045. atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
  1046. spin_unlock(&adapter->mdio_lock);
  1047. }
  1048. static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
  1049. {
  1050. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  1051. struct atl1e_tx_buffer *tx_buffer = NULL;
  1052. u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
  1053. u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
  1054. while (next_to_clean != hw_next_to_clean) {
  1055. tx_buffer = &tx_ring->tx_buffer[next_to_clean];
  1056. if (tx_buffer->dma) {
  1057. if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
  1058. pci_unmap_single(adapter->pdev, tx_buffer->dma,
  1059. tx_buffer->length, PCI_DMA_TODEVICE);
  1060. else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
  1061. pci_unmap_page(adapter->pdev, tx_buffer->dma,
  1062. tx_buffer->length, PCI_DMA_TODEVICE);
  1063. tx_buffer->dma = 0;
  1064. }
  1065. if (tx_buffer->skb) {
  1066. dev_kfree_skb_irq(tx_buffer->skb);
  1067. tx_buffer->skb = NULL;
  1068. }
  1069. if (++next_to_clean == tx_ring->count)
  1070. next_to_clean = 0;
  1071. }
  1072. atomic_set(&tx_ring->next_to_clean, next_to_clean);
  1073. if (netif_queue_stopped(adapter->netdev) &&
  1074. netif_carrier_ok(adapter->netdev)) {
  1075. netif_wake_queue(adapter->netdev);
  1076. }
  1077. return true;
  1078. }
  1079. /**
  1080. * atl1e_intr - Interrupt Handler
  1081. * @irq: interrupt number
  1082. * @data: pointer to a network interface device structure
  1083. */
  1084. static irqreturn_t atl1e_intr(int irq, void *data)
  1085. {
  1086. struct net_device *netdev = data;
  1087. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1088. struct atl1e_hw *hw = &adapter->hw;
  1089. int max_ints = AT_MAX_INT_WORK;
  1090. int handled = IRQ_NONE;
  1091. u32 status;
  1092. do {
  1093. status = AT_READ_REG(hw, REG_ISR);
  1094. if ((status & IMR_NORMAL_MASK) == 0 ||
  1095. (status & ISR_DIS_INT) != 0) {
  1096. if (max_ints != AT_MAX_INT_WORK)
  1097. handled = IRQ_HANDLED;
  1098. break;
  1099. }
  1100. /* link event */
  1101. if (status & ISR_GPHY)
  1102. atl1e_clear_phy_int(adapter);
  1103. /* Ack ISR */
  1104. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1105. handled = IRQ_HANDLED;
  1106. /* check if PCIE PHY Link down */
  1107. if (status & ISR_PHY_LINKDOWN) {
  1108. netdev_err(adapter->netdev,
  1109. "pcie phy linkdown %x\n", status);
  1110. if (netif_running(adapter->netdev)) {
  1111. /* reset MAC */
  1112. atl1e_irq_reset(adapter);
  1113. schedule_work(&adapter->reset_task);
  1114. break;
  1115. }
  1116. }
  1117. /* check if DMA read/write error */
  1118. if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
  1119. netdev_err(adapter->netdev,
  1120. "PCIE DMA RW error (status = 0x%x)\n",
  1121. status);
  1122. atl1e_irq_reset(adapter);
  1123. schedule_work(&adapter->reset_task);
  1124. break;
  1125. }
  1126. if (status & ISR_SMB)
  1127. atl1e_update_hw_stats(adapter);
  1128. /* link event */
  1129. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1130. netdev->stats.tx_carrier_errors++;
  1131. atl1e_link_chg_event(adapter);
  1132. break;
  1133. }
  1134. /* transmit event */
  1135. if (status & ISR_TX_EVENT)
  1136. atl1e_clean_tx_irq(adapter);
  1137. if (status & ISR_RX_EVENT) {
  1138. /*
  1139. * disable rx interrupts, without
  1140. * the synchronize_irq bit
  1141. */
  1142. AT_WRITE_REG(hw, REG_IMR,
  1143. IMR_NORMAL_MASK & ~ISR_RX_EVENT);
  1144. AT_WRITE_FLUSH(hw);
  1145. if (likely(napi_schedule_prep(
  1146. &adapter->napi)))
  1147. __napi_schedule(&adapter->napi);
  1148. }
  1149. } while (--max_ints > 0);
  1150. /* re-enable Interrupt*/
  1151. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1152. return handled;
  1153. }
  1154. static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
  1155. struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
  1156. {
  1157. u8 *packet = (u8 *)(prrs + 1);
  1158. struct iphdr *iph;
  1159. u16 head_len = ETH_HLEN;
  1160. u16 pkt_flags;
  1161. u16 err_flags;
  1162. skb_checksum_none_assert(skb);
  1163. pkt_flags = prrs->pkt_flag;
  1164. err_flags = prrs->err_flag;
  1165. if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
  1166. ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
  1167. if (pkt_flags & RRS_IS_IPV4) {
  1168. if (pkt_flags & RRS_IS_802_3)
  1169. head_len += 8;
  1170. iph = (struct iphdr *) (packet + head_len);
  1171. if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
  1172. goto hw_xsum;
  1173. }
  1174. if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
  1175. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1176. return;
  1177. }
  1178. }
  1179. hw_xsum :
  1180. return;
  1181. }
  1182. static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
  1183. u8 que)
  1184. {
  1185. struct atl1e_rx_page_desc *rx_page_desc =
  1186. (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
  1187. u8 rx_using = rx_page_desc[que].rx_using;
  1188. return &(rx_page_desc[que].rx_page[rx_using]);
  1189. }
  1190. static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
  1191. int *work_done, int work_to_do)
  1192. {
  1193. struct net_device *netdev = adapter->netdev;
  1194. struct atl1e_rx_ring *rx_ring = &adapter->rx_ring;
  1195. struct atl1e_rx_page_desc *rx_page_desc =
  1196. (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
  1197. struct sk_buff *skb = NULL;
  1198. struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
  1199. u32 packet_size, write_offset;
  1200. struct atl1e_recv_ret_status *prrs;
  1201. write_offset = *(rx_page->write_offset_addr);
  1202. if (likely(rx_page->read_offset < write_offset)) {
  1203. do {
  1204. if (*work_done >= work_to_do)
  1205. break;
  1206. (*work_done)++;
  1207. /* get new packet's rrs */
  1208. prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
  1209. rx_page->read_offset);
  1210. /* check sequence number */
  1211. if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
  1212. netdev_err(netdev,
  1213. "rx sequence number error (rx=%d) (expect=%d)\n",
  1214. prrs->seq_num,
  1215. rx_page_desc[que].rx_nxseq);
  1216. rx_page_desc[que].rx_nxseq++;
  1217. /* just for debug use */
  1218. AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
  1219. (((u32)prrs->seq_num) << 16) |
  1220. rx_page_desc[que].rx_nxseq);
  1221. goto fatal_err;
  1222. }
  1223. rx_page_desc[que].rx_nxseq++;
  1224. /* error packet */
  1225. if ((prrs->pkt_flag & RRS_IS_ERR_FRAME) &&
  1226. !(netdev->features & NETIF_F_RXALL)) {
  1227. if (prrs->err_flag & (RRS_ERR_BAD_CRC |
  1228. RRS_ERR_DRIBBLE | RRS_ERR_CODE |
  1229. RRS_ERR_TRUNC)) {
  1230. /* hardware error, discard this packet*/
  1231. netdev_err(netdev,
  1232. "rx packet desc error %x\n",
  1233. *((u32 *)prrs + 1));
  1234. goto skip_pkt;
  1235. }
  1236. }
  1237. packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
  1238. RRS_PKT_SIZE_MASK);
  1239. if (likely(!(netdev->features & NETIF_F_RXFCS)))
  1240. packet_size -= 4; /* CRC */
  1241. skb = netdev_alloc_skb_ip_align(netdev, packet_size);
  1242. if (skb == NULL)
  1243. goto skip_pkt;
  1244. memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
  1245. skb_put(skb, packet_size);
  1246. skb->protocol = eth_type_trans(skb, netdev);
  1247. atl1e_rx_checksum(adapter, skb, prrs);
  1248. if (prrs->pkt_flag & RRS_IS_VLAN_TAG) {
  1249. u16 vlan_tag = (prrs->vtag >> 4) |
  1250. ((prrs->vtag & 7) << 13) |
  1251. ((prrs->vtag & 8) << 9);
  1252. netdev_dbg(netdev,
  1253. "RXD VLAN TAG<RRD>=0x%04x\n",
  1254. prrs->vtag);
  1255. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
  1256. }
  1257. napi_gro_receive(&adapter->napi, skb);
  1258. skip_pkt:
  1259. /* skip current packet whether it's ok or not. */
  1260. rx_page->read_offset +=
  1261. (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
  1262. RRS_PKT_SIZE_MASK) +
  1263. sizeof(struct atl1e_recv_ret_status) + 31) &
  1264. 0xFFFFFFE0);
  1265. if (rx_page->read_offset >= rx_ring->page_size) {
  1266. /* mark this page clean */
  1267. u16 reg_addr;
  1268. u8 rx_using;
  1269. rx_page->read_offset =
  1270. *(rx_page->write_offset_addr) = 0;
  1271. rx_using = rx_page_desc[que].rx_using;
  1272. reg_addr =
  1273. atl1e_rx_page_vld_regs[que][rx_using];
  1274. AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
  1275. rx_page_desc[que].rx_using ^= 1;
  1276. rx_page = atl1e_get_rx_page(adapter, que);
  1277. }
  1278. write_offset = *(rx_page->write_offset_addr);
  1279. } while (rx_page->read_offset < write_offset);
  1280. }
  1281. return;
  1282. fatal_err:
  1283. if (!test_bit(__AT_DOWN, &adapter->flags))
  1284. schedule_work(&adapter->reset_task);
  1285. }
  1286. /**
  1287. * atl1e_clean - NAPI Rx polling callback
  1288. */
  1289. static int atl1e_clean(struct napi_struct *napi, int budget)
  1290. {
  1291. struct atl1e_adapter *adapter =
  1292. container_of(napi, struct atl1e_adapter, napi);
  1293. u32 imr_data;
  1294. int work_done = 0;
  1295. /* Keep link state information with original netdev */
  1296. if (!netif_carrier_ok(adapter->netdev))
  1297. goto quit_polling;
  1298. atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
  1299. /* If no Tx and not enough Rx work done, exit the polling mode */
  1300. if (work_done < budget) {
  1301. quit_polling:
  1302. napi_complete_done(napi, work_done);
  1303. imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
  1304. AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
  1305. /* test debug */
  1306. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1307. atomic_dec(&adapter->irq_sem);
  1308. netdev_err(adapter->netdev,
  1309. "atl1e_clean is called when AT_DOWN\n");
  1310. }
  1311. /* reenable RX intr */
  1312. /*atl1e_irq_enable(adapter); */
  1313. }
  1314. return work_done;
  1315. }
  1316. #ifdef CONFIG_NET_POLL_CONTROLLER
  1317. /*
  1318. * Polling 'interrupt' - used by things like netconsole to send skbs
  1319. * without having to re-enable interrupts. It's not called while
  1320. * the interrupt routine is executing.
  1321. */
  1322. static void atl1e_netpoll(struct net_device *netdev)
  1323. {
  1324. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1325. disable_irq(adapter->pdev->irq);
  1326. atl1e_intr(adapter->pdev->irq, netdev);
  1327. enable_irq(adapter->pdev->irq);
  1328. }
  1329. #endif
  1330. static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
  1331. {
  1332. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  1333. u16 next_to_use = 0;
  1334. u16 next_to_clean = 0;
  1335. next_to_clean = atomic_read(&tx_ring->next_to_clean);
  1336. next_to_use = tx_ring->next_to_use;
  1337. return (u16)(next_to_clean > next_to_use) ?
  1338. (next_to_clean - next_to_use - 1) :
  1339. (tx_ring->count + next_to_clean - next_to_use - 1);
  1340. }
  1341. /*
  1342. * get next usable tpd
  1343. * Note: should call atl1e_tdp_avail to make sure
  1344. * there is enough tpd to use
  1345. */
  1346. static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
  1347. {
  1348. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  1349. u16 next_to_use = 0;
  1350. next_to_use = tx_ring->next_to_use;
  1351. if (++tx_ring->next_to_use == tx_ring->count)
  1352. tx_ring->next_to_use = 0;
  1353. memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
  1354. return &tx_ring->desc[next_to_use];
  1355. }
  1356. static struct atl1e_tx_buffer *
  1357. atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
  1358. {
  1359. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  1360. return &tx_ring->tx_buffer[tpd - tx_ring->desc];
  1361. }
  1362. /* Calculate the transmit packet descript needed*/
  1363. static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
  1364. {
  1365. int i = 0;
  1366. u16 tpd_req = 1;
  1367. u16 fg_size = 0;
  1368. u16 proto_hdr_len = 0;
  1369. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1370. fg_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
  1371. tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
  1372. }
  1373. if (skb_is_gso(skb)) {
  1374. if (skb->protocol == htons(ETH_P_IP) ||
  1375. (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
  1376. proto_hdr_len = skb_transport_offset(skb) +
  1377. tcp_hdrlen(skb);
  1378. if (proto_hdr_len < skb_headlen(skb)) {
  1379. tpd_req += ((skb_headlen(skb) - proto_hdr_len +
  1380. MAX_TX_BUF_LEN - 1) >>
  1381. MAX_TX_BUF_SHIFT);
  1382. }
  1383. }
  1384. }
  1385. return tpd_req;
  1386. }
  1387. static int atl1e_tso_csum(struct atl1e_adapter *adapter,
  1388. struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
  1389. {
  1390. unsigned short offload_type;
  1391. u8 hdr_len;
  1392. u32 real_len;
  1393. if (skb_is_gso(skb)) {
  1394. int err;
  1395. err = skb_cow_head(skb, 0);
  1396. if (err < 0)
  1397. return err;
  1398. offload_type = skb_shinfo(skb)->gso_type;
  1399. if (offload_type & SKB_GSO_TCPV4) {
  1400. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1401. + ntohs(ip_hdr(skb)->tot_len));
  1402. if (real_len < skb->len)
  1403. pskb_trim(skb, real_len);
  1404. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1405. if (unlikely(skb->len == hdr_len)) {
  1406. /* only xsum need */
  1407. netdev_warn(adapter->netdev,
  1408. "IPV4 tso with zero data??\n");
  1409. goto check_sum;
  1410. } else {
  1411. ip_hdr(skb)->check = 0;
  1412. ip_hdr(skb)->tot_len = 0;
  1413. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1414. ip_hdr(skb)->saddr,
  1415. ip_hdr(skb)->daddr,
  1416. 0, IPPROTO_TCP, 0);
  1417. tpd->word3 |= (ip_hdr(skb)->ihl &
  1418. TDP_V4_IPHL_MASK) <<
  1419. TPD_V4_IPHL_SHIFT;
  1420. tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
  1421. TPD_TCPHDRLEN_MASK) <<
  1422. TPD_TCPHDRLEN_SHIFT;
  1423. tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
  1424. TPD_MSS_MASK) << TPD_MSS_SHIFT;
  1425. tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
  1426. }
  1427. return 0;
  1428. }
  1429. }
  1430. check_sum:
  1431. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1432. u8 css, cso;
  1433. cso = skb_checksum_start_offset(skb);
  1434. if (unlikely(cso & 0x1)) {
  1435. netdev_err(adapter->netdev,
  1436. "payload offset should not ant event number\n");
  1437. return -1;
  1438. } else {
  1439. css = cso + skb->csum_offset;
  1440. tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
  1441. TPD_PLOADOFFSET_SHIFT;
  1442. tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
  1443. TPD_CCSUMOFFSET_SHIFT;
  1444. tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
  1445. }
  1446. }
  1447. return 0;
  1448. }
  1449. static int atl1e_tx_map(struct atl1e_adapter *adapter,
  1450. struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
  1451. {
  1452. struct atl1e_tpd_desc *use_tpd = NULL;
  1453. struct atl1e_tx_buffer *tx_buffer = NULL;
  1454. u16 buf_len = skb_headlen(skb);
  1455. u16 map_len = 0;
  1456. u16 mapped_len = 0;
  1457. u16 hdr_len = 0;
  1458. u16 nr_frags;
  1459. u16 f;
  1460. int segment;
  1461. int ring_start = adapter->tx_ring.next_to_use;
  1462. int ring_end;
  1463. nr_frags = skb_shinfo(skb)->nr_frags;
  1464. segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
  1465. if (segment) {
  1466. /* TSO */
  1467. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1468. use_tpd = tpd;
  1469. tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
  1470. tx_buffer->length = map_len;
  1471. tx_buffer->dma = pci_map_single(adapter->pdev,
  1472. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1473. if (dma_mapping_error(&adapter->pdev->dev, tx_buffer->dma))
  1474. return -ENOSPC;
  1475. ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
  1476. mapped_len += map_len;
  1477. use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
  1478. use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
  1479. ((cpu_to_le32(tx_buffer->length) &
  1480. TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
  1481. }
  1482. while (mapped_len < buf_len) {
  1483. /* mapped_len == 0, means we should use the first tpd,
  1484. which is given by caller */
  1485. if (mapped_len == 0) {
  1486. use_tpd = tpd;
  1487. } else {
  1488. use_tpd = atl1e_get_tpd(adapter);
  1489. memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
  1490. }
  1491. tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
  1492. tx_buffer->skb = NULL;
  1493. tx_buffer->length = map_len =
  1494. ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
  1495. MAX_TX_BUF_LEN : (buf_len - mapped_len);
  1496. tx_buffer->dma =
  1497. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1498. map_len, PCI_DMA_TODEVICE);
  1499. if (dma_mapping_error(&adapter->pdev->dev, tx_buffer->dma)) {
  1500. /* We need to unwind the mappings we've done */
  1501. ring_end = adapter->tx_ring.next_to_use;
  1502. adapter->tx_ring.next_to_use = ring_start;
  1503. while (adapter->tx_ring.next_to_use != ring_end) {
  1504. tpd = atl1e_get_tpd(adapter);
  1505. tx_buffer = atl1e_get_tx_buffer(adapter, tpd);
  1506. pci_unmap_single(adapter->pdev, tx_buffer->dma,
  1507. tx_buffer->length, PCI_DMA_TODEVICE);
  1508. }
  1509. /* Reset the tx rings next pointer */
  1510. adapter->tx_ring.next_to_use = ring_start;
  1511. return -ENOSPC;
  1512. }
  1513. ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
  1514. mapped_len += map_len;
  1515. use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
  1516. use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
  1517. ((cpu_to_le32(tx_buffer->length) &
  1518. TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
  1519. }
  1520. for (f = 0; f < nr_frags; f++) {
  1521. const struct skb_frag_struct *frag;
  1522. u16 i;
  1523. u16 seg_num;
  1524. frag = &skb_shinfo(skb)->frags[f];
  1525. buf_len = skb_frag_size(frag);
  1526. seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
  1527. for (i = 0; i < seg_num; i++) {
  1528. use_tpd = atl1e_get_tpd(adapter);
  1529. memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
  1530. tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
  1531. BUG_ON(tx_buffer->skb);
  1532. tx_buffer->skb = NULL;
  1533. tx_buffer->length =
  1534. (buf_len > MAX_TX_BUF_LEN) ?
  1535. MAX_TX_BUF_LEN : buf_len;
  1536. buf_len -= tx_buffer->length;
  1537. tx_buffer->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1538. frag,
  1539. (i * MAX_TX_BUF_LEN),
  1540. tx_buffer->length,
  1541. DMA_TO_DEVICE);
  1542. if (dma_mapping_error(&adapter->pdev->dev, tx_buffer->dma)) {
  1543. /* We need to unwind the mappings we've done */
  1544. ring_end = adapter->tx_ring.next_to_use;
  1545. adapter->tx_ring.next_to_use = ring_start;
  1546. while (adapter->tx_ring.next_to_use != ring_end) {
  1547. tpd = atl1e_get_tpd(adapter);
  1548. tx_buffer = atl1e_get_tx_buffer(adapter, tpd);
  1549. dma_unmap_page(&adapter->pdev->dev, tx_buffer->dma,
  1550. tx_buffer->length, DMA_TO_DEVICE);
  1551. }
  1552. /* Reset the ring next to use pointer */
  1553. adapter->tx_ring.next_to_use = ring_start;
  1554. return -ENOSPC;
  1555. }
  1556. ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_PAGE);
  1557. use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
  1558. use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
  1559. ((cpu_to_le32(tx_buffer->length) &
  1560. TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
  1561. }
  1562. }
  1563. if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
  1564. /* note this one is a tcp header */
  1565. tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
  1566. /* The last tpd */
  1567. use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
  1568. /* The last buffer info contain the skb address,
  1569. so it will be free after unmap */
  1570. tx_buffer->skb = skb;
  1571. return 0;
  1572. }
  1573. static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
  1574. struct atl1e_tpd_desc *tpd)
  1575. {
  1576. struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
  1577. /* Force memory writes to complete before letting h/w
  1578. * know there are new descriptors to fetch. (Only
  1579. * applicable for weak-ordered memory model archs,
  1580. * such as IA-64). */
  1581. wmb();
  1582. AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
  1583. }
  1584. static netdev_tx_t atl1e_xmit_frame(struct sk_buff *skb,
  1585. struct net_device *netdev)
  1586. {
  1587. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1588. u16 tpd_req = 1;
  1589. struct atl1e_tpd_desc *tpd;
  1590. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1591. dev_kfree_skb_any(skb);
  1592. return NETDEV_TX_OK;
  1593. }
  1594. if (unlikely(skb->len <= 0)) {
  1595. dev_kfree_skb_any(skb);
  1596. return NETDEV_TX_OK;
  1597. }
  1598. tpd_req = atl1e_cal_tdp_req(skb);
  1599. if (atl1e_tpd_avail(adapter) < tpd_req) {
  1600. /* no enough descriptor, just stop queue */
  1601. netif_stop_queue(netdev);
  1602. return NETDEV_TX_BUSY;
  1603. }
  1604. tpd = atl1e_get_tpd(adapter);
  1605. if (skb_vlan_tag_present(skb)) {
  1606. u16 vlan_tag = skb_vlan_tag_get(skb);
  1607. u16 atl1e_vlan_tag;
  1608. tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
  1609. AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
  1610. tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
  1611. TPD_VLAN_SHIFT;
  1612. }
  1613. if (skb->protocol == htons(ETH_P_8021Q))
  1614. tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
  1615. if (skb_network_offset(skb) != ETH_HLEN)
  1616. tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
  1617. /* do TSO and check sum */
  1618. if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
  1619. dev_kfree_skb_any(skb);
  1620. return NETDEV_TX_OK;
  1621. }
  1622. if (atl1e_tx_map(adapter, skb, tpd)) {
  1623. dev_kfree_skb_any(skb);
  1624. goto out;
  1625. }
  1626. atl1e_tx_queue(adapter, tpd_req, tpd);
  1627. out:
  1628. return NETDEV_TX_OK;
  1629. }
  1630. static void atl1e_free_irq(struct atl1e_adapter *adapter)
  1631. {
  1632. struct net_device *netdev = adapter->netdev;
  1633. free_irq(adapter->pdev->irq, netdev);
  1634. }
  1635. static int atl1e_request_irq(struct atl1e_adapter *adapter)
  1636. {
  1637. struct pci_dev *pdev = adapter->pdev;
  1638. struct net_device *netdev = adapter->netdev;
  1639. int err = 0;
  1640. err = request_irq(pdev->irq, atl1e_intr, IRQF_SHARED, netdev->name,
  1641. netdev);
  1642. if (err) {
  1643. netdev_dbg(adapter->netdev,
  1644. "Unable to allocate interrupt Error: %d\n", err);
  1645. return err;
  1646. }
  1647. netdev_dbg(netdev, "atl1e_request_irq OK\n");
  1648. return err;
  1649. }
  1650. int atl1e_up(struct atl1e_adapter *adapter)
  1651. {
  1652. struct net_device *netdev = adapter->netdev;
  1653. int err = 0;
  1654. u32 val;
  1655. /* hardware has been reset, we need to reload some things */
  1656. err = atl1e_init_hw(&adapter->hw);
  1657. if (err) {
  1658. err = -EIO;
  1659. return err;
  1660. }
  1661. atl1e_init_ring_ptrs(adapter);
  1662. atl1e_set_multi(netdev);
  1663. atl1e_restore_vlan(adapter);
  1664. if (atl1e_configure(adapter)) {
  1665. err = -EIO;
  1666. goto err_up;
  1667. }
  1668. clear_bit(__AT_DOWN, &adapter->flags);
  1669. napi_enable(&adapter->napi);
  1670. atl1e_irq_enable(adapter);
  1671. val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
  1672. AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
  1673. val | MASTER_CTRL_MANUAL_INT);
  1674. err_up:
  1675. return err;
  1676. }
  1677. void atl1e_down(struct atl1e_adapter *adapter)
  1678. {
  1679. struct net_device *netdev = adapter->netdev;
  1680. /* signal that we're down so the interrupt handler does not
  1681. * reschedule our watchdog timer */
  1682. set_bit(__AT_DOWN, &adapter->flags);
  1683. netif_stop_queue(netdev);
  1684. /* reset MAC to disable all RX/TX */
  1685. atl1e_reset_hw(&adapter->hw);
  1686. msleep(1);
  1687. napi_disable(&adapter->napi);
  1688. atl1e_del_timer(adapter);
  1689. atl1e_irq_disable(adapter);
  1690. netif_carrier_off(netdev);
  1691. adapter->link_speed = SPEED_0;
  1692. adapter->link_duplex = -1;
  1693. atl1e_clean_tx_ring(adapter);
  1694. atl1e_clean_rx_ring(adapter);
  1695. }
  1696. /**
  1697. * atl1e_open - Called when a network interface is made active
  1698. * @netdev: network interface device structure
  1699. *
  1700. * Returns 0 on success, negative value on failure
  1701. *
  1702. * The open entry point is called when a network interface is made
  1703. * active by the system (IFF_UP). At this point all resources needed
  1704. * for transmit and receive operations are allocated, the interrupt
  1705. * handler is registered with the OS, the watchdog timer is started,
  1706. * and the stack is notified that the interface is ready.
  1707. */
  1708. static int atl1e_open(struct net_device *netdev)
  1709. {
  1710. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1711. int err;
  1712. /* disallow open during test */
  1713. if (test_bit(__AT_TESTING, &adapter->flags))
  1714. return -EBUSY;
  1715. /* allocate rx/tx dma buffer & descriptors */
  1716. atl1e_init_ring_resources(adapter);
  1717. err = atl1e_setup_ring_resources(adapter);
  1718. if (unlikely(err))
  1719. return err;
  1720. err = atl1e_request_irq(adapter);
  1721. if (unlikely(err))
  1722. goto err_req_irq;
  1723. err = atl1e_up(adapter);
  1724. if (unlikely(err))
  1725. goto err_up;
  1726. return 0;
  1727. err_up:
  1728. atl1e_free_irq(adapter);
  1729. err_req_irq:
  1730. atl1e_free_ring_resources(adapter);
  1731. atl1e_reset_hw(&adapter->hw);
  1732. return err;
  1733. }
  1734. /**
  1735. * atl1e_close - Disables a network interface
  1736. * @netdev: network interface device structure
  1737. *
  1738. * Returns 0, this is not allowed to fail
  1739. *
  1740. * The close entry point is called when an interface is de-activated
  1741. * by the OS. The hardware is still under the drivers control, but
  1742. * needs to be disabled. A global MAC reset is issued to stop the
  1743. * hardware, and all transmit and receive resources are freed.
  1744. */
  1745. static int atl1e_close(struct net_device *netdev)
  1746. {
  1747. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1748. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  1749. atl1e_down(adapter);
  1750. atl1e_free_irq(adapter);
  1751. atl1e_free_ring_resources(adapter);
  1752. return 0;
  1753. }
  1754. static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
  1755. {
  1756. struct net_device *netdev = pci_get_drvdata(pdev);
  1757. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1758. struct atl1e_hw *hw = &adapter->hw;
  1759. u32 ctrl = 0;
  1760. u32 mac_ctrl_data = 0;
  1761. u32 wol_ctrl_data = 0;
  1762. u16 mii_advertise_data = 0;
  1763. u16 mii_bmsr_data = 0;
  1764. u16 mii_intr_status_data = 0;
  1765. u32 wufc = adapter->wol;
  1766. u32 i;
  1767. #ifdef CONFIG_PM
  1768. int retval = 0;
  1769. #endif
  1770. if (netif_running(netdev)) {
  1771. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  1772. atl1e_down(adapter);
  1773. }
  1774. netif_device_detach(netdev);
  1775. #ifdef CONFIG_PM
  1776. retval = pci_save_state(pdev);
  1777. if (retval)
  1778. return retval;
  1779. #endif
  1780. if (wufc) {
  1781. /* get link status */
  1782. atl1e_read_phy_reg(hw, MII_BMSR, &mii_bmsr_data);
  1783. atl1e_read_phy_reg(hw, MII_BMSR, &mii_bmsr_data);
  1784. mii_advertise_data = ADVERTISE_10HALF;
  1785. if ((atl1e_write_phy_reg(hw, MII_CTRL1000, 0) != 0) ||
  1786. (atl1e_write_phy_reg(hw,
  1787. MII_ADVERTISE, mii_advertise_data) != 0) ||
  1788. (atl1e_phy_commit(hw)) != 0) {
  1789. netdev_dbg(adapter->netdev, "set phy register failed\n");
  1790. goto wol_dis;
  1791. }
  1792. hw->phy_configured = false; /* re-init PHY when resume */
  1793. /* turn on magic packet wol */
  1794. if (wufc & AT_WUFC_MAG)
  1795. wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
  1796. if (wufc & AT_WUFC_LNKC) {
  1797. /* if orignal link status is link, just wait for retrive link */
  1798. if (mii_bmsr_data & BMSR_LSTATUS) {
  1799. for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
  1800. msleep(100);
  1801. atl1e_read_phy_reg(hw, MII_BMSR,
  1802. &mii_bmsr_data);
  1803. if (mii_bmsr_data & BMSR_LSTATUS)
  1804. break;
  1805. }
  1806. if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
  1807. netdev_dbg(adapter->netdev,
  1808. "Link may change when suspend\n");
  1809. }
  1810. wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
  1811. /* only link up can wake up */
  1812. if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
  1813. netdev_dbg(adapter->netdev,
  1814. "read write phy register failed\n");
  1815. goto wol_dis;
  1816. }
  1817. }
  1818. /* clear phy interrupt */
  1819. atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
  1820. /* Config MAC Ctrl register */
  1821. mac_ctrl_data = MAC_CTRL_RX_EN;
  1822. /* set to 10/100M halt duplex */
  1823. mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
  1824. mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
  1825. MAC_CTRL_PRMLEN_MASK) <<
  1826. MAC_CTRL_PRMLEN_SHIFT);
  1827. __atl1e_vlan_mode(netdev->features, &mac_ctrl_data);
  1828. /* magic packet maybe Broadcast&multicast&Unicast frame */
  1829. if (wufc & AT_WUFC_MAG)
  1830. mac_ctrl_data |= MAC_CTRL_BC_EN;
  1831. netdev_dbg(adapter->netdev, "suspend MAC=0x%x\n",
  1832. mac_ctrl_data);
  1833. AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
  1834. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  1835. /* pcie patch */
  1836. ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
  1837. ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
  1838. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
  1839. pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
  1840. goto suspend_exit;
  1841. }
  1842. wol_dis:
  1843. /* WOL disabled */
  1844. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1845. /* pcie patch */
  1846. ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
  1847. ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
  1848. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
  1849. atl1e_force_ps(hw);
  1850. hw->phy_configured = false; /* re-init PHY when resume */
  1851. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  1852. suspend_exit:
  1853. if (netif_running(netdev))
  1854. atl1e_free_irq(adapter);
  1855. pci_disable_device(pdev);
  1856. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  1857. return 0;
  1858. }
  1859. #ifdef CONFIG_PM
  1860. static int atl1e_resume(struct pci_dev *pdev)
  1861. {
  1862. struct net_device *netdev = pci_get_drvdata(pdev);
  1863. struct atl1e_adapter *adapter = netdev_priv(netdev);
  1864. u32 err;
  1865. pci_set_power_state(pdev, PCI_D0);
  1866. pci_restore_state(pdev);
  1867. err = pci_enable_device(pdev);
  1868. if (err) {
  1869. netdev_err(adapter->netdev,
  1870. "Cannot enable PCI device from suspend\n");
  1871. return err;
  1872. }
  1873. pci_set_master(pdev);
  1874. AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
  1875. pci_enable_wake(pdev, PCI_D3hot, 0);
  1876. pci_enable_wake(pdev, PCI_D3cold, 0);
  1877. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  1878. if (netif_running(netdev)) {
  1879. err = atl1e_request_irq(adapter);
  1880. if (err)
  1881. return err;
  1882. }
  1883. atl1e_reset_hw(&adapter->hw);
  1884. if (netif_running(netdev))
  1885. atl1e_up(adapter);
  1886. netif_device_attach(netdev);
  1887. return 0;
  1888. }
  1889. #endif
  1890. static void atl1e_shutdown(struct pci_dev *pdev)
  1891. {
  1892. atl1e_suspend(pdev, PMSG_SUSPEND);
  1893. }
  1894. static const struct net_device_ops atl1e_netdev_ops = {
  1895. .ndo_open = atl1e_open,
  1896. .ndo_stop = atl1e_close,
  1897. .ndo_start_xmit = atl1e_xmit_frame,
  1898. .ndo_get_stats = atl1e_get_stats,
  1899. .ndo_set_rx_mode = atl1e_set_multi,
  1900. .ndo_validate_addr = eth_validate_addr,
  1901. .ndo_set_mac_address = atl1e_set_mac_addr,
  1902. .ndo_fix_features = atl1e_fix_features,
  1903. .ndo_set_features = atl1e_set_features,
  1904. .ndo_change_mtu = atl1e_change_mtu,
  1905. .ndo_do_ioctl = atl1e_ioctl,
  1906. .ndo_tx_timeout = atl1e_tx_timeout,
  1907. #ifdef CONFIG_NET_POLL_CONTROLLER
  1908. .ndo_poll_controller = atl1e_netpoll,
  1909. #endif
  1910. };
  1911. static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  1912. {
  1913. SET_NETDEV_DEV(netdev, &pdev->dev);
  1914. pci_set_drvdata(pdev, netdev);
  1915. netdev->netdev_ops = &atl1e_netdev_ops;
  1916. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  1917. /* MTU range: 42 - 8170 */
  1918. netdev->min_mtu = ETH_ZLEN - (ETH_HLEN + VLAN_HLEN);
  1919. netdev->max_mtu = MAX_JUMBO_FRAME_SIZE -
  1920. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  1921. atl1e_set_ethtool_ops(netdev);
  1922. netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO |
  1923. NETIF_F_HW_VLAN_CTAG_RX;
  1924. netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_TX;
  1925. /* not enabled by default */
  1926. netdev->hw_features |= NETIF_F_RXALL | NETIF_F_RXFCS;
  1927. return 0;
  1928. }
  1929. /**
  1930. * atl1e_probe - Device Initialization Routine
  1931. * @pdev: PCI device information struct
  1932. * @ent: entry in atl1e_pci_tbl
  1933. *
  1934. * Returns 0 on success, negative on failure
  1935. *
  1936. * atl1e_probe initializes an adapter identified by a pci_dev structure.
  1937. * The OS initialization, configuring of the adapter private structure,
  1938. * and a hardware reset occur.
  1939. */
  1940. static int atl1e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1941. {
  1942. struct net_device *netdev;
  1943. struct atl1e_adapter *adapter = NULL;
  1944. static int cards_found;
  1945. int err = 0;
  1946. err = pci_enable_device(pdev);
  1947. if (err) {
  1948. dev_err(&pdev->dev, "cannot enable PCI device\n");
  1949. return err;
  1950. }
  1951. /*
  1952. * The atl1e chip can DMA to 64-bit addresses, but it uses a single
  1953. * shared register for the high 32 bits, so only a single, aligned,
  1954. * 4 GB physical address range can be used at a time.
  1955. *
  1956. * Supporting 64-bit DMA on this hardware is more trouble than it's
  1957. * worth. It is far easier to limit to 32-bit DMA than update
  1958. * various kernel subsystems to support the mechanics required by a
  1959. * fixed-high-32-bit system.
  1960. */
  1961. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  1962. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  1963. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  1964. goto err_dma;
  1965. }
  1966. err = pci_request_regions(pdev, atl1e_driver_name);
  1967. if (err) {
  1968. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  1969. goto err_pci_reg;
  1970. }
  1971. pci_set_master(pdev);
  1972. netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
  1973. if (netdev == NULL) {
  1974. err = -ENOMEM;
  1975. goto err_alloc_etherdev;
  1976. }
  1977. err = atl1e_init_netdev(netdev, pdev);
  1978. if (err) {
  1979. netdev_err(netdev, "init netdevice failed\n");
  1980. goto err_init_netdev;
  1981. }
  1982. adapter = netdev_priv(netdev);
  1983. adapter->bd_number = cards_found;
  1984. adapter->netdev = netdev;
  1985. adapter->pdev = pdev;
  1986. adapter->hw.adapter = adapter;
  1987. adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
  1988. if (!adapter->hw.hw_addr) {
  1989. err = -EIO;
  1990. netdev_err(netdev, "cannot map device registers\n");
  1991. goto err_ioremap;
  1992. }
  1993. /* init mii data */
  1994. adapter->mii.dev = netdev;
  1995. adapter->mii.mdio_read = atl1e_mdio_read;
  1996. adapter->mii.mdio_write = atl1e_mdio_write;
  1997. adapter->mii.phy_id_mask = 0x1f;
  1998. adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
  1999. netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
  2000. timer_setup(&adapter->phy_config_timer, atl1e_phy_config, 0);
  2001. /* get user settings */
  2002. atl1e_check_options(adapter);
  2003. /*
  2004. * Mark all PCI regions associated with PCI device
  2005. * pdev as being reserved by owner atl1e_driver_name
  2006. * Enables bus-mastering on the device and calls
  2007. * pcibios_set_master to do the needed arch specific settings
  2008. */
  2009. atl1e_setup_pcicmd(pdev);
  2010. /* setup the private structure */
  2011. err = atl1e_sw_init(adapter);
  2012. if (err) {
  2013. netdev_err(netdev, "net device private data init failed\n");
  2014. goto err_sw_init;
  2015. }
  2016. /* Init GPHY as early as possible due to power saving issue */
  2017. atl1e_phy_init(&adapter->hw);
  2018. /* reset the controller to
  2019. * put the device in a known good starting state */
  2020. err = atl1e_reset_hw(&adapter->hw);
  2021. if (err) {
  2022. err = -EIO;
  2023. goto err_reset;
  2024. }
  2025. if (atl1e_read_mac_addr(&adapter->hw) != 0) {
  2026. err = -EIO;
  2027. netdev_err(netdev, "get mac address failed\n");
  2028. goto err_eeprom;
  2029. }
  2030. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2031. netdev_dbg(netdev, "mac address : %pM\n", adapter->hw.mac_addr);
  2032. INIT_WORK(&adapter->reset_task, atl1e_reset_task);
  2033. INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
  2034. netif_set_gso_max_size(netdev, MAX_TSO_SEG_SIZE);
  2035. err = register_netdev(netdev);
  2036. if (err) {
  2037. netdev_err(netdev, "register netdevice failed\n");
  2038. goto err_register;
  2039. }
  2040. /* assume we have no link for now */
  2041. netif_stop_queue(netdev);
  2042. netif_carrier_off(netdev);
  2043. cards_found++;
  2044. return 0;
  2045. err_reset:
  2046. err_register:
  2047. err_sw_init:
  2048. err_eeprom:
  2049. pci_iounmap(pdev, adapter->hw.hw_addr);
  2050. err_init_netdev:
  2051. err_ioremap:
  2052. free_netdev(netdev);
  2053. err_alloc_etherdev:
  2054. pci_release_regions(pdev);
  2055. err_pci_reg:
  2056. err_dma:
  2057. pci_disable_device(pdev);
  2058. return err;
  2059. }
  2060. /**
  2061. * atl1e_remove - Device Removal Routine
  2062. * @pdev: PCI device information struct
  2063. *
  2064. * atl1e_remove is called by the PCI subsystem to alert the driver
  2065. * that it should release a PCI device. The could be caused by a
  2066. * Hot-Plug event, or because the driver is going to be removed from
  2067. * memory.
  2068. */
  2069. static void atl1e_remove(struct pci_dev *pdev)
  2070. {
  2071. struct net_device *netdev = pci_get_drvdata(pdev);
  2072. struct atl1e_adapter *adapter = netdev_priv(netdev);
  2073. /*
  2074. * flush_scheduled work may reschedule our watchdog task, so
  2075. * explicitly disable watchdog tasks from being rescheduled
  2076. */
  2077. set_bit(__AT_DOWN, &adapter->flags);
  2078. atl1e_del_timer(adapter);
  2079. atl1e_cancel_work(adapter);
  2080. unregister_netdev(netdev);
  2081. atl1e_free_ring_resources(adapter);
  2082. atl1e_force_ps(&adapter->hw);
  2083. pci_iounmap(pdev, adapter->hw.hw_addr);
  2084. pci_release_regions(pdev);
  2085. free_netdev(netdev);
  2086. pci_disable_device(pdev);
  2087. }
  2088. /**
  2089. * atl1e_io_error_detected - called when PCI error is detected
  2090. * @pdev: Pointer to PCI device
  2091. * @state: The current pci connection state
  2092. *
  2093. * This function is called after a PCI bus error affecting
  2094. * this device has been detected.
  2095. */
  2096. static pci_ers_result_t
  2097. atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  2098. {
  2099. struct net_device *netdev = pci_get_drvdata(pdev);
  2100. struct atl1e_adapter *adapter = netdev_priv(netdev);
  2101. netif_device_detach(netdev);
  2102. if (state == pci_channel_io_perm_failure)
  2103. return PCI_ERS_RESULT_DISCONNECT;
  2104. if (netif_running(netdev))
  2105. atl1e_down(adapter);
  2106. pci_disable_device(pdev);
  2107. /* Request a slot slot reset. */
  2108. return PCI_ERS_RESULT_NEED_RESET;
  2109. }
  2110. /**
  2111. * atl1e_io_slot_reset - called after the pci bus has been reset.
  2112. * @pdev: Pointer to PCI device
  2113. *
  2114. * Restart the card from scratch, as if from a cold-boot. Implementation
  2115. * resembles the first-half of the e1000_resume routine.
  2116. */
  2117. static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
  2118. {
  2119. struct net_device *netdev = pci_get_drvdata(pdev);
  2120. struct atl1e_adapter *adapter = netdev_priv(netdev);
  2121. if (pci_enable_device(pdev)) {
  2122. netdev_err(adapter->netdev,
  2123. "Cannot re-enable PCI device after reset\n");
  2124. return PCI_ERS_RESULT_DISCONNECT;
  2125. }
  2126. pci_set_master(pdev);
  2127. pci_enable_wake(pdev, PCI_D3hot, 0);
  2128. pci_enable_wake(pdev, PCI_D3cold, 0);
  2129. atl1e_reset_hw(&adapter->hw);
  2130. return PCI_ERS_RESULT_RECOVERED;
  2131. }
  2132. /**
  2133. * atl1e_io_resume - called when traffic can start flowing again.
  2134. * @pdev: Pointer to PCI device
  2135. *
  2136. * This callback is called when the error recovery driver tells us that
  2137. * its OK to resume normal operation. Implementation resembles the
  2138. * second-half of the atl1e_resume routine.
  2139. */
  2140. static void atl1e_io_resume(struct pci_dev *pdev)
  2141. {
  2142. struct net_device *netdev = pci_get_drvdata(pdev);
  2143. struct atl1e_adapter *adapter = netdev_priv(netdev);
  2144. if (netif_running(netdev)) {
  2145. if (atl1e_up(adapter)) {
  2146. netdev_err(adapter->netdev,
  2147. "can't bring device back up after reset\n");
  2148. return;
  2149. }
  2150. }
  2151. netif_device_attach(netdev);
  2152. }
  2153. static const struct pci_error_handlers atl1e_err_handler = {
  2154. .error_detected = atl1e_io_error_detected,
  2155. .slot_reset = atl1e_io_slot_reset,
  2156. .resume = atl1e_io_resume,
  2157. };
  2158. static struct pci_driver atl1e_driver = {
  2159. .name = atl1e_driver_name,
  2160. .id_table = atl1e_pci_tbl,
  2161. .probe = atl1e_probe,
  2162. .remove = atl1e_remove,
  2163. /* Power Management Hooks */
  2164. #ifdef CONFIG_PM
  2165. .suspend = atl1e_suspend,
  2166. .resume = atl1e_resume,
  2167. #endif
  2168. .shutdown = atl1e_shutdown,
  2169. .err_handler = &atl1e_err_handler
  2170. };
  2171. module_pci_driver(atl1e_driver);