nand_base.c 171 KB

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  1. /*
  2. * Overview:
  3. * This is the generic MTD driver for NAND flash devices. It should be
  4. * capable of working with almost all NAND chips currently available.
  5. *
  6. * Additional technical information is available on
  7. * http://www.linux-mtd.infradead.org/doc/nand.html
  8. *
  9. * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  10. * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
  11. *
  12. * Credits:
  13. * David Woodhouse for adding multichip support
  14. *
  15. * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  16. * rework for 2K page size chips
  17. *
  18. * TODO:
  19. * Enable cached programming for 2k page size chips
  20. * Check, if mtd->ecctype should be set to MTD_ECC_HW
  21. * if we have HW ECC support.
  22. * BBT table is not serialized, has to be fixed
  23. *
  24. * This program is free software; you can redistribute it and/or modify
  25. * it under the terms of the GNU General Public License version 2 as
  26. * published by the Free Software Foundation.
  27. *
  28. */
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/module.h>
  31. #include <linux/delay.h>
  32. #include <linux/errno.h>
  33. #include <linux/err.h>
  34. #include <linux/sched.h>
  35. #include <linux/slab.h>
  36. #include <linux/mm.h>
  37. #include <linux/nmi.h>
  38. #include <linux/types.h>
  39. #include <linux/mtd/mtd.h>
  40. #include <linux/mtd/rawnand.h>
  41. #include <linux/mtd/nand_ecc.h>
  42. #include <linux/mtd/nand_bch.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/bitops.h>
  45. #include <linux/io.h>
  46. #include <linux/mtd/partitions.h>
  47. #include <linux/of.h>
  48. static int nand_get_device(struct mtd_info *mtd, int new_state);
  49. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  50. struct mtd_oob_ops *ops);
  51. /* Define default oob placement schemes for large and small page devices */
  52. static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
  53. struct mtd_oob_region *oobregion)
  54. {
  55. struct nand_chip *chip = mtd_to_nand(mtd);
  56. struct nand_ecc_ctrl *ecc = &chip->ecc;
  57. if (section > 1)
  58. return -ERANGE;
  59. if (!section) {
  60. oobregion->offset = 0;
  61. if (mtd->oobsize == 16)
  62. oobregion->length = 4;
  63. else
  64. oobregion->length = 3;
  65. } else {
  66. if (mtd->oobsize == 8)
  67. return -ERANGE;
  68. oobregion->offset = 6;
  69. oobregion->length = ecc->total - 4;
  70. }
  71. return 0;
  72. }
  73. static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
  74. struct mtd_oob_region *oobregion)
  75. {
  76. if (section > 1)
  77. return -ERANGE;
  78. if (mtd->oobsize == 16) {
  79. if (section)
  80. return -ERANGE;
  81. oobregion->length = 8;
  82. oobregion->offset = 8;
  83. } else {
  84. oobregion->length = 2;
  85. if (!section)
  86. oobregion->offset = 3;
  87. else
  88. oobregion->offset = 6;
  89. }
  90. return 0;
  91. }
  92. const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
  93. .ecc = nand_ooblayout_ecc_sp,
  94. .free = nand_ooblayout_free_sp,
  95. };
  96. EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
  97. static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
  98. struct mtd_oob_region *oobregion)
  99. {
  100. struct nand_chip *chip = mtd_to_nand(mtd);
  101. struct nand_ecc_ctrl *ecc = &chip->ecc;
  102. if (section || !ecc->total)
  103. return -ERANGE;
  104. oobregion->length = ecc->total;
  105. oobregion->offset = mtd->oobsize - oobregion->length;
  106. return 0;
  107. }
  108. static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
  109. struct mtd_oob_region *oobregion)
  110. {
  111. struct nand_chip *chip = mtd_to_nand(mtd);
  112. struct nand_ecc_ctrl *ecc = &chip->ecc;
  113. if (section)
  114. return -ERANGE;
  115. oobregion->length = mtd->oobsize - ecc->total - 2;
  116. oobregion->offset = 2;
  117. return 0;
  118. }
  119. const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
  120. .ecc = nand_ooblayout_ecc_lp,
  121. .free = nand_ooblayout_free_lp,
  122. };
  123. EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
  124. /*
  125. * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
  126. * are placed at a fixed offset.
  127. */
  128. static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
  129. struct mtd_oob_region *oobregion)
  130. {
  131. struct nand_chip *chip = mtd_to_nand(mtd);
  132. struct nand_ecc_ctrl *ecc = &chip->ecc;
  133. if (section)
  134. return -ERANGE;
  135. switch (mtd->oobsize) {
  136. case 64:
  137. oobregion->offset = 40;
  138. break;
  139. case 128:
  140. oobregion->offset = 80;
  141. break;
  142. default:
  143. return -EINVAL;
  144. }
  145. oobregion->length = ecc->total;
  146. if (oobregion->offset + oobregion->length > mtd->oobsize)
  147. return -ERANGE;
  148. return 0;
  149. }
  150. static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
  151. struct mtd_oob_region *oobregion)
  152. {
  153. struct nand_chip *chip = mtd_to_nand(mtd);
  154. struct nand_ecc_ctrl *ecc = &chip->ecc;
  155. int ecc_offset = 0;
  156. if (section < 0 || section > 1)
  157. return -ERANGE;
  158. switch (mtd->oobsize) {
  159. case 64:
  160. ecc_offset = 40;
  161. break;
  162. case 128:
  163. ecc_offset = 80;
  164. break;
  165. default:
  166. return -EINVAL;
  167. }
  168. if (section == 0) {
  169. oobregion->offset = 2;
  170. oobregion->length = ecc_offset - 2;
  171. } else {
  172. oobregion->offset = ecc_offset + ecc->total;
  173. oobregion->length = mtd->oobsize - oobregion->offset;
  174. }
  175. return 0;
  176. }
  177. static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
  178. .ecc = nand_ooblayout_ecc_lp_hamming,
  179. .free = nand_ooblayout_free_lp_hamming,
  180. };
  181. static int check_offs_len(struct mtd_info *mtd,
  182. loff_t ofs, uint64_t len)
  183. {
  184. struct nand_chip *chip = mtd_to_nand(mtd);
  185. int ret = 0;
  186. /* Start address must align on block boundary */
  187. if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
  188. pr_debug("%s: unaligned address\n", __func__);
  189. ret = -EINVAL;
  190. }
  191. /* Length must align on block boundary */
  192. if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
  193. pr_debug("%s: length not block aligned\n", __func__);
  194. ret = -EINVAL;
  195. }
  196. return ret;
  197. }
  198. /**
  199. * nand_release_device - [GENERIC] release chip
  200. * @mtd: MTD device structure
  201. *
  202. * Release chip lock and wake up anyone waiting on the device.
  203. */
  204. static void nand_release_device(struct mtd_info *mtd)
  205. {
  206. struct nand_chip *chip = mtd_to_nand(mtd);
  207. /* Release the controller and the chip */
  208. spin_lock(&chip->controller->lock);
  209. chip->controller->active = NULL;
  210. chip->state = FL_READY;
  211. wake_up(&chip->controller->wq);
  212. spin_unlock(&chip->controller->lock);
  213. }
  214. /**
  215. * nand_read_byte - [DEFAULT] read one byte from the chip
  216. * @mtd: MTD device structure
  217. *
  218. * Default read function for 8bit buswidth
  219. */
  220. static uint8_t nand_read_byte(struct mtd_info *mtd)
  221. {
  222. struct nand_chip *chip = mtd_to_nand(mtd);
  223. return readb(chip->IO_ADDR_R);
  224. }
  225. /**
  226. * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  227. * @mtd: MTD device structure
  228. *
  229. * Default read function for 16bit buswidth with endianness conversion.
  230. *
  231. */
  232. static uint8_t nand_read_byte16(struct mtd_info *mtd)
  233. {
  234. struct nand_chip *chip = mtd_to_nand(mtd);
  235. return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
  236. }
  237. /**
  238. * nand_read_word - [DEFAULT] read one word from the chip
  239. * @mtd: MTD device structure
  240. *
  241. * Default read function for 16bit buswidth without endianness conversion.
  242. */
  243. static u16 nand_read_word(struct mtd_info *mtd)
  244. {
  245. struct nand_chip *chip = mtd_to_nand(mtd);
  246. return readw(chip->IO_ADDR_R);
  247. }
  248. /**
  249. * nand_select_chip - [DEFAULT] control CE line
  250. * @mtd: MTD device structure
  251. * @chipnr: chipnumber to select, -1 for deselect
  252. *
  253. * Default select function for 1 chip devices.
  254. */
  255. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  256. {
  257. struct nand_chip *chip = mtd_to_nand(mtd);
  258. switch (chipnr) {
  259. case -1:
  260. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  261. break;
  262. case 0:
  263. break;
  264. default:
  265. BUG();
  266. }
  267. }
  268. /**
  269. * nand_write_byte - [DEFAULT] write single byte to chip
  270. * @mtd: MTD device structure
  271. * @byte: value to write
  272. *
  273. * Default function to write a byte to I/O[7:0]
  274. */
  275. static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
  276. {
  277. struct nand_chip *chip = mtd_to_nand(mtd);
  278. chip->write_buf(mtd, &byte, 1);
  279. }
  280. /**
  281. * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
  282. * @mtd: MTD device structure
  283. * @byte: value to write
  284. *
  285. * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
  286. */
  287. static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
  288. {
  289. struct nand_chip *chip = mtd_to_nand(mtd);
  290. uint16_t word = byte;
  291. /*
  292. * It's not entirely clear what should happen to I/O[15:8] when writing
  293. * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
  294. *
  295. * When the host supports a 16-bit bus width, only data is
  296. * transferred at the 16-bit width. All address and command line
  297. * transfers shall use only the lower 8-bits of the data bus. During
  298. * command transfers, the host may place any value on the upper
  299. * 8-bits of the data bus. During address transfers, the host shall
  300. * set the upper 8-bits of the data bus to 00h.
  301. *
  302. * One user of the write_byte callback is nand_set_features. The
  303. * four parameters are specified to be written to I/O[7:0], but this is
  304. * neither an address nor a command transfer. Let's assume a 0 on the
  305. * upper I/O lines is OK.
  306. */
  307. chip->write_buf(mtd, (uint8_t *)&word, 2);
  308. }
  309. /**
  310. * nand_write_buf - [DEFAULT] write buffer to chip
  311. * @mtd: MTD device structure
  312. * @buf: data buffer
  313. * @len: number of bytes to write
  314. *
  315. * Default write function for 8bit buswidth.
  316. */
  317. static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  318. {
  319. struct nand_chip *chip = mtd_to_nand(mtd);
  320. iowrite8_rep(chip->IO_ADDR_W, buf, len);
  321. }
  322. /**
  323. * nand_read_buf - [DEFAULT] read chip data into buffer
  324. * @mtd: MTD device structure
  325. * @buf: buffer to store date
  326. * @len: number of bytes to read
  327. *
  328. * Default read function for 8bit buswidth.
  329. */
  330. static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  331. {
  332. struct nand_chip *chip = mtd_to_nand(mtd);
  333. ioread8_rep(chip->IO_ADDR_R, buf, len);
  334. }
  335. /**
  336. * nand_write_buf16 - [DEFAULT] write buffer to chip
  337. * @mtd: MTD device structure
  338. * @buf: data buffer
  339. * @len: number of bytes to write
  340. *
  341. * Default write function for 16bit buswidth.
  342. */
  343. static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  344. {
  345. struct nand_chip *chip = mtd_to_nand(mtd);
  346. u16 *p = (u16 *) buf;
  347. iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
  348. }
  349. /**
  350. * nand_read_buf16 - [DEFAULT] read chip data into buffer
  351. * @mtd: MTD device structure
  352. * @buf: buffer to store date
  353. * @len: number of bytes to read
  354. *
  355. * Default read function for 16bit buswidth.
  356. */
  357. static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  358. {
  359. struct nand_chip *chip = mtd_to_nand(mtd);
  360. u16 *p = (u16 *) buf;
  361. ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
  362. }
  363. /**
  364. * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  365. * @mtd: MTD device structure
  366. * @ofs: offset from device start
  367. *
  368. * Check, if the block is bad.
  369. */
  370. static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  371. {
  372. int page, page_end, res;
  373. struct nand_chip *chip = mtd_to_nand(mtd);
  374. u8 bad;
  375. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  376. ofs += mtd->erasesize - mtd->writesize;
  377. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  378. page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1);
  379. for (; page < page_end; page++) {
  380. res = chip->ecc.read_oob(mtd, chip, page);
  381. if (res)
  382. return res;
  383. bad = chip->oob_poi[chip->badblockpos];
  384. if (likely(chip->badblockbits == 8))
  385. res = bad != 0xFF;
  386. else
  387. res = hweight8(bad) < chip->badblockbits;
  388. if (res)
  389. return res;
  390. }
  391. return 0;
  392. }
  393. /**
  394. * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
  395. * @mtd: MTD device structure
  396. * @ofs: offset from device start
  397. *
  398. * This is the default implementation, which can be overridden by a hardware
  399. * specific driver. It provides the details for writing a bad block marker to a
  400. * block.
  401. */
  402. static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
  403. {
  404. struct nand_chip *chip = mtd_to_nand(mtd);
  405. struct mtd_oob_ops ops;
  406. uint8_t buf[2] = { 0, 0 };
  407. int ret = 0, res, i = 0;
  408. memset(&ops, 0, sizeof(ops));
  409. ops.oobbuf = buf;
  410. ops.ooboffs = chip->badblockpos;
  411. if (chip->options & NAND_BUSWIDTH_16) {
  412. ops.ooboffs &= ~0x01;
  413. ops.len = ops.ooblen = 2;
  414. } else {
  415. ops.len = ops.ooblen = 1;
  416. }
  417. ops.mode = MTD_OPS_PLACE_OOB;
  418. /* Write to first/last page(s) if necessary */
  419. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  420. ofs += mtd->erasesize - mtd->writesize;
  421. do {
  422. res = nand_do_write_oob(mtd, ofs, &ops);
  423. if (!ret)
  424. ret = res;
  425. i++;
  426. ofs += mtd->writesize;
  427. } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
  428. return ret;
  429. }
  430. /**
  431. * nand_block_markbad_lowlevel - mark a block bad
  432. * @mtd: MTD device structure
  433. * @ofs: offset from device start
  434. *
  435. * This function performs the generic NAND bad block marking steps (i.e., bad
  436. * block table(s) and/or marker(s)). We only allow the hardware driver to
  437. * specify how to write bad block markers to OOB (chip->block_markbad).
  438. *
  439. * We try operations in the following order:
  440. *
  441. * (1) erase the affected block, to allow OOB marker to be written cleanly
  442. * (2) write bad block marker to OOB area of affected block (unless flag
  443. * NAND_BBT_NO_OOB_BBM is present)
  444. * (3) update the BBT
  445. *
  446. * Note that we retain the first error encountered in (2) or (3), finish the
  447. * procedures, and dump the error in the end.
  448. */
  449. static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
  450. {
  451. struct nand_chip *chip = mtd_to_nand(mtd);
  452. int res, ret = 0;
  453. if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
  454. struct erase_info einfo;
  455. /* Attempt erase before marking OOB */
  456. memset(&einfo, 0, sizeof(einfo));
  457. einfo.addr = ofs;
  458. einfo.len = 1ULL << chip->phys_erase_shift;
  459. nand_erase_nand(mtd, &einfo, 0);
  460. /* Write bad block marker to OOB */
  461. nand_get_device(mtd, FL_WRITING);
  462. ret = chip->block_markbad(mtd, ofs);
  463. nand_release_device(mtd);
  464. }
  465. /* Mark block bad in BBT */
  466. if (chip->bbt) {
  467. res = nand_markbad_bbt(mtd, ofs);
  468. if (!ret)
  469. ret = res;
  470. }
  471. if (!ret)
  472. mtd->ecc_stats.badblocks++;
  473. return ret;
  474. }
  475. /**
  476. * nand_check_wp - [GENERIC] check if the chip is write protected
  477. * @mtd: MTD device structure
  478. *
  479. * Check, if the device is write protected. The function expects, that the
  480. * device is already selected.
  481. */
  482. static int nand_check_wp(struct mtd_info *mtd)
  483. {
  484. struct nand_chip *chip = mtd_to_nand(mtd);
  485. u8 status;
  486. int ret;
  487. /* Broken xD cards report WP despite being writable */
  488. if (chip->options & NAND_BROKEN_XD)
  489. return 0;
  490. /* Check the WP bit */
  491. ret = nand_status_op(chip, &status);
  492. if (ret)
  493. return ret;
  494. return status & NAND_STATUS_WP ? 0 : 1;
  495. }
  496. /**
  497. * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
  498. * @mtd: MTD device structure
  499. * @ofs: offset from device start
  500. *
  501. * Check if the block is marked as reserved.
  502. */
  503. static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
  504. {
  505. struct nand_chip *chip = mtd_to_nand(mtd);
  506. if (!chip->bbt)
  507. return 0;
  508. /* Return info from the table */
  509. return nand_isreserved_bbt(mtd, ofs);
  510. }
  511. /**
  512. * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  513. * @mtd: MTD device structure
  514. * @ofs: offset from device start
  515. * @allowbbt: 1, if its allowed to access the bbt area
  516. *
  517. * Check, if the block is bad. Either by reading the bad block table or
  518. * calling of the scan function.
  519. */
  520. static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
  521. {
  522. struct nand_chip *chip = mtd_to_nand(mtd);
  523. if (!chip->bbt)
  524. return chip->block_bad(mtd, ofs);
  525. /* Return info from the table */
  526. return nand_isbad_bbt(mtd, ofs, allowbbt);
  527. }
  528. /**
  529. * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
  530. * @mtd: MTD device structure
  531. * @timeo: Timeout
  532. *
  533. * Helper function for nand_wait_ready used when needing to wait in interrupt
  534. * context.
  535. */
  536. static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
  537. {
  538. struct nand_chip *chip = mtd_to_nand(mtd);
  539. int i;
  540. /* Wait for the device to get ready */
  541. for (i = 0; i < timeo; i++) {
  542. if (chip->dev_ready(mtd))
  543. break;
  544. touch_softlockup_watchdog();
  545. mdelay(1);
  546. }
  547. }
  548. /**
  549. * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
  550. * @mtd: MTD device structure
  551. *
  552. * Wait for the ready pin after a command, and warn if a timeout occurs.
  553. */
  554. void nand_wait_ready(struct mtd_info *mtd)
  555. {
  556. struct nand_chip *chip = mtd_to_nand(mtd);
  557. unsigned long timeo = 400;
  558. if (in_interrupt() || oops_in_progress)
  559. return panic_nand_wait_ready(mtd, timeo);
  560. /* Wait until command is processed or timeout occurs */
  561. timeo = jiffies + msecs_to_jiffies(timeo);
  562. do {
  563. if (chip->dev_ready(mtd))
  564. return;
  565. cond_resched();
  566. } while (time_before(jiffies, timeo));
  567. if (!chip->dev_ready(mtd))
  568. pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
  569. }
  570. EXPORT_SYMBOL_GPL(nand_wait_ready);
  571. /**
  572. * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
  573. * @mtd: MTD device structure
  574. * @timeo: Timeout in ms
  575. *
  576. * Wait for status ready (i.e. command done) or timeout.
  577. */
  578. static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
  579. {
  580. register struct nand_chip *chip = mtd_to_nand(mtd);
  581. int ret;
  582. timeo = jiffies + msecs_to_jiffies(timeo);
  583. do {
  584. u8 status;
  585. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  586. if (ret)
  587. return;
  588. if (status & NAND_STATUS_READY)
  589. break;
  590. touch_softlockup_watchdog();
  591. } while (time_before(jiffies, timeo));
  592. };
  593. /**
  594. * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
  595. * @chip: NAND chip structure
  596. * @timeout_ms: Timeout in ms
  597. *
  598. * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
  599. * If that does not happen whitin the specified timeout, -ETIMEDOUT is
  600. * returned.
  601. *
  602. * This helper is intended to be used when the controller does not have access
  603. * to the NAND R/B pin.
  604. *
  605. * Be aware that calling this helper from an ->exec_op() implementation means
  606. * ->exec_op() must be re-entrant.
  607. *
  608. * Return 0 if the NAND chip is ready, a negative error otherwise.
  609. */
  610. int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
  611. {
  612. u8 status = 0;
  613. int ret;
  614. if (!chip->exec_op)
  615. return -ENOTSUPP;
  616. ret = nand_status_op(chip, NULL);
  617. if (ret)
  618. return ret;
  619. timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
  620. do {
  621. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  622. if (ret)
  623. break;
  624. if (status & NAND_STATUS_READY)
  625. break;
  626. /*
  627. * Typical lowest execution time for a tR on most NANDs is 10us,
  628. * use this as polling delay before doing something smarter (ie.
  629. * deriving a delay from the timeout value, timeout_ms/ratio).
  630. */
  631. udelay(10);
  632. } while (time_before(jiffies, timeout_ms));
  633. /*
  634. * We have to exit READ_STATUS mode in order to read real data on the
  635. * bus in case the WAITRDY instruction is preceding a DATA_IN
  636. * instruction.
  637. */
  638. nand_exit_status_op(chip);
  639. if (ret)
  640. return ret;
  641. return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
  642. };
  643. EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
  644. /**
  645. * nand_command - [DEFAULT] Send command to NAND device
  646. * @mtd: MTD device structure
  647. * @command: the command to be sent
  648. * @column: the column address for this command, -1 if none
  649. * @page_addr: the page address for this command, -1 if none
  650. *
  651. * Send command to NAND device. This function is used for small page devices
  652. * (512 Bytes per page).
  653. */
  654. static void nand_command(struct mtd_info *mtd, unsigned int command,
  655. int column, int page_addr)
  656. {
  657. register struct nand_chip *chip = mtd_to_nand(mtd);
  658. int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
  659. /* Write out the command to the device */
  660. if (command == NAND_CMD_SEQIN) {
  661. int readcmd;
  662. if (column >= mtd->writesize) {
  663. /* OOB area */
  664. column -= mtd->writesize;
  665. readcmd = NAND_CMD_READOOB;
  666. } else if (column < 256) {
  667. /* First 256 bytes --> READ0 */
  668. readcmd = NAND_CMD_READ0;
  669. } else {
  670. column -= 256;
  671. readcmd = NAND_CMD_READ1;
  672. }
  673. chip->cmd_ctrl(mtd, readcmd, ctrl);
  674. ctrl &= ~NAND_CTRL_CHANGE;
  675. }
  676. if (command != NAND_CMD_NONE)
  677. chip->cmd_ctrl(mtd, command, ctrl);
  678. /* Address cycle, when necessary */
  679. ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
  680. /* Serially input address */
  681. if (column != -1) {
  682. /* Adjust columns for 16 bit buswidth */
  683. if (chip->options & NAND_BUSWIDTH_16 &&
  684. !nand_opcode_8bits(command))
  685. column >>= 1;
  686. chip->cmd_ctrl(mtd, column, ctrl);
  687. ctrl &= ~NAND_CTRL_CHANGE;
  688. }
  689. if (page_addr != -1) {
  690. chip->cmd_ctrl(mtd, page_addr, ctrl);
  691. ctrl &= ~NAND_CTRL_CHANGE;
  692. chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
  693. if (chip->options & NAND_ROW_ADDR_3)
  694. chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
  695. }
  696. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  697. /*
  698. * Program and erase have their own busy handlers status and sequential
  699. * in needs no delay
  700. */
  701. switch (command) {
  702. case NAND_CMD_NONE:
  703. case NAND_CMD_PAGEPROG:
  704. case NAND_CMD_ERASE1:
  705. case NAND_CMD_ERASE2:
  706. case NAND_CMD_SEQIN:
  707. case NAND_CMD_STATUS:
  708. case NAND_CMD_READID:
  709. case NAND_CMD_SET_FEATURES:
  710. return;
  711. case NAND_CMD_RESET:
  712. if (chip->dev_ready)
  713. break;
  714. udelay(chip->chip_delay);
  715. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  716. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  717. chip->cmd_ctrl(mtd,
  718. NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  719. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  720. nand_wait_status_ready(mtd, 250);
  721. return;
  722. /* This applies to read commands */
  723. case NAND_CMD_READ0:
  724. /*
  725. * READ0 is sometimes used to exit GET STATUS mode. When this
  726. * is the case no address cycles are requested, and we can use
  727. * this information to detect that we should not wait for the
  728. * device to be ready.
  729. */
  730. if (column == -1 && page_addr == -1)
  731. return;
  732. default:
  733. /*
  734. * If we don't have access to the busy pin, we apply the given
  735. * command delay
  736. */
  737. if (!chip->dev_ready) {
  738. udelay(chip->chip_delay);
  739. return;
  740. }
  741. }
  742. /*
  743. * Apply this short delay always to ensure that we do wait tWB in
  744. * any case on any machine.
  745. */
  746. ndelay(100);
  747. nand_wait_ready(mtd);
  748. }
  749. static void nand_ccs_delay(struct nand_chip *chip)
  750. {
  751. /*
  752. * The controller already takes care of waiting for tCCS when the RNDIN
  753. * or RNDOUT command is sent, return directly.
  754. */
  755. if (!(chip->options & NAND_WAIT_TCCS))
  756. return;
  757. /*
  758. * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
  759. * (which should be safe for all NANDs).
  760. */
  761. if (chip->setup_data_interface)
  762. ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
  763. else
  764. ndelay(500);
  765. }
  766. /**
  767. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  768. * @mtd: MTD device structure
  769. * @command: the command to be sent
  770. * @column: the column address for this command, -1 if none
  771. * @page_addr: the page address for this command, -1 if none
  772. *
  773. * Send command to NAND device. This is the version for the new large page
  774. * devices. We don't have the separate regions as we have in the small page
  775. * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  776. */
  777. static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
  778. int column, int page_addr)
  779. {
  780. register struct nand_chip *chip = mtd_to_nand(mtd);
  781. /* Emulate NAND_CMD_READOOB */
  782. if (command == NAND_CMD_READOOB) {
  783. column += mtd->writesize;
  784. command = NAND_CMD_READ0;
  785. }
  786. /* Command latch cycle */
  787. if (command != NAND_CMD_NONE)
  788. chip->cmd_ctrl(mtd, command,
  789. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  790. if (column != -1 || page_addr != -1) {
  791. int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
  792. /* Serially input address */
  793. if (column != -1) {
  794. /* Adjust columns for 16 bit buswidth */
  795. if (chip->options & NAND_BUSWIDTH_16 &&
  796. !nand_opcode_8bits(command))
  797. column >>= 1;
  798. chip->cmd_ctrl(mtd, column, ctrl);
  799. ctrl &= ~NAND_CTRL_CHANGE;
  800. /* Only output a single addr cycle for 8bits opcodes. */
  801. if (!nand_opcode_8bits(command))
  802. chip->cmd_ctrl(mtd, column >> 8, ctrl);
  803. }
  804. if (page_addr != -1) {
  805. chip->cmd_ctrl(mtd, page_addr, ctrl);
  806. chip->cmd_ctrl(mtd, page_addr >> 8,
  807. NAND_NCE | NAND_ALE);
  808. if (chip->options & NAND_ROW_ADDR_3)
  809. chip->cmd_ctrl(mtd, page_addr >> 16,
  810. NAND_NCE | NAND_ALE);
  811. }
  812. }
  813. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  814. /*
  815. * Program and erase have their own busy handlers status, sequential
  816. * in and status need no delay.
  817. */
  818. switch (command) {
  819. case NAND_CMD_NONE:
  820. case NAND_CMD_CACHEDPROG:
  821. case NAND_CMD_PAGEPROG:
  822. case NAND_CMD_ERASE1:
  823. case NAND_CMD_ERASE2:
  824. case NAND_CMD_SEQIN:
  825. case NAND_CMD_STATUS:
  826. case NAND_CMD_READID:
  827. case NAND_CMD_SET_FEATURES:
  828. return;
  829. case NAND_CMD_RNDIN:
  830. nand_ccs_delay(chip);
  831. return;
  832. case NAND_CMD_RESET:
  833. if (chip->dev_ready)
  834. break;
  835. udelay(chip->chip_delay);
  836. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  837. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  838. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  839. NAND_NCE | NAND_CTRL_CHANGE);
  840. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  841. nand_wait_status_ready(mtd, 250);
  842. return;
  843. case NAND_CMD_RNDOUT:
  844. /* No ready / busy check necessary */
  845. chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
  846. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  847. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  848. NAND_NCE | NAND_CTRL_CHANGE);
  849. nand_ccs_delay(chip);
  850. return;
  851. case NAND_CMD_READ0:
  852. /*
  853. * READ0 is sometimes used to exit GET STATUS mode. When this
  854. * is the case no address cycles are requested, and we can use
  855. * this information to detect that READSTART should not be
  856. * issued.
  857. */
  858. if (column == -1 && page_addr == -1)
  859. return;
  860. chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
  861. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  862. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  863. NAND_NCE | NAND_CTRL_CHANGE);
  864. /* This applies to read commands */
  865. default:
  866. /*
  867. * If we don't have access to the busy pin, we apply the given
  868. * command delay.
  869. */
  870. if (!chip->dev_ready) {
  871. udelay(chip->chip_delay);
  872. return;
  873. }
  874. }
  875. /*
  876. * Apply this short delay always to ensure that we do wait tWB in
  877. * any case on any machine.
  878. */
  879. ndelay(100);
  880. nand_wait_ready(mtd);
  881. }
  882. /**
  883. * panic_nand_get_device - [GENERIC] Get chip for selected access
  884. * @chip: the nand chip descriptor
  885. * @mtd: MTD device structure
  886. * @new_state: the state which is requested
  887. *
  888. * Used when in panic, no locks are taken.
  889. */
  890. static void panic_nand_get_device(struct nand_chip *chip,
  891. struct mtd_info *mtd, int new_state)
  892. {
  893. /* Hardware controller shared among independent devices */
  894. chip->controller->active = chip;
  895. chip->state = new_state;
  896. }
  897. /**
  898. * nand_get_device - [GENERIC] Get chip for selected access
  899. * @mtd: MTD device structure
  900. * @new_state: the state which is requested
  901. *
  902. * Get the device and lock it for exclusive access
  903. */
  904. static int
  905. nand_get_device(struct mtd_info *mtd, int new_state)
  906. {
  907. struct nand_chip *chip = mtd_to_nand(mtd);
  908. spinlock_t *lock = &chip->controller->lock;
  909. wait_queue_head_t *wq = &chip->controller->wq;
  910. DECLARE_WAITQUEUE(wait, current);
  911. retry:
  912. spin_lock(lock);
  913. /* Hardware controller shared among independent devices */
  914. if (!chip->controller->active)
  915. chip->controller->active = chip;
  916. if (chip->controller->active == chip && chip->state == FL_READY) {
  917. chip->state = new_state;
  918. spin_unlock(lock);
  919. return 0;
  920. }
  921. if (new_state == FL_PM_SUSPENDED) {
  922. if (chip->controller->active->state == FL_PM_SUSPENDED) {
  923. chip->state = FL_PM_SUSPENDED;
  924. spin_unlock(lock);
  925. return 0;
  926. }
  927. }
  928. set_current_state(TASK_UNINTERRUPTIBLE);
  929. add_wait_queue(wq, &wait);
  930. spin_unlock(lock);
  931. schedule();
  932. remove_wait_queue(wq, &wait);
  933. goto retry;
  934. }
  935. /**
  936. * panic_nand_wait - [GENERIC] wait until the command is done
  937. * @mtd: MTD device structure
  938. * @chip: NAND chip structure
  939. * @timeo: timeout
  940. *
  941. * Wait for command done. This is a helper function for nand_wait used when
  942. * we are in interrupt context. May happen when in panic and trying to write
  943. * an oops through mtdoops.
  944. */
  945. static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  946. unsigned long timeo)
  947. {
  948. int i;
  949. for (i = 0; i < timeo; i++) {
  950. if (chip->dev_ready) {
  951. if (chip->dev_ready(mtd))
  952. break;
  953. } else {
  954. int ret;
  955. u8 status;
  956. ret = nand_read_data_op(chip, &status, sizeof(status),
  957. true);
  958. if (ret)
  959. return;
  960. if (status & NAND_STATUS_READY)
  961. break;
  962. }
  963. mdelay(1);
  964. }
  965. }
  966. /**
  967. * nand_wait - [DEFAULT] wait until the command is done
  968. * @mtd: MTD device structure
  969. * @chip: NAND chip structure
  970. *
  971. * Wait for command done. This applies to erase and program only.
  972. */
  973. static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
  974. {
  975. unsigned long timeo = 400;
  976. u8 status;
  977. int ret;
  978. /*
  979. * Apply this short delay always to ensure that we do wait tWB in any
  980. * case on any machine.
  981. */
  982. ndelay(100);
  983. ret = nand_status_op(chip, NULL);
  984. if (ret)
  985. return ret;
  986. if (in_interrupt() || oops_in_progress)
  987. panic_nand_wait(mtd, chip, timeo);
  988. else {
  989. timeo = jiffies + msecs_to_jiffies(timeo);
  990. do {
  991. if (chip->dev_ready) {
  992. if (chip->dev_ready(mtd))
  993. break;
  994. } else {
  995. ret = nand_read_data_op(chip, &status,
  996. sizeof(status), true);
  997. if (ret)
  998. return ret;
  999. if (status & NAND_STATUS_READY)
  1000. break;
  1001. }
  1002. cond_resched();
  1003. } while (time_before(jiffies, timeo));
  1004. }
  1005. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  1006. if (ret)
  1007. return ret;
  1008. /* This can happen if in case of timeout or buggy dev_ready */
  1009. WARN_ON(!(status & NAND_STATUS_READY));
  1010. return status;
  1011. }
  1012. static bool nand_supports_get_features(struct nand_chip *chip, int addr)
  1013. {
  1014. return (chip->parameters.supports_set_get_features &&
  1015. test_bit(addr, chip->parameters.get_feature_list));
  1016. }
  1017. static bool nand_supports_set_features(struct nand_chip *chip, int addr)
  1018. {
  1019. return (chip->parameters.supports_set_get_features &&
  1020. test_bit(addr, chip->parameters.set_feature_list));
  1021. }
  1022. /**
  1023. * nand_get_features - wrapper to perform a GET_FEATURE
  1024. * @chip: NAND chip info structure
  1025. * @addr: feature address
  1026. * @subfeature_param: the subfeature parameters, a four bytes array
  1027. *
  1028. * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
  1029. * operation cannot be handled.
  1030. */
  1031. int nand_get_features(struct nand_chip *chip, int addr,
  1032. u8 *subfeature_param)
  1033. {
  1034. struct mtd_info *mtd = nand_to_mtd(chip);
  1035. if (!nand_supports_get_features(chip, addr))
  1036. return -ENOTSUPP;
  1037. return chip->get_features(mtd, chip, addr, subfeature_param);
  1038. }
  1039. EXPORT_SYMBOL_GPL(nand_get_features);
  1040. /**
  1041. * nand_set_features - wrapper to perform a SET_FEATURE
  1042. * @chip: NAND chip info structure
  1043. * @addr: feature address
  1044. * @subfeature_param: the subfeature parameters, a four bytes array
  1045. *
  1046. * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
  1047. * operation cannot be handled.
  1048. */
  1049. int nand_set_features(struct nand_chip *chip, int addr,
  1050. u8 *subfeature_param)
  1051. {
  1052. struct mtd_info *mtd = nand_to_mtd(chip);
  1053. if (!nand_supports_set_features(chip, addr))
  1054. return -ENOTSUPP;
  1055. return chip->set_features(mtd, chip, addr, subfeature_param);
  1056. }
  1057. EXPORT_SYMBOL_GPL(nand_set_features);
  1058. /**
  1059. * nand_reset_data_interface - Reset data interface and timings
  1060. * @chip: The NAND chip
  1061. * @chipnr: Internal die id
  1062. *
  1063. * Reset the Data interface and timings to ONFI mode 0.
  1064. *
  1065. * Returns 0 for success or negative error code otherwise.
  1066. */
  1067. static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
  1068. {
  1069. struct mtd_info *mtd = nand_to_mtd(chip);
  1070. int ret;
  1071. if (!chip->setup_data_interface)
  1072. return 0;
  1073. /*
  1074. * The ONFI specification says:
  1075. * "
  1076. * To transition from NV-DDR or NV-DDR2 to the SDR data
  1077. * interface, the host shall use the Reset (FFh) command
  1078. * using SDR timing mode 0. A device in any timing mode is
  1079. * required to recognize Reset (FFh) command issued in SDR
  1080. * timing mode 0.
  1081. * "
  1082. *
  1083. * Configure the data interface in SDR mode and set the
  1084. * timings to timing mode 0.
  1085. */
  1086. onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
  1087. ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface);
  1088. if (ret)
  1089. pr_err("Failed to configure data interface to SDR timing mode 0\n");
  1090. return ret;
  1091. }
  1092. /**
  1093. * nand_setup_data_interface - Setup the best data interface and timings
  1094. * @chip: The NAND chip
  1095. * @chipnr: Internal die id
  1096. *
  1097. * Find and configure the best data interface and NAND timings supported by
  1098. * the chip and the driver.
  1099. * First tries to retrieve supported timing modes from ONFI information,
  1100. * and if the NAND chip does not support ONFI, relies on the
  1101. * ->onfi_timing_mode_default specified in the nand_ids table.
  1102. *
  1103. * Returns 0 for success or negative error code otherwise.
  1104. */
  1105. static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
  1106. {
  1107. struct mtd_info *mtd = nand_to_mtd(chip);
  1108. u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
  1109. chip->onfi_timing_mode_default,
  1110. };
  1111. int ret;
  1112. if (!chip->setup_data_interface)
  1113. return 0;
  1114. /* Change the mode on the chip side (if supported by the NAND chip) */
  1115. if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
  1116. chip->select_chip(mtd, chipnr);
  1117. ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
  1118. tmode_param);
  1119. chip->select_chip(mtd, -1);
  1120. if (ret)
  1121. return ret;
  1122. }
  1123. /* Change the mode on the controller side */
  1124. ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface);
  1125. if (ret)
  1126. return ret;
  1127. /* Check the mode has been accepted by the chip, if supported */
  1128. if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
  1129. return 0;
  1130. memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
  1131. chip->select_chip(mtd, chipnr);
  1132. ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
  1133. tmode_param);
  1134. chip->select_chip(mtd, -1);
  1135. if (ret)
  1136. goto err_reset_chip;
  1137. if (tmode_param[0] != chip->onfi_timing_mode_default) {
  1138. pr_warn("timing mode %d not acknowledged by the NAND chip\n",
  1139. chip->onfi_timing_mode_default);
  1140. goto err_reset_chip;
  1141. }
  1142. return 0;
  1143. err_reset_chip:
  1144. /*
  1145. * Fallback to mode 0 if the chip explicitly did not ack the chosen
  1146. * timing mode.
  1147. */
  1148. nand_reset_data_interface(chip, chipnr);
  1149. chip->select_chip(mtd, chipnr);
  1150. nand_reset_op(chip);
  1151. chip->select_chip(mtd, -1);
  1152. return ret;
  1153. }
  1154. /**
  1155. * nand_init_data_interface - find the best data interface and timings
  1156. * @chip: The NAND chip
  1157. *
  1158. * Find the best data interface and NAND timings supported by the chip
  1159. * and the driver.
  1160. * First tries to retrieve supported timing modes from ONFI information,
  1161. * and if the NAND chip does not support ONFI, relies on the
  1162. * ->onfi_timing_mode_default specified in the nand_ids table. After this
  1163. * function nand_chip->data_interface is initialized with the best timing mode
  1164. * available.
  1165. *
  1166. * Returns 0 for success or negative error code otherwise.
  1167. */
  1168. static int nand_init_data_interface(struct nand_chip *chip)
  1169. {
  1170. struct mtd_info *mtd = nand_to_mtd(chip);
  1171. int modes, mode, ret;
  1172. if (!chip->setup_data_interface)
  1173. return 0;
  1174. /*
  1175. * First try to identify the best timings from ONFI parameters and
  1176. * if the NAND does not support ONFI, fallback to the default ONFI
  1177. * timing mode.
  1178. */
  1179. modes = onfi_get_async_timing_mode(chip);
  1180. if (modes == ONFI_TIMING_MODE_UNKNOWN) {
  1181. if (!chip->onfi_timing_mode_default)
  1182. return 0;
  1183. modes = GENMASK(chip->onfi_timing_mode_default, 0);
  1184. }
  1185. for (mode = fls(modes) - 1; mode >= 0; mode--) {
  1186. ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode);
  1187. if (ret)
  1188. continue;
  1189. /*
  1190. * Pass NAND_DATA_IFACE_CHECK_ONLY to only check if the
  1191. * controller supports the requested timings.
  1192. */
  1193. ret = chip->setup_data_interface(mtd,
  1194. NAND_DATA_IFACE_CHECK_ONLY,
  1195. &chip->data_interface);
  1196. if (!ret) {
  1197. chip->onfi_timing_mode_default = mode;
  1198. break;
  1199. }
  1200. }
  1201. return 0;
  1202. }
  1203. /**
  1204. * nand_fill_column_cycles - fill the column cycles of an address
  1205. * @chip: The NAND chip
  1206. * @addrs: Array of address cycles to fill
  1207. * @offset_in_page: The offset in the page
  1208. *
  1209. * Fills the first or the first two bytes of the @addrs field depending
  1210. * on the NAND bus width and the page size.
  1211. *
  1212. * Returns the number of cycles needed to encode the column, or a negative
  1213. * error code in case one of the arguments is invalid.
  1214. */
  1215. static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
  1216. unsigned int offset_in_page)
  1217. {
  1218. struct mtd_info *mtd = nand_to_mtd(chip);
  1219. /* Make sure the offset is less than the actual page size. */
  1220. if (offset_in_page > mtd->writesize + mtd->oobsize)
  1221. return -EINVAL;
  1222. /*
  1223. * On small page NANDs, there's a dedicated command to access the OOB
  1224. * area, and the column address is relative to the start of the OOB
  1225. * area, not the start of the page. Asjust the address accordingly.
  1226. */
  1227. if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize)
  1228. offset_in_page -= mtd->writesize;
  1229. /*
  1230. * The offset in page is expressed in bytes, if the NAND bus is 16-bit
  1231. * wide, then it must be divided by 2.
  1232. */
  1233. if (chip->options & NAND_BUSWIDTH_16) {
  1234. if (WARN_ON(offset_in_page % 2))
  1235. return -EINVAL;
  1236. offset_in_page /= 2;
  1237. }
  1238. addrs[0] = offset_in_page;
  1239. /*
  1240. * Small page NANDs use 1 cycle for the columns, while large page NANDs
  1241. * need 2
  1242. */
  1243. if (mtd->writesize <= 512)
  1244. return 1;
  1245. addrs[1] = offset_in_page >> 8;
  1246. return 2;
  1247. }
  1248. static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
  1249. unsigned int offset_in_page, void *buf,
  1250. unsigned int len)
  1251. {
  1252. struct mtd_info *mtd = nand_to_mtd(chip);
  1253. const struct nand_sdr_timings *sdr =
  1254. nand_get_sdr_timings(&chip->data_interface);
  1255. u8 addrs[4];
  1256. struct nand_op_instr instrs[] = {
  1257. NAND_OP_CMD(NAND_CMD_READ0, 0),
  1258. NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)),
  1259. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
  1260. PSEC_TO_NSEC(sdr->tRR_min)),
  1261. NAND_OP_DATA_IN(len, buf, 0),
  1262. };
  1263. struct nand_operation op = NAND_OPERATION(instrs);
  1264. int ret;
  1265. /* Drop the DATA_IN instruction if len is set to 0. */
  1266. if (!len)
  1267. op.ninstrs--;
  1268. if (offset_in_page >= mtd->writesize)
  1269. instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
  1270. else if (offset_in_page >= 256 &&
  1271. !(chip->options & NAND_BUSWIDTH_16))
  1272. instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
  1273. ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
  1274. if (ret < 0)
  1275. return ret;
  1276. addrs[1] = page;
  1277. addrs[2] = page >> 8;
  1278. if (chip->options & NAND_ROW_ADDR_3) {
  1279. addrs[3] = page >> 16;
  1280. instrs[1].ctx.addr.naddrs++;
  1281. }
  1282. return nand_exec_op(chip, &op);
  1283. }
  1284. static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
  1285. unsigned int offset_in_page, void *buf,
  1286. unsigned int len)
  1287. {
  1288. const struct nand_sdr_timings *sdr =
  1289. nand_get_sdr_timings(&chip->data_interface);
  1290. u8 addrs[5];
  1291. struct nand_op_instr instrs[] = {
  1292. NAND_OP_CMD(NAND_CMD_READ0, 0),
  1293. NAND_OP_ADDR(4, addrs, 0),
  1294. NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)),
  1295. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
  1296. PSEC_TO_NSEC(sdr->tRR_min)),
  1297. NAND_OP_DATA_IN(len, buf, 0),
  1298. };
  1299. struct nand_operation op = NAND_OPERATION(instrs);
  1300. int ret;
  1301. /* Drop the DATA_IN instruction if len is set to 0. */
  1302. if (!len)
  1303. op.ninstrs--;
  1304. ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
  1305. if (ret < 0)
  1306. return ret;
  1307. addrs[2] = page;
  1308. addrs[3] = page >> 8;
  1309. if (chip->options & NAND_ROW_ADDR_3) {
  1310. addrs[4] = page >> 16;
  1311. instrs[1].ctx.addr.naddrs++;
  1312. }
  1313. return nand_exec_op(chip, &op);
  1314. }
  1315. /**
  1316. * nand_read_page_op - Do a READ PAGE operation
  1317. * @chip: The NAND chip
  1318. * @page: page to read
  1319. * @offset_in_page: offset within the page
  1320. * @buf: buffer used to store the data
  1321. * @len: length of the buffer
  1322. *
  1323. * This function issues a READ PAGE operation.
  1324. * This function does not select/unselect the CS line.
  1325. *
  1326. * Returns 0 on success, a negative error code otherwise.
  1327. */
  1328. int nand_read_page_op(struct nand_chip *chip, unsigned int page,
  1329. unsigned int offset_in_page, void *buf, unsigned int len)
  1330. {
  1331. struct mtd_info *mtd = nand_to_mtd(chip);
  1332. if (len && !buf)
  1333. return -EINVAL;
  1334. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1335. return -EINVAL;
  1336. if (chip->exec_op) {
  1337. if (mtd->writesize > 512)
  1338. return nand_lp_exec_read_page_op(chip, page,
  1339. offset_in_page, buf,
  1340. len);
  1341. return nand_sp_exec_read_page_op(chip, page, offset_in_page,
  1342. buf, len);
  1343. }
  1344. chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
  1345. if (len)
  1346. chip->read_buf(mtd, buf, len);
  1347. return 0;
  1348. }
  1349. EXPORT_SYMBOL_GPL(nand_read_page_op);
  1350. /**
  1351. * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
  1352. * @chip: The NAND chip
  1353. * @page: parameter page to read
  1354. * @buf: buffer used to store the data
  1355. * @len: length of the buffer
  1356. *
  1357. * This function issues a READ PARAMETER PAGE operation.
  1358. * This function does not select/unselect the CS line.
  1359. *
  1360. * Returns 0 on success, a negative error code otherwise.
  1361. */
  1362. static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
  1363. unsigned int len)
  1364. {
  1365. struct mtd_info *mtd = nand_to_mtd(chip);
  1366. unsigned int i;
  1367. u8 *p = buf;
  1368. if (len && !buf)
  1369. return -EINVAL;
  1370. if (chip->exec_op) {
  1371. const struct nand_sdr_timings *sdr =
  1372. nand_get_sdr_timings(&chip->data_interface);
  1373. struct nand_op_instr instrs[] = {
  1374. NAND_OP_CMD(NAND_CMD_PARAM, 0),
  1375. NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)),
  1376. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
  1377. PSEC_TO_NSEC(sdr->tRR_min)),
  1378. NAND_OP_8BIT_DATA_IN(len, buf, 0),
  1379. };
  1380. struct nand_operation op = NAND_OPERATION(instrs);
  1381. /* Drop the DATA_IN instruction if len is set to 0. */
  1382. if (!len)
  1383. op.ninstrs--;
  1384. return nand_exec_op(chip, &op);
  1385. }
  1386. chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
  1387. for (i = 0; i < len; i++)
  1388. p[i] = chip->read_byte(mtd);
  1389. return 0;
  1390. }
  1391. /**
  1392. * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
  1393. * @chip: The NAND chip
  1394. * @offset_in_page: offset within the page
  1395. * @buf: buffer used to store the data
  1396. * @len: length of the buffer
  1397. * @force_8bit: force 8-bit bus access
  1398. *
  1399. * This function issues a CHANGE READ COLUMN operation.
  1400. * This function does not select/unselect the CS line.
  1401. *
  1402. * Returns 0 on success, a negative error code otherwise.
  1403. */
  1404. int nand_change_read_column_op(struct nand_chip *chip,
  1405. unsigned int offset_in_page, void *buf,
  1406. unsigned int len, bool force_8bit)
  1407. {
  1408. struct mtd_info *mtd = nand_to_mtd(chip);
  1409. if (len && !buf)
  1410. return -EINVAL;
  1411. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1412. return -EINVAL;
  1413. /* Small page NANDs do not support column change. */
  1414. if (mtd->writesize <= 512)
  1415. return -ENOTSUPP;
  1416. if (chip->exec_op) {
  1417. const struct nand_sdr_timings *sdr =
  1418. nand_get_sdr_timings(&chip->data_interface);
  1419. u8 addrs[2] = {};
  1420. struct nand_op_instr instrs[] = {
  1421. NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
  1422. NAND_OP_ADDR(2, addrs, 0),
  1423. NAND_OP_CMD(NAND_CMD_RNDOUTSTART,
  1424. PSEC_TO_NSEC(sdr->tCCS_min)),
  1425. NAND_OP_DATA_IN(len, buf, 0),
  1426. };
  1427. struct nand_operation op = NAND_OPERATION(instrs);
  1428. int ret;
  1429. ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
  1430. if (ret < 0)
  1431. return ret;
  1432. /* Drop the DATA_IN instruction if len is set to 0. */
  1433. if (!len)
  1434. op.ninstrs--;
  1435. instrs[3].ctx.data.force_8bit = force_8bit;
  1436. return nand_exec_op(chip, &op);
  1437. }
  1438. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
  1439. if (len)
  1440. chip->read_buf(mtd, buf, len);
  1441. return 0;
  1442. }
  1443. EXPORT_SYMBOL_GPL(nand_change_read_column_op);
  1444. /**
  1445. * nand_read_oob_op - Do a READ OOB operation
  1446. * @chip: The NAND chip
  1447. * @page: page to read
  1448. * @offset_in_oob: offset within the OOB area
  1449. * @buf: buffer used to store the data
  1450. * @len: length of the buffer
  1451. *
  1452. * This function issues a READ OOB operation.
  1453. * This function does not select/unselect the CS line.
  1454. *
  1455. * Returns 0 on success, a negative error code otherwise.
  1456. */
  1457. int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
  1458. unsigned int offset_in_oob, void *buf, unsigned int len)
  1459. {
  1460. struct mtd_info *mtd = nand_to_mtd(chip);
  1461. if (len && !buf)
  1462. return -EINVAL;
  1463. if (offset_in_oob + len > mtd->oobsize)
  1464. return -EINVAL;
  1465. if (chip->exec_op)
  1466. return nand_read_page_op(chip, page,
  1467. mtd->writesize + offset_in_oob,
  1468. buf, len);
  1469. chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
  1470. if (len)
  1471. chip->read_buf(mtd, buf, len);
  1472. return 0;
  1473. }
  1474. EXPORT_SYMBOL_GPL(nand_read_oob_op);
  1475. static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
  1476. unsigned int offset_in_page, const void *buf,
  1477. unsigned int len, bool prog)
  1478. {
  1479. struct mtd_info *mtd = nand_to_mtd(chip);
  1480. const struct nand_sdr_timings *sdr =
  1481. nand_get_sdr_timings(&chip->data_interface);
  1482. u8 addrs[5] = {};
  1483. struct nand_op_instr instrs[] = {
  1484. /*
  1485. * The first instruction will be dropped if we're dealing
  1486. * with a large page NAND and adjusted if we're dealing
  1487. * with a small page NAND and the page offset is > 255.
  1488. */
  1489. NAND_OP_CMD(NAND_CMD_READ0, 0),
  1490. NAND_OP_CMD(NAND_CMD_SEQIN, 0),
  1491. NAND_OP_ADDR(0, addrs, PSEC_TO_NSEC(sdr->tADL_min)),
  1492. NAND_OP_DATA_OUT(len, buf, 0),
  1493. NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)),
  1494. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
  1495. };
  1496. struct nand_operation op = NAND_OPERATION(instrs);
  1497. int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
  1498. int ret;
  1499. u8 status;
  1500. if (naddrs < 0)
  1501. return naddrs;
  1502. addrs[naddrs++] = page;
  1503. addrs[naddrs++] = page >> 8;
  1504. if (chip->options & NAND_ROW_ADDR_3)
  1505. addrs[naddrs++] = page >> 16;
  1506. instrs[2].ctx.addr.naddrs = naddrs;
  1507. /* Drop the last two instructions if we're not programming the page. */
  1508. if (!prog) {
  1509. op.ninstrs -= 2;
  1510. /* Also drop the DATA_OUT instruction if empty. */
  1511. if (!len)
  1512. op.ninstrs--;
  1513. }
  1514. if (mtd->writesize <= 512) {
  1515. /*
  1516. * Small pages need some more tweaking: we have to adjust the
  1517. * first instruction depending on the page offset we're trying
  1518. * to access.
  1519. */
  1520. if (offset_in_page >= mtd->writesize)
  1521. instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
  1522. else if (offset_in_page >= 256 &&
  1523. !(chip->options & NAND_BUSWIDTH_16))
  1524. instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
  1525. } else {
  1526. /*
  1527. * Drop the first command if we're dealing with a large page
  1528. * NAND.
  1529. */
  1530. op.instrs++;
  1531. op.ninstrs--;
  1532. }
  1533. ret = nand_exec_op(chip, &op);
  1534. if (!prog || ret)
  1535. return ret;
  1536. ret = nand_status_op(chip, &status);
  1537. if (ret)
  1538. return ret;
  1539. return status;
  1540. }
  1541. /**
  1542. * nand_prog_page_begin_op - starts a PROG PAGE operation
  1543. * @chip: The NAND chip
  1544. * @page: page to write
  1545. * @offset_in_page: offset within the page
  1546. * @buf: buffer containing the data to write to the page
  1547. * @len: length of the buffer
  1548. *
  1549. * This function issues the first half of a PROG PAGE operation.
  1550. * This function does not select/unselect the CS line.
  1551. *
  1552. * Returns 0 on success, a negative error code otherwise.
  1553. */
  1554. int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
  1555. unsigned int offset_in_page, const void *buf,
  1556. unsigned int len)
  1557. {
  1558. struct mtd_info *mtd = nand_to_mtd(chip);
  1559. if (len && !buf)
  1560. return -EINVAL;
  1561. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1562. return -EINVAL;
  1563. if (chip->exec_op)
  1564. return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
  1565. len, false);
  1566. chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
  1567. if (buf)
  1568. chip->write_buf(mtd, buf, len);
  1569. return 0;
  1570. }
  1571. EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
  1572. /**
  1573. * nand_prog_page_end_op - ends a PROG PAGE operation
  1574. * @chip: The NAND chip
  1575. *
  1576. * This function issues the second half of a PROG PAGE operation.
  1577. * This function does not select/unselect the CS line.
  1578. *
  1579. * Returns 0 on success, a negative error code otherwise.
  1580. */
  1581. int nand_prog_page_end_op(struct nand_chip *chip)
  1582. {
  1583. struct mtd_info *mtd = nand_to_mtd(chip);
  1584. int ret;
  1585. u8 status;
  1586. if (chip->exec_op) {
  1587. const struct nand_sdr_timings *sdr =
  1588. nand_get_sdr_timings(&chip->data_interface);
  1589. struct nand_op_instr instrs[] = {
  1590. NAND_OP_CMD(NAND_CMD_PAGEPROG,
  1591. PSEC_TO_NSEC(sdr->tWB_max)),
  1592. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
  1593. };
  1594. struct nand_operation op = NAND_OPERATION(instrs);
  1595. ret = nand_exec_op(chip, &op);
  1596. if (ret)
  1597. return ret;
  1598. ret = nand_status_op(chip, &status);
  1599. if (ret)
  1600. return ret;
  1601. } else {
  1602. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1603. ret = chip->waitfunc(mtd, chip);
  1604. if (ret < 0)
  1605. return ret;
  1606. status = ret;
  1607. }
  1608. if (status & NAND_STATUS_FAIL)
  1609. return -EIO;
  1610. return 0;
  1611. }
  1612. EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
  1613. /**
  1614. * nand_prog_page_op - Do a full PROG PAGE operation
  1615. * @chip: The NAND chip
  1616. * @page: page to write
  1617. * @offset_in_page: offset within the page
  1618. * @buf: buffer containing the data to write to the page
  1619. * @len: length of the buffer
  1620. *
  1621. * This function issues a full PROG PAGE operation.
  1622. * This function does not select/unselect the CS line.
  1623. *
  1624. * Returns 0 on success, a negative error code otherwise.
  1625. */
  1626. int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
  1627. unsigned int offset_in_page, const void *buf,
  1628. unsigned int len)
  1629. {
  1630. struct mtd_info *mtd = nand_to_mtd(chip);
  1631. int status;
  1632. if (!len || !buf)
  1633. return -EINVAL;
  1634. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1635. return -EINVAL;
  1636. if (chip->exec_op) {
  1637. status = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
  1638. len, true);
  1639. } else {
  1640. chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
  1641. chip->write_buf(mtd, buf, len);
  1642. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1643. status = chip->waitfunc(mtd, chip);
  1644. }
  1645. if (status & NAND_STATUS_FAIL)
  1646. return -EIO;
  1647. return 0;
  1648. }
  1649. EXPORT_SYMBOL_GPL(nand_prog_page_op);
  1650. /**
  1651. * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
  1652. * @chip: The NAND chip
  1653. * @offset_in_page: offset within the page
  1654. * @buf: buffer containing the data to send to the NAND
  1655. * @len: length of the buffer
  1656. * @force_8bit: force 8-bit bus access
  1657. *
  1658. * This function issues a CHANGE WRITE COLUMN operation.
  1659. * This function does not select/unselect the CS line.
  1660. *
  1661. * Returns 0 on success, a negative error code otherwise.
  1662. */
  1663. int nand_change_write_column_op(struct nand_chip *chip,
  1664. unsigned int offset_in_page,
  1665. const void *buf, unsigned int len,
  1666. bool force_8bit)
  1667. {
  1668. struct mtd_info *mtd = nand_to_mtd(chip);
  1669. if (len && !buf)
  1670. return -EINVAL;
  1671. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1672. return -EINVAL;
  1673. /* Small page NANDs do not support column change. */
  1674. if (mtd->writesize <= 512)
  1675. return -ENOTSUPP;
  1676. if (chip->exec_op) {
  1677. const struct nand_sdr_timings *sdr =
  1678. nand_get_sdr_timings(&chip->data_interface);
  1679. u8 addrs[2];
  1680. struct nand_op_instr instrs[] = {
  1681. NAND_OP_CMD(NAND_CMD_RNDIN, 0),
  1682. NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)),
  1683. NAND_OP_DATA_OUT(len, buf, 0),
  1684. };
  1685. struct nand_operation op = NAND_OPERATION(instrs);
  1686. int ret;
  1687. ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
  1688. if (ret < 0)
  1689. return ret;
  1690. instrs[2].ctx.data.force_8bit = force_8bit;
  1691. /* Drop the DATA_OUT instruction if len is set to 0. */
  1692. if (!len)
  1693. op.ninstrs--;
  1694. return nand_exec_op(chip, &op);
  1695. }
  1696. chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
  1697. if (len)
  1698. chip->write_buf(mtd, buf, len);
  1699. return 0;
  1700. }
  1701. EXPORT_SYMBOL_GPL(nand_change_write_column_op);
  1702. /**
  1703. * nand_readid_op - Do a READID operation
  1704. * @chip: The NAND chip
  1705. * @addr: address cycle to pass after the READID command
  1706. * @buf: buffer used to store the ID
  1707. * @len: length of the buffer
  1708. *
  1709. * This function sends a READID command and reads back the ID returned by the
  1710. * NAND.
  1711. * This function does not select/unselect the CS line.
  1712. *
  1713. * Returns 0 on success, a negative error code otherwise.
  1714. */
  1715. int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
  1716. unsigned int len)
  1717. {
  1718. struct mtd_info *mtd = nand_to_mtd(chip);
  1719. unsigned int i;
  1720. u8 *id = buf;
  1721. if (len && !buf)
  1722. return -EINVAL;
  1723. if (chip->exec_op) {
  1724. const struct nand_sdr_timings *sdr =
  1725. nand_get_sdr_timings(&chip->data_interface);
  1726. struct nand_op_instr instrs[] = {
  1727. NAND_OP_CMD(NAND_CMD_READID, 0),
  1728. NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)),
  1729. NAND_OP_8BIT_DATA_IN(len, buf, 0),
  1730. };
  1731. struct nand_operation op = NAND_OPERATION(instrs);
  1732. /* Drop the DATA_IN instruction if len is set to 0. */
  1733. if (!len)
  1734. op.ninstrs--;
  1735. return nand_exec_op(chip, &op);
  1736. }
  1737. chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
  1738. for (i = 0; i < len; i++)
  1739. id[i] = chip->read_byte(mtd);
  1740. return 0;
  1741. }
  1742. EXPORT_SYMBOL_GPL(nand_readid_op);
  1743. /**
  1744. * nand_status_op - Do a STATUS operation
  1745. * @chip: The NAND chip
  1746. * @status: out variable to store the NAND status
  1747. *
  1748. * This function sends a STATUS command and reads back the status returned by
  1749. * the NAND.
  1750. * This function does not select/unselect the CS line.
  1751. *
  1752. * Returns 0 on success, a negative error code otherwise.
  1753. */
  1754. int nand_status_op(struct nand_chip *chip, u8 *status)
  1755. {
  1756. struct mtd_info *mtd = nand_to_mtd(chip);
  1757. if (chip->exec_op) {
  1758. const struct nand_sdr_timings *sdr =
  1759. nand_get_sdr_timings(&chip->data_interface);
  1760. struct nand_op_instr instrs[] = {
  1761. NAND_OP_CMD(NAND_CMD_STATUS,
  1762. PSEC_TO_NSEC(sdr->tADL_min)),
  1763. NAND_OP_8BIT_DATA_IN(1, status, 0),
  1764. };
  1765. struct nand_operation op = NAND_OPERATION(instrs);
  1766. if (!status)
  1767. op.ninstrs--;
  1768. return nand_exec_op(chip, &op);
  1769. }
  1770. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  1771. if (status)
  1772. *status = chip->read_byte(mtd);
  1773. return 0;
  1774. }
  1775. EXPORT_SYMBOL_GPL(nand_status_op);
  1776. /**
  1777. * nand_exit_status_op - Exit a STATUS operation
  1778. * @chip: The NAND chip
  1779. *
  1780. * This function sends a READ0 command to cancel the effect of the STATUS
  1781. * command to avoid reading only the status until a new read command is sent.
  1782. *
  1783. * This function does not select/unselect the CS line.
  1784. *
  1785. * Returns 0 on success, a negative error code otherwise.
  1786. */
  1787. int nand_exit_status_op(struct nand_chip *chip)
  1788. {
  1789. struct mtd_info *mtd = nand_to_mtd(chip);
  1790. if (chip->exec_op) {
  1791. struct nand_op_instr instrs[] = {
  1792. NAND_OP_CMD(NAND_CMD_READ0, 0),
  1793. };
  1794. struct nand_operation op = NAND_OPERATION(instrs);
  1795. return nand_exec_op(chip, &op);
  1796. }
  1797. chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
  1798. return 0;
  1799. }
  1800. EXPORT_SYMBOL_GPL(nand_exit_status_op);
  1801. /**
  1802. * nand_erase_op - Do an erase operation
  1803. * @chip: The NAND chip
  1804. * @eraseblock: block to erase
  1805. *
  1806. * This function sends an ERASE command and waits for the NAND to be ready
  1807. * before returning.
  1808. * This function does not select/unselect the CS line.
  1809. *
  1810. * Returns 0 on success, a negative error code otherwise.
  1811. */
  1812. int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
  1813. {
  1814. struct mtd_info *mtd = nand_to_mtd(chip);
  1815. unsigned int page = eraseblock <<
  1816. (chip->phys_erase_shift - chip->page_shift);
  1817. int ret;
  1818. u8 status;
  1819. if (chip->exec_op) {
  1820. const struct nand_sdr_timings *sdr =
  1821. nand_get_sdr_timings(&chip->data_interface);
  1822. u8 addrs[3] = { page, page >> 8, page >> 16 };
  1823. struct nand_op_instr instrs[] = {
  1824. NAND_OP_CMD(NAND_CMD_ERASE1, 0),
  1825. NAND_OP_ADDR(2, addrs, 0),
  1826. NAND_OP_CMD(NAND_CMD_ERASE2,
  1827. PSEC_TO_MSEC(sdr->tWB_max)),
  1828. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tBERS_max), 0),
  1829. };
  1830. struct nand_operation op = NAND_OPERATION(instrs);
  1831. if (chip->options & NAND_ROW_ADDR_3)
  1832. instrs[1].ctx.addr.naddrs++;
  1833. ret = nand_exec_op(chip, &op);
  1834. if (ret)
  1835. return ret;
  1836. ret = nand_status_op(chip, &status);
  1837. if (ret)
  1838. return ret;
  1839. } else {
  1840. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1841. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1842. ret = chip->waitfunc(mtd, chip);
  1843. if (ret < 0)
  1844. return ret;
  1845. status = ret;
  1846. }
  1847. if (status & NAND_STATUS_FAIL)
  1848. return -EIO;
  1849. return 0;
  1850. }
  1851. EXPORT_SYMBOL_GPL(nand_erase_op);
  1852. /**
  1853. * nand_set_features_op - Do a SET FEATURES operation
  1854. * @chip: The NAND chip
  1855. * @feature: feature id
  1856. * @data: 4 bytes of data
  1857. *
  1858. * This function sends a SET FEATURES command and waits for the NAND to be
  1859. * ready before returning.
  1860. * This function does not select/unselect the CS line.
  1861. *
  1862. * Returns 0 on success, a negative error code otherwise.
  1863. */
  1864. static int nand_set_features_op(struct nand_chip *chip, u8 feature,
  1865. const void *data)
  1866. {
  1867. struct mtd_info *mtd = nand_to_mtd(chip);
  1868. const u8 *params = data;
  1869. int i, ret;
  1870. u8 status;
  1871. if (chip->exec_op) {
  1872. const struct nand_sdr_timings *sdr =
  1873. nand_get_sdr_timings(&chip->data_interface);
  1874. struct nand_op_instr instrs[] = {
  1875. NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
  1876. NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)),
  1877. NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data,
  1878. PSEC_TO_NSEC(sdr->tWB_max)),
  1879. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 0),
  1880. };
  1881. struct nand_operation op = NAND_OPERATION(instrs);
  1882. ret = nand_exec_op(chip, &op);
  1883. if (ret)
  1884. return ret;
  1885. ret = nand_status_op(chip, &status);
  1886. if (ret)
  1887. return ret;
  1888. } else {
  1889. chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
  1890. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  1891. chip->write_byte(mtd, params[i]);
  1892. ret = chip->waitfunc(mtd, chip);
  1893. if (ret < 0)
  1894. return ret;
  1895. status = ret;
  1896. }
  1897. if (status & NAND_STATUS_FAIL)
  1898. return -EIO;
  1899. return 0;
  1900. }
  1901. /**
  1902. * nand_get_features_op - Do a GET FEATURES operation
  1903. * @chip: The NAND chip
  1904. * @feature: feature id
  1905. * @data: 4 bytes of data
  1906. *
  1907. * This function sends a GET FEATURES command and waits for the NAND to be
  1908. * ready before returning.
  1909. * This function does not select/unselect the CS line.
  1910. *
  1911. * Returns 0 on success, a negative error code otherwise.
  1912. */
  1913. static int nand_get_features_op(struct nand_chip *chip, u8 feature,
  1914. void *data)
  1915. {
  1916. struct mtd_info *mtd = nand_to_mtd(chip);
  1917. u8 *params = data;
  1918. int i;
  1919. if (chip->exec_op) {
  1920. const struct nand_sdr_timings *sdr =
  1921. nand_get_sdr_timings(&chip->data_interface);
  1922. struct nand_op_instr instrs[] = {
  1923. NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
  1924. NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)),
  1925. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max),
  1926. PSEC_TO_NSEC(sdr->tRR_min)),
  1927. NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,
  1928. data, 0),
  1929. };
  1930. struct nand_operation op = NAND_OPERATION(instrs);
  1931. return nand_exec_op(chip, &op);
  1932. }
  1933. chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
  1934. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  1935. params[i] = chip->read_byte(mtd);
  1936. return 0;
  1937. }
  1938. /**
  1939. * nand_reset_op - Do a reset operation
  1940. * @chip: The NAND chip
  1941. *
  1942. * This function sends a RESET command and waits for the NAND to be ready
  1943. * before returning.
  1944. * This function does not select/unselect the CS line.
  1945. *
  1946. * Returns 0 on success, a negative error code otherwise.
  1947. */
  1948. int nand_reset_op(struct nand_chip *chip)
  1949. {
  1950. struct mtd_info *mtd = nand_to_mtd(chip);
  1951. if (chip->exec_op) {
  1952. const struct nand_sdr_timings *sdr =
  1953. nand_get_sdr_timings(&chip->data_interface);
  1954. struct nand_op_instr instrs[] = {
  1955. NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)),
  1956. NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0),
  1957. };
  1958. struct nand_operation op = NAND_OPERATION(instrs);
  1959. return nand_exec_op(chip, &op);
  1960. }
  1961. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1962. return 0;
  1963. }
  1964. EXPORT_SYMBOL_GPL(nand_reset_op);
  1965. /**
  1966. * nand_read_data_op - Read data from the NAND
  1967. * @chip: The NAND chip
  1968. * @buf: buffer used to store the data
  1969. * @len: length of the buffer
  1970. * @force_8bit: force 8-bit bus access
  1971. *
  1972. * This function does a raw data read on the bus. Usually used after launching
  1973. * another NAND operation like nand_read_page_op().
  1974. * This function does not select/unselect the CS line.
  1975. *
  1976. * Returns 0 on success, a negative error code otherwise.
  1977. */
  1978. int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
  1979. bool force_8bit)
  1980. {
  1981. struct mtd_info *mtd = nand_to_mtd(chip);
  1982. if (!len || !buf)
  1983. return -EINVAL;
  1984. if (chip->exec_op) {
  1985. struct nand_op_instr instrs[] = {
  1986. NAND_OP_DATA_IN(len, buf, 0),
  1987. };
  1988. struct nand_operation op = NAND_OPERATION(instrs);
  1989. instrs[0].ctx.data.force_8bit = force_8bit;
  1990. return nand_exec_op(chip, &op);
  1991. }
  1992. if (force_8bit) {
  1993. u8 *p = buf;
  1994. unsigned int i;
  1995. for (i = 0; i < len; i++)
  1996. p[i] = chip->read_byte(mtd);
  1997. } else {
  1998. chip->read_buf(mtd, buf, len);
  1999. }
  2000. return 0;
  2001. }
  2002. EXPORT_SYMBOL_GPL(nand_read_data_op);
  2003. /**
  2004. * nand_write_data_op - Write data from the NAND
  2005. * @chip: The NAND chip
  2006. * @buf: buffer containing the data to send on the bus
  2007. * @len: length of the buffer
  2008. * @force_8bit: force 8-bit bus access
  2009. *
  2010. * This function does a raw data write on the bus. Usually used after launching
  2011. * another NAND operation like nand_write_page_begin_op().
  2012. * This function does not select/unselect the CS line.
  2013. *
  2014. * Returns 0 on success, a negative error code otherwise.
  2015. */
  2016. int nand_write_data_op(struct nand_chip *chip, const void *buf,
  2017. unsigned int len, bool force_8bit)
  2018. {
  2019. struct mtd_info *mtd = nand_to_mtd(chip);
  2020. if (!len || !buf)
  2021. return -EINVAL;
  2022. if (chip->exec_op) {
  2023. struct nand_op_instr instrs[] = {
  2024. NAND_OP_DATA_OUT(len, buf, 0),
  2025. };
  2026. struct nand_operation op = NAND_OPERATION(instrs);
  2027. instrs[0].ctx.data.force_8bit = force_8bit;
  2028. return nand_exec_op(chip, &op);
  2029. }
  2030. if (force_8bit) {
  2031. const u8 *p = buf;
  2032. unsigned int i;
  2033. for (i = 0; i < len; i++)
  2034. chip->write_byte(mtd, p[i]);
  2035. } else {
  2036. chip->write_buf(mtd, buf, len);
  2037. }
  2038. return 0;
  2039. }
  2040. EXPORT_SYMBOL_GPL(nand_write_data_op);
  2041. /**
  2042. * struct nand_op_parser_ctx - Context used by the parser
  2043. * @instrs: array of all the instructions that must be addressed
  2044. * @ninstrs: length of the @instrs array
  2045. * @subop: Sub-operation to be passed to the NAND controller
  2046. *
  2047. * This structure is used by the core to split NAND operations into
  2048. * sub-operations that can be handled by the NAND controller.
  2049. */
  2050. struct nand_op_parser_ctx {
  2051. const struct nand_op_instr *instrs;
  2052. unsigned int ninstrs;
  2053. struct nand_subop subop;
  2054. };
  2055. /**
  2056. * nand_op_parser_must_split_instr - Checks if an instruction must be split
  2057. * @pat: the parser pattern element that matches @instr
  2058. * @instr: pointer to the instruction to check
  2059. * @start_offset: this is an in/out parameter. If @instr has already been
  2060. * split, then @start_offset is the offset from which to start
  2061. * (either an address cycle or an offset in the data buffer).
  2062. * Conversely, if the function returns true (ie. instr must be
  2063. * split), this parameter is updated to point to the first
  2064. * data/address cycle that has not been taken care of.
  2065. *
  2066. * Some NAND controllers are limited and cannot send X address cycles with a
  2067. * unique operation, or cannot read/write more than Y bytes at the same time.
  2068. * In this case, split the instruction that does not fit in a single
  2069. * controller-operation into two or more chunks.
  2070. *
  2071. * Returns true if the instruction must be split, false otherwise.
  2072. * The @start_offset parameter is also updated to the offset at which the next
  2073. * bundle of instruction must start (if an address or a data instruction).
  2074. */
  2075. static bool
  2076. nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat,
  2077. const struct nand_op_instr *instr,
  2078. unsigned int *start_offset)
  2079. {
  2080. switch (pat->type) {
  2081. case NAND_OP_ADDR_INSTR:
  2082. if (!pat->ctx.addr.maxcycles)
  2083. break;
  2084. if (instr->ctx.addr.naddrs - *start_offset >
  2085. pat->ctx.addr.maxcycles) {
  2086. *start_offset += pat->ctx.addr.maxcycles;
  2087. return true;
  2088. }
  2089. break;
  2090. case NAND_OP_DATA_IN_INSTR:
  2091. case NAND_OP_DATA_OUT_INSTR:
  2092. if (!pat->ctx.data.maxlen)
  2093. break;
  2094. if (instr->ctx.data.len - *start_offset >
  2095. pat->ctx.data.maxlen) {
  2096. *start_offset += pat->ctx.data.maxlen;
  2097. return true;
  2098. }
  2099. break;
  2100. default:
  2101. break;
  2102. }
  2103. return false;
  2104. }
  2105. /**
  2106. * nand_op_parser_match_pat - Checks if a pattern matches the instructions
  2107. * remaining in the parser context
  2108. * @pat: the pattern to test
  2109. * @ctx: the parser context structure to match with the pattern @pat
  2110. *
  2111. * Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
  2112. * Returns true if this is the case, false ortherwise. When true is returned,
  2113. * @ctx->subop is updated with the set of instructions to be passed to the
  2114. * controller driver.
  2115. */
  2116. static bool
  2117. nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat,
  2118. struct nand_op_parser_ctx *ctx)
  2119. {
  2120. unsigned int instr_offset = ctx->subop.first_instr_start_off;
  2121. const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs;
  2122. const struct nand_op_instr *instr = ctx->subop.instrs;
  2123. unsigned int i, ninstrs;
  2124. for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) {
  2125. /*
  2126. * The pattern instruction does not match the operation
  2127. * instruction. If the instruction is marked optional in the
  2128. * pattern definition, we skip the pattern element and continue
  2129. * to the next one. If the element is mandatory, there's no
  2130. * match and we can return false directly.
  2131. */
  2132. if (instr->type != pat->elems[i].type) {
  2133. if (!pat->elems[i].optional)
  2134. return false;
  2135. continue;
  2136. }
  2137. /*
  2138. * Now check the pattern element constraints. If the pattern is
  2139. * not able to handle the whole instruction in a single step,
  2140. * we have to split it.
  2141. * The last_instr_end_off value comes back updated to point to
  2142. * the position where we have to split the instruction (the
  2143. * start of the next subop chunk).
  2144. */
  2145. if (nand_op_parser_must_split_instr(&pat->elems[i], instr,
  2146. &instr_offset)) {
  2147. ninstrs++;
  2148. i++;
  2149. break;
  2150. }
  2151. instr++;
  2152. ninstrs++;
  2153. instr_offset = 0;
  2154. }
  2155. /*
  2156. * This can happen if all instructions of a pattern are optional.
  2157. * Still, if there's not at least one instruction handled by this
  2158. * pattern, this is not a match, and we should try the next one (if
  2159. * any).
  2160. */
  2161. if (!ninstrs)
  2162. return false;
  2163. /*
  2164. * We had a match on the pattern head, but the pattern may be longer
  2165. * than the instructions we're asked to execute. We need to make sure
  2166. * there's no mandatory elements in the pattern tail.
  2167. */
  2168. for (; i < pat->nelems; i++) {
  2169. if (!pat->elems[i].optional)
  2170. return false;
  2171. }
  2172. /*
  2173. * We have a match: update the subop structure accordingly and return
  2174. * true.
  2175. */
  2176. ctx->subop.ninstrs = ninstrs;
  2177. ctx->subop.last_instr_end_off = instr_offset;
  2178. return true;
  2179. }
  2180. #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
  2181. static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
  2182. {
  2183. const struct nand_op_instr *instr;
  2184. char *prefix = " ";
  2185. unsigned int i;
  2186. pr_debug("executing subop:\n");
  2187. for (i = 0; i < ctx->ninstrs; i++) {
  2188. instr = &ctx->instrs[i];
  2189. if (instr == &ctx->subop.instrs[0])
  2190. prefix = " ->";
  2191. switch (instr->type) {
  2192. case NAND_OP_CMD_INSTR:
  2193. pr_debug("%sCMD [0x%02x]\n", prefix,
  2194. instr->ctx.cmd.opcode);
  2195. break;
  2196. case NAND_OP_ADDR_INSTR:
  2197. pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
  2198. instr->ctx.addr.naddrs,
  2199. instr->ctx.addr.naddrs < 64 ?
  2200. instr->ctx.addr.naddrs : 64,
  2201. instr->ctx.addr.addrs);
  2202. break;
  2203. case NAND_OP_DATA_IN_INSTR:
  2204. pr_debug("%sDATA_IN [%d B%s]\n", prefix,
  2205. instr->ctx.data.len,
  2206. instr->ctx.data.force_8bit ?
  2207. ", force 8-bit" : "");
  2208. break;
  2209. case NAND_OP_DATA_OUT_INSTR:
  2210. pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
  2211. instr->ctx.data.len,
  2212. instr->ctx.data.force_8bit ?
  2213. ", force 8-bit" : "");
  2214. break;
  2215. case NAND_OP_WAITRDY_INSTR:
  2216. pr_debug("%sWAITRDY [max %d ms]\n", prefix,
  2217. instr->ctx.waitrdy.timeout_ms);
  2218. break;
  2219. }
  2220. if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])
  2221. prefix = " ";
  2222. }
  2223. }
  2224. #else
  2225. static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
  2226. {
  2227. /* NOP */
  2228. }
  2229. #endif
  2230. /**
  2231. * nand_op_parser_exec_op - exec_op parser
  2232. * @chip: the NAND chip
  2233. * @parser: patterns description provided by the controller driver
  2234. * @op: the NAND operation to address
  2235. * @check_only: when true, the function only checks if @op can be handled but
  2236. * does not execute the operation
  2237. *
  2238. * Helper function designed to ease integration of NAND controller drivers that
  2239. * only support a limited set of instruction sequences. The supported sequences
  2240. * are described in @parser, and the framework takes care of splitting @op into
  2241. * multiple sub-operations (if required) and pass them back to the ->exec()
  2242. * callback of the matching pattern if @check_only is set to false.
  2243. *
  2244. * NAND controller drivers should call this function from their own ->exec_op()
  2245. * implementation.
  2246. *
  2247. * Returns 0 on success, a negative error code otherwise. A failure can be
  2248. * caused by an unsupported operation (none of the supported patterns is able
  2249. * to handle the requested operation), or an error returned by one of the
  2250. * matching pattern->exec() hook.
  2251. */
  2252. int nand_op_parser_exec_op(struct nand_chip *chip,
  2253. const struct nand_op_parser *parser,
  2254. const struct nand_operation *op, bool check_only)
  2255. {
  2256. struct nand_op_parser_ctx ctx = {
  2257. .subop.instrs = op->instrs,
  2258. .instrs = op->instrs,
  2259. .ninstrs = op->ninstrs,
  2260. };
  2261. unsigned int i;
  2262. while (ctx.subop.instrs < op->instrs + op->ninstrs) {
  2263. int ret;
  2264. for (i = 0; i < parser->npatterns; i++) {
  2265. const struct nand_op_parser_pattern *pattern;
  2266. pattern = &parser->patterns[i];
  2267. if (!nand_op_parser_match_pat(pattern, &ctx))
  2268. continue;
  2269. nand_op_parser_trace(&ctx);
  2270. if (check_only)
  2271. break;
  2272. ret = pattern->exec(chip, &ctx.subop);
  2273. if (ret)
  2274. return ret;
  2275. break;
  2276. }
  2277. if (i == parser->npatterns) {
  2278. pr_debug("->exec_op() parser: pattern not found!\n");
  2279. return -ENOTSUPP;
  2280. }
  2281. /*
  2282. * Update the context structure by pointing to the start of the
  2283. * next subop.
  2284. */
  2285. ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs;
  2286. if (ctx.subop.last_instr_end_off)
  2287. ctx.subop.instrs -= 1;
  2288. ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off;
  2289. }
  2290. return 0;
  2291. }
  2292. EXPORT_SYMBOL_GPL(nand_op_parser_exec_op);
  2293. static bool nand_instr_is_data(const struct nand_op_instr *instr)
  2294. {
  2295. return instr && (instr->type == NAND_OP_DATA_IN_INSTR ||
  2296. instr->type == NAND_OP_DATA_OUT_INSTR);
  2297. }
  2298. static bool nand_subop_instr_is_valid(const struct nand_subop *subop,
  2299. unsigned int instr_idx)
  2300. {
  2301. return subop && instr_idx < subop->ninstrs;
  2302. }
  2303. static int nand_subop_get_start_off(const struct nand_subop *subop,
  2304. unsigned int instr_idx)
  2305. {
  2306. if (instr_idx)
  2307. return 0;
  2308. return subop->first_instr_start_off;
  2309. }
  2310. /**
  2311. * nand_subop_get_addr_start_off - Get the start offset in an address array
  2312. * @subop: The entire sub-operation
  2313. * @instr_idx: Index of the instruction inside the sub-operation
  2314. *
  2315. * During driver development, one could be tempted to directly use the
  2316. * ->addr.addrs field of address instructions. This is wrong as address
  2317. * instructions might be split.
  2318. *
  2319. * Given an address instruction, returns the offset of the first cycle to issue.
  2320. */
  2321. int nand_subop_get_addr_start_off(const struct nand_subop *subop,
  2322. unsigned int instr_idx)
  2323. {
  2324. if (!nand_subop_instr_is_valid(subop, instr_idx) ||
  2325. subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)
  2326. return -EINVAL;
  2327. return nand_subop_get_start_off(subop, instr_idx);
  2328. }
  2329. EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off);
  2330. /**
  2331. * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
  2332. * @subop: The entire sub-operation
  2333. * @instr_idx: Index of the instruction inside the sub-operation
  2334. *
  2335. * During driver development, one could be tempted to directly use the
  2336. * ->addr->naddrs field of a data instruction. This is wrong as instructions
  2337. * might be split.
  2338. *
  2339. * Given an address instruction, returns the number of address cycle to issue.
  2340. */
  2341. int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
  2342. unsigned int instr_idx)
  2343. {
  2344. int start_off, end_off;
  2345. if (!nand_subop_instr_is_valid(subop, instr_idx) ||
  2346. subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)
  2347. return -EINVAL;
  2348. start_off = nand_subop_get_addr_start_off(subop, instr_idx);
  2349. if (instr_idx == subop->ninstrs - 1 &&
  2350. subop->last_instr_end_off)
  2351. end_off = subop->last_instr_end_off;
  2352. else
  2353. end_off = subop->instrs[instr_idx].ctx.addr.naddrs;
  2354. return end_off - start_off;
  2355. }
  2356. EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc);
  2357. /**
  2358. * nand_subop_get_data_start_off - Get the start offset in a data array
  2359. * @subop: The entire sub-operation
  2360. * @instr_idx: Index of the instruction inside the sub-operation
  2361. *
  2362. * During driver development, one could be tempted to directly use the
  2363. * ->data->buf.{in,out} field of data instructions. This is wrong as data
  2364. * instructions might be split.
  2365. *
  2366. * Given a data instruction, returns the offset to start from.
  2367. */
  2368. int nand_subop_get_data_start_off(const struct nand_subop *subop,
  2369. unsigned int instr_idx)
  2370. {
  2371. if (!nand_subop_instr_is_valid(subop, instr_idx) ||
  2372. !nand_instr_is_data(&subop->instrs[instr_idx]))
  2373. return -EINVAL;
  2374. return nand_subop_get_start_off(subop, instr_idx);
  2375. }
  2376. EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off);
  2377. /**
  2378. * nand_subop_get_data_len - Get the number of bytes to retrieve
  2379. * @subop: The entire sub-operation
  2380. * @instr_idx: Index of the instruction inside the sub-operation
  2381. *
  2382. * During driver development, one could be tempted to directly use the
  2383. * ->data->len field of a data instruction. This is wrong as data instructions
  2384. * might be split.
  2385. *
  2386. * Returns the length of the chunk of data to send/receive.
  2387. */
  2388. int nand_subop_get_data_len(const struct nand_subop *subop,
  2389. unsigned int instr_idx)
  2390. {
  2391. int start_off = 0, end_off;
  2392. if (!nand_subop_instr_is_valid(subop, instr_idx) ||
  2393. !nand_instr_is_data(&subop->instrs[instr_idx]))
  2394. return -EINVAL;
  2395. start_off = nand_subop_get_data_start_off(subop, instr_idx);
  2396. if (instr_idx == subop->ninstrs - 1 &&
  2397. subop->last_instr_end_off)
  2398. end_off = subop->last_instr_end_off;
  2399. else
  2400. end_off = subop->instrs[instr_idx].ctx.data.len;
  2401. return end_off - start_off;
  2402. }
  2403. EXPORT_SYMBOL_GPL(nand_subop_get_data_len);
  2404. /**
  2405. * nand_reset - Reset and initialize a NAND device
  2406. * @chip: The NAND chip
  2407. * @chipnr: Internal die id
  2408. *
  2409. * Save the timings data structure, then apply SDR timings mode 0 (see
  2410. * nand_reset_data_interface for details), do the reset operation, and
  2411. * apply back the previous timings.
  2412. *
  2413. * Returns 0 on success, a negative error code otherwise.
  2414. */
  2415. int nand_reset(struct nand_chip *chip, int chipnr)
  2416. {
  2417. struct mtd_info *mtd = nand_to_mtd(chip);
  2418. struct nand_data_interface saved_data_intf = chip->data_interface;
  2419. int ret;
  2420. ret = nand_reset_data_interface(chip, chipnr);
  2421. if (ret)
  2422. return ret;
  2423. /*
  2424. * The CS line has to be released before we can apply the new NAND
  2425. * interface settings, hence this weird ->select_chip() dance.
  2426. */
  2427. chip->select_chip(mtd, chipnr);
  2428. ret = nand_reset_op(chip);
  2429. chip->select_chip(mtd, -1);
  2430. if (ret)
  2431. return ret;
  2432. /*
  2433. * A nand_reset_data_interface() put both the NAND chip and the NAND
  2434. * controller in timings mode 0. If the default mode for this chip is
  2435. * also 0, no need to proceed to the change again. Plus, at probe time,
  2436. * nand_setup_data_interface() uses ->set/get_features() which would
  2437. * fail anyway as the parameter page is not available yet.
  2438. */
  2439. if (!chip->onfi_timing_mode_default)
  2440. return 0;
  2441. chip->data_interface = saved_data_intf;
  2442. ret = nand_setup_data_interface(chip, chipnr);
  2443. if (ret)
  2444. return ret;
  2445. return 0;
  2446. }
  2447. EXPORT_SYMBOL_GPL(nand_reset);
  2448. /**
  2449. * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
  2450. * @buf: buffer to test
  2451. * @len: buffer length
  2452. * @bitflips_threshold: maximum number of bitflips
  2453. *
  2454. * Check if a buffer contains only 0xff, which means the underlying region
  2455. * has been erased and is ready to be programmed.
  2456. * The bitflips_threshold specify the maximum number of bitflips before
  2457. * considering the region is not erased.
  2458. * Note: The logic of this function has been extracted from the memweight
  2459. * implementation, except that nand_check_erased_buf function exit before
  2460. * testing the whole buffer if the number of bitflips exceed the
  2461. * bitflips_threshold value.
  2462. *
  2463. * Returns a positive number of bitflips less than or equal to
  2464. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  2465. * threshold.
  2466. */
  2467. static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
  2468. {
  2469. const unsigned char *bitmap = buf;
  2470. int bitflips = 0;
  2471. int weight;
  2472. for (; len && ((uintptr_t)bitmap) % sizeof(long);
  2473. len--, bitmap++) {
  2474. weight = hweight8(*bitmap);
  2475. bitflips += BITS_PER_BYTE - weight;
  2476. if (unlikely(bitflips > bitflips_threshold))
  2477. return -EBADMSG;
  2478. }
  2479. for (; len >= sizeof(long);
  2480. len -= sizeof(long), bitmap += sizeof(long)) {
  2481. unsigned long d = *((unsigned long *)bitmap);
  2482. if (d == ~0UL)
  2483. continue;
  2484. weight = hweight_long(d);
  2485. bitflips += BITS_PER_LONG - weight;
  2486. if (unlikely(bitflips > bitflips_threshold))
  2487. return -EBADMSG;
  2488. }
  2489. for (; len > 0; len--, bitmap++) {
  2490. weight = hweight8(*bitmap);
  2491. bitflips += BITS_PER_BYTE - weight;
  2492. if (unlikely(bitflips > bitflips_threshold))
  2493. return -EBADMSG;
  2494. }
  2495. return bitflips;
  2496. }
  2497. /**
  2498. * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
  2499. * 0xff data
  2500. * @data: data buffer to test
  2501. * @datalen: data length
  2502. * @ecc: ECC buffer
  2503. * @ecclen: ECC length
  2504. * @extraoob: extra OOB buffer
  2505. * @extraooblen: extra OOB length
  2506. * @bitflips_threshold: maximum number of bitflips
  2507. *
  2508. * Check if a data buffer and its associated ECC and OOB data contains only
  2509. * 0xff pattern, which means the underlying region has been erased and is
  2510. * ready to be programmed.
  2511. * The bitflips_threshold specify the maximum number of bitflips before
  2512. * considering the region as not erased.
  2513. *
  2514. * Note:
  2515. * 1/ ECC algorithms are working on pre-defined block sizes which are usually
  2516. * different from the NAND page size. When fixing bitflips, ECC engines will
  2517. * report the number of errors per chunk, and the NAND core infrastructure
  2518. * expect you to return the maximum number of bitflips for the whole page.
  2519. * This is why you should always use this function on a single chunk and
  2520. * not on the whole page. After checking each chunk you should update your
  2521. * max_bitflips value accordingly.
  2522. * 2/ When checking for bitflips in erased pages you should not only check
  2523. * the payload data but also their associated ECC data, because a user might
  2524. * have programmed almost all bits to 1 but a few. In this case, we
  2525. * shouldn't consider the chunk as erased, and checking ECC bytes prevent
  2526. * this case.
  2527. * 3/ The extraoob argument is optional, and should be used if some of your OOB
  2528. * data are protected by the ECC engine.
  2529. * It could also be used if you support subpages and want to attach some
  2530. * extra OOB data to an ECC chunk.
  2531. *
  2532. * Returns a positive number of bitflips less than or equal to
  2533. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  2534. * threshold. In case of success, the passed buffers are filled with 0xff.
  2535. */
  2536. int nand_check_erased_ecc_chunk(void *data, int datalen,
  2537. void *ecc, int ecclen,
  2538. void *extraoob, int extraooblen,
  2539. int bitflips_threshold)
  2540. {
  2541. int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
  2542. data_bitflips = nand_check_erased_buf(data, datalen,
  2543. bitflips_threshold);
  2544. if (data_bitflips < 0)
  2545. return data_bitflips;
  2546. bitflips_threshold -= data_bitflips;
  2547. ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
  2548. if (ecc_bitflips < 0)
  2549. return ecc_bitflips;
  2550. bitflips_threshold -= ecc_bitflips;
  2551. extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
  2552. bitflips_threshold);
  2553. if (extraoob_bitflips < 0)
  2554. return extraoob_bitflips;
  2555. if (data_bitflips)
  2556. memset(data, 0xff, datalen);
  2557. if (ecc_bitflips)
  2558. memset(ecc, 0xff, ecclen);
  2559. if (extraoob_bitflips)
  2560. memset(extraoob, 0xff, extraooblen);
  2561. return data_bitflips + ecc_bitflips + extraoob_bitflips;
  2562. }
  2563. EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
  2564. /**
  2565. * nand_read_page_raw - [INTERN] read raw page data without ecc
  2566. * @mtd: mtd info structure
  2567. * @chip: nand chip info structure
  2568. * @buf: buffer to store read data
  2569. * @oob_required: caller requires OOB data read to chip->oob_poi
  2570. * @page: page number to read
  2571. *
  2572. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  2573. */
  2574. int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  2575. uint8_t *buf, int oob_required, int page)
  2576. {
  2577. int ret;
  2578. ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
  2579. if (ret)
  2580. return ret;
  2581. if (oob_required) {
  2582. ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
  2583. false);
  2584. if (ret)
  2585. return ret;
  2586. }
  2587. return 0;
  2588. }
  2589. EXPORT_SYMBOL(nand_read_page_raw);
  2590. /**
  2591. * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
  2592. * @mtd: mtd info structure
  2593. * @chip: nand chip info structure
  2594. * @buf: buffer to store read data
  2595. * @oob_required: caller requires OOB data read to chip->oob_poi
  2596. * @page: page number to read
  2597. *
  2598. * We need a special oob layout and handling even when OOB isn't used.
  2599. */
  2600. static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
  2601. struct nand_chip *chip, uint8_t *buf,
  2602. int oob_required, int page)
  2603. {
  2604. int eccsize = chip->ecc.size;
  2605. int eccbytes = chip->ecc.bytes;
  2606. uint8_t *oob = chip->oob_poi;
  2607. int steps, size, ret;
  2608. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  2609. if (ret)
  2610. return ret;
  2611. for (steps = chip->ecc.steps; steps > 0; steps--) {
  2612. ret = nand_read_data_op(chip, buf, eccsize, false);
  2613. if (ret)
  2614. return ret;
  2615. buf += eccsize;
  2616. if (chip->ecc.prepad) {
  2617. ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
  2618. false);
  2619. if (ret)
  2620. return ret;
  2621. oob += chip->ecc.prepad;
  2622. }
  2623. ret = nand_read_data_op(chip, oob, eccbytes, false);
  2624. if (ret)
  2625. return ret;
  2626. oob += eccbytes;
  2627. if (chip->ecc.postpad) {
  2628. ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
  2629. false);
  2630. if (ret)
  2631. return ret;
  2632. oob += chip->ecc.postpad;
  2633. }
  2634. }
  2635. size = mtd->oobsize - (oob - chip->oob_poi);
  2636. if (size) {
  2637. ret = nand_read_data_op(chip, oob, size, false);
  2638. if (ret)
  2639. return ret;
  2640. }
  2641. return 0;
  2642. }
  2643. /**
  2644. * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
  2645. * @mtd: mtd info structure
  2646. * @chip: nand chip info structure
  2647. * @buf: buffer to store read data
  2648. * @oob_required: caller requires OOB data read to chip->oob_poi
  2649. * @page: page number to read
  2650. */
  2651. static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  2652. uint8_t *buf, int oob_required, int page)
  2653. {
  2654. int i, eccsize = chip->ecc.size, ret;
  2655. int eccbytes = chip->ecc.bytes;
  2656. int eccsteps = chip->ecc.steps;
  2657. uint8_t *p = buf;
  2658. uint8_t *ecc_calc = chip->ecc.calc_buf;
  2659. uint8_t *ecc_code = chip->ecc.code_buf;
  2660. unsigned int max_bitflips = 0;
  2661. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  2662. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  2663. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2664. ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
  2665. chip->ecc.total);
  2666. if (ret)
  2667. return ret;
  2668. eccsteps = chip->ecc.steps;
  2669. p = buf;
  2670. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2671. int stat;
  2672. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  2673. if (stat < 0) {
  2674. mtd->ecc_stats.failed++;
  2675. } else {
  2676. mtd->ecc_stats.corrected += stat;
  2677. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  2678. }
  2679. }
  2680. return max_bitflips;
  2681. }
  2682. /**
  2683. * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
  2684. * @mtd: mtd info structure
  2685. * @chip: nand chip info structure
  2686. * @data_offs: offset of requested data within the page
  2687. * @readlen: data length
  2688. * @bufpoi: buffer to store read data
  2689. * @page: page number to read
  2690. */
  2691. static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  2692. uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
  2693. int page)
  2694. {
  2695. int start_step, end_step, num_steps, ret;
  2696. uint8_t *p;
  2697. int data_col_addr, i, gaps = 0;
  2698. int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
  2699. int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
  2700. int index, section = 0;
  2701. unsigned int max_bitflips = 0;
  2702. struct mtd_oob_region oobregion = { };
  2703. /* Column address within the page aligned to ECC size (256bytes) */
  2704. start_step = data_offs / chip->ecc.size;
  2705. end_step = (data_offs + readlen - 1) / chip->ecc.size;
  2706. num_steps = end_step - start_step + 1;
  2707. index = start_step * chip->ecc.bytes;
  2708. /* Data size aligned to ECC ecc.size */
  2709. datafrag_len = num_steps * chip->ecc.size;
  2710. eccfrag_len = num_steps * chip->ecc.bytes;
  2711. data_col_addr = start_step * chip->ecc.size;
  2712. /* If we read not a page aligned data */
  2713. p = bufpoi + data_col_addr;
  2714. ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);
  2715. if (ret)
  2716. return ret;
  2717. /* Calculate ECC */
  2718. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
  2719. chip->ecc.calculate(mtd, p, &chip->ecc.calc_buf[i]);
  2720. /*
  2721. * The performance is faster if we position offsets according to
  2722. * ecc.pos. Let's make sure that there are no gaps in ECC positions.
  2723. */
  2724. ret = mtd_ooblayout_find_eccregion(mtd, index, &section, &oobregion);
  2725. if (ret)
  2726. return ret;
  2727. if (oobregion.length < eccfrag_len)
  2728. gaps = 1;
  2729. if (gaps) {
  2730. ret = nand_change_read_column_op(chip, mtd->writesize,
  2731. chip->oob_poi, mtd->oobsize,
  2732. false);
  2733. if (ret)
  2734. return ret;
  2735. } else {
  2736. /*
  2737. * Send the command to read the particular ECC bytes take care
  2738. * about buswidth alignment in read_buf.
  2739. */
  2740. aligned_pos = oobregion.offset & ~(busw - 1);
  2741. aligned_len = eccfrag_len;
  2742. if (oobregion.offset & (busw - 1))
  2743. aligned_len++;
  2744. if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
  2745. (busw - 1))
  2746. aligned_len++;
  2747. ret = nand_change_read_column_op(chip,
  2748. mtd->writesize + aligned_pos,
  2749. &chip->oob_poi[aligned_pos],
  2750. aligned_len, false);
  2751. if (ret)
  2752. return ret;
  2753. }
  2754. ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf,
  2755. chip->oob_poi, index, eccfrag_len);
  2756. if (ret)
  2757. return ret;
  2758. p = bufpoi + data_col_addr;
  2759. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
  2760. int stat;
  2761. stat = chip->ecc.correct(mtd, p, &chip->ecc.code_buf[i],
  2762. &chip->ecc.calc_buf[i]);
  2763. if (stat == -EBADMSG &&
  2764. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  2765. /* check for empty pages with bitflips */
  2766. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  2767. &chip->ecc.code_buf[i],
  2768. chip->ecc.bytes,
  2769. NULL, 0,
  2770. chip->ecc.strength);
  2771. }
  2772. if (stat < 0) {
  2773. mtd->ecc_stats.failed++;
  2774. } else {
  2775. mtd->ecc_stats.corrected += stat;
  2776. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  2777. }
  2778. }
  2779. return max_bitflips;
  2780. }
  2781. /**
  2782. * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
  2783. * @mtd: mtd info structure
  2784. * @chip: nand chip info structure
  2785. * @buf: buffer to store read data
  2786. * @oob_required: caller requires OOB data read to chip->oob_poi
  2787. * @page: page number to read
  2788. *
  2789. * Not for syndrome calculating ECC controllers which need a special oob layout.
  2790. */
  2791. static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  2792. uint8_t *buf, int oob_required, int page)
  2793. {
  2794. int i, eccsize = chip->ecc.size, ret;
  2795. int eccbytes = chip->ecc.bytes;
  2796. int eccsteps = chip->ecc.steps;
  2797. uint8_t *p = buf;
  2798. uint8_t *ecc_calc = chip->ecc.calc_buf;
  2799. uint8_t *ecc_code = chip->ecc.code_buf;
  2800. unsigned int max_bitflips = 0;
  2801. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  2802. if (ret)
  2803. return ret;
  2804. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2805. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  2806. ret = nand_read_data_op(chip, p, eccsize, false);
  2807. if (ret)
  2808. return ret;
  2809. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2810. }
  2811. ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  2812. if (ret)
  2813. return ret;
  2814. ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
  2815. chip->ecc.total);
  2816. if (ret)
  2817. return ret;
  2818. eccsteps = chip->ecc.steps;
  2819. p = buf;
  2820. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2821. int stat;
  2822. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  2823. if (stat == -EBADMSG &&
  2824. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  2825. /* check for empty pages with bitflips */
  2826. stat = nand_check_erased_ecc_chunk(p, eccsize,
  2827. &ecc_code[i], eccbytes,
  2828. NULL, 0,
  2829. chip->ecc.strength);
  2830. }
  2831. if (stat < 0) {
  2832. mtd->ecc_stats.failed++;
  2833. } else {
  2834. mtd->ecc_stats.corrected += stat;
  2835. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  2836. }
  2837. }
  2838. return max_bitflips;
  2839. }
  2840. /**
  2841. * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
  2842. * @mtd: mtd info structure
  2843. * @chip: nand chip info structure
  2844. * @buf: buffer to store read data
  2845. * @oob_required: caller requires OOB data read to chip->oob_poi
  2846. * @page: page number to read
  2847. *
  2848. * Hardware ECC for large page chips, require OOB to be read first. For this
  2849. * ECC mode, the write_page method is re-used from ECC_HW. These methods
  2850. * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
  2851. * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
  2852. * the data area, by overwriting the NAND manufacturer bad block markings.
  2853. */
  2854. static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
  2855. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  2856. {
  2857. int i, eccsize = chip->ecc.size, ret;
  2858. int eccbytes = chip->ecc.bytes;
  2859. int eccsteps = chip->ecc.steps;
  2860. uint8_t *p = buf;
  2861. uint8_t *ecc_code = chip->ecc.code_buf;
  2862. uint8_t *ecc_calc = chip->ecc.calc_buf;
  2863. unsigned int max_bitflips = 0;
  2864. /* Read the OOB area first */
  2865. ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
  2866. if (ret)
  2867. return ret;
  2868. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  2869. if (ret)
  2870. return ret;
  2871. ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
  2872. chip->ecc.total);
  2873. if (ret)
  2874. return ret;
  2875. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2876. int stat;
  2877. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  2878. ret = nand_read_data_op(chip, p, eccsize, false);
  2879. if (ret)
  2880. return ret;
  2881. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2882. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  2883. if (stat == -EBADMSG &&
  2884. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  2885. /* check for empty pages with bitflips */
  2886. stat = nand_check_erased_ecc_chunk(p, eccsize,
  2887. &ecc_code[i], eccbytes,
  2888. NULL, 0,
  2889. chip->ecc.strength);
  2890. }
  2891. if (stat < 0) {
  2892. mtd->ecc_stats.failed++;
  2893. } else {
  2894. mtd->ecc_stats.corrected += stat;
  2895. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  2896. }
  2897. }
  2898. return max_bitflips;
  2899. }
  2900. /**
  2901. * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
  2902. * @mtd: mtd info structure
  2903. * @chip: nand chip info structure
  2904. * @buf: buffer to store read data
  2905. * @oob_required: caller requires OOB data read to chip->oob_poi
  2906. * @page: page number to read
  2907. *
  2908. * The hw generator calculates the error syndrome automatically. Therefore we
  2909. * need a special oob layout and handling.
  2910. */
  2911. static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  2912. uint8_t *buf, int oob_required, int page)
  2913. {
  2914. int ret, i, eccsize = chip->ecc.size;
  2915. int eccbytes = chip->ecc.bytes;
  2916. int eccsteps = chip->ecc.steps;
  2917. int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  2918. uint8_t *p = buf;
  2919. uint8_t *oob = chip->oob_poi;
  2920. unsigned int max_bitflips = 0;
  2921. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  2922. if (ret)
  2923. return ret;
  2924. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2925. int stat;
  2926. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  2927. ret = nand_read_data_op(chip, p, eccsize, false);
  2928. if (ret)
  2929. return ret;
  2930. if (chip->ecc.prepad) {
  2931. ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
  2932. false);
  2933. if (ret)
  2934. return ret;
  2935. oob += chip->ecc.prepad;
  2936. }
  2937. chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
  2938. ret = nand_read_data_op(chip, oob, eccbytes, false);
  2939. if (ret)
  2940. return ret;
  2941. stat = chip->ecc.correct(mtd, p, oob, NULL);
  2942. oob += eccbytes;
  2943. if (chip->ecc.postpad) {
  2944. ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
  2945. false);
  2946. if (ret)
  2947. return ret;
  2948. oob += chip->ecc.postpad;
  2949. }
  2950. if (stat == -EBADMSG &&
  2951. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  2952. /* check for empty pages with bitflips */
  2953. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  2954. oob - eccpadbytes,
  2955. eccpadbytes,
  2956. NULL, 0,
  2957. chip->ecc.strength);
  2958. }
  2959. if (stat < 0) {
  2960. mtd->ecc_stats.failed++;
  2961. } else {
  2962. mtd->ecc_stats.corrected += stat;
  2963. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  2964. }
  2965. }
  2966. /* Calculate remaining oob bytes */
  2967. i = mtd->oobsize - (oob - chip->oob_poi);
  2968. if (i) {
  2969. ret = nand_read_data_op(chip, oob, i, false);
  2970. if (ret)
  2971. return ret;
  2972. }
  2973. return max_bitflips;
  2974. }
  2975. /**
  2976. * nand_transfer_oob - [INTERN] Transfer oob to client buffer
  2977. * @mtd: mtd info structure
  2978. * @oob: oob destination address
  2979. * @ops: oob ops structure
  2980. * @len: size of oob to transfer
  2981. */
  2982. static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
  2983. struct mtd_oob_ops *ops, size_t len)
  2984. {
  2985. struct nand_chip *chip = mtd_to_nand(mtd);
  2986. int ret;
  2987. switch (ops->mode) {
  2988. case MTD_OPS_PLACE_OOB:
  2989. case MTD_OPS_RAW:
  2990. memcpy(oob, chip->oob_poi + ops->ooboffs, len);
  2991. return oob + len;
  2992. case MTD_OPS_AUTO_OOB:
  2993. ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
  2994. ops->ooboffs, len);
  2995. BUG_ON(ret);
  2996. return oob + len;
  2997. default:
  2998. BUG();
  2999. }
  3000. return NULL;
  3001. }
  3002. /**
  3003. * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
  3004. * @mtd: MTD device structure
  3005. * @retry_mode: the retry mode to use
  3006. *
  3007. * Some vendors supply a special command to shift the Vt threshold, to be used
  3008. * when there are too many bitflips in a page (i.e., ECC error). After setting
  3009. * a new threshold, the host should retry reading the page.
  3010. */
  3011. static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
  3012. {
  3013. struct nand_chip *chip = mtd_to_nand(mtd);
  3014. pr_debug("setting READ RETRY mode %d\n", retry_mode);
  3015. if (retry_mode >= chip->read_retries)
  3016. return -EINVAL;
  3017. if (!chip->setup_read_retry)
  3018. return -EOPNOTSUPP;
  3019. return chip->setup_read_retry(mtd, retry_mode);
  3020. }
  3021. /**
  3022. * nand_do_read_ops - [INTERN] Read data with ECC
  3023. * @mtd: MTD device structure
  3024. * @from: offset to read from
  3025. * @ops: oob ops structure
  3026. *
  3027. * Internal function. Called with chip held.
  3028. */
  3029. static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
  3030. struct mtd_oob_ops *ops)
  3031. {
  3032. int chipnr, page, realpage, col, bytes, aligned, oob_required;
  3033. struct nand_chip *chip = mtd_to_nand(mtd);
  3034. int ret = 0;
  3035. uint32_t readlen = ops->len;
  3036. uint32_t oobreadlen = ops->ooblen;
  3037. uint32_t max_oobsize = mtd_oobavail(mtd, ops);
  3038. uint8_t *bufpoi, *oob, *buf;
  3039. int use_bufpoi;
  3040. unsigned int max_bitflips = 0;
  3041. int retry_mode = 0;
  3042. bool ecc_fail = false;
  3043. chipnr = (int)(from >> chip->chip_shift);
  3044. chip->select_chip(mtd, chipnr);
  3045. realpage = (int)(from >> chip->page_shift);
  3046. page = realpage & chip->pagemask;
  3047. col = (int)(from & (mtd->writesize - 1));
  3048. buf = ops->datbuf;
  3049. oob = ops->oobbuf;
  3050. oob_required = oob ? 1 : 0;
  3051. while (1) {
  3052. unsigned int ecc_failures = mtd->ecc_stats.failed;
  3053. bytes = min(mtd->writesize - col, readlen);
  3054. aligned = (bytes == mtd->writesize);
  3055. if (!aligned)
  3056. use_bufpoi = 1;
  3057. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  3058. use_bufpoi = !virt_addr_valid(buf) ||
  3059. !IS_ALIGNED((unsigned long)buf,
  3060. chip->buf_align);
  3061. else
  3062. use_bufpoi = 0;
  3063. /* Is the current page in the buffer? */
  3064. if (realpage != chip->pagebuf || oob) {
  3065. bufpoi = use_bufpoi ? chip->data_buf : buf;
  3066. if (use_bufpoi && aligned)
  3067. pr_debug("%s: using read bounce buffer for buf@%p\n",
  3068. __func__, buf);
  3069. read_retry:
  3070. /*
  3071. * Now read the page into the buffer. Absent an error,
  3072. * the read methods return max bitflips per ecc step.
  3073. */
  3074. if (unlikely(ops->mode == MTD_OPS_RAW))
  3075. ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
  3076. oob_required,
  3077. page);
  3078. else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
  3079. !oob)
  3080. ret = chip->ecc.read_subpage(mtd, chip,
  3081. col, bytes, bufpoi,
  3082. page);
  3083. else
  3084. ret = chip->ecc.read_page(mtd, chip, bufpoi,
  3085. oob_required, page);
  3086. if (ret < 0) {
  3087. if (use_bufpoi)
  3088. /* Invalidate page cache */
  3089. chip->pagebuf = -1;
  3090. break;
  3091. }
  3092. /* Transfer not aligned data */
  3093. if (use_bufpoi) {
  3094. if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
  3095. !(mtd->ecc_stats.failed - ecc_failures) &&
  3096. (ops->mode != MTD_OPS_RAW)) {
  3097. chip->pagebuf = realpage;
  3098. chip->pagebuf_bitflips = ret;
  3099. } else {
  3100. /* Invalidate page cache */
  3101. chip->pagebuf = -1;
  3102. }
  3103. memcpy(buf, chip->data_buf + col, bytes);
  3104. }
  3105. if (unlikely(oob)) {
  3106. int toread = min(oobreadlen, max_oobsize);
  3107. if (toread) {
  3108. oob = nand_transfer_oob(mtd,
  3109. oob, ops, toread);
  3110. oobreadlen -= toread;
  3111. }
  3112. }
  3113. if (chip->options & NAND_NEED_READRDY) {
  3114. /* Apply delay or wait for ready/busy pin */
  3115. if (!chip->dev_ready)
  3116. udelay(chip->chip_delay);
  3117. else
  3118. nand_wait_ready(mtd);
  3119. }
  3120. if (mtd->ecc_stats.failed - ecc_failures) {
  3121. if (retry_mode + 1 < chip->read_retries) {
  3122. retry_mode++;
  3123. ret = nand_setup_read_retry(mtd,
  3124. retry_mode);
  3125. if (ret < 0)
  3126. break;
  3127. /* Reset failures; retry */
  3128. mtd->ecc_stats.failed = ecc_failures;
  3129. goto read_retry;
  3130. } else {
  3131. /* No more retry modes; real failure */
  3132. ecc_fail = true;
  3133. }
  3134. }
  3135. buf += bytes;
  3136. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  3137. } else {
  3138. memcpy(buf, chip->data_buf + col, bytes);
  3139. buf += bytes;
  3140. max_bitflips = max_t(unsigned int, max_bitflips,
  3141. chip->pagebuf_bitflips);
  3142. }
  3143. readlen -= bytes;
  3144. /* Reset to retry mode 0 */
  3145. if (retry_mode) {
  3146. ret = nand_setup_read_retry(mtd, 0);
  3147. if (ret < 0)
  3148. break;
  3149. retry_mode = 0;
  3150. }
  3151. if (!readlen)
  3152. break;
  3153. /* For subsequent reads align to page boundary */
  3154. col = 0;
  3155. /* Increment page address */
  3156. realpage++;
  3157. page = realpage & chip->pagemask;
  3158. /* Check, if we cross a chip boundary */
  3159. if (!page) {
  3160. chipnr++;
  3161. chip->select_chip(mtd, -1);
  3162. chip->select_chip(mtd, chipnr);
  3163. }
  3164. }
  3165. chip->select_chip(mtd, -1);
  3166. ops->retlen = ops->len - (size_t) readlen;
  3167. if (oob)
  3168. ops->oobretlen = ops->ooblen - oobreadlen;
  3169. if (ret < 0)
  3170. return ret;
  3171. if (ecc_fail)
  3172. return -EBADMSG;
  3173. return max_bitflips;
  3174. }
  3175. /**
  3176. * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
  3177. * @mtd: mtd info structure
  3178. * @chip: nand chip info structure
  3179. * @page: page number to read
  3180. */
  3181. int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
  3182. {
  3183. return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
  3184. }
  3185. EXPORT_SYMBOL(nand_read_oob_std);
  3186. /**
  3187. * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
  3188. * with syndromes
  3189. * @mtd: mtd info structure
  3190. * @chip: nand chip info structure
  3191. * @page: page number to read
  3192. */
  3193. int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  3194. int page)
  3195. {
  3196. int length = mtd->oobsize;
  3197. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  3198. int eccsize = chip->ecc.size;
  3199. uint8_t *bufpoi = chip->oob_poi;
  3200. int i, toread, sndrnd = 0, pos, ret;
  3201. ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
  3202. if (ret)
  3203. return ret;
  3204. for (i = 0; i < chip->ecc.steps; i++) {
  3205. if (sndrnd) {
  3206. int ret;
  3207. pos = eccsize + i * (eccsize + chunk);
  3208. if (mtd->writesize > 512)
  3209. ret = nand_change_read_column_op(chip, pos,
  3210. NULL, 0,
  3211. false);
  3212. else
  3213. ret = nand_read_page_op(chip, page, pos, NULL,
  3214. 0);
  3215. if (ret)
  3216. return ret;
  3217. } else
  3218. sndrnd = 1;
  3219. toread = min_t(int, length, chunk);
  3220. ret = nand_read_data_op(chip, bufpoi, toread, false);
  3221. if (ret)
  3222. return ret;
  3223. bufpoi += toread;
  3224. length -= toread;
  3225. }
  3226. if (length > 0) {
  3227. ret = nand_read_data_op(chip, bufpoi, length, false);
  3228. if (ret)
  3229. return ret;
  3230. }
  3231. return 0;
  3232. }
  3233. EXPORT_SYMBOL(nand_read_oob_syndrome);
  3234. /**
  3235. * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
  3236. * @mtd: mtd info structure
  3237. * @chip: nand chip info structure
  3238. * @page: page number to write
  3239. */
  3240. int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
  3241. {
  3242. return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
  3243. mtd->oobsize);
  3244. }
  3245. EXPORT_SYMBOL(nand_write_oob_std);
  3246. /**
  3247. * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
  3248. * with syndrome - only for large page flash
  3249. * @mtd: mtd info structure
  3250. * @chip: nand chip info structure
  3251. * @page: page number to write
  3252. */
  3253. int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  3254. int page)
  3255. {
  3256. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  3257. int eccsize = chip->ecc.size, length = mtd->oobsize;
  3258. int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
  3259. const uint8_t *bufpoi = chip->oob_poi;
  3260. /*
  3261. * data-ecc-data-ecc ... ecc-oob
  3262. * or
  3263. * data-pad-ecc-pad-data-pad .... ecc-pad-oob
  3264. */
  3265. if (!chip->ecc.prepad && !chip->ecc.postpad) {
  3266. pos = steps * (eccsize + chunk);
  3267. steps = 0;
  3268. } else
  3269. pos = eccsize;
  3270. ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
  3271. if (ret)
  3272. return ret;
  3273. for (i = 0; i < steps; i++) {
  3274. if (sndcmd) {
  3275. if (mtd->writesize <= 512) {
  3276. uint32_t fill = 0xFFFFFFFF;
  3277. len = eccsize;
  3278. while (len > 0) {
  3279. int num = min_t(int, len, 4);
  3280. ret = nand_write_data_op(chip, &fill,
  3281. num, false);
  3282. if (ret)
  3283. return ret;
  3284. len -= num;
  3285. }
  3286. } else {
  3287. pos = eccsize + i * (eccsize + chunk);
  3288. ret = nand_change_write_column_op(chip, pos,
  3289. NULL, 0,
  3290. false);
  3291. if (ret)
  3292. return ret;
  3293. }
  3294. } else
  3295. sndcmd = 1;
  3296. len = min_t(int, length, chunk);
  3297. ret = nand_write_data_op(chip, bufpoi, len, false);
  3298. if (ret)
  3299. return ret;
  3300. bufpoi += len;
  3301. length -= len;
  3302. }
  3303. if (length > 0) {
  3304. ret = nand_write_data_op(chip, bufpoi, length, false);
  3305. if (ret)
  3306. return ret;
  3307. }
  3308. return nand_prog_page_end_op(chip);
  3309. }
  3310. EXPORT_SYMBOL(nand_write_oob_syndrome);
  3311. /**
  3312. * nand_do_read_oob - [INTERN] NAND read out-of-band
  3313. * @mtd: MTD device structure
  3314. * @from: offset to read from
  3315. * @ops: oob operations description structure
  3316. *
  3317. * NAND read out-of-band data from the spare area.
  3318. */
  3319. static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
  3320. struct mtd_oob_ops *ops)
  3321. {
  3322. unsigned int max_bitflips = 0;
  3323. int page, realpage, chipnr;
  3324. struct nand_chip *chip = mtd_to_nand(mtd);
  3325. struct mtd_ecc_stats stats;
  3326. int readlen = ops->ooblen;
  3327. int len;
  3328. uint8_t *buf = ops->oobbuf;
  3329. int ret = 0;
  3330. pr_debug("%s: from = 0x%08Lx, len = %i\n",
  3331. __func__, (unsigned long long)from, readlen);
  3332. stats = mtd->ecc_stats;
  3333. len = mtd_oobavail(mtd, ops);
  3334. chipnr = (int)(from >> chip->chip_shift);
  3335. chip->select_chip(mtd, chipnr);
  3336. /* Shift to get page */
  3337. realpage = (int)(from >> chip->page_shift);
  3338. page = realpage & chip->pagemask;
  3339. while (1) {
  3340. if (ops->mode == MTD_OPS_RAW)
  3341. ret = chip->ecc.read_oob_raw(mtd, chip, page);
  3342. else
  3343. ret = chip->ecc.read_oob(mtd, chip, page);
  3344. if (ret < 0)
  3345. break;
  3346. len = min(len, readlen);
  3347. buf = nand_transfer_oob(mtd, buf, ops, len);
  3348. if (chip->options & NAND_NEED_READRDY) {
  3349. /* Apply delay or wait for ready/busy pin */
  3350. if (!chip->dev_ready)
  3351. udelay(chip->chip_delay);
  3352. else
  3353. nand_wait_ready(mtd);
  3354. }
  3355. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  3356. readlen -= len;
  3357. if (!readlen)
  3358. break;
  3359. /* Increment page address */
  3360. realpage++;
  3361. page = realpage & chip->pagemask;
  3362. /* Check, if we cross a chip boundary */
  3363. if (!page) {
  3364. chipnr++;
  3365. chip->select_chip(mtd, -1);
  3366. chip->select_chip(mtd, chipnr);
  3367. }
  3368. }
  3369. chip->select_chip(mtd, -1);
  3370. ops->oobretlen = ops->ooblen - readlen;
  3371. if (ret < 0)
  3372. return ret;
  3373. if (mtd->ecc_stats.failed - stats.failed)
  3374. return -EBADMSG;
  3375. return max_bitflips;
  3376. }
  3377. /**
  3378. * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  3379. * @mtd: MTD device structure
  3380. * @from: offset to read from
  3381. * @ops: oob operation description structure
  3382. *
  3383. * NAND read data and/or out-of-band data.
  3384. */
  3385. static int nand_read_oob(struct mtd_info *mtd, loff_t from,
  3386. struct mtd_oob_ops *ops)
  3387. {
  3388. int ret;
  3389. ops->retlen = 0;
  3390. if (ops->mode != MTD_OPS_PLACE_OOB &&
  3391. ops->mode != MTD_OPS_AUTO_OOB &&
  3392. ops->mode != MTD_OPS_RAW)
  3393. return -ENOTSUPP;
  3394. nand_get_device(mtd, FL_READING);
  3395. if (!ops->datbuf)
  3396. ret = nand_do_read_oob(mtd, from, ops);
  3397. else
  3398. ret = nand_do_read_ops(mtd, from, ops);
  3399. nand_release_device(mtd);
  3400. return ret;
  3401. }
  3402. /**
  3403. * nand_write_page_raw - [INTERN] raw page write function
  3404. * @mtd: mtd info structure
  3405. * @chip: nand chip info structure
  3406. * @buf: data buffer
  3407. * @oob_required: must write chip->oob_poi to OOB
  3408. * @page: page number to write
  3409. *
  3410. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  3411. */
  3412. int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  3413. const uint8_t *buf, int oob_required, int page)
  3414. {
  3415. int ret;
  3416. ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
  3417. if (ret)
  3418. return ret;
  3419. if (oob_required) {
  3420. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
  3421. false);
  3422. if (ret)
  3423. return ret;
  3424. }
  3425. return nand_prog_page_end_op(chip);
  3426. }
  3427. EXPORT_SYMBOL(nand_write_page_raw);
  3428. /**
  3429. * nand_write_page_raw_syndrome - [INTERN] raw page write function
  3430. * @mtd: mtd info structure
  3431. * @chip: nand chip info structure
  3432. * @buf: data buffer
  3433. * @oob_required: must write chip->oob_poi to OOB
  3434. * @page: page number to write
  3435. *
  3436. * We need a special oob layout and handling even when ECC isn't checked.
  3437. */
  3438. static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  3439. struct nand_chip *chip,
  3440. const uint8_t *buf, int oob_required,
  3441. int page)
  3442. {
  3443. int eccsize = chip->ecc.size;
  3444. int eccbytes = chip->ecc.bytes;
  3445. uint8_t *oob = chip->oob_poi;
  3446. int steps, size, ret;
  3447. ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  3448. if (ret)
  3449. return ret;
  3450. for (steps = chip->ecc.steps; steps > 0; steps--) {
  3451. ret = nand_write_data_op(chip, buf, eccsize, false);
  3452. if (ret)
  3453. return ret;
  3454. buf += eccsize;
  3455. if (chip->ecc.prepad) {
  3456. ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
  3457. false);
  3458. if (ret)
  3459. return ret;
  3460. oob += chip->ecc.prepad;
  3461. }
  3462. ret = nand_write_data_op(chip, oob, eccbytes, false);
  3463. if (ret)
  3464. return ret;
  3465. oob += eccbytes;
  3466. if (chip->ecc.postpad) {
  3467. ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
  3468. false);
  3469. if (ret)
  3470. return ret;
  3471. oob += chip->ecc.postpad;
  3472. }
  3473. }
  3474. size = mtd->oobsize - (oob - chip->oob_poi);
  3475. if (size) {
  3476. ret = nand_write_data_op(chip, oob, size, false);
  3477. if (ret)
  3478. return ret;
  3479. }
  3480. return nand_prog_page_end_op(chip);
  3481. }
  3482. /**
  3483. * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
  3484. * @mtd: mtd info structure
  3485. * @chip: nand chip info structure
  3486. * @buf: data buffer
  3487. * @oob_required: must write chip->oob_poi to OOB
  3488. * @page: page number to write
  3489. */
  3490. static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  3491. const uint8_t *buf, int oob_required,
  3492. int page)
  3493. {
  3494. int i, eccsize = chip->ecc.size, ret;
  3495. int eccbytes = chip->ecc.bytes;
  3496. int eccsteps = chip->ecc.steps;
  3497. uint8_t *ecc_calc = chip->ecc.calc_buf;
  3498. const uint8_t *p = buf;
  3499. /* Software ECC calculation */
  3500. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  3501. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  3502. ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
  3503. chip->ecc.total);
  3504. if (ret)
  3505. return ret;
  3506. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  3507. }
  3508. /**
  3509. * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
  3510. * @mtd: mtd info structure
  3511. * @chip: nand chip info structure
  3512. * @buf: data buffer
  3513. * @oob_required: must write chip->oob_poi to OOB
  3514. * @page: page number to write
  3515. */
  3516. static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  3517. const uint8_t *buf, int oob_required,
  3518. int page)
  3519. {
  3520. int i, eccsize = chip->ecc.size, ret;
  3521. int eccbytes = chip->ecc.bytes;
  3522. int eccsteps = chip->ecc.steps;
  3523. uint8_t *ecc_calc = chip->ecc.calc_buf;
  3524. const uint8_t *p = buf;
  3525. ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  3526. if (ret)
  3527. return ret;
  3528. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  3529. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  3530. ret = nand_write_data_op(chip, p, eccsize, false);
  3531. if (ret)
  3532. return ret;
  3533. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  3534. }
  3535. ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
  3536. chip->ecc.total);
  3537. if (ret)
  3538. return ret;
  3539. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  3540. if (ret)
  3541. return ret;
  3542. return nand_prog_page_end_op(chip);
  3543. }
  3544. /**
  3545. * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
  3546. * @mtd: mtd info structure
  3547. * @chip: nand chip info structure
  3548. * @offset: column address of subpage within the page
  3549. * @data_len: data length
  3550. * @buf: data buffer
  3551. * @oob_required: must write chip->oob_poi to OOB
  3552. * @page: page number to write
  3553. */
  3554. static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  3555. struct nand_chip *chip, uint32_t offset,
  3556. uint32_t data_len, const uint8_t *buf,
  3557. int oob_required, int page)
  3558. {
  3559. uint8_t *oob_buf = chip->oob_poi;
  3560. uint8_t *ecc_calc = chip->ecc.calc_buf;
  3561. int ecc_size = chip->ecc.size;
  3562. int ecc_bytes = chip->ecc.bytes;
  3563. int ecc_steps = chip->ecc.steps;
  3564. uint32_t start_step = offset / ecc_size;
  3565. uint32_t end_step = (offset + data_len - 1) / ecc_size;
  3566. int oob_bytes = mtd->oobsize / ecc_steps;
  3567. int step, ret;
  3568. ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  3569. if (ret)
  3570. return ret;
  3571. for (step = 0; step < ecc_steps; step++) {
  3572. /* configure controller for WRITE access */
  3573. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  3574. /* write data (untouched subpages already masked by 0xFF) */
  3575. ret = nand_write_data_op(chip, buf, ecc_size, false);
  3576. if (ret)
  3577. return ret;
  3578. /* mask ECC of un-touched subpages by padding 0xFF */
  3579. if ((step < start_step) || (step > end_step))
  3580. memset(ecc_calc, 0xff, ecc_bytes);
  3581. else
  3582. chip->ecc.calculate(mtd, buf, ecc_calc);
  3583. /* mask OOB of un-touched subpages by padding 0xFF */
  3584. /* if oob_required, preserve OOB metadata of written subpage */
  3585. if (!oob_required || (step < start_step) || (step > end_step))
  3586. memset(oob_buf, 0xff, oob_bytes);
  3587. buf += ecc_size;
  3588. ecc_calc += ecc_bytes;
  3589. oob_buf += oob_bytes;
  3590. }
  3591. /* copy calculated ECC for whole page to chip->buffer->oob */
  3592. /* this include masked-value(0xFF) for unwritten subpages */
  3593. ecc_calc = chip->ecc.calc_buf;
  3594. ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
  3595. chip->ecc.total);
  3596. if (ret)
  3597. return ret;
  3598. /* write OOB buffer to NAND device */
  3599. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  3600. if (ret)
  3601. return ret;
  3602. return nand_prog_page_end_op(chip);
  3603. }
  3604. /**
  3605. * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
  3606. * @mtd: mtd info structure
  3607. * @chip: nand chip info structure
  3608. * @buf: data buffer
  3609. * @oob_required: must write chip->oob_poi to OOB
  3610. * @page: page number to write
  3611. *
  3612. * The hw generator calculates the error syndrome automatically. Therefore we
  3613. * need a special oob layout and handling.
  3614. */
  3615. static int nand_write_page_syndrome(struct mtd_info *mtd,
  3616. struct nand_chip *chip,
  3617. const uint8_t *buf, int oob_required,
  3618. int page)
  3619. {
  3620. int i, eccsize = chip->ecc.size;
  3621. int eccbytes = chip->ecc.bytes;
  3622. int eccsteps = chip->ecc.steps;
  3623. const uint8_t *p = buf;
  3624. uint8_t *oob = chip->oob_poi;
  3625. int ret;
  3626. ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  3627. if (ret)
  3628. return ret;
  3629. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  3630. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  3631. ret = nand_write_data_op(chip, p, eccsize, false);
  3632. if (ret)
  3633. return ret;
  3634. if (chip->ecc.prepad) {
  3635. ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
  3636. false);
  3637. if (ret)
  3638. return ret;
  3639. oob += chip->ecc.prepad;
  3640. }
  3641. chip->ecc.calculate(mtd, p, oob);
  3642. ret = nand_write_data_op(chip, oob, eccbytes, false);
  3643. if (ret)
  3644. return ret;
  3645. oob += eccbytes;
  3646. if (chip->ecc.postpad) {
  3647. ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
  3648. false);
  3649. if (ret)
  3650. return ret;
  3651. oob += chip->ecc.postpad;
  3652. }
  3653. }
  3654. /* Calculate remaining oob bytes */
  3655. i = mtd->oobsize - (oob - chip->oob_poi);
  3656. if (i) {
  3657. ret = nand_write_data_op(chip, oob, i, false);
  3658. if (ret)
  3659. return ret;
  3660. }
  3661. return nand_prog_page_end_op(chip);
  3662. }
  3663. /**
  3664. * nand_write_page - write one page
  3665. * @mtd: MTD device structure
  3666. * @chip: NAND chip descriptor
  3667. * @offset: address offset within the page
  3668. * @data_len: length of actual data to be written
  3669. * @buf: the data to write
  3670. * @oob_required: must write chip->oob_poi to OOB
  3671. * @page: page number to write
  3672. * @raw: use _raw version of write_page
  3673. */
  3674. static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  3675. uint32_t offset, int data_len, const uint8_t *buf,
  3676. int oob_required, int page, int raw)
  3677. {
  3678. int status, subpage;
  3679. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
  3680. chip->ecc.write_subpage)
  3681. subpage = offset || (data_len < mtd->writesize);
  3682. else
  3683. subpage = 0;
  3684. if (unlikely(raw))
  3685. status = chip->ecc.write_page_raw(mtd, chip, buf,
  3686. oob_required, page);
  3687. else if (subpage)
  3688. status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
  3689. buf, oob_required, page);
  3690. else
  3691. status = chip->ecc.write_page(mtd, chip, buf, oob_required,
  3692. page);
  3693. if (status < 0)
  3694. return status;
  3695. return 0;
  3696. }
  3697. /**
  3698. * nand_fill_oob - [INTERN] Transfer client buffer to oob
  3699. * @mtd: MTD device structure
  3700. * @oob: oob data buffer
  3701. * @len: oob data write length
  3702. * @ops: oob ops structure
  3703. */
  3704. static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
  3705. struct mtd_oob_ops *ops)
  3706. {
  3707. struct nand_chip *chip = mtd_to_nand(mtd);
  3708. int ret;
  3709. /*
  3710. * Initialise to all 0xFF, to avoid the possibility of left over OOB
  3711. * data from a previous OOB read.
  3712. */
  3713. memset(chip->oob_poi, 0xff, mtd->oobsize);
  3714. switch (ops->mode) {
  3715. case MTD_OPS_PLACE_OOB:
  3716. case MTD_OPS_RAW:
  3717. memcpy(chip->oob_poi + ops->ooboffs, oob, len);
  3718. return oob + len;
  3719. case MTD_OPS_AUTO_OOB:
  3720. ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
  3721. ops->ooboffs, len);
  3722. BUG_ON(ret);
  3723. return oob + len;
  3724. default:
  3725. BUG();
  3726. }
  3727. return NULL;
  3728. }
  3729. #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
  3730. /**
  3731. * nand_do_write_ops - [INTERN] NAND write with ECC
  3732. * @mtd: MTD device structure
  3733. * @to: offset to write to
  3734. * @ops: oob operations description structure
  3735. *
  3736. * NAND write with ECC.
  3737. */
  3738. static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
  3739. struct mtd_oob_ops *ops)
  3740. {
  3741. int chipnr, realpage, page, column;
  3742. struct nand_chip *chip = mtd_to_nand(mtd);
  3743. uint32_t writelen = ops->len;
  3744. uint32_t oobwritelen = ops->ooblen;
  3745. uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
  3746. uint8_t *oob = ops->oobbuf;
  3747. uint8_t *buf = ops->datbuf;
  3748. int ret;
  3749. int oob_required = oob ? 1 : 0;
  3750. ops->retlen = 0;
  3751. if (!writelen)
  3752. return 0;
  3753. /* Reject writes, which are not page aligned */
  3754. if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
  3755. pr_notice("%s: attempt to write non page aligned data\n",
  3756. __func__);
  3757. return -EINVAL;
  3758. }
  3759. column = to & (mtd->writesize - 1);
  3760. chipnr = (int)(to >> chip->chip_shift);
  3761. chip->select_chip(mtd, chipnr);
  3762. /* Check, if it is write protected */
  3763. if (nand_check_wp(mtd)) {
  3764. ret = -EIO;
  3765. goto err_out;
  3766. }
  3767. realpage = (int)(to >> chip->page_shift);
  3768. page = realpage & chip->pagemask;
  3769. /* Invalidate the page cache, when we write to the cached page */
  3770. if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
  3771. ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
  3772. chip->pagebuf = -1;
  3773. /* Don't allow multipage oob writes with offset */
  3774. if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
  3775. ret = -EINVAL;
  3776. goto err_out;
  3777. }
  3778. while (1) {
  3779. int bytes = mtd->writesize;
  3780. uint8_t *wbuf = buf;
  3781. int use_bufpoi;
  3782. int part_pagewr = (column || writelen < mtd->writesize);
  3783. if (part_pagewr)
  3784. use_bufpoi = 1;
  3785. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  3786. use_bufpoi = !virt_addr_valid(buf) ||
  3787. !IS_ALIGNED((unsigned long)buf,
  3788. chip->buf_align);
  3789. else
  3790. use_bufpoi = 0;
  3791. /* Partial page write?, or need to use bounce buffer */
  3792. if (use_bufpoi) {
  3793. pr_debug("%s: using write bounce buffer for buf@%p\n",
  3794. __func__, buf);
  3795. if (part_pagewr)
  3796. bytes = min_t(int, bytes - column, writelen);
  3797. chip->pagebuf = -1;
  3798. memset(chip->data_buf, 0xff, mtd->writesize);
  3799. memcpy(&chip->data_buf[column], buf, bytes);
  3800. wbuf = chip->data_buf;
  3801. }
  3802. if (unlikely(oob)) {
  3803. size_t len = min(oobwritelen, oobmaxlen);
  3804. oob = nand_fill_oob(mtd, oob, len, ops);
  3805. oobwritelen -= len;
  3806. } else {
  3807. /* We still need to erase leftover OOB data */
  3808. memset(chip->oob_poi, 0xff, mtd->oobsize);
  3809. }
  3810. ret = nand_write_page(mtd, chip, column, bytes, wbuf,
  3811. oob_required, page,
  3812. (ops->mode == MTD_OPS_RAW));
  3813. if (ret)
  3814. break;
  3815. writelen -= bytes;
  3816. if (!writelen)
  3817. break;
  3818. column = 0;
  3819. buf += bytes;
  3820. realpage++;
  3821. page = realpage & chip->pagemask;
  3822. /* Check, if we cross a chip boundary */
  3823. if (!page) {
  3824. chipnr++;
  3825. chip->select_chip(mtd, -1);
  3826. chip->select_chip(mtd, chipnr);
  3827. }
  3828. }
  3829. ops->retlen = ops->len - writelen;
  3830. if (unlikely(oob))
  3831. ops->oobretlen = ops->ooblen;
  3832. err_out:
  3833. chip->select_chip(mtd, -1);
  3834. return ret;
  3835. }
  3836. /**
  3837. * panic_nand_write - [MTD Interface] NAND write with ECC
  3838. * @mtd: MTD device structure
  3839. * @to: offset to write to
  3840. * @len: number of bytes to write
  3841. * @retlen: pointer to variable to store the number of written bytes
  3842. * @buf: the data to write
  3843. *
  3844. * NAND write with ECC. Used when performing writes in interrupt context, this
  3845. * may for example be called by mtdoops when writing an oops while in panic.
  3846. */
  3847. static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
  3848. size_t *retlen, const uint8_t *buf)
  3849. {
  3850. struct nand_chip *chip = mtd_to_nand(mtd);
  3851. int chipnr = (int)(to >> chip->chip_shift);
  3852. struct mtd_oob_ops ops;
  3853. int ret;
  3854. /* Grab the device */
  3855. panic_nand_get_device(chip, mtd, FL_WRITING);
  3856. chip->select_chip(mtd, chipnr);
  3857. /* Wait for the device to get ready */
  3858. panic_nand_wait(mtd, chip, 400);
  3859. memset(&ops, 0, sizeof(ops));
  3860. ops.len = len;
  3861. ops.datbuf = (uint8_t *)buf;
  3862. ops.mode = MTD_OPS_PLACE_OOB;
  3863. ret = nand_do_write_ops(mtd, to, &ops);
  3864. *retlen = ops.retlen;
  3865. return ret;
  3866. }
  3867. /**
  3868. * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  3869. * @mtd: MTD device structure
  3870. * @to: offset to write to
  3871. * @ops: oob operation description structure
  3872. *
  3873. * NAND write out-of-band.
  3874. */
  3875. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  3876. struct mtd_oob_ops *ops)
  3877. {
  3878. int chipnr, page, status, len;
  3879. struct nand_chip *chip = mtd_to_nand(mtd);
  3880. pr_debug("%s: to = 0x%08x, len = %i\n",
  3881. __func__, (unsigned int)to, (int)ops->ooblen);
  3882. len = mtd_oobavail(mtd, ops);
  3883. /* Do not allow write past end of page */
  3884. if ((ops->ooboffs + ops->ooblen) > len) {
  3885. pr_debug("%s: attempt to write past end of page\n",
  3886. __func__);
  3887. return -EINVAL;
  3888. }
  3889. chipnr = (int)(to >> chip->chip_shift);
  3890. /*
  3891. * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
  3892. * of my DiskOnChip 2000 test units) will clear the whole data page too
  3893. * if we don't do this. I have no clue why, but I seem to have 'fixed'
  3894. * it in the doc2000 driver in August 1999. dwmw2.
  3895. */
  3896. nand_reset(chip, chipnr);
  3897. chip->select_chip(mtd, chipnr);
  3898. /* Shift to get page */
  3899. page = (int)(to >> chip->page_shift);
  3900. /* Check, if it is write protected */
  3901. if (nand_check_wp(mtd)) {
  3902. chip->select_chip(mtd, -1);
  3903. return -EROFS;
  3904. }
  3905. /* Invalidate the page cache, if we write to the cached page */
  3906. if (page == chip->pagebuf)
  3907. chip->pagebuf = -1;
  3908. nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
  3909. if (ops->mode == MTD_OPS_RAW)
  3910. status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
  3911. else
  3912. status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
  3913. chip->select_chip(mtd, -1);
  3914. if (status)
  3915. return status;
  3916. ops->oobretlen = ops->ooblen;
  3917. return 0;
  3918. }
  3919. /**
  3920. * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
  3921. * @mtd: MTD device structure
  3922. * @to: offset to write to
  3923. * @ops: oob operation description structure
  3924. */
  3925. static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  3926. struct mtd_oob_ops *ops)
  3927. {
  3928. int ret = -ENOTSUPP;
  3929. ops->retlen = 0;
  3930. nand_get_device(mtd, FL_WRITING);
  3931. switch (ops->mode) {
  3932. case MTD_OPS_PLACE_OOB:
  3933. case MTD_OPS_AUTO_OOB:
  3934. case MTD_OPS_RAW:
  3935. break;
  3936. default:
  3937. goto out;
  3938. }
  3939. if (!ops->datbuf)
  3940. ret = nand_do_write_oob(mtd, to, ops);
  3941. else
  3942. ret = nand_do_write_ops(mtd, to, ops);
  3943. out:
  3944. nand_release_device(mtd);
  3945. return ret;
  3946. }
  3947. /**
  3948. * single_erase - [GENERIC] NAND standard block erase command function
  3949. * @mtd: MTD device structure
  3950. * @page: the page address of the block which will be erased
  3951. *
  3952. * Standard erase command for NAND chips. Returns NAND status.
  3953. */
  3954. static int single_erase(struct mtd_info *mtd, int page)
  3955. {
  3956. struct nand_chip *chip = mtd_to_nand(mtd);
  3957. unsigned int eraseblock;
  3958. /* Send commands to erase a block */
  3959. eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
  3960. return nand_erase_op(chip, eraseblock);
  3961. }
  3962. /**
  3963. * nand_erase - [MTD Interface] erase block(s)
  3964. * @mtd: MTD device structure
  3965. * @instr: erase instruction
  3966. *
  3967. * Erase one ore more blocks.
  3968. */
  3969. static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
  3970. {
  3971. return nand_erase_nand(mtd, instr, 0);
  3972. }
  3973. /**
  3974. * nand_erase_nand - [INTERN] erase block(s)
  3975. * @mtd: MTD device structure
  3976. * @instr: erase instruction
  3977. * @allowbbt: allow erasing the bbt area
  3978. *
  3979. * Erase one ore more blocks.
  3980. */
  3981. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  3982. int allowbbt)
  3983. {
  3984. int page, status, pages_per_block, ret, chipnr;
  3985. struct nand_chip *chip = mtd_to_nand(mtd);
  3986. loff_t len;
  3987. pr_debug("%s: start = 0x%012llx, len = %llu\n",
  3988. __func__, (unsigned long long)instr->addr,
  3989. (unsigned long long)instr->len);
  3990. if (check_offs_len(mtd, instr->addr, instr->len))
  3991. return -EINVAL;
  3992. /* Grab the lock and see if the device is available */
  3993. nand_get_device(mtd, FL_ERASING);
  3994. /* Shift to get first page */
  3995. page = (int)(instr->addr >> chip->page_shift);
  3996. chipnr = (int)(instr->addr >> chip->chip_shift);
  3997. /* Calculate pages in each block */
  3998. pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
  3999. /* Select the NAND device */
  4000. chip->select_chip(mtd, chipnr);
  4001. /* Check, if it is write protected */
  4002. if (nand_check_wp(mtd)) {
  4003. pr_debug("%s: device is write protected!\n",
  4004. __func__);
  4005. ret = -EIO;
  4006. goto erase_exit;
  4007. }
  4008. /* Loop through the pages */
  4009. len = instr->len;
  4010. while (len) {
  4011. /* Check if we have a bad block, we do not erase bad blocks! */
  4012. if (nand_block_checkbad(mtd, ((loff_t) page) <<
  4013. chip->page_shift, allowbbt)) {
  4014. pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
  4015. __func__, page);
  4016. ret = -EIO;
  4017. goto erase_exit;
  4018. }
  4019. /*
  4020. * Invalidate the page cache, if we erase the block which
  4021. * contains the current cached page.
  4022. */
  4023. if (page <= chip->pagebuf && chip->pagebuf <
  4024. (page + pages_per_block))
  4025. chip->pagebuf = -1;
  4026. status = chip->erase(mtd, page & chip->pagemask);
  4027. /* See if block erase succeeded */
  4028. if (status) {
  4029. pr_debug("%s: failed erase, page 0x%08x\n",
  4030. __func__, page);
  4031. ret = -EIO;
  4032. instr->fail_addr =
  4033. ((loff_t)page << chip->page_shift);
  4034. goto erase_exit;
  4035. }
  4036. /* Increment page address and decrement length */
  4037. len -= (1ULL << chip->phys_erase_shift);
  4038. page += pages_per_block;
  4039. /* Check, if we cross a chip boundary */
  4040. if (len && !(page & chip->pagemask)) {
  4041. chipnr++;
  4042. chip->select_chip(mtd, -1);
  4043. chip->select_chip(mtd, chipnr);
  4044. }
  4045. }
  4046. ret = 0;
  4047. erase_exit:
  4048. /* Deselect and wake up anyone waiting on the device */
  4049. chip->select_chip(mtd, -1);
  4050. nand_release_device(mtd);
  4051. /* Return more or less happy */
  4052. return ret;
  4053. }
  4054. /**
  4055. * nand_sync - [MTD Interface] sync
  4056. * @mtd: MTD device structure
  4057. *
  4058. * Sync is actually a wait for chip ready function.
  4059. */
  4060. static void nand_sync(struct mtd_info *mtd)
  4061. {
  4062. pr_debug("%s: called\n", __func__);
  4063. /* Grab the lock and see if the device is available */
  4064. nand_get_device(mtd, FL_SYNCING);
  4065. /* Release it and go back */
  4066. nand_release_device(mtd);
  4067. }
  4068. /**
  4069. * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  4070. * @mtd: MTD device structure
  4071. * @offs: offset relative to mtd start
  4072. */
  4073. static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
  4074. {
  4075. struct nand_chip *chip = mtd_to_nand(mtd);
  4076. int chipnr = (int)(offs >> chip->chip_shift);
  4077. int ret;
  4078. /* Select the NAND device */
  4079. nand_get_device(mtd, FL_READING);
  4080. chip->select_chip(mtd, chipnr);
  4081. ret = nand_block_checkbad(mtd, offs, 0);
  4082. chip->select_chip(mtd, -1);
  4083. nand_release_device(mtd);
  4084. return ret;
  4085. }
  4086. /**
  4087. * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  4088. * @mtd: MTD device structure
  4089. * @ofs: offset relative to mtd start
  4090. */
  4091. static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
  4092. {
  4093. int ret;
  4094. ret = nand_block_isbad(mtd, ofs);
  4095. if (ret) {
  4096. /* If it was bad already, return success and do nothing */
  4097. if (ret > 0)
  4098. return 0;
  4099. return ret;
  4100. }
  4101. return nand_block_markbad_lowlevel(mtd, ofs);
  4102. }
  4103. /**
  4104. * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
  4105. * @mtd: MTD device structure
  4106. * @ofs: offset relative to mtd start
  4107. * @len: length of mtd
  4108. */
  4109. static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
  4110. {
  4111. struct nand_chip *chip = mtd_to_nand(mtd);
  4112. u32 part_start_block;
  4113. u32 part_end_block;
  4114. u32 part_start_die;
  4115. u32 part_end_die;
  4116. /*
  4117. * max_bb_per_die and blocks_per_die used to determine
  4118. * the maximum bad block count.
  4119. */
  4120. if (!chip->max_bb_per_die || !chip->blocks_per_die)
  4121. return -ENOTSUPP;
  4122. /* Get the start and end of the partition in erase blocks. */
  4123. part_start_block = mtd_div_by_eb(ofs, mtd);
  4124. part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1;
  4125. /* Get the start and end LUNs of the partition. */
  4126. part_start_die = part_start_block / chip->blocks_per_die;
  4127. part_end_die = part_end_block / chip->blocks_per_die;
  4128. /*
  4129. * Look up the bad blocks per unit and multiply by the number of units
  4130. * that the partition spans.
  4131. */
  4132. return chip->max_bb_per_die * (part_end_die - part_start_die + 1);
  4133. }
  4134. /**
  4135. * nand_default_set_features- [REPLACEABLE] set NAND chip features
  4136. * @mtd: MTD device structure
  4137. * @chip: nand chip info structure
  4138. * @addr: feature address.
  4139. * @subfeature_param: the subfeature parameters, a four bytes array.
  4140. */
  4141. static int nand_default_set_features(struct mtd_info *mtd,
  4142. struct nand_chip *chip, int addr,
  4143. uint8_t *subfeature_param)
  4144. {
  4145. return nand_set_features_op(chip, addr, subfeature_param);
  4146. }
  4147. /**
  4148. * nand_default_get_features- [REPLACEABLE] get NAND chip features
  4149. * @mtd: MTD device structure
  4150. * @chip: nand chip info structure
  4151. * @addr: feature address.
  4152. * @subfeature_param: the subfeature parameters, a four bytes array.
  4153. */
  4154. static int nand_default_get_features(struct mtd_info *mtd,
  4155. struct nand_chip *chip, int addr,
  4156. uint8_t *subfeature_param)
  4157. {
  4158. return nand_get_features_op(chip, addr, subfeature_param);
  4159. }
  4160. /**
  4161. * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
  4162. * @mtd: MTD device structure
  4163. * @chip: nand chip info structure
  4164. * @addr: feature address.
  4165. * @subfeature_param: the subfeature parameters, a four bytes array.
  4166. *
  4167. * Should be used by NAND controller drivers that do not support the SET/GET
  4168. * FEATURES operations.
  4169. */
  4170. int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
  4171. int addr, u8 *subfeature_param)
  4172. {
  4173. return -ENOTSUPP;
  4174. }
  4175. EXPORT_SYMBOL(nand_get_set_features_notsupp);
  4176. /**
  4177. * nand_suspend - [MTD Interface] Suspend the NAND flash
  4178. * @mtd: MTD device structure
  4179. */
  4180. static int nand_suspend(struct mtd_info *mtd)
  4181. {
  4182. return nand_get_device(mtd, FL_PM_SUSPENDED);
  4183. }
  4184. /**
  4185. * nand_resume - [MTD Interface] Resume the NAND flash
  4186. * @mtd: MTD device structure
  4187. */
  4188. static void nand_resume(struct mtd_info *mtd)
  4189. {
  4190. struct nand_chip *chip = mtd_to_nand(mtd);
  4191. if (chip->state == FL_PM_SUSPENDED)
  4192. nand_release_device(mtd);
  4193. else
  4194. pr_err("%s called for a chip which is not in suspended state\n",
  4195. __func__);
  4196. }
  4197. /**
  4198. * nand_shutdown - [MTD Interface] Finish the current NAND operation and
  4199. * prevent further operations
  4200. * @mtd: MTD device structure
  4201. */
  4202. static void nand_shutdown(struct mtd_info *mtd)
  4203. {
  4204. nand_get_device(mtd, FL_PM_SUSPENDED);
  4205. }
  4206. /* Set default functions */
  4207. static void nand_set_defaults(struct nand_chip *chip)
  4208. {
  4209. unsigned int busw = chip->options & NAND_BUSWIDTH_16;
  4210. /* check for proper chip_delay setup, set 20us if not */
  4211. if (!chip->chip_delay)
  4212. chip->chip_delay = 20;
  4213. /* check, if a user supplied command function given */
  4214. if (!chip->cmdfunc && !chip->exec_op)
  4215. chip->cmdfunc = nand_command;
  4216. /* check, if a user supplied wait function given */
  4217. if (chip->waitfunc == NULL)
  4218. chip->waitfunc = nand_wait;
  4219. if (!chip->select_chip)
  4220. chip->select_chip = nand_select_chip;
  4221. /* set for ONFI nand */
  4222. if (!chip->set_features)
  4223. chip->set_features = nand_default_set_features;
  4224. if (!chip->get_features)
  4225. chip->get_features = nand_default_get_features;
  4226. /* If called twice, pointers that depend on busw may need to be reset */
  4227. if (!chip->read_byte || chip->read_byte == nand_read_byte)
  4228. chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
  4229. if (!chip->read_word)
  4230. chip->read_word = nand_read_word;
  4231. if (!chip->block_bad)
  4232. chip->block_bad = nand_block_bad;
  4233. if (!chip->block_markbad)
  4234. chip->block_markbad = nand_default_block_markbad;
  4235. if (!chip->write_buf || chip->write_buf == nand_write_buf)
  4236. chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
  4237. if (!chip->write_byte || chip->write_byte == nand_write_byte)
  4238. chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
  4239. if (!chip->read_buf || chip->read_buf == nand_read_buf)
  4240. chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
  4241. if (!chip->scan_bbt)
  4242. chip->scan_bbt = nand_default_bbt;
  4243. if (!chip->controller) {
  4244. chip->controller = &chip->hwcontrol;
  4245. nand_hw_control_init(chip->controller);
  4246. }
  4247. if (!chip->buf_align)
  4248. chip->buf_align = 1;
  4249. }
  4250. /* Sanitize ONFI strings so we can safely print them */
  4251. static void sanitize_string(uint8_t *s, size_t len)
  4252. {
  4253. ssize_t i;
  4254. /* Null terminate */
  4255. s[len - 1] = 0;
  4256. /* Remove non printable chars */
  4257. for (i = 0; i < len - 1; i++) {
  4258. if (s[i] < ' ' || s[i] > 127)
  4259. s[i] = '?';
  4260. }
  4261. /* Remove trailing spaces */
  4262. strim(s);
  4263. }
  4264. static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
  4265. {
  4266. int i;
  4267. while (len--) {
  4268. crc ^= *p++ << 8;
  4269. for (i = 0; i < 8; i++)
  4270. crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
  4271. }
  4272. return crc;
  4273. }
  4274. /* Parse the Extended Parameter Page. */
  4275. static int nand_flash_detect_ext_param_page(struct nand_chip *chip,
  4276. struct nand_onfi_params *p)
  4277. {
  4278. struct onfi_ext_param_page *ep;
  4279. struct onfi_ext_section *s;
  4280. struct onfi_ext_ecc_info *ecc;
  4281. uint8_t *cursor;
  4282. int ret;
  4283. int len;
  4284. int i;
  4285. len = le16_to_cpu(p->ext_param_page_length) * 16;
  4286. ep = kmalloc(len, GFP_KERNEL);
  4287. if (!ep)
  4288. return -ENOMEM;
  4289. /* Send our own NAND_CMD_PARAM. */
  4290. ret = nand_read_param_page_op(chip, 0, NULL, 0);
  4291. if (ret)
  4292. goto ext_out;
  4293. /* Use the Change Read Column command to skip the ONFI param pages. */
  4294. ret = nand_change_read_column_op(chip,
  4295. sizeof(*p) * p->num_of_param_pages,
  4296. ep, len, true);
  4297. if (ret)
  4298. goto ext_out;
  4299. ret = -EINVAL;
  4300. if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
  4301. != le16_to_cpu(ep->crc))) {
  4302. pr_debug("fail in the CRC.\n");
  4303. goto ext_out;
  4304. }
  4305. /*
  4306. * Check the signature.
  4307. * Do not strictly follow the ONFI spec, maybe changed in future.
  4308. */
  4309. if (strncmp(ep->sig, "EPPS", 4)) {
  4310. pr_debug("The signature is invalid.\n");
  4311. goto ext_out;
  4312. }
  4313. /* find the ECC section. */
  4314. cursor = (uint8_t *)(ep + 1);
  4315. for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
  4316. s = ep->sections + i;
  4317. if (s->type == ONFI_SECTION_TYPE_2)
  4318. break;
  4319. cursor += s->length * 16;
  4320. }
  4321. if (i == ONFI_EXT_SECTION_MAX) {
  4322. pr_debug("We can not find the ECC section.\n");
  4323. goto ext_out;
  4324. }
  4325. /* get the info we want. */
  4326. ecc = (struct onfi_ext_ecc_info *)cursor;
  4327. if (!ecc->codeword_size) {
  4328. pr_debug("Invalid codeword size\n");
  4329. goto ext_out;
  4330. }
  4331. chip->ecc_strength_ds = ecc->ecc_bits;
  4332. chip->ecc_step_ds = 1 << ecc->codeword_size;
  4333. ret = 0;
  4334. ext_out:
  4335. kfree(ep);
  4336. return ret;
  4337. }
  4338. /*
  4339. * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
  4340. */
  4341. static int nand_flash_detect_onfi(struct nand_chip *chip)
  4342. {
  4343. struct mtd_info *mtd = nand_to_mtd(chip);
  4344. struct nand_onfi_params *p;
  4345. char id[4];
  4346. int i, ret, val;
  4347. /* Try ONFI for unknown chip or LP */
  4348. ret = nand_readid_op(chip, 0x20, id, sizeof(id));
  4349. if (ret || strncmp(id, "ONFI", 4))
  4350. return 0;
  4351. /* ONFI chip: allocate a buffer to hold its parameter page */
  4352. p = kzalloc(sizeof(*p), GFP_KERNEL);
  4353. if (!p)
  4354. return -ENOMEM;
  4355. ret = nand_read_param_page_op(chip, 0, NULL, 0);
  4356. if (ret) {
  4357. ret = 0;
  4358. goto free_onfi_param_page;
  4359. }
  4360. for (i = 0; i < 3; i++) {
  4361. ret = nand_read_data_op(chip, p, sizeof(*p), true);
  4362. if (ret) {
  4363. ret = 0;
  4364. goto free_onfi_param_page;
  4365. }
  4366. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
  4367. le16_to_cpu(p->crc)) {
  4368. break;
  4369. }
  4370. }
  4371. if (i == 3) {
  4372. pr_err("Could not find valid ONFI parameter page; aborting\n");
  4373. goto free_onfi_param_page;
  4374. }
  4375. /* Check version */
  4376. val = le16_to_cpu(p->revision);
  4377. if (val & (1 << 5))
  4378. chip->parameters.onfi.version = 23;
  4379. else if (val & (1 << 4))
  4380. chip->parameters.onfi.version = 22;
  4381. else if (val & (1 << 3))
  4382. chip->parameters.onfi.version = 21;
  4383. else if (val & (1 << 2))
  4384. chip->parameters.onfi.version = 20;
  4385. else if (val & (1 << 1))
  4386. chip->parameters.onfi.version = 10;
  4387. if (!chip->parameters.onfi.version) {
  4388. pr_info("unsupported ONFI version: %d\n", val);
  4389. goto free_onfi_param_page;
  4390. } else {
  4391. ret = 1;
  4392. }
  4393. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  4394. sanitize_string(p->model, sizeof(p->model));
  4395. strncpy(chip->parameters.model, p->model,
  4396. sizeof(chip->parameters.model) - 1);
  4397. mtd->writesize = le32_to_cpu(p->byte_per_page);
  4398. /*
  4399. * pages_per_block and blocks_per_lun may not be a power-of-2 size
  4400. * (don't ask me who thought of this...). MTD assumes that these
  4401. * dimensions will be power-of-2, so just truncate the remaining area.
  4402. */
  4403. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  4404. mtd->erasesize *= mtd->writesize;
  4405. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  4406. /* See erasesize comment */
  4407. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  4408. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  4409. chip->bits_per_cell = p->bits_per_cell;
  4410. chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun);
  4411. chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun);
  4412. if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS)
  4413. chip->options |= NAND_BUSWIDTH_16;
  4414. if (p->ecc_bits != 0xff) {
  4415. chip->ecc_strength_ds = p->ecc_bits;
  4416. chip->ecc_step_ds = 512;
  4417. } else if (chip->parameters.onfi.version >= 21 &&
  4418. (le16_to_cpu(p->features) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
  4419. /*
  4420. * The nand_flash_detect_ext_param_page() uses the
  4421. * Change Read Column command which maybe not supported
  4422. * by the chip->cmdfunc. So try to update the chip->cmdfunc
  4423. * now. We do not replace user supplied command function.
  4424. */
  4425. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  4426. chip->cmdfunc = nand_command_lp;
  4427. /* The Extended Parameter Page is supported since ONFI 2.1. */
  4428. if (nand_flash_detect_ext_param_page(chip, p))
  4429. pr_warn("Failed to detect ONFI extended param page\n");
  4430. } else {
  4431. pr_warn("Could not retrieve ONFI ECC requirements\n");
  4432. }
  4433. /* Save some parameters from the parameter page for future use */
  4434. if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_SET_GET_FEATURES) {
  4435. chip->parameters.supports_set_get_features = true;
  4436. bitmap_set(chip->parameters.get_feature_list,
  4437. ONFI_FEATURE_ADDR_TIMING_MODE, 1);
  4438. bitmap_set(chip->parameters.set_feature_list,
  4439. ONFI_FEATURE_ADDR_TIMING_MODE, 1);
  4440. }
  4441. chip->parameters.onfi.tPROG = le16_to_cpu(p->t_prog);
  4442. chip->parameters.onfi.tBERS = le16_to_cpu(p->t_bers);
  4443. chip->parameters.onfi.tR = le16_to_cpu(p->t_r);
  4444. chip->parameters.onfi.tCCS = le16_to_cpu(p->t_ccs);
  4445. chip->parameters.onfi.async_timing_mode =
  4446. le16_to_cpu(p->async_timing_mode);
  4447. chip->parameters.onfi.vendor_revision =
  4448. le16_to_cpu(p->vendor_revision);
  4449. memcpy(chip->parameters.onfi.vendor, p->vendor,
  4450. sizeof(p->vendor));
  4451. free_onfi_param_page:
  4452. kfree(p);
  4453. return ret;
  4454. }
  4455. /*
  4456. * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
  4457. */
  4458. static int nand_flash_detect_jedec(struct nand_chip *chip)
  4459. {
  4460. struct mtd_info *mtd = nand_to_mtd(chip);
  4461. struct nand_jedec_params *p;
  4462. struct jedec_ecc_info *ecc;
  4463. int jedec_version = 0;
  4464. char id[5];
  4465. int i, val, ret;
  4466. /* Try JEDEC for unknown chip or LP */
  4467. ret = nand_readid_op(chip, 0x40, id, sizeof(id));
  4468. if (ret || strncmp(id, "JEDEC", sizeof(id)))
  4469. return 0;
  4470. /* JEDEC chip: allocate a buffer to hold its parameter page */
  4471. p = kzalloc(sizeof(*p), GFP_KERNEL);
  4472. if (!p)
  4473. return -ENOMEM;
  4474. ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
  4475. if (ret) {
  4476. ret = 0;
  4477. goto free_jedec_param_page;
  4478. }
  4479. for (i = 0; i < 3; i++) {
  4480. ret = nand_read_data_op(chip, p, sizeof(*p), true);
  4481. if (ret) {
  4482. ret = 0;
  4483. goto free_jedec_param_page;
  4484. }
  4485. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
  4486. le16_to_cpu(p->crc))
  4487. break;
  4488. }
  4489. if (i == 3) {
  4490. pr_err("Could not find valid JEDEC parameter page; aborting\n");
  4491. goto free_jedec_param_page;
  4492. }
  4493. /* Check version */
  4494. val = le16_to_cpu(p->revision);
  4495. if (val & (1 << 2))
  4496. jedec_version = 10;
  4497. else if (val & (1 << 1))
  4498. jedec_version = 1; /* vendor specific version */
  4499. if (!jedec_version) {
  4500. pr_info("unsupported JEDEC version: %d\n", val);
  4501. goto free_jedec_param_page;
  4502. }
  4503. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  4504. sanitize_string(p->model, sizeof(p->model));
  4505. strncpy(chip->parameters.model, p->model,
  4506. sizeof(chip->parameters.model) - 1);
  4507. mtd->writesize = le32_to_cpu(p->byte_per_page);
  4508. /* Please reference to the comment for nand_flash_detect_onfi. */
  4509. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  4510. mtd->erasesize *= mtd->writesize;
  4511. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  4512. /* Please reference to the comment for nand_flash_detect_onfi. */
  4513. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  4514. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  4515. chip->bits_per_cell = p->bits_per_cell;
  4516. if (le16_to_cpu(p->features) & JEDEC_FEATURE_16_BIT_BUS)
  4517. chip->options |= NAND_BUSWIDTH_16;
  4518. /* ECC info */
  4519. ecc = &p->ecc_info[0];
  4520. if (ecc->codeword_size >= 9) {
  4521. chip->ecc_strength_ds = ecc->ecc_bits;
  4522. chip->ecc_step_ds = 1 << ecc->codeword_size;
  4523. } else {
  4524. pr_warn("Invalid codeword size\n");
  4525. }
  4526. free_jedec_param_page:
  4527. kfree(p);
  4528. return ret;
  4529. }
  4530. /*
  4531. * nand_id_has_period - Check if an ID string has a given wraparound period
  4532. * @id_data: the ID string
  4533. * @arrlen: the length of the @id_data array
  4534. * @period: the period of repitition
  4535. *
  4536. * Check if an ID string is repeated within a given sequence of bytes at
  4537. * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
  4538. * period of 3). This is a helper function for nand_id_len(). Returns non-zero
  4539. * if the repetition has a period of @period; otherwise, returns zero.
  4540. */
  4541. static int nand_id_has_period(u8 *id_data, int arrlen, int period)
  4542. {
  4543. int i, j;
  4544. for (i = 0; i < period; i++)
  4545. for (j = i + period; j < arrlen; j += period)
  4546. if (id_data[i] != id_data[j])
  4547. return 0;
  4548. return 1;
  4549. }
  4550. /*
  4551. * nand_id_len - Get the length of an ID string returned by CMD_READID
  4552. * @id_data: the ID string
  4553. * @arrlen: the length of the @id_data array
  4554. * Returns the length of the ID string, according to known wraparound/trailing
  4555. * zero patterns. If no pattern exists, returns the length of the array.
  4556. */
  4557. static int nand_id_len(u8 *id_data, int arrlen)
  4558. {
  4559. int last_nonzero, period;
  4560. /* Find last non-zero byte */
  4561. for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
  4562. if (id_data[last_nonzero])
  4563. break;
  4564. /* All zeros */
  4565. if (last_nonzero < 0)
  4566. return 0;
  4567. /* Calculate wraparound period */
  4568. for (period = 1; period < arrlen; period++)
  4569. if (nand_id_has_period(id_data, arrlen, period))
  4570. break;
  4571. /* There's a repeated pattern */
  4572. if (period < arrlen)
  4573. return period;
  4574. /* There are trailing zeros */
  4575. if (last_nonzero < arrlen - 1)
  4576. return last_nonzero + 1;
  4577. /* No pattern detected */
  4578. return arrlen;
  4579. }
  4580. /* Extract the bits of per cell from the 3rd byte of the extended ID */
  4581. static int nand_get_bits_per_cell(u8 cellinfo)
  4582. {
  4583. int bits;
  4584. bits = cellinfo & NAND_CI_CELLTYPE_MSK;
  4585. bits >>= NAND_CI_CELLTYPE_SHIFT;
  4586. return bits + 1;
  4587. }
  4588. /*
  4589. * Many new NAND share similar device ID codes, which represent the size of the
  4590. * chip. The rest of the parameters must be decoded according to generic or
  4591. * manufacturer-specific "extended ID" decoding patterns.
  4592. */
  4593. void nand_decode_ext_id(struct nand_chip *chip)
  4594. {
  4595. struct mtd_info *mtd = nand_to_mtd(chip);
  4596. int extid;
  4597. u8 *id_data = chip->id.data;
  4598. /* The 3rd id byte holds MLC / multichip data */
  4599. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  4600. /* The 4th id byte is the important one */
  4601. extid = id_data[3];
  4602. /* Calc pagesize */
  4603. mtd->writesize = 1024 << (extid & 0x03);
  4604. extid >>= 2;
  4605. /* Calc oobsize */
  4606. mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
  4607. extid >>= 2;
  4608. /* Calc blocksize. Blocksize is multiples of 64KiB */
  4609. mtd->erasesize = (64 * 1024) << (extid & 0x03);
  4610. extid >>= 2;
  4611. /* Get buswidth information */
  4612. if (extid & 0x1)
  4613. chip->options |= NAND_BUSWIDTH_16;
  4614. }
  4615. EXPORT_SYMBOL_GPL(nand_decode_ext_id);
  4616. /*
  4617. * Old devices have chip data hardcoded in the device ID table. nand_decode_id
  4618. * decodes a matching ID table entry and assigns the MTD size parameters for
  4619. * the chip.
  4620. */
  4621. static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
  4622. {
  4623. struct mtd_info *mtd = nand_to_mtd(chip);
  4624. mtd->erasesize = type->erasesize;
  4625. mtd->writesize = type->pagesize;
  4626. mtd->oobsize = mtd->writesize / 32;
  4627. /* All legacy ID NAND are small-page, SLC */
  4628. chip->bits_per_cell = 1;
  4629. }
  4630. /*
  4631. * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  4632. * heuristic patterns using various detected parameters (e.g., manufacturer,
  4633. * page size, cell-type information).
  4634. */
  4635. static void nand_decode_bbm_options(struct nand_chip *chip)
  4636. {
  4637. struct mtd_info *mtd = nand_to_mtd(chip);
  4638. /* Set the bad block position */
  4639. if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
  4640. chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
  4641. else
  4642. chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
  4643. }
  4644. static inline bool is_full_id_nand(struct nand_flash_dev *type)
  4645. {
  4646. return type->id_len;
  4647. }
  4648. static bool find_full_id_nand(struct nand_chip *chip,
  4649. struct nand_flash_dev *type)
  4650. {
  4651. struct mtd_info *mtd = nand_to_mtd(chip);
  4652. u8 *id_data = chip->id.data;
  4653. if (!strncmp(type->id, id_data, type->id_len)) {
  4654. mtd->writesize = type->pagesize;
  4655. mtd->erasesize = type->erasesize;
  4656. mtd->oobsize = type->oobsize;
  4657. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  4658. chip->chipsize = (uint64_t)type->chipsize << 20;
  4659. chip->options |= type->options;
  4660. chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
  4661. chip->ecc_step_ds = NAND_ECC_STEP(type);
  4662. chip->onfi_timing_mode_default =
  4663. type->onfi_timing_mode_default;
  4664. strncpy(chip->parameters.model, type->name,
  4665. sizeof(chip->parameters.model) - 1);
  4666. return true;
  4667. }
  4668. return false;
  4669. }
  4670. /*
  4671. * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
  4672. * compliant and does not have a full-id or legacy-id entry in the nand_ids
  4673. * table.
  4674. */
  4675. static void nand_manufacturer_detect(struct nand_chip *chip)
  4676. {
  4677. /*
  4678. * Try manufacturer detection if available and use
  4679. * nand_decode_ext_id() otherwise.
  4680. */
  4681. if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
  4682. chip->manufacturer.desc->ops->detect) {
  4683. /* The 3rd id byte holds MLC / multichip data */
  4684. chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
  4685. chip->manufacturer.desc->ops->detect(chip);
  4686. } else {
  4687. nand_decode_ext_id(chip);
  4688. }
  4689. }
  4690. /*
  4691. * Manufacturer initialization. This function is called for all NANDs including
  4692. * ONFI and JEDEC compliant ones.
  4693. * Manufacturer drivers should put all their specific initialization code in
  4694. * their ->init() hook.
  4695. */
  4696. static int nand_manufacturer_init(struct nand_chip *chip)
  4697. {
  4698. if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
  4699. !chip->manufacturer.desc->ops->init)
  4700. return 0;
  4701. return chip->manufacturer.desc->ops->init(chip);
  4702. }
  4703. /*
  4704. * Manufacturer cleanup. This function is called for all NANDs including
  4705. * ONFI and JEDEC compliant ones.
  4706. * Manufacturer drivers should put all their specific cleanup code in their
  4707. * ->cleanup() hook.
  4708. */
  4709. static void nand_manufacturer_cleanup(struct nand_chip *chip)
  4710. {
  4711. /* Release manufacturer private data */
  4712. if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
  4713. chip->manufacturer.desc->ops->cleanup)
  4714. chip->manufacturer.desc->ops->cleanup(chip);
  4715. }
  4716. /*
  4717. * Get the flash and manufacturer id and lookup if the type is supported.
  4718. */
  4719. static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
  4720. {
  4721. const struct nand_manufacturer *manufacturer;
  4722. struct mtd_info *mtd = nand_to_mtd(chip);
  4723. int busw, ret;
  4724. u8 *id_data = chip->id.data;
  4725. u8 maf_id, dev_id;
  4726. /*
  4727. * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
  4728. * after power-up.
  4729. */
  4730. ret = nand_reset(chip, 0);
  4731. if (ret)
  4732. return ret;
  4733. /* Select the device */
  4734. chip->select_chip(mtd, 0);
  4735. /* Send the command for reading device ID */
  4736. ret = nand_readid_op(chip, 0, id_data, 2);
  4737. if (ret)
  4738. return ret;
  4739. /* Read manufacturer and device IDs */
  4740. maf_id = id_data[0];
  4741. dev_id = id_data[1];
  4742. /*
  4743. * Try again to make sure, as some systems the bus-hold or other
  4744. * interface concerns can cause random data which looks like a
  4745. * possibly credible NAND flash to appear. If the two results do
  4746. * not match, ignore the device completely.
  4747. */
  4748. /* Read entire ID string */
  4749. ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
  4750. if (ret)
  4751. return ret;
  4752. if (id_data[0] != maf_id || id_data[1] != dev_id) {
  4753. pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
  4754. maf_id, dev_id, id_data[0], id_data[1]);
  4755. return -ENODEV;
  4756. }
  4757. chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
  4758. /* Try to identify manufacturer */
  4759. manufacturer = nand_get_manufacturer(maf_id);
  4760. chip->manufacturer.desc = manufacturer;
  4761. if (!type)
  4762. type = nand_flash_ids;
  4763. /*
  4764. * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
  4765. * override it.
  4766. * This is required to make sure initial NAND bus width set by the
  4767. * NAND controller driver is coherent with the real NAND bus width
  4768. * (extracted by auto-detection code).
  4769. */
  4770. busw = chip->options & NAND_BUSWIDTH_16;
  4771. /*
  4772. * The flag is only set (never cleared), reset it to its default value
  4773. * before starting auto-detection.
  4774. */
  4775. chip->options &= ~NAND_BUSWIDTH_16;
  4776. for (; type->name != NULL; type++) {
  4777. if (is_full_id_nand(type)) {
  4778. if (find_full_id_nand(chip, type))
  4779. goto ident_done;
  4780. } else if (dev_id == type->dev_id) {
  4781. break;
  4782. }
  4783. }
  4784. chip->parameters.onfi.version = 0;
  4785. if (!type->name || !type->pagesize) {
  4786. /* Check if the chip is ONFI compliant */
  4787. ret = nand_flash_detect_onfi(chip);
  4788. if (ret < 0)
  4789. return ret;
  4790. else if (ret)
  4791. goto ident_done;
  4792. /* Check if the chip is JEDEC compliant */
  4793. ret = nand_flash_detect_jedec(chip);
  4794. if (ret < 0)
  4795. return ret;
  4796. else if (ret)
  4797. goto ident_done;
  4798. }
  4799. if (!type->name)
  4800. return -ENODEV;
  4801. strncpy(chip->parameters.model, type->name,
  4802. sizeof(chip->parameters.model) - 1);
  4803. chip->chipsize = (uint64_t)type->chipsize << 20;
  4804. if (!type->pagesize)
  4805. nand_manufacturer_detect(chip);
  4806. else
  4807. nand_decode_id(chip, type);
  4808. /* Get chip options */
  4809. chip->options |= type->options;
  4810. ident_done:
  4811. if (!mtd->name)
  4812. mtd->name = chip->parameters.model;
  4813. if (chip->options & NAND_BUSWIDTH_AUTO) {
  4814. WARN_ON(busw & NAND_BUSWIDTH_16);
  4815. nand_set_defaults(chip);
  4816. } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
  4817. /*
  4818. * Check, if buswidth is correct. Hardware drivers should set
  4819. * chip correct!
  4820. */
  4821. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  4822. maf_id, dev_id);
  4823. pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
  4824. mtd->name);
  4825. pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
  4826. (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
  4827. return -EINVAL;
  4828. }
  4829. nand_decode_bbm_options(chip);
  4830. /* Calculate the address shift from the page size */
  4831. chip->page_shift = ffs(mtd->writesize) - 1;
  4832. /* Convert chipsize to number of pages per chip -1 */
  4833. chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
  4834. chip->bbt_erase_shift = chip->phys_erase_shift =
  4835. ffs(mtd->erasesize) - 1;
  4836. if (chip->chipsize & 0xffffffff)
  4837. chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
  4838. else {
  4839. chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
  4840. chip->chip_shift += 32 - 1;
  4841. }
  4842. if (chip->chip_shift - chip->page_shift > 16)
  4843. chip->options |= NAND_ROW_ADDR_3;
  4844. chip->badblockbits = 8;
  4845. chip->erase = single_erase;
  4846. /* Do not replace user supplied command function! */
  4847. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  4848. chip->cmdfunc = nand_command_lp;
  4849. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  4850. maf_id, dev_id);
  4851. pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
  4852. chip->parameters.model);
  4853. pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
  4854. (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
  4855. mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
  4856. return 0;
  4857. }
  4858. static const char * const nand_ecc_modes[] = {
  4859. [NAND_ECC_NONE] = "none",
  4860. [NAND_ECC_SOFT] = "soft",
  4861. [NAND_ECC_HW] = "hw",
  4862. [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
  4863. [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
  4864. [NAND_ECC_ON_DIE] = "on-die",
  4865. };
  4866. static int of_get_nand_ecc_mode(struct device_node *np)
  4867. {
  4868. const char *pm;
  4869. int err, i;
  4870. err = of_property_read_string(np, "nand-ecc-mode", &pm);
  4871. if (err < 0)
  4872. return err;
  4873. for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
  4874. if (!strcasecmp(pm, nand_ecc_modes[i]))
  4875. return i;
  4876. /*
  4877. * For backward compatibility we support few obsoleted values that don't
  4878. * have their mappings into nand_ecc_modes_t anymore (they were merged
  4879. * with other enums).
  4880. */
  4881. if (!strcasecmp(pm, "soft_bch"))
  4882. return NAND_ECC_SOFT;
  4883. return -ENODEV;
  4884. }
  4885. static const char * const nand_ecc_algos[] = {
  4886. [NAND_ECC_HAMMING] = "hamming",
  4887. [NAND_ECC_BCH] = "bch",
  4888. };
  4889. static int of_get_nand_ecc_algo(struct device_node *np)
  4890. {
  4891. const char *pm;
  4892. int err, i;
  4893. err = of_property_read_string(np, "nand-ecc-algo", &pm);
  4894. if (!err) {
  4895. for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
  4896. if (!strcasecmp(pm, nand_ecc_algos[i]))
  4897. return i;
  4898. return -ENODEV;
  4899. }
  4900. /*
  4901. * For backward compatibility we also read "nand-ecc-mode" checking
  4902. * for some obsoleted values that were specifying ECC algorithm.
  4903. */
  4904. err = of_property_read_string(np, "nand-ecc-mode", &pm);
  4905. if (err < 0)
  4906. return err;
  4907. if (!strcasecmp(pm, "soft"))
  4908. return NAND_ECC_HAMMING;
  4909. else if (!strcasecmp(pm, "soft_bch"))
  4910. return NAND_ECC_BCH;
  4911. return -ENODEV;
  4912. }
  4913. static int of_get_nand_ecc_step_size(struct device_node *np)
  4914. {
  4915. int ret;
  4916. u32 val;
  4917. ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
  4918. return ret ? ret : val;
  4919. }
  4920. static int of_get_nand_ecc_strength(struct device_node *np)
  4921. {
  4922. int ret;
  4923. u32 val;
  4924. ret = of_property_read_u32(np, "nand-ecc-strength", &val);
  4925. return ret ? ret : val;
  4926. }
  4927. static int of_get_nand_bus_width(struct device_node *np)
  4928. {
  4929. u32 val;
  4930. if (of_property_read_u32(np, "nand-bus-width", &val))
  4931. return 8;
  4932. switch (val) {
  4933. case 8:
  4934. case 16:
  4935. return val;
  4936. default:
  4937. return -EIO;
  4938. }
  4939. }
  4940. static bool of_get_nand_on_flash_bbt(struct device_node *np)
  4941. {
  4942. return of_property_read_bool(np, "nand-on-flash-bbt");
  4943. }
  4944. static int nand_dt_init(struct nand_chip *chip)
  4945. {
  4946. struct device_node *dn = nand_get_flash_node(chip);
  4947. int ecc_mode, ecc_algo, ecc_strength, ecc_step;
  4948. if (!dn)
  4949. return 0;
  4950. if (of_get_nand_bus_width(dn) == 16)
  4951. chip->options |= NAND_BUSWIDTH_16;
  4952. if (of_get_nand_on_flash_bbt(dn))
  4953. chip->bbt_options |= NAND_BBT_USE_FLASH;
  4954. ecc_mode = of_get_nand_ecc_mode(dn);
  4955. ecc_algo = of_get_nand_ecc_algo(dn);
  4956. ecc_strength = of_get_nand_ecc_strength(dn);
  4957. ecc_step = of_get_nand_ecc_step_size(dn);
  4958. if (ecc_mode >= 0)
  4959. chip->ecc.mode = ecc_mode;
  4960. if (ecc_algo >= 0)
  4961. chip->ecc.algo = ecc_algo;
  4962. if (ecc_strength >= 0)
  4963. chip->ecc.strength = ecc_strength;
  4964. if (ecc_step > 0)
  4965. chip->ecc.size = ecc_step;
  4966. if (of_property_read_bool(dn, "nand-ecc-maximize"))
  4967. chip->ecc.options |= NAND_ECC_MAXIMIZE;
  4968. return 0;
  4969. }
  4970. /**
  4971. * nand_scan_ident - [NAND Interface] Scan for the NAND device
  4972. * @mtd: MTD device structure
  4973. * @maxchips: number of chips to scan for
  4974. * @table: alternative NAND ID table
  4975. *
  4976. * This is the first phase of the normal nand_scan() function. It reads the
  4977. * flash ID and sets up MTD fields accordingly.
  4978. *
  4979. */
  4980. int nand_scan_ident(struct mtd_info *mtd, int maxchips,
  4981. struct nand_flash_dev *table)
  4982. {
  4983. int i, nand_maf_id, nand_dev_id;
  4984. struct nand_chip *chip = mtd_to_nand(mtd);
  4985. int ret;
  4986. /* Enforce the right timings for reset/detection */
  4987. onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
  4988. ret = nand_dt_init(chip);
  4989. if (ret)
  4990. return ret;
  4991. if (!mtd->name && mtd->dev.parent)
  4992. mtd->name = dev_name(mtd->dev.parent);
  4993. /*
  4994. * ->cmdfunc() is legacy and will only be used if ->exec_op() is not
  4995. * populated.
  4996. */
  4997. if (!chip->exec_op) {
  4998. /*
  4999. * Default functions assigned for ->cmdfunc() and
  5000. * ->select_chip() both expect ->cmd_ctrl() to be populated.
  5001. */
  5002. if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
  5003. pr_err("->cmd_ctrl() should be provided\n");
  5004. return -EINVAL;
  5005. }
  5006. }
  5007. /* Set the default functions */
  5008. nand_set_defaults(chip);
  5009. /* Read the flash type */
  5010. ret = nand_detect(chip, table);
  5011. if (ret) {
  5012. if (!(chip->options & NAND_SCAN_SILENT_NODEV))
  5013. pr_warn("No NAND device found\n");
  5014. chip->select_chip(mtd, -1);
  5015. return ret;
  5016. }
  5017. nand_maf_id = chip->id.data[0];
  5018. nand_dev_id = chip->id.data[1];
  5019. chip->select_chip(mtd, -1);
  5020. /* Check for a chip array */
  5021. for (i = 1; i < maxchips; i++) {
  5022. u8 id[2];
  5023. /* See comment in nand_get_flash_type for reset */
  5024. nand_reset(chip, i);
  5025. chip->select_chip(mtd, i);
  5026. /* Send the command for reading device ID */
  5027. nand_readid_op(chip, 0, id, sizeof(id));
  5028. /* Read manufacturer and device IDs */
  5029. if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
  5030. chip->select_chip(mtd, -1);
  5031. break;
  5032. }
  5033. chip->select_chip(mtd, -1);
  5034. }
  5035. if (i > 1)
  5036. pr_info("%d chips detected\n", i);
  5037. /* Store the number of chips and calc total size for mtd */
  5038. chip->numchips = i;
  5039. mtd->size = i * chip->chipsize;
  5040. return 0;
  5041. }
  5042. EXPORT_SYMBOL(nand_scan_ident);
  5043. static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
  5044. {
  5045. struct nand_chip *chip = mtd_to_nand(mtd);
  5046. struct nand_ecc_ctrl *ecc = &chip->ecc;
  5047. if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
  5048. return -EINVAL;
  5049. switch (ecc->algo) {
  5050. case NAND_ECC_HAMMING:
  5051. ecc->calculate = nand_calculate_ecc;
  5052. ecc->correct = nand_correct_data;
  5053. ecc->read_page = nand_read_page_swecc;
  5054. ecc->read_subpage = nand_read_subpage;
  5055. ecc->write_page = nand_write_page_swecc;
  5056. ecc->read_page_raw = nand_read_page_raw;
  5057. ecc->write_page_raw = nand_write_page_raw;
  5058. ecc->read_oob = nand_read_oob_std;
  5059. ecc->write_oob = nand_write_oob_std;
  5060. if (!ecc->size)
  5061. ecc->size = 256;
  5062. ecc->bytes = 3;
  5063. ecc->strength = 1;
  5064. return 0;
  5065. case NAND_ECC_BCH:
  5066. if (!mtd_nand_has_bch()) {
  5067. WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
  5068. return -EINVAL;
  5069. }
  5070. ecc->calculate = nand_bch_calculate_ecc;
  5071. ecc->correct = nand_bch_correct_data;
  5072. ecc->read_page = nand_read_page_swecc;
  5073. ecc->read_subpage = nand_read_subpage;
  5074. ecc->write_page = nand_write_page_swecc;
  5075. ecc->read_page_raw = nand_read_page_raw;
  5076. ecc->write_page_raw = nand_write_page_raw;
  5077. ecc->read_oob = nand_read_oob_std;
  5078. ecc->write_oob = nand_write_oob_std;
  5079. /*
  5080. * Board driver should supply ecc.size and ecc.strength
  5081. * values to select how many bits are correctable.
  5082. * Otherwise, default to 4 bits for large page devices.
  5083. */
  5084. if (!ecc->size && (mtd->oobsize >= 64)) {
  5085. ecc->size = 512;
  5086. ecc->strength = 4;
  5087. }
  5088. /*
  5089. * if no ecc placement scheme was provided pickup the default
  5090. * large page one.
  5091. */
  5092. if (!mtd->ooblayout) {
  5093. /* handle large page devices only */
  5094. if (mtd->oobsize < 64) {
  5095. WARN(1, "OOB layout is required when using software BCH on small pages\n");
  5096. return -EINVAL;
  5097. }
  5098. mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
  5099. }
  5100. /*
  5101. * We can only maximize ECC config when the default layout is
  5102. * used, otherwise we don't know how many bytes can really be
  5103. * used.
  5104. */
  5105. if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
  5106. ecc->options & NAND_ECC_MAXIMIZE) {
  5107. int steps, bytes;
  5108. /* Always prefer 1k blocks over 512bytes ones */
  5109. ecc->size = 1024;
  5110. steps = mtd->writesize / ecc->size;
  5111. /* Reserve 2 bytes for the BBM */
  5112. bytes = (mtd->oobsize - 2) / steps;
  5113. ecc->strength = bytes * 8 / fls(8 * ecc->size);
  5114. }
  5115. /* See nand_bch_init() for details. */
  5116. ecc->bytes = 0;
  5117. ecc->priv = nand_bch_init(mtd);
  5118. if (!ecc->priv) {
  5119. WARN(1, "BCH ECC initialization failed!\n");
  5120. return -EINVAL;
  5121. }
  5122. return 0;
  5123. default:
  5124. WARN(1, "Unsupported ECC algorithm!\n");
  5125. return -EINVAL;
  5126. }
  5127. }
  5128. /**
  5129. * nand_check_ecc_caps - check the sanity of preset ECC settings
  5130. * @chip: nand chip info structure
  5131. * @caps: ECC caps info structure
  5132. * @oobavail: OOB size that the ECC engine can use
  5133. *
  5134. * When ECC step size and strength are already set, check if they are supported
  5135. * by the controller and the calculated ECC bytes fit within the chip's OOB.
  5136. * On success, the calculated ECC bytes is set.
  5137. */
  5138. int nand_check_ecc_caps(struct nand_chip *chip,
  5139. const struct nand_ecc_caps *caps, int oobavail)
  5140. {
  5141. struct mtd_info *mtd = nand_to_mtd(chip);
  5142. const struct nand_ecc_step_info *stepinfo;
  5143. int preset_step = chip->ecc.size;
  5144. int preset_strength = chip->ecc.strength;
  5145. int nsteps, ecc_bytes;
  5146. int i, j;
  5147. if (WARN_ON(oobavail < 0))
  5148. return -EINVAL;
  5149. if (!preset_step || !preset_strength)
  5150. return -ENODATA;
  5151. nsteps = mtd->writesize / preset_step;
  5152. for (i = 0; i < caps->nstepinfos; i++) {
  5153. stepinfo = &caps->stepinfos[i];
  5154. if (stepinfo->stepsize != preset_step)
  5155. continue;
  5156. for (j = 0; j < stepinfo->nstrengths; j++) {
  5157. if (stepinfo->strengths[j] != preset_strength)
  5158. continue;
  5159. ecc_bytes = caps->calc_ecc_bytes(preset_step,
  5160. preset_strength);
  5161. if (WARN_ON_ONCE(ecc_bytes < 0))
  5162. return ecc_bytes;
  5163. if (ecc_bytes * nsteps > oobavail) {
  5164. pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
  5165. preset_step, preset_strength);
  5166. return -ENOSPC;
  5167. }
  5168. chip->ecc.bytes = ecc_bytes;
  5169. return 0;
  5170. }
  5171. }
  5172. pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
  5173. preset_step, preset_strength);
  5174. return -ENOTSUPP;
  5175. }
  5176. EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
  5177. /**
  5178. * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
  5179. * @chip: nand chip info structure
  5180. * @caps: ECC engine caps info structure
  5181. * @oobavail: OOB size that the ECC engine can use
  5182. *
  5183. * If a chip's ECC requirement is provided, try to meet it with the least
  5184. * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
  5185. * On success, the chosen ECC settings are set.
  5186. */
  5187. int nand_match_ecc_req(struct nand_chip *chip,
  5188. const struct nand_ecc_caps *caps, int oobavail)
  5189. {
  5190. struct mtd_info *mtd = nand_to_mtd(chip);
  5191. const struct nand_ecc_step_info *stepinfo;
  5192. int req_step = chip->ecc_step_ds;
  5193. int req_strength = chip->ecc_strength_ds;
  5194. int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
  5195. int best_step, best_strength, best_ecc_bytes;
  5196. int best_ecc_bytes_total = INT_MAX;
  5197. int i, j;
  5198. if (WARN_ON(oobavail < 0))
  5199. return -EINVAL;
  5200. /* No information provided by the NAND chip */
  5201. if (!req_step || !req_strength)
  5202. return -ENOTSUPP;
  5203. /* number of correctable bits the chip requires in a page */
  5204. req_corr = mtd->writesize / req_step * req_strength;
  5205. for (i = 0; i < caps->nstepinfos; i++) {
  5206. stepinfo = &caps->stepinfos[i];
  5207. step_size = stepinfo->stepsize;
  5208. for (j = 0; j < stepinfo->nstrengths; j++) {
  5209. strength = stepinfo->strengths[j];
  5210. /*
  5211. * If both step size and strength are smaller than the
  5212. * chip's requirement, it is not easy to compare the
  5213. * resulted reliability.
  5214. */
  5215. if (step_size < req_step && strength < req_strength)
  5216. continue;
  5217. if (mtd->writesize % step_size)
  5218. continue;
  5219. nsteps = mtd->writesize / step_size;
  5220. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  5221. if (WARN_ON_ONCE(ecc_bytes < 0))
  5222. continue;
  5223. ecc_bytes_total = ecc_bytes * nsteps;
  5224. if (ecc_bytes_total > oobavail ||
  5225. strength * nsteps < req_corr)
  5226. continue;
  5227. /*
  5228. * We assume the best is to meet the chip's requrement
  5229. * with the least number of ECC bytes.
  5230. */
  5231. if (ecc_bytes_total < best_ecc_bytes_total) {
  5232. best_ecc_bytes_total = ecc_bytes_total;
  5233. best_step = step_size;
  5234. best_strength = strength;
  5235. best_ecc_bytes = ecc_bytes;
  5236. }
  5237. }
  5238. }
  5239. if (best_ecc_bytes_total == INT_MAX)
  5240. return -ENOTSUPP;
  5241. chip->ecc.size = best_step;
  5242. chip->ecc.strength = best_strength;
  5243. chip->ecc.bytes = best_ecc_bytes;
  5244. return 0;
  5245. }
  5246. EXPORT_SYMBOL_GPL(nand_match_ecc_req);
  5247. /**
  5248. * nand_maximize_ecc - choose the max ECC strength available
  5249. * @chip: nand chip info structure
  5250. * @caps: ECC engine caps info structure
  5251. * @oobavail: OOB size that the ECC engine can use
  5252. *
  5253. * Choose the max ECC strength that is supported on the controller, and can fit
  5254. * within the chip's OOB. On success, the chosen ECC settings are set.
  5255. */
  5256. int nand_maximize_ecc(struct nand_chip *chip,
  5257. const struct nand_ecc_caps *caps, int oobavail)
  5258. {
  5259. struct mtd_info *mtd = nand_to_mtd(chip);
  5260. const struct nand_ecc_step_info *stepinfo;
  5261. int step_size, strength, nsteps, ecc_bytes, corr;
  5262. int best_corr = 0;
  5263. int best_step = 0;
  5264. int best_strength, best_ecc_bytes;
  5265. int i, j;
  5266. if (WARN_ON(oobavail < 0))
  5267. return -EINVAL;
  5268. for (i = 0; i < caps->nstepinfos; i++) {
  5269. stepinfo = &caps->stepinfos[i];
  5270. step_size = stepinfo->stepsize;
  5271. /* If chip->ecc.size is already set, respect it */
  5272. if (chip->ecc.size && step_size != chip->ecc.size)
  5273. continue;
  5274. for (j = 0; j < stepinfo->nstrengths; j++) {
  5275. strength = stepinfo->strengths[j];
  5276. if (mtd->writesize % step_size)
  5277. continue;
  5278. nsteps = mtd->writesize / step_size;
  5279. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  5280. if (WARN_ON_ONCE(ecc_bytes < 0))
  5281. continue;
  5282. if (ecc_bytes * nsteps > oobavail)
  5283. continue;
  5284. corr = strength * nsteps;
  5285. /*
  5286. * If the number of correctable bits is the same,
  5287. * bigger step_size has more reliability.
  5288. */
  5289. if (corr > best_corr ||
  5290. (corr == best_corr && step_size > best_step)) {
  5291. best_corr = corr;
  5292. best_step = step_size;
  5293. best_strength = strength;
  5294. best_ecc_bytes = ecc_bytes;
  5295. }
  5296. }
  5297. }
  5298. if (!best_corr)
  5299. return -ENOTSUPP;
  5300. chip->ecc.size = best_step;
  5301. chip->ecc.strength = best_strength;
  5302. chip->ecc.bytes = best_ecc_bytes;
  5303. return 0;
  5304. }
  5305. EXPORT_SYMBOL_GPL(nand_maximize_ecc);
  5306. /*
  5307. * Check if the chip configuration meet the datasheet requirements.
  5308. * If our configuration corrects A bits per B bytes and the minimum
  5309. * required correction level is X bits per Y bytes, then we must ensure
  5310. * both of the following are true:
  5311. *
  5312. * (1) A / B >= X / Y
  5313. * (2) A >= X
  5314. *
  5315. * Requirement (1) ensures we can correct for the required bitflip density.
  5316. * Requirement (2) ensures we can correct even when all bitflips are clumped
  5317. * in the same sector.
  5318. */
  5319. static bool nand_ecc_strength_good(struct mtd_info *mtd)
  5320. {
  5321. struct nand_chip *chip = mtd_to_nand(mtd);
  5322. struct nand_ecc_ctrl *ecc = &chip->ecc;
  5323. int corr, ds_corr;
  5324. if (ecc->size == 0 || chip->ecc_step_ds == 0)
  5325. /* Not enough information */
  5326. return true;
  5327. /*
  5328. * We get the number of corrected bits per page to compare
  5329. * the correction density.
  5330. */
  5331. corr = (mtd->writesize * ecc->strength) / ecc->size;
  5332. ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
  5333. return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
  5334. }
  5335. /**
  5336. * nand_scan_tail - [NAND Interface] Scan for the NAND device
  5337. * @mtd: MTD device structure
  5338. *
  5339. * This is the second phase of the normal nand_scan() function. It fills out
  5340. * all the uninitialized function pointers with the defaults and scans for a
  5341. * bad block table if appropriate.
  5342. */
  5343. int nand_scan_tail(struct mtd_info *mtd)
  5344. {
  5345. struct nand_chip *chip = mtd_to_nand(mtd);
  5346. struct nand_ecc_ctrl *ecc = &chip->ecc;
  5347. int ret, i;
  5348. /* New bad blocks should be marked in OOB, flash-based BBT, or both */
  5349. if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
  5350. !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
  5351. return -EINVAL;
  5352. }
  5353. chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
  5354. if (!chip->data_buf)
  5355. return -ENOMEM;
  5356. /*
  5357. * FIXME: some NAND manufacturer drivers expect the first die to be
  5358. * selected when manufacturer->init() is called. They should be fixed
  5359. * to explictly select the relevant die when interacting with the NAND
  5360. * chip.
  5361. */
  5362. chip->select_chip(mtd, 0);
  5363. ret = nand_manufacturer_init(chip);
  5364. chip->select_chip(mtd, -1);
  5365. if (ret)
  5366. goto err_free_buf;
  5367. /* Set the internal oob buffer location, just after the page data */
  5368. chip->oob_poi = chip->data_buf + mtd->writesize;
  5369. /*
  5370. * If no default placement scheme is given, select an appropriate one.
  5371. */
  5372. if (!mtd->ooblayout &&
  5373. !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
  5374. switch (mtd->oobsize) {
  5375. case 8:
  5376. case 16:
  5377. mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
  5378. break;
  5379. case 64:
  5380. case 128:
  5381. mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
  5382. break;
  5383. default:
  5384. /*
  5385. * Expose the whole OOB area to users if ECC_NONE
  5386. * is passed. We could do that for all kind of
  5387. * ->oobsize, but we must keep the old large/small
  5388. * page with ECC layout when ->oobsize <= 128 for
  5389. * compatibility reasons.
  5390. */
  5391. if (ecc->mode == NAND_ECC_NONE) {
  5392. mtd_set_ooblayout(mtd,
  5393. &nand_ooblayout_lp_ops);
  5394. break;
  5395. }
  5396. WARN(1, "No oob scheme defined for oobsize %d\n",
  5397. mtd->oobsize);
  5398. ret = -EINVAL;
  5399. goto err_nand_manuf_cleanup;
  5400. }
  5401. }
  5402. /*
  5403. * Check ECC mode, default to software if 3byte/512byte hardware ECC is
  5404. * selected and we have 256 byte pagesize fallback to software ECC
  5405. */
  5406. switch (ecc->mode) {
  5407. case NAND_ECC_HW_OOB_FIRST:
  5408. /* Similar to NAND_ECC_HW, but a separate read_page handle */
  5409. if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
  5410. WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
  5411. ret = -EINVAL;
  5412. goto err_nand_manuf_cleanup;
  5413. }
  5414. if (!ecc->read_page)
  5415. ecc->read_page = nand_read_page_hwecc_oob_first;
  5416. case NAND_ECC_HW:
  5417. /* Use standard hwecc read page function? */
  5418. if (!ecc->read_page)
  5419. ecc->read_page = nand_read_page_hwecc;
  5420. if (!ecc->write_page)
  5421. ecc->write_page = nand_write_page_hwecc;
  5422. if (!ecc->read_page_raw)
  5423. ecc->read_page_raw = nand_read_page_raw;
  5424. if (!ecc->write_page_raw)
  5425. ecc->write_page_raw = nand_write_page_raw;
  5426. if (!ecc->read_oob)
  5427. ecc->read_oob = nand_read_oob_std;
  5428. if (!ecc->write_oob)
  5429. ecc->write_oob = nand_write_oob_std;
  5430. if (!ecc->read_subpage)
  5431. ecc->read_subpage = nand_read_subpage;
  5432. if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
  5433. ecc->write_subpage = nand_write_subpage_hwecc;
  5434. case NAND_ECC_HW_SYNDROME:
  5435. if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
  5436. (!ecc->read_page ||
  5437. ecc->read_page == nand_read_page_hwecc ||
  5438. !ecc->write_page ||
  5439. ecc->write_page == nand_write_page_hwecc)) {
  5440. WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
  5441. ret = -EINVAL;
  5442. goto err_nand_manuf_cleanup;
  5443. }
  5444. /* Use standard syndrome read/write page function? */
  5445. if (!ecc->read_page)
  5446. ecc->read_page = nand_read_page_syndrome;
  5447. if (!ecc->write_page)
  5448. ecc->write_page = nand_write_page_syndrome;
  5449. if (!ecc->read_page_raw)
  5450. ecc->read_page_raw = nand_read_page_raw_syndrome;
  5451. if (!ecc->write_page_raw)
  5452. ecc->write_page_raw = nand_write_page_raw_syndrome;
  5453. if (!ecc->read_oob)
  5454. ecc->read_oob = nand_read_oob_syndrome;
  5455. if (!ecc->write_oob)
  5456. ecc->write_oob = nand_write_oob_syndrome;
  5457. if (mtd->writesize >= ecc->size) {
  5458. if (!ecc->strength) {
  5459. WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
  5460. ret = -EINVAL;
  5461. goto err_nand_manuf_cleanup;
  5462. }
  5463. break;
  5464. }
  5465. pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
  5466. ecc->size, mtd->writesize);
  5467. ecc->mode = NAND_ECC_SOFT;
  5468. ecc->algo = NAND_ECC_HAMMING;
  5469. case NAND_ECC_SOFT:
  5470. ret = nand_set_ecc_soft_ops(mtd);
  5471. if (ret) {
  5472. ret = -EINVAL;
  5473. goto err_nand_manuf_cleanup;
  5474. }
  5475. break;
  5476. case NAND_ECC_ON_DIE:
  5477. if (!ecc->read_page || !ecc->write_page) {
  5478. WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
  5479. ret = -EINVAL;
  5480. goto err_nand_manuf_cleanup;
  5481. }
  5482. if (!ecc->read_oob)
  5483. ecc->read_oob = nand_read_oob_std;
  5484. if (!ecc->write_oob)
  5485. ecc->write_oob = nand_write_oob_std;
  5486. break;
  5487. case NAND_ECC_NONE:
  5488. pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
  5489. ecc->read_page = nand_read_page_raw;
  5490. ecc->write_page = nand_write_page_raw;
  5491. ecc->read_oob = nand_read_oob_std;
  5492. ecc->read_page_raw = nand_read_page_raw;
  5493. ecc->write_page_raw = nand_write_page_raw;
  5494. ecc->write_oob = nand_write_oob_std;
  5495. ecc->size = mtd->writesize;
  5496. ecc->bytes = 0;
  5497. ecc->strength = 0;
  5498. break;
  5499. default:
  5500. WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
  5501. ret = -EINVAL;
  5502. goto err_nand_manuf_cleanup;
  5503. }
  5504. if (ecc->correct || ecc->calculate) {
  5505. ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
  5506. ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
  5507. if (!ecc->calc_buf || !ecc->code_buf) {
  5508. ret = -ENOMEM;
  5509. goto err_nand_manuf_cleanup;
  5510. }
  5511. }
  5512. /* For many systems, the standard OOB write also works for raw */
  5513. if (!ecc->read_oob_raw)
  5514. ecc->read_oob_raw = ecc->read_oob;
  5515. if (!ecc->write_oob_raw)
  5516. ecc->write_oob_raw = ecc->write_oob;
  5517. /* propagate ecc info to mtd_info */
  5518. mtd->ecc_strength = ecc->strength;
  5519. mtd->ecc_step_size = ecc->size;
  5520. /*
  5521. * Set the number of read / write steps for one page depending on ECC
  5522. * mode.
  5523. */
  5524. ecc->steps = mtd->writesize / ecc->size;
  5525. if (ecc->steps * ecc->size != mtd->writesize) {
  5526. WARN(1, "Invalid ECC parameters\n");
  5527. ret = -EINVAL;
  5528. goto err_nand_manuf_cleanup;
  5529. }
  5530. ecc->total = ecc->steps * ecc->bytes;
  5531. if (ecc->total > mtd->oobsize) {
  5532. WARN(1, "Total number of ECC bytes exceeded oobsize\n");
  5533. ret = -EINVAL;
  5534. goto err_nand_manuf_cleanup;
  5535. }
  5536. /*
  5537. * The number of bytes available for a client to place data into
  5538. * the out of band area.
  5539. */
  5540. ret = mtd_ooblayout_count_freebytes(mtd);
  5541. if (ret < 0)
  5542. ret = 0;
  5543. mtd->oobavail = ret;
  5544. /* ECC sanity check: warn if it's too weak */
  5545. if (!nand_ecc_strength_good(mtd))
  5546. pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
  5547. mtd->name);
  5548. /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
  5549. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
  5550. switch (ecc->steps) {
  5551. case 2:
  5552. mtd->subpage_sft = 1;
  5553. break;
  5554. case 4:
  5555. case 8:
  5556. case 16:
  5557. mtd->subpage_sft = 2;
  5558. break;
  5559. }
  5560. }
  5561. chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
  5562. /* Initialize state */
  5563. chip->state = FL_READY;
  5564. /* Invalidate the pagebuffer reference */
  5565. chip->pagebuf = -1;
  5566. /* Large page NAND with SOFT_ECC should support subpage reads */
  5567. switch (ecc->mode) {
  5568. case NAND_ECC_SOFT:
  5569. if (chip->page_shift > 9)
  5570. chip->options |= NAND_SUBPAGE_READ;
  5571. break;
  5572. default:
  5573. break;
  5574. }
  5575. /* Fill in remaining MTD driver data */
  5576. mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
  5577. mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
  5578. MTD_CAP_NANDFLASH;
  5579. mtd->_erase = nand_erase;
  5580. mtd->_point = NULL;
  5581. mtd->_unpoint = NULL;
  5582. mtd->_panic_write = panic_nand_write;
  5583. mtd->_read_oob = nand_read_oob;
  5584. mtd->_write_oob = nand_write_oob;
  5585. mtd->_sync = nand_sync;
  5586. mtd->_lock = NULL;
  5587. mtd->_unlock = NULL;
  5588. mtd->_suspend = nand_suspend;
  5589. mtd->_resume = nand_resume;
  5590. mtd->_reboot = nand_shutdown;
  5591. mtd->_block_isreserved = nand_block_isreserved;
  5592. mtd->_block_isbad = nand_block_isbad;
  5593. mtd->_block_markbad = nand_block_markbad;
  5594. mtd->_max_bad_blocks = nand_max_bad_blocks;
  5595. mtd->writebufsize = mtd->writesize;
  5596. /*
  5597. * Initialize bitflip_threshold to its default prior scan_bbt() call.
  5598. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
  5599. * properly set.
  5600. */
  5601. if (!mtd->bitflip_threshold)
  5602. mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
  5603. /* Initialize the ->data_interface field. */
  5604. ret = nand_init_data_interface(chip);
  5605. if (ret)
  5606. goto err_nand_manuf_cleanup;
  5607. /* Enter fastest possible mode on all dies. */
  5608. for (i = 0; i < chip->numchips; i++) {
  5609. ret = nand_setup_data_interface(chip, i);
  5610. if (ret)
  5611. goto err_nand_manuf_cleanup;
  5612. }
  5613. /* Check, if we should skip the bad block table scan */
  5614. if (chip->options & NAND_SKIP_BBTSCAN)
  5615. return 0;
  5616. /* Build bad block table */
  5617. ret = chip->scan_bbt(mtd);
  5618. if (ret)
  5619. goto err_nand_manuf_cleanup;
  5620. return 0;
  5621. err_nand_manuf_cleanup:
  5622. nand_manufacturer_cleanup(chip);
  5623. err_free_buf:
  5624. kfree(chip->data_buf);
  5625. kfree(ecc->code_buf);
  5626. kfree(ecc->calc_buf);
  5627. return ret;
  5628. }
  5629. EXPORT_SYMBOL(nand_scan_tail);
  5630. /*
  5631. * is_module_text_address() isn't exported, and it's mostly a pointless
  5632. * test if this is a module _anyway_ -- they'd have to try _really_ hard
  5633. * to call us from in-kernel code if the core NAND support is modular.
  5634. */
  5635. #ifdef MODULE
  5636. #define caller_is_module() (1)
  5637. #else
  5638. #define caller_is_module() \
  5639. is_module_text_address((unsigned long)__builtin_return_address(0))
  5640. #endif
  5641. /**
  5642. * nand_scan - [NAND Interface] Scan for the NAND device
  5643. * @mtd: MTD device structure
  5644. * @maxchips: number of chips to scan for
  5645. *
  5646. * This fills out all the uninitialized function pointers with the defaults.
  5647. * The flash ID is read and the mtd/chip structures are filled with the
  5648. * appropriate values.
  5649. */
  5650. int nand_scan(struct mtd_info *mtd, int maxchips)
  5651. {
  5652. int ret;
  5653. ret = nand_scan_ident(mtd, maxchips, NULL);
  5654. if (!ret)
  5655. ret = nand_scan_tail(mtd);
  5656. return ret;
  5657. }
  5658. EXPORT_SYMBOL(nand_scan);
  5659. /**
  5660. * nand_cleanup - [NAND Interface] Free resources held by the NAND device
  5661. * @chip: NAND chip object
  5662. */
  5663. void nand_cleanup(struct nand_chip *chip)
  5664. {
  5665. if (chip->ecc.mode == NAND_ECC_SOFT &&
  5666. chip->ecc.algo == NAND_ECC_BCH)
  5667. nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
  5668. /* Free bad block table memory */
  5669. kfree(chip->bbt);
  5670. kfree(chip->data_buf);
  5671. kfree(chip->ecc.code_buf);
  5672. kfree(chip->ecc.calc_buf);
  5673. /* Free bad block descriptor memory */
  5674. if (chip->badblock_pattern && chip->badblock_pattern->options
  5675. & NAND_BBT_DYNAMICSTRUCT)
  5676. kfree(chip->badblock_pattern);
  5677. /* Free manufacturer priv data. */
  5678. nand_manufacturer_cleanup(chip);
  5679. }
  5680. EXPORT_SYMBOL_GPL(nand_cleanup);
  5681. /**
  5682. * nand_release - [NAND Interface] Unregister the MTD device and free resources
  5683. * held by the NAND device
  5684. * @mtd: MTD device structure
  5685. */
  5686. void nand_release(struct mtd_info *mtd)
  5687. {
  5688. mtd_device_unregister(mtd);
  5689. nand_cleanup(mtd_to_nand(mtd));
  5690. }
  5691. EXPORT_SYMBOL_GPL(nand_release);
  5692. MODULE_LICENSE("GPL");
  5693. MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
  5694. MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
  5695. MODULE_DESCRIPTION("Generic NAND flash driver code");