renesas_sdhi_sys_dmac.c 14 KB

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  1. /*
  2. * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  3. *
  4. * Copyright (C) 2016-17 Renesas Electronics Corporation
  5. * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
  6. * Copyright (C) 2017 Horms Solutions, Simon Horman
  7. * Copyright (C) 2010-2011 Guennadi Liakhovetski
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/device.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmaengine.h>
  16. #include <linux/mfd/tmio.h>
  17. #include <linux/mmc/host.h>
  18. #include <linux/mod_devicetable.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/pagemap.h>
  22. #include <linux/scatterlist.h>
  23. #include <linux/sys_soc.h>
  24. #include "renesas_sdhi.h"
  25. #include "tmio_mmc.h"
  26. #define TMIO_MMC_MIN_DMA_LEN 8
  27. static const struct renesas_sdhi_of_data of_default_cfg = {
  28. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  29. };
  30. static const struct renesas_sdhi_of_data of_rz_compatible = {
  31. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
  32. TMIO_MMC_HAVE_CBSY,
  33. .tmio_ocr_mask = MMC_VDD_32_33,
  34. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  35. };
  36. static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
  37. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
  38. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  39. };
  40. /* Definitions for sampling clocks */
  41. static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
  42. {
  43. .clk_rate = 156000000,
  44. .tap = 0x00000703,
  45. },
  46. {
  47. .clk_rate = 0,
  48. .tap = 0x00000300,
  49. },
  50. };
  51. static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
  52. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  53. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  54. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  55. MMC_CAP_CMD23,
  56. .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
  57. .dma_rx_offset = 0x2000,
  58. .scc_offset = 0x0300,
  59. .taps = rcar_gen2_scc_taps,
  60. .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
  61. };
  62. /* Definitions for sampling clocks */
  63. static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  64. {
  65. .clk_rate = 0,
  66. .tap = 0x00000300,
  67. },
  68. };
  69. static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  70. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  71. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  72. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  73. MMC_CAP_CMD23,
  74. .bus_shift = 2,
  75. .scc_offset = 0x1000,
  76. .taps = rcar_gen3_scc_taps,
  77. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  78. };
  79. static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
  80. { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
  81. { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
  82. { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
  83. { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
  84. { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
  85. { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
  86. { .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
  87. { .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
  88. { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
  89. { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
  90. { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
  91. { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
  92. { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
  93. { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
  94. { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
  95. { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
  96. { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
  97. { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
  98. { .compatible = "renesas,sdhi-shmobile" },
  99. {},
  100. };
  101. MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
  102. static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
  103. bool enable)
  104. {
  105. struct renesas_sdhi *priv = host_to_priv(host);
  106. if (!host->chan_tx || !host->chan_rx)
  107. return;
  108. if (priv->dma_priv.enable)
  109. priv->dma_priv.enable(host, enable);
  110. }
  111. static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
  112. {
  113. renesas_sdhi_sys_dmac_enable_dma(host, false);
  114. if (host->chan_rx)
  115. dmaengine_terminate_all(host->chan_rx);
  116. if (host->chan_tx)
  117. dmaengine_terminate_all(host->chan_tx);
  118. renesas_sdhi_sys_dmac_enable_dma(host, true);
  119. }
  120. static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
  121. {
  122. struct renesas_sdhi *priv = host_to_priv(host);
  123. complete(&priv->dma_priv.dma_dataend);
  124. }
  125. static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
  126. {
  127. struct tmio_mmc_host *host = arg;
  128. struct renesas_sdhi *priv = host_to_priv(host);
  129. spin_lock_irq(&host->lock);
  130. if (!host->data)
  131. goto out;
  132. if (host->data->flags & MMC_DATA_READ)
  133. dma_unmap_sg(host->chan_rx->device->dev,
  134. host->sg_ptr, host->sg_len,
  135. DMA_FROM_DEVICE);
  136. else
  137. dma_unmap_sg(host->chan_tx->device->dev,
  138. host->sg_ptr, host->sg_len,
  139. DMA_TO_DEVICE);
  140. spin_unlock_irq(&host->lock);
  141. wait_for_completion(&priv->dma_priv.dma_dataend);
  142. spin_lock_irq(&host->lock);
  143. tmio_mmc_do_data_irq(host);
  144. out:
  145. spin_unlock_irq(&host->lock);
  146. }
  147. static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
  148. {
  149. struct renesas_sdhi *priv = host_to_priv(host);
  150. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  151. struct dma_async_tx_descriptor *desc = NULL;
  152. struct dma_chan *chan = host->chan_rx;
  153. dma_cookie_t cookie;
  154. int ret, i;
  155. bool aligned = true, multiple = true;
  156. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  157. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  158. if (sg_tmp->offset & align)
  159. aligned = false;
  160. if (sg_tmp->length & align) {
  161. multiple = false;
  162. break;
  163. }
  164. }
  165. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  166. (align & PAGE_MASK))) || !multiple) {
  167. ret = -EINVAL;
  168. goto pio;
  169. }
  170. if (sg->length < TMIO_MMC_MIN_DMA_LEN) {
  171. host->force_pio = true;
  172. return;
  173. }
  174. /* The only sg element can be unaligned, use our bounce buffer then */
  175. if (!aligned) {
  176. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  177. host->sg_ptr = &host->bounce_sg;
  178. sg = host->sg_ptr;
  179. }
  180. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
  181. if (ret > 0)
  182. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
  183. DMA_CTRL_ACK);
  184. if (desc) {
  185. reinit_completion(&priv->dma_priv.dma_dataend);
  186. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  187. desc->callback_param = host;
  188. cookie = dmaengine_submit(desc);
  189. if (cookie < 0) {
  190. desc = NULL;
  191. ret = cookie;
  192. }
  193. }
  194. pio:
  195. if (!desc) {
  196. /* DMA failed, fall back to PIO */
  197. renesas_sdhi_sys_dmac_enable_dma(host, false);
  198. if (ret >= 0)
  199. ret = -EIO;
  200. host->chan_rx = NULL;
  201. dma_release_channel(chan);
  202. /* Free the Tx channel too */
  203. chan = host->chan_tx;
  204. if (chan) {
  205. host->chan_tx = NULL;
  206. dma_release_channel(chan);
  207. }
  208. dev_warn(&host->pdev->dev,
  209. "DMA failed: %d, falling back to PIO\n", ret);
  210. }
  211. }
  212. static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
  213. {
  214. struct renesas_sdhi *priv = host_to_priv(host);
  215. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  216. struct dma_async_tx_descriptor *desc = NULL;
  217. struct dma_chan *chan = host->chan_tx;
  218. dma_cookie_t cookie;
  219. int ret, i;
  220. bool aligned = true, multiple = true;
  221. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  222. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  223. if (sg_tmp->offset & align)
  224. aligned = false;
  225. if (sg_tmp->length & align) {
  226. multiple = false;
  227. break;
  228. }
  229. }
  230. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  231. (align & PAGE_MASK))) || !multiple) {
  232. ret = -EINVAL;
  233. goto pio;
  234. }
  235. if (sg->length < TMIO_MMC_MIN_DMA_LEN) {
  236. host->force_pio = true;
  237. return;
  238. }
  239. /* The only sg element can be unaligned, use our bounce buffer then */
  240. if (!aligned) {
  241. unsigned long flags;
  242. void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
  243. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  244. memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
  245. tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
  246. host->sg_ptr = &host->bounce_sg;
  247. sg = host->sg_ptr;
  248. }
  249. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
  250. if (ret > 0)
  251. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
  252. DMA_CTRL_ACK);
  253. if (desc) {
  254. reinit_completion(&priv->dma_priv.dma_dataend);
  255. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  256. desc->callback_param = host;
  257. cookie = dmaengine_submit(desc);
  258. if (cookie < 0) {
  259. desc = NULL;
  260. ret = cookie;
  261. }
  262. }
  263. pio:
  264. if (!desc) {
  265. /* DMA failed, fall back to PIO */
  266. renesas_sdhi_sys_dmac_enable_dma(host, false);
  267. if (ret >= 0)
  268. ret = -EIO;
  269. host->chan_tx = NULL;
  270. dma_release_channel(chan);
  271. /* Free the Rx channel too */
  272. chan = host->chan_rx;
  273. if (chan) {
  274. host->chan_rx = NULL;
  275. dma_release_channel(chan);
  276. }
  277. dev_warn(&host->pdev->dev,
  278. "DMA failed: %d, falling back to PIO\n", ret);
  279. }
  280. }
  281. static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
  282. struct mmc_data *data)
  283. {
  284. if (data->flags & MMC_DATA_READ) {
  285. if (host->chan_rx)
  286. renesas_sdhi_sys_dmac_start_dma_rx(host);
  287. } else {
  288. if (host->chan_tx)
  289. renesas_sdhi_sys_dmac_start_dma_tx(host);
  290. }
  291. }
  292. static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
  293. {
  294. struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
  295. struct dma_chan *chan = NULL;
  296. spin_lock_irq(&host->lock);
  297. if (host->data) {
  298. if (host->data->flags & MMC_DATA_READ)
  299. chan = host->chan_rx;
  300. else
  301. chan = host->chan_tx;
  302. }
  303. spin_unlock_irq(&host->lock);
  304. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  305. if (chan)
  306. dma_async_issue_pending(chan);
  307. }
  308. static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
  309. struct tmio_mmc_data *pdata)
  310. {
  311. struct renesas_sdhi *priv = host_to_priv(host);
  312. /* We can only either use DMA for both Tx and Rx or not use it at all */
  313. if (!host->pdev->dev.of_node &&
  314. (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
  315. return;
  316. if (!host->chan_tx && !host->chan_rx) {
  317. struct resource *res = platform_get_resource(host->pdev,
  318. IORESOURCE_MEM, 0);
  319. struct dma_slave_config cfg = {};
  320. dma_cap_mask_t mask;
  321. int ret;
  322. if (!res)
  323. return;
  324. dma_cap_zero(mask);
  325. dma_cap_set(DMA_SLAVE, mask);
  326. host->chan_tx = dma_request_slave_channel_compat(mask,
  327. priv->dma_priv.filter, pdata->chan_priv_tx,
  328. &host->pdev->dev, "tx");
  329. dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
  330. host->chan_tx);
  331. if (!host->chan_tx)
  332. return;
  333. cfg.direction = DMA_MEM_TO_DEV;
  334. cfg.dst_addr = res->start +
  335. (CTL_SD_DATA_PORT << host->bus_shift);
  336. cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
  337. if (!cfg.dst_addr_width)
  338. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  339. cfg.src_addr = 0;
  340. ret = dmaengine_slave_config(host->chan_tx, &cfg);
  341. if (ret < 0)
  342. goto ecfgtx;
  343. host->chan_rx = dma_request_slave_channel_compat(mask,
  344. priv->dma_priv.filter, pdata->chan_priv_rx,
  345. &host->pdev->dev, "rx");
  346. dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
  347. host->chan_rx);
  348. if (!host->chan_rx)
  349. goto ereqrx;
  350. cfg.direction = DMA_DEV_TO_MEM;
  351. cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
  352. cfg.src_addr_width = priv->dma_priv.dma_buswidth;
  353. if (!cfg.src_addr_width)
  354. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  355. cfg.dst_addr = 0;
  356. ret = dmaengine_slave_config(host->chan_rx, &cfg);
  357. if (ret < 0)
  358. goto ecfgrx;
  359. host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
  360. if (!host->bounce_buf)
  361. goto ebouncebuf;
  362. init_completion(&priv->dma_priv.dma_dataend);
  363. tasklet_init(&host->dma_issue,
  364. renesas_sdhi_sys_dmac_issue_tasklet_fn,
  365. (unsigned long)host);
  366. }
  367. renesas_sdhi_sys_dmac_enable_dma(host, true);
  368. return;
  369. ebouncebuf:
  370. ecfgrx:
  371. dma_release_channel(host->chan_rx);
  372. host->chan_rx = NULL;
  373. ereqrx:
  374. ecfgtx:
  375. dma_release_channel(host->chan_tx);
  376. host->chan_tx = NULL;
  377. }
  378. static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
  379. {
  380. if (host->chan_tx) {
  381. struct dma_chan *chan = host->chan_tx;
  382. host->chan_tx = NULL;
  383. dma_release_channel(chan);
  384. }
  385. if (host->chan_rx) {
  386. struct dma_chan *chan = host->chan_rx;
  387. host->chan_rx = NULL;
  388. dma_release_channel(chan);
  389. }
  390. if (host->bounce_buf) {
  391. free_pages((unsigned long)host->bounce_buf, 0);
  392. host->bounce_buf = NULL;
  393. }
  394. }
  395. static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
  396. .start = renesas_sdhi_sys_dmac_start_dma,
  397. .enable = renesas_sdhi_sys_dmac_enable_dma,
  398. .request = renesas_sdhi_sys_dmac_request_dma,
  399. .release = renesas_sdhi_sys_dmac_release_dma,
  400. .abort = renesas_sdhi_sys_dmac_abort_dma,
  401. .dataend = renesas_sdhi_sys_dmac_dataend_dma,
  402. };
  403. /*
  404. * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
  405. * implementation. Currently empty as all supported ES versions use
  406. * the internal DMAC.
  407. */
  408. static const struct soc_device_attribute gen3_soc_whitelist[] = {
  409. { /* sentinel */ }
  410. };
  411. static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
  412. {
  413. if (of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible &&
  414. !soc_device_match(gen3_soc_whitelist))
  415. return -ENODEV;
  416. return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
  417. }
  418. static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
  419. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  420. pm_runtime_force_resume)
  421. SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
  422. tmio_mmc_host_runtime_resume,
  423. NULL)
  424. };
  425. static struct platform_driver renesas_sys_dmac_sdhi_driver = {
  426. .driver = {
  427. .name = "sh_mobile_sdhi",
  428. .pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
  429. .of_match_table = renesas_sdhi_sys_dmac_of_match,
  430. },
  431. .probe = renesas_sdhi_sys_dmac_probe,
  432. .remove = renesas_sdhi_remove,
  433. };
  434. module_platform_driver(renesas_sys_dmac_sdhi_driver);
  435. MODULE_DESCRIPTION("Renesas SDHI driver");
  436. MODULE_AUTHOR("Magnus Damm");
  437. MODULE_LICENSE("GPL v2");
  438. MODULE_ALIAS("platform:sh_mobile_sdhi");