dw_mmc.c 89 KB

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  1. /*
  2. * Synopsys DesignWare Multimedia Card Interface driver
  3. * (Based on NXP driver for lpc 31xx)
  4. *
  5. * Copyright (C) 2009 NXP Semiconductors
  6. * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/blkdev.h>
  14. #include <linux/clk.h>
  15. #include <linux/debugfs.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/err.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/ioport.h>
  23. #include <linux/module.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/slab.h>
  28. #include <linux/stat.h>
  29. #include <linux/delay.h>
  30. #include <linux/irq.h>
  31. #include <linux/mmc/card.h>
  32. #include <linux/mmc/host.h>
  33. #include <linux/mmc/mmc.h>
  34. #include <linux/mmc/sd.h>
  35. #include <linux/mmc/sdio.h>
  36. #include <linux/bitops.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/of.h>
  39. #include <linux/of_gpio.h>
  40. #include <linux/mmc/slot-gpio.h>
  41. #include "dw_mmc.h"
  42. /* Common flag combinations */
  43. #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  44. SDMMC_INT_HTO | SDMMC_INT_SBE | \
  45. SDMMC_INT_EBE | SDMMC_INT_HLE)
  46. #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  47. SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  48. #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
  49. DW_MCI_CMD_ERROR_FLAGS)
  50. #define DW_MCI_SEND_STATUS 1
  51. #define DW_MCI_RECV_STATUS 2
  52. #define DW_MCI_DMA_THRESHOLD 16
  53. #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
  54. #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
  55. #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  56. SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  57. SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  58. SDMMC_IDMAC_INT_TI)
  59. #define DESC_RING_BUF_SZ PAGE_SIZE
  60. struct idmac_desc_64addr {
  61. u32 des0; /* Control Descriptor */
  62. #define IDMAC_OWN_CLR64(x) \
  63. !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  64. u32 des1; /* Reserved */
  65. u32 des2; /*Buffer sizes */
  66. #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  67. ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  68. ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  69. u32 des3; /* Reserved */
  70. u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
  71. u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
  72. u32 des6; /* Lower 32-bits of Next Descriptor Address */
  73. u32 des7; /* Upper 32-bits of Next Descriptor Address */
  74. };
  75. struct idmac_desc {
  76. __le32 des0; /* Control Descriptor */
  77. #define IDMAC_DES0_DIC BIT(1)
  78. #define IDMAC_DES0_LD BIT(2)
  79. #define IDMAC_DES0_FD BIT(3)
  80. #define IDMAC_DES0_CH BIT(4)
  81. #define IDMAC_DES0_ER BIT(5)
  82. #define IDMAC_DES0_CES BIT(30)
  83. #define IDMAC_DES0_OWN BIT(31)
  84. __le32 des1; /* Buffer sizes */
  85. #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  86. ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  87. __le32 des2; /* buffer 1 physical address */
  88. __le32 des3; /* buffer 2 physical address */
  89. };
  90. /* Each descriptor can transfer up to 4KB of data in chained mode */
  91. #define DW_MCI_DESC_DATA_LENGTH 0x1000
  92. #if defined(CONFIG_DEBUG_FS)
  93. static int dw_mci_req_show(struct seq_file *s, void *v)
  94. {
  95. struct dw_mci_slot *slot = s->private;
  96. struct mmc_request *mrq;
  97. struct mmc_command *cmd;
  98. struct mmc_command *stop;
  99. struct mmc_data *data;
  100. /* Make sure we get a consistent snapshot */
  101. spin_lock_bh(&slot->host->lock);
  102. mrq = slot->mrq;
  103. if (mrq) {
  104. cmd = mrq->cmd;
  105. data = mrq->data;
  106. stop = mrq->stop;
  107. if (cmd)
  108. seq_printf(s,
  109. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  110. cmd->opcode, cmd->arg, cmd->flags,
  111. cmd->resp[0], cmd->resp[1], cmd->resp[2],
  112. cmd->resp[2], cmd->error);
  113. if (data)
  114. seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
  115. data->bytes_xfered, data->blocks,
  116. data->blksz, data->flags, data->error);
  117. if (stop)
  118. seq_printf(s,
  119. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  120. stop->opcode, stop->arg, stop->flags,
  121. stop->resp[0], stop->resp[1], stop->resp[2],
  122. stop->resp[2], stop->error);
  123. }
  124. spin_unlock_bh(&slot->host->lock);
  125. return 0;
  126. }
  127. DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
  128. static int dw_mci_regs_show(struct seq_file *s, void *v)
  129. {
  130. struct dw_mci *host = s->private;
  131. pm_runtime_get_sync(host->dev);
  132. seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
  133. seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
  134. seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
  135. seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
  136. seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
  137. seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
  138. pm_runtime_put_autosuspend(host->dev);
  139. return 0;
  140. }
  141. DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
  142. static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
  143. {
  144. struct mmc_host *mmc = slot->mmc;
  145. struct dw_mci *host = slot->host;
  146. struct dentry *root;
  147. struct dentry *node;
  148. root = mmc->debugfs_root;
  149. if (!root)
  150. return;
  151. node = debugfs_create_file("regs", S_IRUSR, root, host,
  152. &dw_mci_regs_fops);
  153. if (!node)
  154. goto err;
  155. node = debugfs_create_file("req", S_IRUSR, root, slot,
  156. &dw_mci_req_fops);
  157. if (!node)
  158. goto err;
  159. node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
  160. if (!node)
  161. goto err;
  162. node = debugfs_create_x32("pending_events", S_IRUSR, root,
  163. (u32 *)&host->pending_events);
  164. if (!node)
  165. goto err;
  166. node = debugfs_create_x32("completed_events", S_IRUSR, root,
  167. (u32 *)&host->completed_events);
  168. if (!node)
  169. goto err;
  170. return;
  171. err:
  172. dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
  173. }
  174. #endif /* defined(CONFIG_DEBUG_FS) */
  175. static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
  176. {
  177. u32 ctrl;
  178. ctrl = mci_readl(host, CTRL);
  179. ctrl |= reset;
  180. mci_writel(host, CTRL, ctrl);
  181. /* wait till resets clear */
  182. if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
  183. !(ctrl & reset),
  184. 1, 500 * USEC_PER_MSEC)) {
  185. dev_err(host->dev,
  186. "Timeout resetting block (ctrl reset %#x)\n",
  187. ctrl & reset);
  188. return false;
  189. }
  190. return true;
  191. }
  192. static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
  193. {
  194. u32 status;
  195. /*
  196. * Databook says that before issuing a new data transfer command
  197. * we need to check to see if the card is busy. Data transfer commands
  198. * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
  199. *
  200. * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
  201. * expected.
  202. */
  203. if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
  204. !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
  205. if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
  206. status,
  207. !(status & SDMMC_STATUS_BUSY),
  208. 10, 500 * USEC_PER_MSEC))
  209. dev_err(host->dev, "Busy; trying anyway\n");
  210. }
  211. }
  212. static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
  213. {
  214. struct dw_mci *host = slot->host;
  215. unsigned int cmd_status = 0;
  216. mci_writel(host, CMDARG, arg);
  217. wmb(); /* drain writebuffer */
  218. dw_mci_wait_while_busy(host, cmd);
  219. mci_writel(host, CMD, SDMMC_CMD_START | cmd);
  220. if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
  221. !(cmd_status & SDMMC_CMD_START),
  222. 1, 500 * USEC_PER_MSEC))
  223. dev_err(&slot->mmc->class_dev,
  224. "Timeout sending command (cmd %#x arg %#x status %#x)\n",
  225. cmd, arg, cmd_status);
  226. }
  227. static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
  228. {
  229. struct dw_mci_slot *slot = mmc_priv(mmc);
  230. struct dw_mci *host = slot->host;
  231. u32 cmdr;
  232. cmd->error = -EINPROGRESS;
  233. cmdr = cmd->opcode;
  234. if (cmd->opcode == MMC_STOP_TRANSMISSION ||
  235. cmd->opcode == MMC_GO_IDLE_STATE ||
  236. cmd->opcode == MMC_GO_INACTIVE_STATE ||
  237. (cmd->opcode == SD_IO_RW_DIRECT &&
  238. ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
  239. cmdr |= SDMMC_CMD_STOP;
  240. else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
  241. cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
  242. if (cmd->opcode == SD_SWITCH_VOLTAGE) {
  243. u32 clk_en_a;
  244. /* Special bit makes CMD11 not die */
  245. cmdr |= SDMMC_CMD_VOLT_SWITCH;
  246. /* Change state to continue to handle CMD11 weirdness */
  247. WARN_ON(slot->host->state != STATE_SENDING_CMD);
  248. slot->host->state = STATE_SENDING_CMD11;
  249. /*
  250. * We need to disable low power mode (automatic clock stop)
  251. * while doing voltage switch so we don't confuse the card,
  252. * since stopping the clock is a specific part of the UHS
  253. * voltage change dance.
  254. *
  255. * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
  256. * unconditionally turned back on in dw_mci_setup_bus() if it's
  257. * ever called with a non-zero clock. That shouldn't happen
  258. * until the voltage change is all done.
  259. */
  260. clk_en_a = mci_readl(host, CLKENA);
  261. clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
  262. mci_writel(host, CLKENA, clk_en_a);
  263. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  264. SDMMC_CMD_PRV_DAT_WAIT, 0);
  265. }
  266. if (cmd->flags & MMC_RSP_PRESENT) {
  267. /* We expect a response, so set this bit */
  268. cmdr |= SDMMC_CMD_RESP_EXP;
  269. if (cmd->flags & MMC_RSP_136)
  270. cmdr |= SDMMC_CMD_RESP_LONG;
  271. }
  272. if (cmd->flags & MMC_RSP_CRC)
  273. cmdr |= SDMMC_CMD_RESP_CRC;
  274. if (cmd->data) {
  275. cmdr |= SDMMC_CMD_DAT_EXP;
  276. if (cmd->data->flags & MMC_DATA_WRITE)
  277. cmdr |= SDMMC_CMD_DAT_WR;
  278. }
  279. if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
  280. cmdr |= SDMMC_CMD_USE_HOLD_REG;
  281. return cmdr;
  282. }
  283. static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
  284. {
  285. struct mmc_command *stop;
  286. u32 cmdr;
  287. if (!cmd->data)
  288. return 0;
  289. stop = &host->stop_abort;
  290. cmdr = cmd->opcode;
  291. memset(stop, 0, sizeof(struct mmc_command));
  292. if (cmdr == MMC_READ_SINGLE_BLOCK ||
  293. cmdr == MMC_READ_MULTIPLE_BLOCK ||
  294. cmdr == MMC_WRITE_BLOCK ||
  295. cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
  296. cmdr == MMC_SEND_TUNING_BLOCK ||
  297. cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
  298. stop->opcode = MMC_STOP_TRANSMISSION;
  299. stop->arg = 0;
  300. stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
  301. } else if (cmdr == SD_IO_RW_EXTENDED) {
  302. stop->opcode = SD_IO_RW_DIRECT;
  303. stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
  304. ((cmd->arg >> 28) & 0x7);
  305. stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
  306. } else {
  307. return 0;
  308. }
  309. cmdr = stop->opcode | SDMMC_CMD_STOP |
  310. SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
  311. if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
  312. cmdr |= SDMMC_CMD_USE_HOLD_REG;
  313. return cmdr;
  314. }
  315. static inline void dw_mci_set_cto(struct dw_mci *host)
  316. {
  317. unsigned int cto_clks;
  318. unsigned int cto_div;
  319. unsigned int cto_ms;
  320. unsigned long irqflags;
  321. cto_clks = mci_readl(host, TMOUT) & 0xff;
  322. cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
  323. if (cto_div == 0)
  324. cto_div = 1;
  325. cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
  326. host->bus_hz);
  327. /* add a bit spare time */
  328. cto_ms += 10;
  329. /*
  330. * The durations we're working with are fairly short so we have to be
  331. * extra careful about synchronization here. Specifically in hardware a
  332. * command timeout is _at most_ 5.1 ms, so that means we expect an
  333. * interrupt (either command done or timeout) to come rather quickly
  334. * after the mci_writel. ...but just in case we have a long interrupt
  335. * latency let's add a bit of paranoia.
  336. *
  337. * In general we'll assume that at least an interrupt will be asserted
  338. * in hardware by the time the cto_timer runs. ...and if it hasn't
  339. * been asserted in hardware by that time then we'll assume it'll never
  340. * come.
  341. */
  342. spin_lock_irqsave(&host->irq_lock, irqflags);
  343. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  344. mod_timer(&host->cto_timer,
  345. jiffies + msecs_to_jiffies(cto_ms) + 1);
  346. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  347. }
  348. static void dw_mci_start_command(struct dw_mci *host,
  349. struct mmc_command *cmd, u32 cmd_flags)
  350. {
  351. host->cmd = cmd;
  352. dev_vdbg(host->dev,
  353. "start command: ARGR=0x%08x CMDR=0x%08x\n",
  354. cmd->arg, cmd_flags);
  355. mci_writel(host, CMDARG, cmd->arg);
  356. wmb(); /* drain writebuffer */
  357. dw_mci_wait_while_busy(host, cmd_flags);
  358. mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
  359. /* response expected command only */
  360. if (cmd_flags & SDMMC_CMD_RESP_EXP)
  361. dw_mci_set_cto(host);
  362. }
  363. static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
  364. {
  365. struct mmc_command *stop = &host->stop_abort;
  366. dw_mci_start_command(host, stop, host->stop_cmdr);
  367. }
  368. /* DMA interface functions */
  369. static void dw_mci_stop_dma(struct dw_mci *host)
  370. {
  371. if (host->using_dma) {
  372. host->dma_ops->stop(host);
  373. host->dma_ops->cleanup(host);
  374. }
  375. /* Data transfer was stopped by the interrupt handler */
  376. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  377. }
  378. static void dw_mci_dma_cleanup(struct dw_mci *host)
  379. {
  380. struct mmc_data *data = host->data;
  381. if (data && data->host_cookie == COOKIE_MAPPED) {
  382. dma_unmap_sg(host->dev,
  383. data->sg,
  384. data->sg_len,
  385. mmc_get_dma_dir(data));
  386. data->host_cookie = COOKIE_UNMAPPED;
  387. }
  388. }
  389. static void dw_mci_idmac_reset(struct dw_mci *host)
  390. {
  391. u32 bmod = mci_readl(host, BMOD);
  392. /* Software reset of DMA */
  393. bmod |= SDMMC_IDMAC_SWRESET;
  394. mci_writel(host, BMOD, bmod);
  395. }
  396. static void dw_mci_idmac_stop_dma(struct dw_mci *host)
  397. {
  398. u32 temp;
  399. /* Disable and reset the IDMAC interface */
  400. temp = mci_readl(host, CTRL);
  401. temp &= ~SDMMC_CTRL_USE_IDMAC;
  402. temp |= SDMMC_CTRL_DMA_RESET;
  403. mci_writel(host, CTRL, temp);
  404. /* Stop the IDMAC running */
  405. temp = mci_readl(host, BMOD);
  406. temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
  407. temp |= SDMMC_IDMAC_SWRESET;
  408. mci_writel(host, BMOD, temp);
  409. }
  410. static void dw_mci_dmac_complete_dma(void *arg)
  411. {
  412. struct dw_mci *host = arg;
  413. struct mmc_data *data = host->data;
  414. dev_vdbg(host->dev, "DMA complete\n");
  415. if ((host->use_dma == TRANS_MODE_EDMAC) &&
  416. data && (data->flags & MMC_DATA_READ))
  417. /* Invalidate cache after read */
  418. dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
  419. data->sg,
  420. data->sg_len,
  421. DMA_FROM_DEVICE);
  422. host->dma_ops->cleanup(host);
  423. /*
  424. * If the card was removed, data will be NULL. No point in trying to
  425. * send the stop command or waiting for NBUSY in this case.
  426. */
  427. if (data) {
  428. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  429. tasklet_schedule(&host->tasklet);
  430. }
  431. }
  432. static int dw_mci_idmac_init(struct dw_mci *host)
  433. {
  434. int i;
  435. if (host->dma_64bit_address == 1) {
  436. struct idmac_desc_64addr *p;
  437. /* Number of descriptors in the ring buffer */
  438. host->ring_size =
  439. DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
  440. /* Forward link the descriptor list */
  441. for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
  442. i++, p++) {
  443. p->des6 = (host->sg_dma +
  444. (sizeof(struct idmac_desc_64addr) *
  445. (i + 1))) & 0xffffffff;
  446. p->des7 = (u64)(host->sg_dma +
  447. (sizeof(struct idmac_desc_64addr) *
  448. (i + 1))) >> 32;
  449. /* Initialize reserved and buffer size fields to "0" */
  450. p->des0 = 0;
  451. p->des1 = 0;
  452. p->des2 = 0;
  453. p->des3 = 0;
  454. }
  455. /* Set the last descriptor as the end-of-ring descriptor */
  456. p->des6 = host->sg_dma & 0xffffffff;
  457. p->des7 = (u64)host->sg_dma >> 32;
  458. p->des0 = IDMAC_DES0_ER;
  459. } else {
  460. struct idmac_desc *p;
  461. /* Number of descriptors in the ring buffer */
  462. host->ring_size =
  463. DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
  464. /* Forward link the descriptor list */
  465. for (i = 0, p = host->sg_cpu;
  466. i < host->ring_size - 1;
  467. i++, p++) {
  468. p->des3 = cpu_to_le32(host->sg_dma +
  469. (sizeof(struct idmac_desc) * (i + 1)));
  470. p->des0 = 0;
  471. p->des1 = 0;
  472. }
  473. /* Set the last descriptor as the end-of-ring descriptor */
  474. p->des3 = cpu_to_le32(host->sg_dma);
  475. p->des0 = cpu_to_le32(IDMAC_DES0_ER);
  476. }
  477. dw_mci_idmac_reset(host);
  478. if (host->dma_64bit_address == 1) {
  479. /* Mask out interrupts - get Tx & Rx complete only */
  480. mci_writel(host, IDSTS64, IDMAC_INT_CLR);
  481. mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
  482. SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
  483. /* Set the descriptor base address */
  484. mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
  485. mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
  486. } else {
  487. /* Mask out interrupts - get Tx & Rx complete only */
  488. mci_writel(host, IDSTS, IDMAC_INT_CLR);
  489. mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
  490. SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
  491. /* Set the descriptor base address */
  492. mci_writel(host, DBADDR, host->sg_dma);
  493. }
  494. return 0;
  495. }
  496. static inline int dw_mci_prepare_desc64(struct dw_mci *host,
  497. struct mmc_data *data,
  498. unsigned int sg_len)
  499. {
  500. unsigned int desc_len;
  501. struct idmac_desc_64addr *desc_first, *desc_last, *desc;
  502. u32 val;
  503. int i;
  504. desc_first = desc_last = desc = host->sg_cpu;
  505. for (i = 0; i < sg_len; i++) {
  506. unsigned int length = sg_dma_len(&data->sg[i]);
  507. u64 mem_addr = sg_dma_address(&data->sg[i]);
  508. for ( ; length ; desc++) {
  509. desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
  510. length : DW_MCI_DESC_DATA_LENGTH;
  511. length -= desc_len;
  512. /*
  513. * Wait for the former clear OWN bit operation
  514. * of IDMAC to make sure that this descriptor
  515. * isn't still owned by IDMAC as IDMAC's write
  516. * ops and CPU's read ops are asynchronous.
  517. */
  518. if (readl_poll_timeout_atomic(&desc->des0, val,
  519. !(val & IDMAC_DES0_OWN),
  520. 10, 100 * USEC_PER_MSEC))
  521. goto err_own_bit;
  522. /*
  523. * Set the OWN bit and disable interrupts
  524. * for this descriptor
  525. */
  526. desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
  527. IDMAC_DES0_CH;
  528. /* Buffer length */
  529. IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
  530. /* Physical address to DMA to/from */
  531. desc->des4 = mem_addr & 0xffffffff;
  532. desc->des5 = mem_addr >> 32;
  533. /* Update physical address for the next desc */
  534. mem_addr += desc_len;
  535. /* Save pointer to the last descriptor */
  536. desc_last = desc;
  537. }
  538. }
  539. /* Set first descriptor */
  540. desc_first->des0 |= IDMAC_DES0_FD;
  541. /* Set last descriptor */
  542. desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
  543. desc_last->des0 |= IDMAC_DES0_LD;
  544. return 0;
  545. err_own_bit:
  546. /* restore the descriptor chain as it's polluted */
  547. dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
  548. memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
  549. dw_mci_idmac_init(host);
  550. return -EINVAL;
  551. }
  552. static inline int dw_mci_prepare_desc32(struct dw_mci *host,
  553. struct mmc_data *data,
  554. unsigned int sg_len)
  555. {
  556. unsigned int desc_len;
  557. struct idmac_desc *desc_first, *desc_last, *desc;
  558. u32 val;
  559. int i;
  560. desc_first = desc_last = desc = host->sg_cpu;
  561. for (i = 0; i < sg_len; i++) {
  562. unsigned int length = sg_dma_len(&data->sg[i]);
  563. u32 mem_addr = sg_dma_address(&data->sg[i]);
  564. for ( ; length ; desc++) {
  565. desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
  566. length : DW_MCI_DESC_DATA_LENGTH;
  567. length -= desc_len;
  568. /*
  569. * Wait for the former clear OWN bit operation
  570. * of IDMAC to make sure that this descriptor
  571. * isn't still owned by IDMAC as IDMAC's write
  572. * ops and CPU's read ops are asynchronous.
  573. */
  574. if (readl_poll_timeout_atomic(&desc->des0, val,
  575. IDMAC_OWN_CLR64(val),
  576. 10,
  577. 100 * USEC_PER_MSEC))
  578. goto err_own_bit;
  579. /*
  580. * Set the OWN bit and disable interrupts
  581. * for this descriptor
  582. */
  583. desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
  584. IDMAC_DES0_DIC |
  585. IDMAC_DES0_CH);
  586. /* Buffer length */
  587. IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
  588. /* Physical address to DMA to/from */
  589. desc->des2 = cpu_to_le32(mem_addr);
  590. /* Update physical address for the next desc */
  591. mem_addr += desc_len;
  592. /* Save pointer to the last descriptor */
  593. desc_last = desc;
  594. }
  595. }
  596. /* Set first descriptor */
  597. desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
  598. /* Set last descriptor */
  599. desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
  600. IDMAC_DES0_DIC));
  601. desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
  602. return 0;
  603. err_own_bit:
  604. /* restore the descriptor chain as it's polluted */
  605. dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
  606. memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
  607. dw_mci_idmac_init(host);
  608. return -EINVAL;
  609. }
  610. static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
  611. {
  612. u32 temp;
  613. int ret;
  614. if (host->dma_64bit_address == 1)
  615. ret = dw_mci_prepare_desc64(host, host->data, sg_len);
  616. else
  617. ret = dw_mci_prepare_desc32(host, host->data, sg_len);
  618. if (ret)
  619. goto out;
  620. /* drain writebuffer */
  621. wmb();
  622. /* Make sure to reset DMA in case we did PIO before this */
  623. dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
  624. dw_mci_idmac_reset(host);
  625. /* Select IDMAC interface */
  626. temp = mci_readl(host, CTRL);
  627. temp |= SDMMC_CTRL_USE_IDMAC;
  628. mci_writel(host, CTRL, temp);
  629. /* drain writebuffer */
  630. wmb();
  631. /* Enable the IDMAC */
  632. temp = mci_readl(host, BMOD);
  633. temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
  634. mci_writel(host, BMOD, temp);
  635. /* Start it running */
  636. mci_writel(host, PLDMND, 1);
  637. out:
  638. return ret;
  639. }
  640. static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
  641. .init = dw_mci_idmac_init,
  642. .start = dw_mci_idmac_start_dma,
  643. .stop = dw_mci_idmac_stop_dma,
  644. .complete = dw_mci_dmac_complete_dma,
  645. .cleanup = dw_mci_dma_cleanup,
  646. };
  647. static void dw_mci_edmac_stop_dma(struct dw_mci *host)
  648. {
  649. dmaengine_terminate_async(host->dms->ch);
  650. }
  651. static int dw_mci_edmac_start_dma(struct dw_mci *host,
  652. unsigned int sg_len)
  653. {
  654. struct dma_slave_config cfg;
  655. struct dma_async_tx_descriptor *desc = NULL;
  656. struct scatterlist *sgl = host->data->sg;
  657. static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  658. u32 sg_elems = host->data->sg_len;
  659. u32 fifoth_val;
  660. u32 fifo_offset = host->fifo_reg - host->regs;
  661. int ret = 0;
  662. /* Set external dma config: burst size, burst width */
  663. cfg.dst_addr = host->phy_regs + fifo_offset;
  664. cfg.src_addr = cfg.dst_addr;
  665. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  666. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  667. /* Match burst msize with external dma config */
  668. fifoth_val = mci_readl(host, FIFOTH);
  669. cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
  670. cfg.src_maxburst = cfg.dst_maxburst;
  671. if (host->data->flags & MMC_DATA_WRITE)
  672. cfg.direction = DMA_MEM_TO_DEV;
  673. else
  674. cfg.direction = DMA_DEV_TO_MEM;
  675. ret = dmaengine_slave_config(host->dms->ch, &cfg);
  676. if (ret) {
  677. dev_err(host->dev, "Failed to config edmac.\n");
  678. return -EBUSY;
  679. }
  680. desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
  681. sg_len, cfg.direction,
  682. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  683. if (!desc) {
  684. dev_err(host->dev, "Can't prepare slave sg.\n");
  685. return -EBUSY;
  686. }
  687. /* Set dw_mci_dmac_complete_dma as callback */
  688. desc->callback = dw_mci_dmac_complete_dma;
  689. desc->callback_param = (void *)host;
  690. dmaengine_submit(desc);
  691. /* Flush cache before write */
  692. if (host->data->flags & MMC_DATA_WRITE)
  693. dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
  694. sg_elems, DMA_TO_DEVICE);
  695. dma_async_issue_pending(host->dms->ch);
  696. return 0;
  697. }
  698. static int dw_mci_edmac_init(struct dw_mci *host)
  699. {
  700. /* Request external dma channel */
  701. host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
  702. if (!host->dms)
  703. return -ENOMEM;
  704. host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
  705. if (!host->dms->ch) {
  706. dev_err(host->dev, "Failed to get external DMA channel.\n");
  707. kfree(host->dms);
  708. host->dms = NULL;
  709. return -ENXIO;
  710. }
  711. return 0;
  712. }
  713. static void dw_mci_edmac_exit(struct dw_mci *host)
  714. {
  715. if (host->dms) {
  716. if (host->dms->ch) {
  717. dma_release_channel(host->dms->ch);
  718. host->dms->ch = NULL;
  719. }
  720. kfree(host->dms);
  721. host->dms = NULL;
  722. }
  723. }
  724. static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
  725. .init = dw_mci_edmac_init,
  726. .exit = dw_mci_edmac_exit,
  727. .start = dw_mci_edmac_start_dma,
  728. .stop = dw_mci_edmac_stop_dma,
  729. .complete = dw_mci_dmac_complete_dma,
  730. .cleanup = dw_mci_dma_cleanup,
  731. };
  732. static int dw_mci_pre_dma_transfer(struct dw_mci *host,
  733. struct mmc_data *data,
  734. int cookie)
  735. {
  736. struct scatterlist *sg;
  737. unsigned int i, sg_len;
  738. if (data->host_cookie == COOKIE_PRE_MAPPED)
  739. return data->sg_len;
  740. /*
  741. * We don't do DMA on "complex" transfers, i.e. with
  742. * non-word-aligned buffers or lengths. Also, we don't bother
  743. * with all the DMA setup overhead for short transfers.
  744. */
  745. if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
  746. return -EINVAL;
  747. if (data->blksz & 3)
  748. return -EINVAL;
  749. for_each_sg(data->sg, sg, data->sg_len, i) {
  750. if (sg->offset & 3 || sg->length & 3)
  751. return -EINVAL;
  752. }
  753. sg_len = dma_map_sg(host->dev,
  754. data->sg,
  755. data->sg_len,
  756. mmc_get_dma_dir(data));
  757. if (sg_len == 0)
  758. return -EINVAL;
  759. data->host_cookie = cookie;
  760. return sg_len;
  761. }
  762. static void dw_mci_pre_req(struct mmc_host *mmc,
  763. struct mmc_request *mrq)
  764. {
  765. struct dw_mci_slot *slot = mmc_priv(mmc);
  766. struct mmc_data *data = mrq->data;
  767. if (!slot->host->use_dma || !data)
  768. return;
  769. /* This data might be unmapped at this time */
  770. data->host_cookie = COOKIE_UNMAPPED;
  771. if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
  772. COOKIE_PRE_MAPPED) < 0)
  773. data->host_cookie = COOKIE_UNMAPPED;
  774. }
  775. static void dw_mci_post_req(struct mmc_host *mmc,
  776. struct mmc_request *mrq,
  777. int err)
  778. {
  779. struct dw_mci_slot *slot = mmc_priv(mmc);
  780. struct mmc_data *data = mrq->data;
  781. if (!slot->host->use_dma || !data)
  782. return;
  783. if (data->host_cookie != COOKIE_UNMAPPED)
  784. dma_unmap_sg(slot->host->dev,
  785. data->sg,
  786. data->sg_len,
  787. mmc_get_dma_dir(data));
  788. data->host_cookie = COOKIE_UNMAPPED;
  789. }
  790. static int dw_mci_get_cd(struct mmc_host *mmc)
  791. {
  792. int present;
  793. struct dw_mci_slot *slot = mmc_priv(mmc);
  794. struct dw_mci *host = slot->host;
  795. int gpio_cd = mmc_gpio_get_cd(mmc);
  796. /* Use platform get_cd function, else try onboard card detect */
  797. if (((mmc->caps & MMC_CAP_NEEDS_POLL)
  798. || !mmc_card_is_removable(mmc))) {
  799. present = 1;
  800. if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
  801. if (mmc->caps & MMC_CAP_NEEDS_POLL) {
  802. dev_info(&mmc->class_dev,
  803. "card is polling.\n");
  804. } else {
  805. dev_info(&mmc->class_dev,
  806. "card is non-removable.\n");
  807. }
  808. set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  809. }
  810. return present;
  811. } else if (gpio_cd >= 0)
  812. present = gpio_cd;
  813. else
  814. present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
  815. == 0 ? 1 : 0;
  816. spin_lock_bh(&host->lock);
  817. if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
  818. dev_dbg(&mmc->class_dev, "card is present\n");
  819. else if (!present &&
  820. !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
  821. dev_dbg(&mmc->class_dev, "card is not present\n");
  822. spin_unlock_bh(&host->lock);
  823. return present;
  824. }
  825. static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
  826. {
  827. unsigned int blksz = data->blksz;
  828. static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  829. u32 fifo_width = 1 << host->data_shift;
  830. u32 blksz_depth = blksz / fifo_width, fifoth_val;
  831. u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
  832. int idx = ARRAY_SIZE(mszs) - 1;
  833. /* pio should ship this scenario */
  834. if (!host->use_dma)
  835. return;
  836. tx_wmark = (host->fifo_depth) / 2;
  837. tx_wmark_invers = host->fifo_depth - tx_wmark;
  838. /*
  839. * MSIZE is '1',
  840. * if blksz is not a multiple of the FIFO width
  841. */
  842. if (blksz % fifo_width)
  843. goto done;
  844. do {
  845. if (!((blksz_depth % mszs[idx]) ||
  846. (tx_wmark_invers % mszs[idx]))) {
  847. msize = idx;
  848. rx_wmark = mszs[idx] - 1;
  849. break;
  850. }
  851. } while (--idx > 0);
  852. /*
  853. * If idx is '0', it won't be tried
  854. * Thus, initial values are uesed
  855. */
  856. done:
  857. fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
  858. mci_writel(host, FIFOTH, fifoth_val);
  859. }
  860. static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
  861. {
  862. unsigned int blksz = data->blksz;
  863. u32 blksz_depth, fifo_depth;
  864. u16 thld_size;
  865. u8 enable;
  866. /*
  867. * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
  868. * in the FIFO region, so we really shouldn't access it).
  869. */
  870. if (host->verid < DW_MMC_240A ||
  871. (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
  872. return;
  873. /*
  874. * Card write Threshold is introduced since 2.80a
  875. * It's used when HS400 mode is enabled.
  876. */
  877. if (data->flags & MMC_DATA_WRITE &&
  878. !(host->timing != MMC_TIMING_MMC_HS400))
  879. return;
  880. if (data->flags & MMC_DATA_WRITE)
  881. enable = SDMMC_CARD_WR_THR_EN;
  882. else
  883. enable = SDMMC_CARD_RD_THR_EN;
  884. if (host->timing != MMC_TIMING_MMC_HS200 &&
  885. host->timing != MMC_TIMING_UHS_SDR104)
  886. goto disable;
  887. blksz_depth = blksz / (1 << host->data_shift);
  888. fifo_depth = host->fifo_depth;
  889. if (blksz_depth > fifo_depth)
  890. goto disable;
  891. /*
  892. * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
  893. * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
  894. * Currently just choose blksz.
  895. */
  896. thld_size = blksz;
  897. mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
  898. return;
  899. disable:
  900. mci_writel(host, CDTHRCTL, 0);
  901. }
  902. static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
  903. {
  904. unsigned long irqflags;
  905. int sg_len;
  906. u32 temp;
  907. host->using_dma = 0;
  908. /* If we don't have a channel, we can't do DMA */
  909. if (!host->use_dma)
  910. return -ENODEV;
  911. sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
  912. if (sg_len < 0) {
  913. host->dma_ops->stop(host);
  914. return sg_len;
  915. }
  916. host->using_dma = 1;
  917. if (host->use_dma == TRANS_MODE_IDMAC)
  918. dev_vdbg(host->dev,
  919. "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
  920. (unsigned long)host->sg_cpu,
  921. (unsigned long)host->sg_dma,
  922. sg_len);
  923. /*
  924. * Decide the MSIZE and RX/TX Watermark.
  925. * If current block size is same with previous size,
  926. * no need to update fifoth.
  927. */
  928. if (host->prev_blksz != data->blksz)
  929. dw_mci_adjust_fifoth(host, data);
  930. /* Enable the DMA interface */
  931. temp = mci_readl(host, CTRL);
  932. temp |= SDMMC_CTRL_DMA_ENABLE;
  933. mci_writel(host, CTRL, temp);
  934. /* Disable RX/TX IRQs, let DMA handle it */
  935. spin_lock_irqsave(&host->irq_lock, irqflags);
  936. temp = mci_readl(host, INTMASK);
  937. temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
  938. mci_writel(host, INTMASK, temp);
  939. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  940. if (host->dma_ops->start(host, sg_len)) {
  941. host->dma_ops->stop(host);
  942. /* We can't do DMA, try PIO for this one */
  943. dev_dbg(host->dev,
  944. "%s: fall back to PIO mode for current transfer\n",
  945. __func__);
  946. return -ENODEV;
  947. }
  948. return 0;
  949. }
  950. static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
  951. {
  952. unsigned long irqflags;
  953. int flags = SG_MITER_ATOMIC;
  954. u32 temp;
  955. data->error = -EINPROGRESS;
  956. WARN_ON(host->data);
  957. host->sg = NULL;
  958. host->data = data;
  959. if (data->flags & MMC_DATA_READ)
  960. host->dir_status = DW_MCI_RECV_STATUS;
  961. else
  962. host->dir_status = DW_MCI_SEND_STATUS;
  963. dw_mci_ctrl_thld(host, data);
  964. if (dw_mci_submit_data_dma(host, data)) {
  965. if (host->data->flags & MMC_DATA_READ)
  966. flags |= SG_MITER_TO_SG;
  967. else
  968. flags |= SG_MITER_FROM_SG;
  969. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  970. host->sg = data->sg;
  971. host->part_buf_start = 0;
  972. host->part_buf_count = 0;
  973. mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
  974. spin_lock_irqsave(&host->irq_lock, irqflags);
  975. temp = mci_readl(host, INTMASK);
  976. temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
  977. mci_writel(host, INTMASK, temp);
  978. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  979. temp = mci_readl(host, CTRL);
  980. temp &= ~SDMMC_CTRL_DMA_ENABLE;
  981. mci_writel(host, CTRL, temp);
  982. /*
  983. * Use the initial fifoth_val for PIO mode. If wm_algined
  984. * is set, we set watermark same as data size.
  985. * If next issued data may be transfered by DMA mode,
  986. * prev_blksz should be invalidated.
  987. */
  988. if (host->wm_aligned)
  989. dw_mci_adjust_fifoth(host, data);
  990. else
  991. mci_writel(host, FIFOTH, host->fifoth_val);
  992. host->prev_blksz = 0;
  993. } else {
  994. /*
  995. * Keep the current block size.
  996. * It will be used to decide whether to update
  997. * fifoth register next time.
  998. */
  999. host->prev_blksz = data->blksz;
  1000. }
  1001. }
  1002. static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
  1003. {
  1004. struct dw_mci *host = slot->host;
  1005. unsigned int clock = slot->clock;
  1006. u32 div;
  1007. u32 clk_en_a;
  1008. u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
  1009. /* We must continue to set bit 28 in CMD until the change is complete */
  1010. if (host->state == STATE_WAITING_CMD11_DONE)
  1011. sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
  1012. if (!clock) {
  1013. mci_writel(host, CLKENA, 0);
  1014. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1015. } else if (clock != host->current_speed || force_clkinit) {
  1016. div = host->bus_hz / clock;
  1017. if (host->bus_hz % clock && host->bus_hz > clock)
  1018. /*
  1019. * move the + 1 after the divide to prevent
  1020. * over-clocking the card.
  1021. */
  1022. div += 1;
  1023. div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
  1024. if ((clock != slot->__clk_old &&
  1025. !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
  1026. force_clkinit) {
  1027. /* Silent the verbose log if calling from PM context */
  1028. if (!force_clkinit)
  1029. dev_info(&slot->mmc->class_dev,
  1030. "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
  1031. slot->id, host->bus_hz, clock,
  1032. div ? ((host->bus_hz / div) >> 1) :
  1033. host->bus_hz, div);
  1034. /*
  1035. * If card is polling, display the message only
  1036. * one time at boot time.
  1037. */
  1038. if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
  1039. slot->mmc->f_min == clock)
  1040. set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
  1041. }
  1042. /* disable clock */
  1043. mci_writel(host, CLKENA, 0);
  1044. mci_writel(host, CLKSRC, 0);
  1045. /* inform CIU */
  1046. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1047. /* set clock to desired speed */
  1048. mci_writel(host, CLKDIV, div);
  1049. /* inform CIU */
  1050. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1051. /* enable clock; only low power if no SDIO */
  1052. clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
  1053. if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
  1054. clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
  1055. mci_writel(host, CLKENA, clk_en_a);
  1056. /* inform CIU */
  1057. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1058. /* keep the last clock value that was requested from core */
  1059. slot->__clk_old = clock;
  1060. }
  1061. host->current_speed = clock;
  1062. /* Set the current slot bus width */
  1063. mci_writel(host, CTYPE, (slot->ctype << slot->id));
  1064. }
  1065. static void __dw_mci_start_request(struct dw_mci *host,
  1066. struct dw_mci_slot *slot,
  1067. struct mmc_command *cmd)
  1068. {
  1069. struct mmc_request *mrq;
  1070. struct mmc_data *data;
  1071. u32 cmdflags;
  1072. mrq = slot->mrq;
  1073. host->mrq = mrq;
  1074. host->pending_events = 0;
  1075. host->completed_events = 0;
  1076. host->cmd_status = 0;
  1077. host->data_status = 0;
  1078. host->dir_status = 0;
  1079. data = cmd->data;
  1080. if (data) {
  1081. mci_writel(host, TMOUT, 0xFFFFFFFF);
  1082. mci_writel(host, BYTCNT, data->blksz*data->blocks);
  1083. mci_writel(host, BLKSIZ, data->blksz);
  1084. }
  1085. cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
  1086. /* this is the first command, send the initialization clock */
  1087. if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
  1088. cmdflags |= SDMMC_CMD_INIT;
  1089. if (data) {
  1090. dw_mci_submit_data(host, data);
  1091. wmb(); /* drain writebuffer */
  1092. }
  1093. dw_mci_start_command(host, cmd, cmdflags);
  1094. if (cmd->opcode == SD_SWITCH_VOLTAGE) {
  1095. unsigned long irqflags;
  1096. /*
  1097. * Databook says to fail after 2ms w/ no response, but evidence
  1098. * shows that sometimes the cmd11 interrupt takes over 130ms.
  1099. * We'll set to 500ms, plus an extra jiffy just in case jiffies
  1100. * is just about to roll over.
  1101. *
  1102. * We do this whole thing under spinlock and only if the
  1103. * command hasn't already completed (indicating the the irq
  1104. * already ran so we don't want the timeout).
  1105. */
  1106. spin_lock_irqsave(&host->irq_lock, irqflags);
  1107. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  1108. mod_timer(&host->cmd11_timer,
  1109. jiffies + msecs_to_jiffies(500) + 1);
  1110. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1111. }
  1112. host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
  1113. }
  1114. static void dw_mci_start_request(struct dw_mci *host,
  1115. struct dw_mci_slot *slot)
  1116. {
  1117. struct mmc_request *mrq = slot->mrq;
  1118. struct mmc_command *cmd;
  1119. cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
  1120. __dw_mci_start_request(host, slot, cmd);
  1121. }
  1122. /* must be called with host->lock held */
  1123. static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
  1124. struct mmc_request *mrq)
  1125. {
  1126. dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
  1127. host->state);
  1128. slot->mrq = mrq;
  1129. if (host->state == STATE_WAITING_CMD11_DONE) {
  1130. dev_warn(&slot->mmc->class_dev,
  1131. "Voltage change didn't complete\n");
  1132. /*
  1133. * this case isn't expected to happen, so we can
  1134. * either crash here or just try to continue on
  1135. * in the closest possible state
  1136. */
  1137. host->state = STATE_IDLE;
  1138. }
  1139. if (host->state == STATE_IDLE) {
  1140. host->state = STATE_SENDING_CMD;
  1141. dw_mci_start_request(host, slot);
  1142. } else {
  1143. list_add_tail(&slot->queue_node, &host->queue);
  1144. }
  1145. }
  1146. static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  1147. {
  1148. struct dw_mci_slot *slot = mmc_priv(mmc);
  1149. struct dw_mci *host = slot->host;
  1150. WARN_ON(slot->mrq);
  1151. /*
  1152. * The check for card presence and queueing of the request must be
  1153. * atomic, otherwise the card could be removed in between and the
  1154. * request wouldn't fail until another card was inserted.
  1155. */
  1156. if (!dw_mci_get_cd(mmc)) {
  1157. mrq->cmd->error = -ENOMEDIUM;
  1158. mmc_request_done(mmc, mrq);
  1159. return;
  1160. }
  1161. spin_lock_bh(&host->lock);
  1162. dw_mci_queue_request(host, slot, mrq);
  1163. spin_unlock_bh(&host->lock);
  1164. }
  1165. static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1166. {
  1167. struct dw_mci_slot *slot = mmc_priv(mmc);
  1168. const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
  1169. u32 regs;
  1170. int ret;
  1171. switch (ios->bus_width) {
  1172. case MMC_BUS_WIDTH_4:
  1173. slot->ctype = SDMMC_CTYPE_4BIT;
  1174. break;
  1175. case MMC_BUS_WIDTH_8:
  1176. slot->ctype = SDMMC_CTYPE_8BIT;
  1177. break;
  1178. default:
  1179. /* set default 1 bit mode */
  1180. slot->ctype = SDMMC_CTYPE_1BIT;
  1181. }
  1182. regs = mci_readl(slot->host, UHS_REG);
  1183. /* DDR mode set */
  1184. if (ios->timing == MMC_TIMING_MMC_DDR52 ||
  1185. ios->timing == MMC_TIMING_UHS_DDR50 ||
  1186. ios->timing == MMC_TIMING_MMC_HS400)
  1187. regs |= ((0x1 << slot->id) << 16);
  1188. else
  1189. regs &= ~((0x1 << slot->id) << 16);
  1190. mci_writel(slot->host, UHS_REG, regs);
  1191. slot->host->timing = ios->timing;
  1192. /*
  1193. * Use mirror of ios->clock to prevent race with mmc
  1194. * core ios update when finding the minimum.
  1195. */
  1196. slot->clock = ios->clock;
  1197. if (drv_data && drv_data->set_ios)
  1198. drv_data->set_ios(slot->host, ios);
  1199. switch (ios->power_mode) {
  1200. case MMC_POWER_UP:
  1201. if (!IS_ERR(mmc->supply.vmmc)) {
  1202. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
  1203. ios->vdd);
  1204. if (ret) {
  1205. dev_err(slot->host->dev,
  1206. "failed to enable vmmc regulator\n");
  1207. /*return, if failed turn on vmmc*/
  1208. return;
  1209. }
  1210. }
  1211. set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
  1212. regs = mci_readl(slot->host, PWREN);
  1213. regs |= (1 << slot->id);
  1214. mci_writel(slot->host, PWREN, regs);
  1215. break;
  1216. case MMC_POWER_ON:
  1217. if (!slot->host->vqmmc_enabled) {
  1218. if (!IS_ERR(mmc->supply.vqmmc)) {
  1219. ret = regulator_enable(mmc->supply.vqmmc);
  1220. if (ret < 0)
  1221. dev_err(slot->host->dev,
  1222. "failed to enable vqmmc\n");
  1223. else
  1224. slot->host->vqmmc_enabled = true;
  1225. } else {
  1226. /* Keep track so we don't reset again */
  1227. slot->host->vqmmc_enabled = true;
  1228. }
  1229. /* Reset our state machine after powering on */
  1230. dw_mci_ctrl_reset(slot->host,
  1231. SDMMC_CTRL_ALL_RESET_FLAGS);
  1232. }
  1233. /* Adjust clock / bus width after power is up */
  1234. dw_mci_setup_bus(slot, false);
  1235. break;
  1236. case MMC_POWER_OFF:
  1237. /* Turn clock off before power goes down */
  1238. dw_mci_setup_bus(slot, false);
  1239. if (!IS_ERR(mmc->supply.vmmc))
  1240. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  1241. if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
  1242. regulator_disable(mmc->supply.vqmmc);
  1243. slot->host->vqmmc_enabled = false;
  1244. regs = mci_readl(slot->host, PWREN);
  1245. regs &= ~(1 << slot->id);
  1246. mci_writel(slot->host, PWREN, regs);
  1247. break;
  1248. default:
  1249. break;
  1250. }
  1251. if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
  1252. slot->host->state = STATE_IDLE;
  1253. }
  1254. static int dw_mci_card_busy(struct mmc_host *mmc)
  1255. {
  1256. struct dw_mci_slot *slot = mmc_priv(mmc);
  1257. u32 status;
  1258. /*
  1259. * Check the busy bit which is low when DAT[3:0]
  1260. * (the data lines) are 0000
  1261. */
  1262. status = mci_readl(slot->host, STATUS);
  1263. return !!(status & SDMMC_STATUS_BUSY);
  1264. }
  1265. static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
  1266. {
  1267. struct dw_mci_slot *slot = mmc_priv(mmc);
  1268. struct dw_mci *host = slot->host;
  1269. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1270. u32 uhs;
  1271. u32 v18 = SDMMC_UHS_18V << slot->id;
  1272. int ret;
  1273. if (drv_data && drv_data->switch_voltage)
  1274. return drv_data->switch_voltage(mmc, ios);
  1275. /*
  1276. * Program the voltage. Note that some instances of dw_mmc may use
  1277. * the UHS_REG for this. For other instances (like exynos) the UHS_REG
  1278. * does no harm but you need to set the regulator directly. Try both.
  1279. */
  1280. uhs = mci_readl(host, UHS_REG);
  1281. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  1282. uhs &= ~v18;
  1283. else
  1284. uhs |= v18;
  1285. if (!IS_ERR(mmc->supply.vqmmc)) {
  1286. ret = mmc_regulator_set_vqmmc(mmc, ios);
  1287. if (ret) {
  1288. dev_dbg(&mmc->class_dev,
  1289. "Regulator set error %d - %s V\n",
  1290. ret, uhs & v18 ? "1.8" : "3.3");
  1291. return ret;
  1292. }
  1293. }
  1294. mci_writel(host, UHS_REG, uhs);
  1295. return 0;
  1296. }
  1297. static int dw_mci_get_ro(struct mmc_host *mmc)
  1298. {
  1299. int read_only;
  1300. struct dw_mci_slot *slot = mmc_priv(mmc);
  1301. int gpio_ro = mmc_gpio_get_ro(mmc);
  1302. /* Use platform get_ro function, else try on board write protect */
  1303. if (gpio_ro >= 0)
  1304. read_only = gpio_ro;
  1305. else
  1306. read_only =
  1307. mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
  1308. dev_dbg(&mmc->class_dev, "card is %s\n",
  1309. read_only ? "read-only" : "read-write");
  1310. return read_only;
  1311. }
  1312. static void dw_mci_hw_reset(struct mmc_host *mmc)
  1313. {
  1314. struct dw_mci_slot *slot = mmc_priv(mmc);
  1315. struct dw_mci *host = slot->host;
  1316. int reset;
  1317. if (host->use_dma == TRANS_MODE_IDMAC)
  1318. dw_mci_idmac_reset(host);
  1319. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
  1320. SDMMC_CTRL_FIFO_RESET))
  1321. return;
  1322. /*
  1323. * According to eMMC spec, card reset procedure:
  1324. * tRstW >= 1us: RST_n pulse width
  1325. * tRSCA >= 200us: RST_n to Command time
  1326. * tRSTH >= 1us: RST_n high period
  1327. */
  1328. reset = mci_readl(host, RST_N);
  1329. reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
  1330. mci_writel(host, RST_N, reset);
  1331. usleep_range(1, 2);
  1332. reset |= SDMMC_RST_HWACTIVE << slot->id;
  1333. mci_writel(host, RST_N, reset);
  1334. usleep_range(200, 300);
  1335. }
  1336. static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1337. {
  1338. struct dw_mci_slot *slot = mmc_priv(mmc);
  1339. struct dw_mci *host = slot->host;
  1340. /*
  1341. * Low power mode will stop the card clock when idle. According to the
  1342. * description of the CLKENA register we should disable low power mode
  1343. * for SDIO cards if we need SDIO interrupts to work.
  1344. */
  1345. if (mmc->caps & MMC_CAP_SDIO_IRQ) {
  1346. const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
  1347. u32 clk_en_a_old;
  1348. u32 clk_en_a;
  1349. clk_en_a_old = mci_readl(host, CLKENA);
  1350. if (card->type == MMC_TYPE_SDIO ||
  1351. card->type == MMC_TYPE_SD_COMBO) {
  1352. set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
  1353. clk_en_a = clk_en_a_old & ~clken_low_pwr;
  1354. } else {
  1355. clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
  1356. clk_en_a = clk_en_a_old | clken_low_pwr;
  1357. }
  1358. if (clk_en_a != clk_en_a_old) {
  1359. mci_writel(host, CLKENA, clk_en_a);
  1360. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  1361. SDMMC_CMD_PRV_DAT_WAIT, 0);
  1362. }
  1363. }
  1364. }
  1365. static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
  1366. {
  1367. struct dw_mci *host = slot->host;
  1368. unsigned long irqflags;
  1369. u32 int_mask;
  1370. spin_lock_irqsave(&host->irq_lock, irqflags);
  1371. /* Enable/disable Slot Specific SDIO interrupt */
  1372. int_mask = mci_readl(host, INTMASK);
  1373. if (enb)
  1374. int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
  1375. else
  1376. int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
  1377. mci_writel(host, INTMASK, int_mask);
  1378. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1379. }
  1380. static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
  1381. {
  1382. struct dw_mci_slot *slot = mmc_priv(mmc);
  1383. struct dw_mci *host = slot->host;
  1384. __dw_mci_enable_sdio_irq(slot, enb);
  1385. /* Avoid runtime suspending the device when SDIO IRQ is enabled */
  1386. if (enb)
  1387. pm_runtime_get_noresume(host->dev);
  1388. else
  1389. pm_runtime_put_noidle(host->dev);
  1390. }
  1391. static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
  1392. {
  1393. struct dw_mci_slot *slot = mmc_priv(mmc);
  1394. __dw_mci_enable_sdio_irq(slot, 1);
  1395. }
  1396. static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
  1397. {
  1398. struct dw_mci_slot *slot = mmc_priv(mmc);
  1399. struct dw_mci *host = slot->host;
  1400. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1401. int err = -EINVAL;
  1402. if (drv_data && drv_data->execute_tuning)
  1403. err = drv_data->execute_tuning(slot, opcode);
  1404. return err;
  1405. }
  1406. static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
  1407. struct mmc_ios *ios)
  1408. {
  1409. struct dw_mci_slot *slot = mmc_priv(mmc);
  1410. struct dw_mci *host = slot->host;
  1411. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1412. if (drv_data && drv_data->prepare_hs400_tuning)
  1413. return drv_data->prepare_hs400_tuning(host, ios);
  1414. return 0;
  1415. }
  1416. static bool dw_mci_reset(struct dw_mci *host)
  1417. {
  1418. u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
  1419. bool ret = false;
  1420. u32 status = 0;
  1421. /*
  1422. * Resetting generates a block interrupt, hence setting
  1423. * the scatter-gather pointer to NULL.
  1424. */
  1425. if (host->sg) {
  1426. sg_miter_stop(&host->sg_miter);
  1427. host->sg = NULL;
  1428. }
  1429. if (host->use_dma)
  1430. flags |= SDMMC_CTRL_DMA_RESET;
  1431. if (dw_mci_ctrl_reset(host, flags)) {
  1432. /*
  1433. * In all cases we clear the RAWINTS
  1434. * register to clear any interrupts.
  1435. */
  1436. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  1437. if (!host->use_dma) {
  1438. ret = true;
  1439. goto ciu_out;
  1440. }
  1441. /* Wait for dma_req to be cleared */
  1442. if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
  1443. status,
  1444. !(status & SDMMC_STATUS_DMA_REQ),
  1445. 1, 500 * USEC_PER_MSEC)) {
  1446. dev_err(host->dev,
  1447. "%s: Timeout waiting for dma_req to be cleared\n",
  1448. __func__);
  1449. goto ciu_out;
  1450. }
  1451. /* when using DMA next we reset the fifo again */
  1452. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
  1453. goto ciu_out;
  1454. } else {
  1455. /* if the controller reset bit did clear, then set clock regs */
  1456. if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
  1457. dev_err(host->dev,
  1458. "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
  1459. __func__);
  1460. goto ciu_out;
  1461. }
  1462. }
  1463. if (host->use_dma == TRANS_MODE_IDMAC)
  1464. /* It is also required that we reinit idmac */
  1465. dw_mci_idmac_init(host);
  1466. ret = true;
  1467. ciu_out:
  1468. /* After a CTRL reset we need to have CIU set clock registers */
  1469. mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
  1470. return ret;
  1471. }
  1472. static const struct mmc_host_ops dw_mci_ops = {
  1473. .request = dw_mci_request,
  1474. .pre_req = dw_mci_pre_req,
  1475. .post_req = dw_mci_post_req,
  1476. .set_ios = dw_mci_set_ios,
  1477. .get_ro = dw_mci_get_ro,
  1478. .get_cd = dw_mci_get_cd,
  1479. .hw_reset = dw_mci_hw_reset,
  1480. .enable_sdio_irq = dw_mci_enable_sdio_irq,
  1481. .ack_sdio_irq = dw_mci_ack_sdio_irq,
  1482. .execute_tuning = dw_mci_execute_tuning,
  1483. .card_busy = dw_mci_card_busy,
  1484. .start_signal_voltage_switch = dw_mci_switch_voltage,
  1485. .init_card = dw_mci_init_card,
  1486. .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
  1487. };
  1488. static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
  1489. __releases(&host->lock)
  1490. __acquires(&host->lock)
  1491. {
  1492. struct dw_mci_slot *slot;
  1493. struct mmc_host *prev_mmc = host->slot->mmc;
  1494. WARN_ON(host->cmd || host->data);
  1495. host->slot->mrq = NULL;
  1496. host->mrq = NULL;
  1497. if (!list_empty(&host->queue)) {
  1498. slot = list_entry(host->queue.next,
  1499. struct dw_mci_slot, queue_node);
  1500. list_del(&slot->queue_node);
  1501. dev_vdbg(host->dev, "list not empty: %s is next\n",
  1502. mmc_hostname(slot->mmc));
  1503. host->state = STATE_SENDING_CMD;
  1504. dw_mci_start_request(host, slot);
  1505. } else {
  1506. dev_vdbg(host->dev, "list empty\n");
  1507. if (host->state == STATE_SENDING_CMD11)
  1508. host->state = STATE_WAITING_CMD11_DONE;
  1509. else
  1510. host->state = STATE_IDLE;
  1511. }
  1512. spin_unlock(&host->lock);
  1513. mmc_request_done(prev_mmc, mrq);
  1514. spin_lock(&host->lock);
  1515. }
  1516. static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
  1517. {
  1518. u32 status = host->cmd_status;
  1519. host->cmd_status = 0;
  1520. /* Read the response from the card (up to 16 bytes) */
  1521. if (cmd->flags & MMC_RSP_PRESENT) {
  1522. if (cmd->flags & MMC_RSP_136) {
  1523. cmd->resp[3] = mci_readl(host, RESP0);
  1524. cmd->resp[2] = mci_readl(host, RESP1);
  1525. cmd->resp[1] = mci_readl(host, RESP2);
  1526. cmd->resp[0] = mci_readl(host, RESP3);
  1527. } else {
  1528. cmd->resp[0] = mci_readl(host, RESP0);
  1529. cmd->resp[1] = 0;
  1530. cmd->resp[2] = 0;
  1531. cmd->resp[3] = 0;
  1532. }
  1533. }
  1534. if (status & SDMMC_INT_RTO)
  1535. cmd->error = -ETIMEDOUT;
  1536. else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
  1537. cmd->error = -EILSEQ;
  1538. else if (status & SDMMC_INT_RESP_ERR)
  1539. cmd->error = -EIO;
  1540. else
  1541. cmd->error = 0;
  1542. return cmd->error;
  1543. }
  1544. static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
  1545. {
  1546. u32 status = host->data_status;
  1547. if (status & DW_MCI_DATA_ERROR_FLAGS) {
  1548. if (status & SDMMC_INT_DRTO) {
  1549. data->error = -ETIMEDOUT;
  1550. } else if (status & SDMMC_INT_DCRC) {
  1551. data->error = -EILSEQ;
  1552. } else if (status & SDMMC_INT_EBE) {
  1553. if (host->dir_status ==
  1554. DW_MCI_SEND_STATUS) {
  1555. /*
  1556. * No data CRC status was returned.
  1557. * The number of bytes transferred
  1558. * will be exaggerated in PIO mode.
  1559. */
  1560. data->bytes_xfered = 0;
  1561. data->error = -ETIMEDOUT;
  1562. } else if (host->dir_status ==
  1563. DW_MCI_RECV_STATUS) {
  1564. data->error = -EILSEQ;
  1565. }
  1566. } else {
  1567. /* SDMMC_INT_SBE is included */
  1568. data->error = -EILSEQ;
  1569. }
  1570. dev_dbg(host->dev, "data error, status 0x%08x\n", status);
  1571. /*
  1572. * After an error, there may be data lingering
  1573. * in the FIFO
  1574. */
  1575. dw_mci_reset(host);
  1576. } else {
  1577. data->bytes_xfered = data->blocks * data->blksz;
  1578. data->error = 0;
  1579. }
  1580. return data->error;
  1581. }
  1582. static void dw_mci_set_drto(struct dw_mci *host)
  1583. {
  1584. unsigned int drto_clks;
  1585. unsigned int drto_div;
  1586. unsigned int drto_ms;
  1587. unsigned long irqflags;
  1588. drto_clks = mci_readl(host, TMOUT) >> 8;
  1589. drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
  1590. if (drto_div == 0)
  1591. drto_div = 1;
  1592. drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
  1593. host->bus_hz);
  1594. /* add a bit spare time */
  1595. drto_ms += 10;
  1596. spin_lock_irqsave(&host->irq_lock, irqflags);
  1597. if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
  1598. mod_timer(&host->dto_timer,
  1599. jiffies + msecs_to_jiffies(drto_ms));
  1600. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1601. }
  1602. static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
  1603. {
  1604. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  1605. return false;
  1606. /*
  1607. * Really be certain that the timer has stopped. This is a bit of
  1608. * paranoia and could only really happen if we had really bad
  1609. * interrupt latency and the interrupt routine and timeout were
  1610. * running concurrently so that the del_timer() in the interrupt
  1611. * handler couldn't run.
  1612. */
  1613. WARN_ON(del_timer_sync(&host->cto_timer));
  1614. clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  1615. return true;
  1616. }
  1617. static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
  1618. {
  1619. if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
  1620. return false;
  1621. /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
  1622. WARN_ON(del_timer_sync(&host->dto_timer));
  1623. clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  1624. return true;
  1625. }
  1626. static void dw_mci_tasklet_func(unsigned long priv)
  1627. {
  1628. struct dw_mci *host = (struct dw_mci *)priv;
  1629. struct mmc_data *data;
  1630. struct mmc_command *cmd;
  1631. struct mmc_request *mrq;
  1632. enum dw_mci_state state;
  1633. enum dw_mci_state prev_state;
  1634. unsigned int err;
  1635. spin_lock(&host->lock);
  1636. state = host->state;
  1637. data = host->data;
  1638. mrq = host->mrq;
  1639. do {
  1640. prev_state = state;
  1641. switch (state) {
  1642. case STATE_IDLE:
  1643. case STATE_WAITING_CMD11_DONE:
  1644. break;
  1645. case STATE_SENDING_CMD11:
  1646. case STATE_SENDING_CMD:
  1647. if (!dw_mci_clear_pending_cmd_complete(host))
  1648. break;
  1649. cmd = host->cmd;
  1650. host->cmd = NULL;
  1651. set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
  1652. err = dw_mci_command_complete(host, cmd);
  1653. if (cmd == mrq->sbc && !err) {
  1654. __dw_mci_start_request(host, host->slot,
  1655. mrq->cmd);
  1656. goto unlock;
  1657. }
  1658. if (cmd->data && err) {
  1659. /*
  1660. * During UHS tuning sequence, sending the stop
  1661. * command after the response CRC error would
  1662. * throw the system into a confused state
  1663. * causing all future tuning phases to report
  1664. * failure.
  1665. *
  1666. * In such case controller will move into a data
  1667. * transfer state after a response error or
  1668. * response CRC error. Let's let that finish
  1669. * before trying to send a stop, so we'll go to
  1670. * STATE_SENDING_DATA.
  1671. *
  1672. * Although letting the data transfer take place
  1673. * will waste a bit of time (we already know
  1674. * the command was bad), it can't cause any
  1675. * errors since it's possible it would have
  1676. * taken place anyway if this tasklet got
  1677. * delayed. Allowing the transfer to take place
  1678. * avoids races and keeps things simple.
  1679. */
  1680. if ((err != -ETIMEDOUT) &&
  1681. (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
  1682. state = STATE_SENDING_DATA;
  1683. continue;
  1684. }
  1685. dw_mci_stop_dma(host);
  1686. send_stop_abort(host, data);
  1687. state = STATE_SENDING_STOP;
  1688. break;
  1689. }
  1690. if (!cmd->data || err) {
  1691. dw_mci_request_end(host, mrq);
  1692. goto unlock;
  1693. }
  1694. prev_state = state = STATE_SENDING_DATA;
  1695. /* fall through */
  1696. case STATE_SENDING_DATA:
  1697. /*
  1698. * We could get a data error and never a transfer
  1699. * complete so we'd better check for it here.
  1700. *
  1701. * Note that we don't really care if we also got a
  1702. * transfer complete; stopping the DMA and sending an
  1703. * abort won't hurt.
  1704. */
  1705. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1706. &host->pending_events)) {
  1707. dw_mci_stop_dma(host);
  1708. if (!(host->data_status & (SDMMC_INT_DRTO |
  1709. SDMMC_INT_EBE)))
  1710. send_stop_abort(host, data);
  1711. state = STATE_DATA_ERROR;
  1712. break;
  1713. }
  1714. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1715. &host->pending_events)) {
  1716. /*
  1717. * If all data-related interrupts don't come
  1718. * within the given time in reading data state.
  1719. */
  1720. if (host->dir_status == DW_MCI_RECV_STATUS)
  1721. dw_mci_set_drto(host);
  1722. break;
  1723. }
  1724. set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
  1725. /*
  1726. * Handle an EVENT_DATA_ERROR that might have shown up
  1727. * before the transfer completed. This might not have
  1728. * been caught by the check above because the interrupt
  1729. * could have gone off between the previous check and
  1730. * the check for transfer complete.
  1731. *
  1732. * Technically this ought not be needed assuming we
  1733. * get a DATA_COMPLETE eventually (we'll notice the
  1734. * error and end the request), but it shouldn't hurt.
  1735. *
  1736. * This has the advantage of sending the stop command.
  1737. */
  1738. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1739. &host->pending_events)) {
  1740. dw_mci_stop_dma(host);
  1741. if (!(host->data_status & (SDMMC_INT_DRTO |
  1742. SDMMC_INT_EBE)))
  1743. send_stop_abort(host, data);
  1744. state = STATE_DATA_ERROR;
  1745. break;
  1746. }
  1747. prev_state = state = STATE_DATA_BUSY;
  1748. /* fall through */
  1749. case STATE_DATA_BUSY:
  1750. if (!dw_mci_clear_pending_data_complete(host)) {
  1751. /*
  1752. * If data error interrupt comes but data over
  1753. * interrupt doesn't come within the given time.
  1754. * in reading data state.
  1755. */
  1756. if (host->dir_status == DW_MCI_RECV_STATUS)
  1757. dw_mci_set_drto(host);
  1758. break;
  1759. }
  1760. host->data = NULL;
  1761. set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
  1762. err = dw_mci_data_complete(host, data);
  1763. if (!err) {
  1764. if (!data->stop || mrq->sbc) {
  1765. if (mrq->sbc && data->stop)
  1766. data->stop->error = 0;
  1767. dw_mci_request_end(host, mrq);
  1768. goto unlock;
  1769. }
  1770. /* stop command for open-ended transfer*/
  1771. if (data->stop)
  1772. send_stop_abort(host, data);
  1773. } else {
  1774. /*
  1775. * If we don't have a command complete now we'll
  1776. * never get one since we just reset everything;
  1777. * better end the request.
  1778. *
  1779. * If we do have a command complete we'll fall
  1780. * through to the SENDING_STOP command and
  1781. * everything will be peachy keen.
  1782. */
  1783. if (!test_bit(EVENT_CMD_COMPLETE,
  1784. &host->pending_events)) {
  1785. host->cmd = NULL;
  1786. dw_mci_request_end(host, mrq);
  1787. goto unlock;
  1788. }
  1789. }
  1790. /*
  1791. * If err has non-zero,
  1792. * stop-abort command has been already issued.
  1793. */
  1794. prev_state = state = STATE_SENDING_STOP;
  1795. /* fall through */
  1796. case STATE_SENDING_STOP:
  1797. if (!dw_mci_clear_pending_cmd_complete(host))
  1798. break;
  1799. /* CMD error in data command */
  1800. if (mrq->cmd->error && mrq->data)
  1801. dw_mci_reset(host);
  1802. host->cmd = NULL;
  1803. host->data = NULL;
  1804. if (!mrq->sbc && mrq->stop)
  1805. dw_mci_command_complete(host, mrq->stop);
  1806. else
  1807. host->cmd_status = 0;
  1808. dw_mci_request_end(host, mrq);
  1809. goto unlock;
  1810. case STATE_DATA_ERROR:
  1811. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1812. &host->pending_events))
  1813. break;
  1814. state = STATE_DATA_BUSY;
  1815. break;
  1816. }
  1817. } while (state != prev_state);
  1818. host->state = state;
  1819. unlock:
  1820. spin_unlock(&host->lock);
  1821. }
  1822. /* push final bytes to part_buf, only use during push */
  1823. static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1824. {
  1825. memcpy((void *)&host->part_buf, buf, cnt);
  1826. host->part_buf_count = cnt;
  1827. }
  1828. /* append bytes to part_buf, only use during push */
  1829. static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1830. {
  1831. cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
  1832. memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
  1833. host->part_buf_count += cnt;
  1834. return cnt;
  1835. }
  1836. /* pull first bytes from part_buf, only use during pull */
  1837. static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1838. {
  1839. cnt = min_t(int, cnt, host->part_buf_count);
  1840. if (cnt) {
  1841. memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
  1842. cnt);
  1843. host->part_buf_count -= cnt;
  1844. host->part_buf_start += cnt;
  1845. }
  1846. return cnt;
  1847. }
  1848. /* pull final bytes from the part_buf, assuming it's just been filled */
  1849. static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
  1850. {
  1851. memcpy(buf, &host->part_buf, cnt);
  1852. host->part_buf_start = cnt;
  1853. host->part_buf_count = (1 << host->data_shift) - cnt;
  1854. }
  1855. static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
  1856. {
  1857. struct mmc_data *data = host->data;
  1858. int init_cnt = cnt;
  1859. /* try and push anything in the part_buf */
  1860. if (unlikely(host->part_buf_count)) {
  1861. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1862. buf += len;
  1863. cnt -= len;
  1864. if (host->part_buf_count == 2) {
  1865. mci_fifo_writew(host->fifo_reg, host->part_buf16);
  1866. host->part_buf_count = 0;
  1867. }
  1868. }
  1869. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1870. if (unlikely((unsigned long)buf & 0x1)) {
  1871. while (cnt >= 2) {
  1872. u16 aligned_buf[64];
  1873. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1874. int items = len >> 1;
  1875. int i;
  1876. /* memcpy from input buffer into aligned buffer */
  1877. memcpy(aligned_buf, buf, len);
  1878. buf += len;
  1879. cnt -= len;
  1880. /* push data from aligned buffer into fifo */
  1881. for (i = 0; i < items; ++i)
  1882. mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
  1883. }
  1884. } else
  1885. #endif
  1886. {
  1887. u16 *pdata = buf;
  1888. for (; cnt >= 2; cnt -= 2)
  1889. mci_fifo_writew(host->fifo_reg, *pdata++);
  1890. buf = pdata;
  1891. }
  1892. /* put anything remaining in the part_buf */
  1893. if (cnt) {
  1894. dw_mci_set_part_bytes(host, buf, cnt);
  1895. /* Push data if we have reached the expected data length */
  1896. if ((data->bytes_xfered + init_cnt) ==
  1897. (data->blksz * data->blocks))
  1898. mci_fifo_writew(host->fifo_reg, host->part_buf16);
  1899. }
  1900. }
  1901. static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
  1902. {
  1903. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1904. if (unlikely((unsigned long)buf & 0x1)) {
  1905. while (cnt >= 2) {
  1906. /* pull data from fifo into aligned buffer */
  1907. u16 aligned_buf[64];
  1908. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1909. int items = len >> 1;
  1910. int i;
  1911. for (i = 0; i < items; ++i)
  1912. aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
  1913. /* memcpy from aligned buffer into output buffer */
  1914. memcpy(buf, aligned_buf, len);
  1915. buf += len;
  1916. cnt -= len;
  1917. }
  1918. } else
  1919. #endif
  1920. {
  1921. u16 *pdata = buf;
  1922. for (; cnt >= 2; cnt -= 2)
  1923. *pdata++ = mci_fifo_readw(host->fifo_reg);
  1924. buf = pdata;
  1925. }
  1926. if (cnt) {
  1927. host->part_buf16 = mci_fifo_readw(host->fifo_reg);
  1928. dw_mci_pull_final_bytes(host, buf, cnt);
  1929. }
  1930. }
  1931. static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
  1932. {
  1933. struct mmc_data *data = host->data;
  1934. int init_cnt = cnt;
  1935. /* try and push anything in the part_buf */
  1936. if (unlikely(host->part_buf_count)) {
  1937. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1938. buf += len;
  1939. cnt -= len;
  1940. if (host->part_buf_count == 4) {
  1941. mci_fifo_writel(host->fifo_reg, host->part_buf32);
  1942. host->part_buf_count = 0;
  1943. }
  1944. }
  1945. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1946. if (unlikely((unsigned long)buf & 0x3)) {
  1947. while (cnt >= 4) {
  1948. u32 aligned_buf[32];
  1949. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1950. int items = len >> 2;
  1951. int i;
  1952. /* memcpy from input buffer into aligned buffer */
  1953. memcpy(aligned_buf, buf, len);
  1954. buf += len;
  1955. cnt -= len;
  1956. /* push data from aligned buffer into fifo */
  1957. for (i = 0; i < items; ++i)
  1958. mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
  1959. }
  1960. } else
  1961. #endif
  1962. {
  1963. u32 *pdata = buf;
  1964. for (; cnt >= 4; cnt -= 4)
  1965. mci_fifo_writel(host->fifo_reg, *pdata++);
  1966. buf = pdata;
  1967. }
  1968. /* put anything remaining in the part_buf */
  1969. if (cnt) {
  1970. dw_mci_set_part_bytes(host, buf, cnt);
  1971. /* Push data if we have reached the expected data length */
  1972. if ((data->bytes_xfered + init_cnt) ==
  1973. (data->blksz * data->blocks))
  1974. mci_fifo_writel(host->fifo_reg, host->part_buf32);
  1975. }
  1976. }
  1977. static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
  1978. {
  1979. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1980. if (unlikely((unsigned long)buf & 0x3)) {
  1981. while (cnt >= 4) {
  1982. /* pull data from fifo into aligned buffer */
  1983. u32 aligned_buf[32];
  1984. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1985. int items = len >> 2;
  1986. int i;
  1987. for (i = 0; i < items; ++i)
  1988. aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
  1989. /* memcpy from aligned buffer into output buffer */
  1990. memcpy(buf, aligned_buf, len);
  1991. buf += len;
  1992. cnt -= len;
  1993. }
  1994. } else
  1995. #endif
  1996. {
  1997. u32 *pdata = buf;
  1998. for (; cnt >= 4; cnt -= 4)
  1999. *pdata++ = mci_fifo_readl(host->fifo_reg);
  2000. buf = pdata;
  2001. }
  2002. if (cnt) {
  2003. host->part_buf32 = mci_fifo_readl(host->fifo_reg);
  2004. dw_mci_pull_final_bytes(host, buf, cnt);
  2005. }
  2006. }
  2007. static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
  2008. {
  2009. struct mmc_data *data = host->data;
  2010. int init_cnt = cnt;
  2011. /* try and push anything in the part_buf */
  2012. if (unlikely(host->part_buf_count)) {
  2013. int len = dw_mci_push_part_bytes(host, buf, cnt);
  2014. buf += len;
  2015. cnt -= len;
  2016. if (host->part_buf_count == 8) {
  2017. mci_fifo_writeq(host->fifo_reg, host->part_buf);
  2018. host->part_buf_count = 0;
  2019. }
  2020. }
  2021. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  2022. if (unlikely((unsigned long)buf & 0x7)) {
  2023. while (cnt >= 8) {
  2024. u64 aligned_buf[16];
  2025. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  2026. int items = len >> 3;
  2027. int i;
  2028. /* memcpy from input buffer into aligned buffer */
  2029. memcpy(aligned_buf, buf, len);
  2030. buf += len;
  2031. cnt -= len;
  2032. /* push data from aligned buffer into fifo */
  2033. for (i = 0; i < items; ++i)
  2034. mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
  2035. }
  2036. } else
  2037. #endif
  2038. {
  2039. u64 *pdata = buf;
  2040. for (; cnt >= 8; cnt -= 8)
  2041. mci_fifo_writeq(host->fifo_reg, *pdata++);
  2042. buf = pdata;
  2043. }
  2044. /* put anything remaining in the part_buf */
  2045. if (cnt) {
  2046. dw_mci_set_part_bytes(host, buf, cnt);
  2047. /* Push data if we have reached the expected data length */
  2048. if ((data->bytes_xfered + init_cnt) ==
  2049. (data->blksz * data->blocks))
  2050. mci_fifo_writeq(host->fifo_reg, host->part_buf);
  2051. }
  2052. }
  2053. static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
  2054. {
  2055. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  2056. if (unlikely((unsigned long)buf & 0x7)) {
  2057. while (cnt >= 8) {
  2058. /* pull data from fifo into aligned buffer */
  2059. u64 aligned_buf[16];
  2060. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  2061. int items = len >> 3;
  2062. int i;
  2063. for (i = 0; i < items; ++i)
  2064. aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
  2065. /* memcpy from aligned buffer into output buffer */
  2066. memcpy(buf, aligned_buf, len);
  2067. buf += len;
  2068. cnt -= len;
  2069. }
  2070. } else
  2071. #endif
  2072. {
  2073. u64 *pdata = buf;
  2074. for (; cnt >= 8; cnt -= 8)
  2075. *pdata++ = mci_fifo_readq(host->fifo_reg);
  2076. buf = pdata;
  2077. }
  2078. if (cnt) {
  2079. host->part_buf = mci_fifo_readq(host->fifo_reg);
  2080. dw_mci_pull_final_bytes(host, buf, cnt);
  2081. }
  2082. }
  2083. static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
  2084. {
  2085. int len;
  2086. /* get remaining partial bytes */
  2087. len = dw_mci_pull_part_bytes(host, buf, cnt);
  2088. if (unlikely(len == cnt))
  2089. return;
  2090. buf += len;
  2091. cnt -= len;
  2092. /* get the rest of the data */
  2093. host->pull_data(host, buf, cnt);
  2094. }
  2095. static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
  2096. {
  2097. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  2098. void *buf;
  2099. unsigned int offset;
  2100. struct mmc_data *data = host->data;
  2101. int shift = host->data_shift;
  2102. u32 status;
  2103. unsigned int len;
  2104. unsigned int remain, fcnt;
  2105. do {
  2106. if (!sg_miter_next(sg_miter))
  2107. goto done;
  2108. host->sg = sg_miter->piter.sg;
  2109. buf = sg_miter->addr;
  2110. remain = sg_miter->length;
  2111. offset = 0;
  2112. do {
  2113. fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
  2114. << shift) + host->part_buf_count;
  2115. len = min(remain, fcnt);
  2116. if (!len)
  2117. break;
  2118. dw_mci_pull_data(host, (void *)(buf + offset), len);
  2119. data->bytes_xfered += len;
  2120. offset += len;
  2121. remain -= len;
  2122. } while (remain);
  2123. sg_miter->consumed = offset;
  2124. status = mci_readl(host, MINTSTS);
  2125. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  2126. /* if the RXDR is ready read again */
  2127. } while ((status & SDMMC_INT_RXDR) ||
  2128. (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
  2129. if (!remain) {
  2130. if (!sg_miter_next(sg_miter))
  2131. goto done;
  2132. sg_miter->consumed = 0;
  2133. }
  2134. sg_miter_stop(sg_miter);
  2135. return;
  2136. done:
  2137. sg_miter_stop(sg_miter);
  2138. host->sg = NULL;
  2139. smp_wmb(); /* drain writebuffer */
  2140. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  2141. }
  2142. static void dw_mci_write_data_pio(struct dw_mci *host)
  2143. {
  2144. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  2145. void *buf;
  2146. unsigned int offset;
  2147. struct mmc_data *data = host->data;
  2148. int shift = host->data_shift;
  2149. u32 status;
  2150. unsigned int len;
  2151. unsigned int fifo_depth = host->fifo_depth;
  2152. unsigned int remain, fcnt;
  2153. do {
  2154. if (!sg_miter_next(sg_miter))
  2155. goto done;
  2156. host->sg = sg_miter->piter.sg;
  2157. buf = sg_miter->addr;
  2158. remain = sg_miter->length;
  2159. offset = 0;
  2160. do {
  2161. fcnt = ((fifo_depth -
  2162. SDMMC_GET_FCNT(mci_readl(host, STATUS)))
  2163. << shift) - host->part_buf_count;
  2164. len = min(remain, fcnt);
  2165. if (!len)
  2166. break;
  2167. host->push_data(host, (void *)(buf + offset), len);
  2168. data->bytes_xfered += len;
  2169. offset += len;
  2170. remain -= len;
  2171. } while (remain);
  2172. sg_miter->consumed = offset;
  2173. status = mci_readl(host, MINTSTS);
  2174. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  2175. } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
  2176. if (!remain) {
  2177. if (!sg_miter_next(sg_miter))
  2178. goto done;
  2179. sg_miter->consumed = 0;
  2180. }
  2181. sg_miter_stop(sg_miter);
  2182. return;
  2183. done:
  2184. sg_miter_stop(sg_miter);
  2185. host->sg = NULL;
  2186. smp_wmb(); /* drain writebuffer */
  2187. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  2188. }
  2189. static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
  2190. {
  2191. del_timer(&host->cto_timer);
  2192. if (!host->cmd_status)
  2193. host->cmd_status = status;
  2194. smp_wmb(); /* drain writebuffer */
  2195. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2196. tasklet_schedule(&host->tasklet);
  2197. }
  2198. static void dw_mci_handle_cd(struct dw_mci *host)
  2199. {
  2200. struct dw_mci_slot *slot = host->slot;
  2201. if (slot->mmc->ops->card_event)
  2202. slot->mmc->ops->card_event(slot->mmc);
  2203. mmc_detect_change(slot->mmc,
  2204. msecs_to_jiffies(host->pdata->detect_delay_ms));
  2205. }
  2206. static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
  2207. {
  2208. struct dw_mci *host = dev_id;
  2209. u32 pending;
  2210. struct dw_mci_slot *slot = host->slot;
  2211. unsigned long irqflags;
  2212. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2213. if (pending) {
  2214. /* Check volt switch first, since it can look like an error */
  2215. if ((host->state == STATE_SENDING_CMD11) &&
  2216. (pending & SDMMC_INT_VOLT_SWITCH)) {
  2217. mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
  2218. pending &= ~SDMMC_INT_VOLT_SWITCH;
  2219. /*
  2220. * Hold the lock; we know cmd11_timer can't be kicked
  2221. * off after the lock is released, so safe to delete.
  2222. */
  2223. spin_lock_irqsave(&host->irq_lock, irqflags);
  2224. dw_mci_cmd_interrupt(host, pending);
  2225. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2226. del_timer(&host->cmd11_timer);
  2227. }
  2228. if (pending & DW_MCI_CMD_ERROR_FLAGS) {
  2229. spin_lock_irqsave(&host->irq_lock, irqflags);
  2230. del_timer(&host->cto_timer);
  2231. mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
  2232. host->cmd_status = pending;
  2233. smp_wmb(); /* drain writebuffer */
  2234. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2235. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2236. }
  2237. if (pending & DW_MCI_DATA_ERROR_FLAGS) {
  2238. /* if there is an error report DATA_ERROR */
  2239. mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
  2240. host->data_status = pending;
  2241. smp_wmb(); /* drain writebuffer */
  2242. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  2243. tasklet_schedule(&host->tasklet);
  2244. }
  2245. if (pending & SDMMC_INT_DATA_OVER) {
  2246. spin_lock_irqsave(&host->irq_lock, irqflags);
  2247. del_timer(&host->dto_timer);
  2248. mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
  2249. if (!host->data_status)
  2250. host->data_status = pending;
  2251. smp_wmb(); /* drain writebuffer */
  2252. if (host->dir_status == DW_MCI_RECV_STATUS) {
  2253. if (host->sg != NULL)
  2254. dw_mci_read_data_pio(host, true);
  2255. }
  2256. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  2257. tasklet_schedule(&host->tasklet);
  2258. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2259. }
  2260. if (pending & SDMMC_INT_RXDR) {
  2261. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  2262. if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
  2263. dw_mci_read_data_pio(host, false);
  2264. }
  2265. if (pending & SDMMC_INT_TXDR) {
  2266. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  2267. if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
  2268. dw_mci_write_data_pio(host);
  2269. }
  2270. if (pending & SDMMC_INT_CMD_DONE) {
  2271. spin_lock_irqsave(&host->irq_lock, irqflags);
  2272. mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
  2273. dw_mci_cmd_interrupt(host, pending);
  2274. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2275. }
  2276. if (pending & SDMMC_INT_CD) {
  2277. mci_writel(host, RINTSTS, SDMMC_INT_CD);
  2278. dw_mci_handle_cd(host);
  2279. }
  2280. if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
  2281. mci_writel(host, RINTSTS,
  2282. SDMMC_INT_SDIO(slot->sdio_id));
  2283. __dw_mci_enable_sdio_irq(slot, 0);
  2284. sdio_signal_irq(slot->mmc);
  2285. }
  2286. }
  2287. if (host->use_dma != TRANS_MODE_IDMAC)
  2288. return IRQ_HANDLED;
  2289. /* Handle IDMA interrupts */
  2290. if (host->dma_64bit_address == 1) {
  2291. pending = mci_readl(host, IDSTS64);
  2292. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  2293. mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
  2294. SDMMC_IDMAC_INT_RI);
  2295. mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
  2296. if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
  2297. host->dma_ops->complete((void *)host);
  2298. }
  2299. } else {
  2300. pending = mci_readl(host, IDSTS);
  2301. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  2302. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
  2303. SDMMC_IDMAC_INT_RI);
  2304. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
  2305. if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
  2306. host->dma_ops->complete((void *)host);
  2307. }
  2308. }
  2309. return IRQ_HANDLED;
  2310. }
  2311. static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
  2312. {
  2313. struct dw_mci *host = slot->host;
  2314. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2315. struct mmc_host *mmc = slot->mmc;
  2316. int ctrl_id;
  2317. if (host->pdata->caps)
  2318. mmc->caps = host->pdata->caps;
  2319. /*
  2320. * Support MMC_CAP_ERASE by default.
  2321. * It needs to use trim/discard/erase commands.
  2322. */
  2323. mmc->caps |= MMC_CAP_ERASE;
  2324. if (host->pdata->pm_caps)
  2325. mmc->pm_caps = host->pdata->pm_caps;
  2326. if (host->dev->of_node) {
  2327. ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
  2328. if (ctrl_id < 0)
  2329. ctrl_id = 0;
  2330. } else {
  2331. ctrl_id = to_platform_device(host->dev)->id;
  2332. }
  2333. if (drv_data && drv_data->caps) {
  2334. if (ctrl_id >= drv_data->num_caps) {
  2335. dev_err(host->dev, "invalid controller id %d\n",
  2336. ctrl_id);
  2337. return -EINVAL;
  2338. }
  2339. mmc->caps |= drv_data->caps[ctrl_id];
  2340. }
  2341. if (host->pdata->caps2)
  2342. mmc->caps2 = host->pdata->caps2;
  2343. mmc->f_min = DW_MCI_FREQ_MIN;
  2344. if (!mmc->f_max)
  2345. mmc->f_max = DW_MCI_FREQ_MAX;
  2346. /* Process SDIO IRQs through the sdio_irq_work. */
  2347. if (mmc->caps & MMC_CAP_SDIO_IRQ)
  2348. mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
  2349. return 0;
  2350. }
  2351. static int dw_mci_init_slot(struct dw_mci *host)
  2352. {
  2353. struct mmc_host *mmc;
  2354. struct dw_mci_slot *slot;
  2355. int ret;
  2356. mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
  2357. if (!mmc)
  2358. return -ENOMEM;
  2359. slot = mmc_priv(mmc);
  2360. slot->id = 0;
  2361. slot->sdio_id = host->sdio_id0 + slot->id;
  2362. slot->mmc = mmc;
  2363. slot->host = host;
  2364. host->slot = slot;
  2365. mmc->ops = &dw_mci_ops;
  2366. /*if there are external regulators, get them*/
  2367. ret = mmc_regulator_get_supply(mmc);
  2368. if (ret)
  2369. goto err_host_allocated;
  2370. if (!mmc->ocr_avail)
  2371. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  2372. ret = mmc_of_parse(mmc);
  2373. if (ret)
  2374. goto err_host_allocated;
  2375. ret = dw_mci_init_slot_caps(slot);
  2376. if (ret)
  2377. goto err_host_allocated;
  2378. /* Useful defaults if platform data is unset. */
  2379. if (host->use_dma == TRANS_MODE_IDMAC) {
  2380. mmc->max_segs = host->ring_size;
  2381. mmc->max_blk_size = 65535;
  2382. mmc->max_seg_size = 0x1000;
  2383. mmc->max_req_size = mmc->max_seg_size * host->ring_size;
  2384. mmc->max_blk_count = mmc->max_req_size / 512;
  2385. } else if (host->use_dma == TRANS_MODE_EDMAC) {
  2386. mmc->max_segs = 64;
  2387. mmc->max_blk_size = 65535;
  2388. mmc->max_blk_count = 65535;
  2389. mmc->max_req_size =
  2390. mmc->max_blk_size * mmc->max_blk_count;
  2391. mmc->max_seg_size = mmc->max_req_size;
  2392. } else {
  2393. /* TRANS_MODE_PIO */
  2394. mmc->max_segs = 64;
  2395. mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
  2396. mmc->max_blk_count = 512;
  2397. mmc->max_req_size = mmc->max_blk_size *
  2398. mmc->max_blk_count;
  2399. mmc->max_seg_size = mmc->max_req_size;
  2400. }
  2401. dw_mci_get_cd(mmc);
  2402. ret = mmc_add_host(mmc);
  2403. if (ret)
  2404. goto err_host_allocated;
  2405. #if defined(CONFIG_DEBUG_FS)
  2406. dw_mci_init_debugfs(slot);
  2407. #endif
  2408. return 0;
  2409. err_host_allocated:
  2410. mmc_free_host(mmc);
  2411. return ret;
  2412. }
  2413. static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
  2414. {
  2415. /* Debugfs stuff is cleaned up by mmc core */
  2416. mmc_remove_host(slot->mmc);
  2417. slot->host->slot = NULL;
  2418. mmc_free_host(slot->mmc);
  2419. }
  2420. static void dw_mci_init_dma(struct dw_mci *host)
  2421. {
  2422. int addr_config;
  2423. struct device *dev = host->dev;
  2424. /*
  2425. * Check tansfer mode from HCON[17:16]
  2426. * Clear the ambiguous description of dw_mmc databook:
  2427. * 2b'00: No DMA Interface -> Actually means using Internal DMA block
  2428. * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
  2429. * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
  2430. * 2b'11: Non DW DMA Interface -> pio only
  2431. * Compared to DesignWare DMA Interface, Generic DMA Interface has a
  2432. * simpler request/acknowledge handshake mechanism and both of them
  2433. * are regarded as external dma master for dw_mmc.
  2434. */
  2435. host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
  2436. if (host->use_dma == DMA_INTERFACE_IDMA) {
  2437. host->use_dma = TRANS_MODE_IDMAC;
  2438. } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
  2439. host->use_dma == DMA_INTERFACE_GDMA) {
  2440. host->use_dma = TRANS_MODE_EDMAC;
  2441. } else {
  2442. goto no_dma;
  2443. }
  2444. /* Determine which DMA interface to use */
  2445. if (host->use_dma == TRANS_MODE_IDMAC) {
  2446. /*
  2447. * Check ADDR_CONFIG bit in HCON to find
  2448. * IDMAC address bus width
  2449. */
  2450. addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
  2451. if (addr_config == 1) {
  2452. /* host supports IDMAC in 64-bit address mode */
  2453. host->dma_64bit_address = 1;
  2454. dev_info(host->dev,
  2455. "IDMAC supports 64-bit address mode.\n");
  2456. if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
  2457. dma_set_coherent_mask(host->dev,
  2458. DMA_BIT_MASK(64));
  2459. } else {
  2460. /* host supports IDMAC in 32-bit address mode */
  2461. host->dma_64bit_address = 0;
  2462. dev_info(host->dev,
  2463. "IDMAC supports 32-bit address mode.\n");
  2464. }
  2465. /* Alloc memory for sg translation */
  2466. host->sg_cpu = dmam_alloc_coherent(host->dev,
  2467. DESC_RING_BUF_SZ,
  2468. &host->sg_dma, GFP_KERNEL);
  2469. if (!host->sg_cpu) {
  2470. dev_err(host->dev,
  2471. "%s: could not alloc DMA memory\n",
  2472. __func__);
  2473. goto no_dma;
  2474. }
  2475. host->dma_ops = &dw_mci_idmac_ops;
  2476. dev_info(host->dev, "Using internal DMA controller.\n");
  2477. } else {
  2478. /* TRANS_MODE_EDMAC: check dma bindings again */
  2479. if ((device_property_read_string_array(dev, "dma-names",
  2480. NULL, 0) < 0) ||
  2481. !device_property_present(dev, "dmas")) {
  2482. goto no_dma;
  2483. }
  2484. host->dma_ops = &dw_mci_edmac_ops;
  2485. dev_info(host->dev, "Using external DMA controller.\n");
  2486. }
  2487. if (host->dma_ops->init && host->dma_ops->start &&
  2488. host->dma_ops->stop && host->dma_ops->cleanup) {
  2489. if (host->dma_ops->init(host)) {
  2490. dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
  2491. __func__);
  2492. goto no_dma;
  2493. }
  2494. } else {
  2495. dev_err(host->dev, "DMA initialization not found.\n");
  2496. goto no_dma;
  2497. }
  2498. return;
  2499. no_dma:
  2500. dev_info(host->dev, "Using PIO mode.\n");
  2501. host->use_dma = TRANS_MODE_PIO;
  2502. }
  2503. static void dw_mci_cmd11_timer(struct timer_list *t)
  2504. {
  2505. struct dw_mci *host = from_timer(host, t, cmd11_timer);
  2506. if (host->state != STATE_SENDING_CMD11) {
  2507. dev_warn(host->dev, "Unexpected CMD11 timeout\n");
  2508. return;
  2509. }
  2510. host->cmd_status = SDMMC_INT_RTO;
  2511. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2512. tasklet_schedule(&host->tasklet);
  2513. }
  2514. static void dw_mci_cto_timer(struct timer_list *t)
  2515. {
  2516. struct dw_mci *host = from_timer(host, t, cto_timer);
  2517. unsigned long irqflags;
  2518. u32 pending;
  2519. spin_lock_irqsave(&host->irq_lock, irqflags);
  2520. /*
  2521. * If somehow we have very bad interrupt latency it's remotely possible
  2522. * that the timer could fire while the interrupt is still pending or
  2523. * while the interrupt is midway through running. Let's be paranoid
  2524. * and detect those two cases. Note that this is paranoia is somewhat
  2525. * justified because in this function we don't actually cancel the
  2526. * pending command in the controller--we just assume it will never come.
  2527. */
  2528. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2529. if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
  2530. /* The interrupt should fire; no need to act but we can warn */
  2531. dev_warn(host->dev, "Unexpected interrupt latency\n");
  2532. goto exit;
  2533. }
  2534. if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
  2535. /* Presumably interrupt handler couldn't delete the timer */
  2536. dev_warn(host->dev, "CTO timeout when already completed\n");
  2537. goto exit;
  2538. }
  2539. /*
  2540. * Continued paranoia to make sure we're in the state we expect.
  2541. * This paranoia isn't really justified but it seems good to be safe.
  2542. */
  2543. switch (host->state) {
  2544. case STATE_SENDING_CMD11:
  2545. case STATE_SENDING_CMD:
  2546. case STATE_SENDING_STOP:
  2547. /*
  2548. * If CMD_DONE interrupt does NOT come in sending command
  2549. * state, we should notify the driver to terminate current
  2550. * transfer and report a command timeout to the core.
  2551. */
  2552. host->cmd_status = SDMMC_INT_RTO;
  2553. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2554. tasklet_schedule(&host->tasklet);
  2555. break;
  2556. default:
  2557. dev_warn(host->dev, "Unexpected command timeout, state %d\n",
  2558. host->state);
  2559. break;
  2560. }
  2561. exit:
  2562. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2563. }
  2564. static void dw_mci_dto_timer(struct timer_list *t)
  2565. {
  2566. struct dw_mci *host = from_timer(host, t, dto_timer);
  2567. unsigned long irqflags;
  2568. u32 pending;
  2569. spin_lock_irqsave(&host->irq_lock, irqflags);
  2570. /*
  2571. * The DTO timer is much longer than the CTO timer, so it's even less
  2572. * likely that we'll these cases, but it pays to be paranoid.
  2573. */
  2574. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2575. if (pending & SDMMC_INT_DATA_OVER) {
  2576. /* The interrupt should fire; no need to act but we can warn */
  2577. dev_warn(host->dev, "Unexpected data interrupt latency\n");
  2578. goto exit;
  2579. }
  2580. if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
  2581. /* Presumably interrupt handler couldn't delete the timer */
  2582. dev_warn(host->dev, "DTO timeout when already completed\n");
  2583. goto exit;
  2584. }
  2585. /*
  2586. * Continued paranoia to make sure we're in the state we expect.
  2587. * This paranoia isn't really justified but it seems good to be safe.
  2588. */
  2589. switch (host->state) {
  2590. case STATE_SENDING_DATA:
  2591. case STATE_DATA_BUSY:
  2592. /*
  2593. * If DTO interrupt does NOT come in sending data state,
  2594. * we should notify the driver to terminate current transfer
  2595. * and report a data timeout to the core.
  2596. */
  2597. host->data_status = SDMMC_INT_DRTO;
  2598. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  2599. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  2600. tasklet_schedule(&host->tasklet);
  2601. break;
  2602. default:
  2603. dev_warn(host->dev, "Unexpected data timeout, state %d\n",
  2604. host->state);
  2605. break;
  2606. }
  2607. exit:
  2608. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2609. }
  2610. #ifdef CONFIG_OF
  2611. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  2612. {
  2613. struct dw_mci_board *pdata;
  2614. struct device *dev = host->dev;
  2615. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2616. int ret;
  2617. u32 clock_frequency;
  2618. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  2619. if (!pdata)
  2620. return ERR_PTR(-ENOMEM);
  2621. /* find reset controller when exist */
  2622. pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
  2623. if (IS_ERR(pdata->rstc)) {
  2624. if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
  2625. return ERR_PTR(-EPROBE_DEFER);
  2626. }
  2627. if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
  2628. dev_info(dev,
  2629. "fifo-depth property not found, using value of FIFOTH register as default\n");
  2630. device_property_read_u32(dev, "card-detect-delay",
  2631. &pdata->detect_delay_ms);
  2632. device_property_read_u32(dev, "data-addr", &host->data_addr_override);
  2633. if (device_property_present(dev, "fifo-watermark-aligned"))
  2634. host->wm_aligned = true;
  2635. if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
  2636. pdata->bus_hz = clock_frequency;
  2637. if (drv_data && drv_data->parse_dt) {
  2638. ret = drv_data->parse_dt(host);
  2639. if (ret)
  2640. return ERR_PTR(ret);
  2641. }
  2642. return pdata;
  2643. }
  2644. #else /* CONFIG_OF */
  2645. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  2646. {
  2647. return ERR_PTR(-EINVAL);
  2648. }
  2649. #endif /* CONFIG_OF */
  2650. static void dw_mci_enable_cd(struct dw_mci *host)
  2651. {
  2652. unsigned long irqflags;
  2653. u32 temp;
  2654. /*
  2655. * No need for CD if all slots have a non-error GPIO
  2656. * as well as broken card detection is found.
  2657. */
  2658. if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
  2659. return;
  2660. if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
  2661. spin_lock_irqsave(&host->irq_lock, irqflags);
  2662. temp = mci_readl(host, INTMASK);
  2663. temp |= SDMMC_INT_CD;
  2664. mci_writel(host, INTMASK, temp);
  2665. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2666. }
  2667. }
  2668. int dw_mci_probe(struct dw_mci *host)
  2669. {
  2670. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2671. int width, i, ret = 0;
  2672. u32 fifo_size;
  2673. if (!host->pdata) {
  2674. host->pdata = dw_mci_parse_dt(host);
  2675. if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
  2676. return -EPROBE_DEFER;
  2677. } else if (IS_ERR(host->pdata)) {
  2678. dev_err(host->dev, "platform data not available\n");
  2679. return -EINVAL;
  2680. }
  2681. }
  2682. host->biu_clk = devm_clk_get(host->dev, "biu");
  2683. if (IS_ERR(host->biu_clk)) {
  2684. dev_dbg(host->dev, "biu clock not available\n");
  2685. } else {
  2686. ret = clk_prepare_enable(host->biu_clk);
  2687. if (ret) {
  2688. dev_err(host->dev, "failed to enable biu clock\n");
  2689. return ret;
  2690. }
  2691. }
  2692. host->ciu_clk = devm_clk_get(host->dev, "ciu");
  2693. if (IS_ERR(host->ciu_clk)) {
  2694. dev_dbg(host->dev, "ciu clock not available\n");
  2695. host->bus_hz = host->pdata->bus_hz;
  2696. } else {
  2697. ret = clk_prepare_enable(host->ciu_clk);
  2698. if (ret) {
  2699. dev_err(host->dev, "failed to enable ciu clock\n");
  2700. goto err_clk_biu;
  2701. }
  2702. if (host->pdata->bus_hz) {
  2703. ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
  2704. if (ret)
  2705. dev_warn(host->dev,
  2706. "Unable to set bus rate to %uHz\n",
  2707. host->pdata->bus_hz);
  2708. }
  2709. host->bus_hz = clk_get_rate(host->ciu_clk);
  2710. }
  2711. if (!host->bus_hz) {
  2712. dev_err(host->dev,
  2713. "Platform data must supply bus speed\n");
  2714. ret = -ENODEV;
  2715. goto err_clk_ciu;
  2716. }
  2717. if (!IS_ERR(host->pdata->rstc)) {
  2718. reset_control_assert(host->pdata->rstc);
  2719. usleep_range(10, 50);
  2720. reset_control_deassert(host->pdata->rstc);
  2721. }
  2722. if (drv_data && drv_data->init) {
  2723. ret = drv_data->init(host);
  2724. if (ret) {
  2725. dev_err(host->dev,
  2726. "implementation specific init failed\n");
  2727. goto err_clk_ciu;
  2728. }
  2729. }
  2730. timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
  2731. timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
  2732. timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
  2733. spin_lock_init(&host->lock);
  2734. spin_lock_init(&host->irq_lock);
  2735. INIT_LIST_HEAD(&host->queue);
  2736. /*
  2737. * Get the host data width - this assumes that HCON has been set with
  2738. * the correct values.
  2739. */
  2740. i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
  2741. if (!i) {
  2742. host->push_data = dw_mci_push_data16;
  2743. host->pull_data = dw_mci_pull_data16;
  2744. width = 16;
  2745. host->data_shift = 1;
  2746. } else if (i == 2) {
  2747. host->push_data = dw_mci_push_data64;
  2748. host->pull_data = dw_mci_pull_data64;
  2749. width = 64;
  2750. host->data_shift = 3;
  2751. } else {
  2752. /* Check for a reserved value, and warn if it is */
  2753. WARN((i != 1),
  2754. "HCON reports a reserved host data width!\n"
  2755. "Defaulting to 32-bit access.\n");
  2756. host->push_data = dw_mci_push_data32;
  2757. host->pull_data = dw_mci_pull_data32;
  2758. width = 32;
  2759. host->data_shift = 2;
  2760. }
  2761. /* Reset all blocks */
  2762. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
  2763. ret = -ENODEV;
  2764. goto err_clk_ciu;
  2765. }
  2766. host->dma_ops = host->pdata->dma_ops;
  2767. dw_mci_init_dma(host);
  2768. /* Clear the interrupts for the host controller */
  2769. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2770. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2771. /* Put in max timeout */
  2772. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2773. /*
  2774. * FIFO threshold settings RxMark = fifo_size / 2 - 1,
  2775. * Tx Mark = fifo_size / 2 DMA Size = 8
  2776. */
  2777. if (!host->pdata->fifo_depth) {
  2778. /*
  2779. * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
  2780. * have been overwritten by the bootloader, just like we're
  2781. * about to do, so if you know the value for your hardware, you
  2782. * should put it in the platform data.
  2783. */
  2784. fifo_size = mci_readl(host, FIFOTH);
  2785. fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
  2786. } else {
  2787. fifo_size = host->pdata->fifo_depth;
  2788. }
  2789. host->fifo_depth = fifo_size;
  2790. host->fifoth_val =
  2791. SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
  2792. mci_writel(host, FIFOTH, host->fifoth_val);
  2793. /* disable clock to CIU */
  2794. mci_writel(host, CLKENA, 0);
  2795. mci_writel(host, CLKSRC, 0);
  2796. /*
  2797. * In 2.40a spec, Data offset is changed.
  2798. * Need to check the version-id and set data-offset for DATA register.
  2799. */
  2800. host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
  2801. dev_info(host->dev, "Version ID is %04x\n", host->verid);
  2802. if (host->data_addr_override)
  2803. host->fifo_reg = host->regs + host->data_addr_override;
  2804. else if (host->verid < DW_MMC_240A)
  2805. host->fifo_reg = host->regs + DATA_OFFSET;
  2806. else
  2807. host->fifo_reg = host->regs + DATA_240A_OFFSET;
  2808. tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
  2809. ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
  2810. host->irq_flags, "dw-mci", host);
  2811. if (ret)
  2812. goto err_dmaunmap;
  2813. /*
  2814. * Enable interrupts for command done, data over, data empty,
  2815. * receive ready and error such as transmit, receive timeout, crc error
  2816. */
  2817. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2818. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2819. DW_MCI_ERROR_FLAGS);
  2820. /* Enable mci interrupt */
  2821. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2822. dev_info(host->dev,
  2823. "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
  2824. host->irq, width, fifo_size);
  2825. /* We need at least one slot to succeed */
  2826. ret = dw_mci_init_slot(host);
  2827. if (ret) {
  2828. dev_dbg(host->dev, "slot %d init failed\n", i);
  2829. goto err_dmaunmap;
  2830. }
  2831. /* Now that slots are all setup, we can enable card detect */
  2832. dw_mci_enable_cd(host);
  2833. return 0;
  2834. err_dmaunmap:
  2835. if (host->use_dma && host->dma_ops->exit)
  2836. host->dma_ops->exit(host);
  2837. if (!IS_ERR(host->pdata->rstc))
  2838. reset_control_assert(host->pdata->rstc);
  2839. err_clk_ciu:
  2840. clk_disable_unprepare(host->ciu_clk);
  2841. err_clk_biu:
  2842. clk_disable_unprepare(host->biu_clk);
  2843. return ret;
  2844. }
  2845. EXPORT_SYMBOL(dw_mci_probe);
  2846. void dw_mci_remove(struct dw_mci *host)
  2847. {
  2848. dev_dbg(host->dev, "remove slot\n");
  2849. if (host->slot)
  2850. dw_mci_cleanup_slot(host->slot);
  2851. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2852. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2853. /* disable clock to CIU */
  2854. mci_writel(host, CLKENA, 0);
  2855. mci_writel(host, CLKSRC, 0);
  2856. if (host->use_dma && host->dma_ops->exit)
  2857. host->dma_ops->exit(host);
  2858. if (!IS_ERR(host->pdata->rstc))
  2859. reset_control_assert(host->pdata->rstc);
  2860. clk_disable_unprepare(host->ciu_clk);
  2861. clk_disable_unprepare(host->biu_clk);
  2862. }
  2863. EXPORT_SYMBOL(dw_mci_remove);
  2864. #ifdef CONFIG_PM
  2865. int dw_mci_runtime_suspend(struct device *dev)
  2866. {
  2867. struct dw_mci *host = dev_get_drvdata(dev);
  2868. if (host->use_dma && host->dma_ops->exit)
  2869. host->dma_ops->exit(host);
  2870. clk_disable_unprepare(host->ciu_clk);
  2871. if (host->slot &&
  2872. (mmc_can_gpio_cd(host->slot->mmc) ||
  2873. !mmc_card_is_removable(host->slot->mmc)))
  2874. clk_disable_unprepare(host->biu_clk);
  2875. return 0;
  2876. }
  2877. EXPORT_SYMBOL(dw_mci_runtime_suspend);
  2878. int dw_mci_runtime_resume(struct device *dev)
  2879. {
  2880. int ret = 0;
  2881. struct dw_mci *host = dev_get_drvdata(dev);
  2882. if (host->slot &&
  2883. (mmc_can_gpio_cd(host->slot->mmc) ||
  2884. !mmc_card_is_removable(host->slot->mmc))) {
  2885. ret = clk_prepare_enable(host->biu_clk);
  2886. if (ret)
  2887. return ret;
  2888. }
  2889. ret = clk_prepare_enable(host->ciu_clk);
  2890. if (ret)
  2891. goto err;
  2892. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
  2893. clk_disable_unprepare(host->ciu_clk);
  2894. ret = -ENODEV;
  2895. goto err;
  2896. }
  2897. if (host->use_dma && host->dma_ops->init)
  2898. host->dma_ops->init(host);
  2899. /*
  2900. * Restore the initial value at FIFOTH register
  2901. * And Invalidate the prev_blksz with zero
  2902. */
  2903. mci_writel(host, FIFOTH, host->fifoth_val);
  2904. host->prev_blksz = 0;
  2905. /* Put in max timeout */
  2906. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2907. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2908. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2909. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2910. DW_MCI_ERROR_FLAGS);
  2911. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2912. if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
  2913. dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
  2914. /* Force setup bus to guarantee available clock output */
  2915. dw_mci_setup_bus(host->slot, true);
  2916. /* Now that slots are all setup, we can enable card detect */
  2917. dw_mci_enable_cd(host);
  2918. return 0;
  2919. err:
  2920. if (host->slot &&
  2921. (mmc_can_gpio_cd(host->slot->mmc) ||
  2922. !mmc_card_is_removable(host->slot->mmc)))
  2923. clk_disable_unprepare(host->biu_clk);
  2924. return ret;
  2925. }
  2926. EXPORT_SYMBOL(dw_mci_runtime_resume);
  2927. #endif /* CONFIG_PM */
  2928. static int __init dw_mci_init(void)
  2929. {
  2930. pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
  2931. return 0;
  2932. }
  2933. static void __exit dw_mci_exit(void)
  2934. {
  2935. }
  2936. module_init(dw_mci_init);
  2937. module_exit(dw_mci_exit);
  2938. MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
  2939. MODULE_AUTHOR("NXP Semiconductor VietNam");
  2940. MODULE_AUTHOR("Imagination Technologies Ltd");
  2941. MODULE_LICENSE("GPL v2");