main.c 155 KB

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  1. /*
  2. * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/debugfs.h>
  33. #include <linux/highmem.h>
  34. #include <linux/module.h>
  35. #include <linux/init.h>
  36. #include <linux/errno.h>
  37. #include <linux/pci.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/slab.h>
  40. #include <linux/bitmap.h>
  41. #if defined(CONFIG_X86)
  42. #include <asm/pat.h>
  43. #endif
  44. #include <linux/sched.h>
  45. #include <linux/sched/mm.h>
  46. #include <linux/sched/task.h>
  47. #include <linux/delay.h>
  48. #include <rdma/ib_user_verbs.h>
  49. #include <rdma/ib_addr.h>
  50. #include <rdma/ib_cache.h>
  51. #include <linux/mlx5/port.h>
  52. #include <linux/mlx5/vport.h>
  53. #include <linux/mlx5/fs.h>
  54. #include <linux/list.h>
  55. #include <rdma/ib_smi.h>
  56. #include <rdma/ib_umem.h>
  57. #include <linux/in.h>
  58. #include <linux/etherdevice.h>
  59. #include "mlx5_ib.h"
  60. #include "ib_rep.h"
  61. #include "cmd.h"
  62. #include <linux/mlx5/fs_helpers.h>
  63. #include <linux/mlx5/accel.h>
  64. #include <rdma/uverbs_std_types.h>
  65. #include <rdma/mlx5_user_ioctl_verbs.h>
  66. #include <rdma/mlx5_user_ioctl_cmds.h>
  67. #define UVERBS_MODULE_NAME mlx5_ib
  68. #include <rdma/uverbs_named_ioctl.h>
  69. #define DRIVER_NAME "mlx5_ib"
  70. #define DRIVER_VERSION "5.0-0"
  71. MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  72. MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  73. MODULE_LICENSE("Dual BSD/GPL");
  74. static char mlx5_version[] =
  75. DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  76. DRIVER_VERSION "\n";
  77. struct mlx5_ib_event_work {
  78. struct work_struct work;
  79. struct mlx5_core_dev *dev;
  80. void *context;
  81. enum mlx5_dev_event event;
  82. unsigned long param;
  83. };
  84. enum {
  85. MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  86. };
  87. static struct workqueue_struct *mlx5_ib_event_wq;
  88. static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  89. static LIST_HEAD(mlx5_ib_dev_list);
  90. /*
  91. * This mutex should be held when accessing either of the above lists
  92. */
  93. static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  94. /* We can't use an array for xlt_emergency_page because dma_map_single
  95. * doesn't work on kernel modules memory
  96. */
  97. static unsigned long xlt_emergency_page;
  98. static struct mutex xlt_emergency_page_mutex;
  99. struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  100. {
  101. struct mlx5_ib_dev *dev;
  102. mutex_lock(&mlx5_ib_multiport_mutex);
  103. dev = mpi->ibdev;
  104. mutex_unlock(&mlx5_ib_multiport_mutex);
  105. return dev;
  106. }
  107. static enum rdma_link_layer
  108. mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  109. {
  110. switch (port_type_cap) {
  111. case MLX5_CAP_PORT_TYPE_IB:
  112. return IB_LINK_LAYER_INFINIBAND;
  113. case MLX5_CAP_PORT_TYPE_ETH:
  114. return IB_LINK_LAYER_ETHERNET;
  115. default:
  116. return IB_LINK_LAYER_UNSPECIFIED;
  117. }
  118. }
  119. static enum rdma_link_layer
  120. mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  121. {
  122. struct mlx5_ib_dev *dev = to_mdev(device);
  123. int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  124. return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  125. }
  126. static int get_port_state(struct ib_device *ibdev,
  127. u8 port_num,
  128. enum ib_port_state *state)
  129. {
  130. struct ib_port_attr attr;
  131. int ret;
  132. memset(&attr, 0, sizeof(attr));
  133. ret = ibdev->query_port(ibdev, port_num, &attr);
  134. if (!ret)
  135. *state = attr.state;
  136. return ret;
  137. }
  138. static int mlx5_netdev_event(struct notifier_block *this,
  139. unsigned long event, void *ptr)
  140. {
  141. struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
  142. struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
  143. u8 port_num = roce->native_port_num;
  144. struct mlx5_core_dev *mdev;
  145. struct mlx5_ib_dev *ibdev;
  146. ibdev = roce->dev;
  147. mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
  148. if (!mdev)
  149. return NOTIFY_DONE;
  150. switch (event) {
  151. case NETDEV_REGISTER:
  152. case NETDEV_UNREGISTER:
  153. write_lock(&roce->netdev_lock);
  154. if (ibdev->rep) {
  155. struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
  156. struct net_device *rep_ndev;
  157. rep_ndev = mlx5_ib_get_rep_netdev(esw,
  158. ibdev->rep->vport);
  159. if (rep_ndev == ndev)
  160. roce->netdev = (event == NETDEV_UNREGISTER) ?
  161. NULL : ndev;
  162. } else if (ndev->dev.parent == &mdev->pdev->dev) {
  163. roce->netdev = (event == NETDEV_UNREGISTER) ?
  164. NULL : ndev;
  165. }
  166. write_unlock(&roce->netdev_lock);
  167. break;
  168. case NETDEV_CHANGE:
  169. case NETDEV_UP:
  170. case NETDEV_DOWN: {
  171. struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
  172. struct net_device *upper = NULL;
  173. if (lag_ndev) {
  174. upper = netdev_master_upper_dev_get(lag_ndev);
  175. dev_put(lag_ndev);
  176. }
  177. if ((upper == ndev || (!upper && ndev == roce->netdev))
  178. && ibdev->ib_active) {
  179. struct ib_event ibev = { };
  180. enum ib_port_state port_state;
  181. if (get_port_state(&ibdev->ib_dev, port_num,
  182. &port_state))
  183. goto done;
  184. if (roce->last_port_state == port_state)
  185. goto done;
  186. roce->last_port_state = port_state;
  187. ibev.device = &ibdev->ib_dev;
  188. if (port_state == IB_PORT_DOWN)
  189. ibev.event = IB_EVENT_PORT_ERR;
  190. else if (port_state == IB_PORT_ACTIVE)
  191. ibev.event = IB_EVENT_PORT_ACTIVE;
  192. else
  193. goto done;
  194. ibev.element.port_num = port_num;
  195. ib_dispatch_event(&ibev);
  196. }
  197. break;
  198. }
  199. default:
  200. break;
  201. }
  202. done:
  203. mlx5_ib_put_native_port_mdev(ibdev, port_num);
  204. return NOTIFY_DONE;
  205. }
  206. static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
  207. u8 port_num)
  208. {
  209. struct mlx5_ib_dev *ibdev = to_mdev(device);
  210. struct net_device *ndev;
  211. struct mlx5_core_dev *mdev;
  212. mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
  213. if (!mdev)
  214. return NULL;
  215. ndev = mlx5_lag_get_roce_netdev(mdev);
  216. if (ndev)
  217. goto out;
  218. /* Ensure ndev does not disappear before we invoke dev_hold()
  219. */
  220. read_lock(&ibdev->roce[port_num - 1].netdev_lock);
  221. ndev = ibdev->roce[port_num - 1].netdev;
  222. if (ndev)
  223. dev_hold(ndev);
  224. read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
  225. out:
  226. mlx5_ib_put_native_port_mdev(ibdev, port_num);
  227. return ndev;
  228. }
  229. struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
  230. u8 ib_port_num,
  231. u8 *native_port_num)
  232. {
  233. enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
  234. ib_port_num);
  235. struct mlx5_core_dev *mdev = NULL;
  236. struct mlx5_ib_multiport_info *mpi;
  237. struct mlx5_ib_port *port;
  238. if (!mlx5_core_mp_enabled(ibdev->mdev) ||
  239. ll != IB_LINK_LAYER_ETHERNET) {
  240. if (native_port_num)
  241. *native_port_num = ib_port_num;
  242. return ibdev->mdev;
  243. }
  244. if (native_port_num)
  245. *native_port_num = 1;
  246. port = &ibdev->port[ib_port_num - 1];
  247. if (!port)
  248. return NULL;
  249. spin_lock(&port->mp.mpi_lock);
  250. mpi = ibdev->port[ib_port_num - 1].mp.mpi;
  251. if (mpi && !mpi->unaffiliate) {
  252. mdev = mpi->mdev;
  253. /* If it's the master no need to refcount, it'll exist
  254. * as long as the ib_dev exists.
  255. */
  256. if (!mpi->is_master)
  257. mpi->mdev_refcnt++;
  258. }
  259. spin_unlock(&port->mp.mpi_lock);
  260. return mdev;
  261. }
  262. void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
  263. {
  264. enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
  265. port_num);
  266. struct mlx5_ib_multiport_info *mpi;
  267. struct mlx5_ib_port *port;
  268. if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
  269. return;
  270. port = &ibdev->port[port_num - 1];
  271. spin_lock(&port->mp.mpi_lock);
  272. mpi = ibdev->port[port_num - 1].mp.mpi;
  273. if (mpi->is_master)
  274. goto out;
  275. mpi->mdev_refcnt--;
  276. if (mpi->unaffiliate)
  277. complete(&mpi->unref_comp);
  278. out:
  279. spin_unlock(&port->mp.mpi_lock);
  280. }
  281. static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
  282. u8 *active_width)
  283. {
  284. switch (eth_proto_oper) {
  285. case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
  286. case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
  287. case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
  288. case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
  289. *active_width = IB_WIDTH_1X;
  290. *active_speed = IB_SPEED_SDR;
  291. break;
  292. case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
  293. case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
  294. case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
  295. case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
  296. case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
  297. case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
  298. case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
  299. *active_width = IB_WIDTH_1X;
  300. *active_speed = IB_SPEED_QDR;
  301. break;
  302. case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
  303. case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
  304. case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
  305. *active_width = IB_WIDTH_1X;
  306. *active_speed = IB_SPEED_EDR;
  307. break;
  308. case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
  309. case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
  310. case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
  311. case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
  312. *active_width = IB_WIDTH_4X;
  313. *active_speed = IB_SPEED_QDR;
  314. break;
  315. case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
  316. case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
  317. case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
  318. *active_width = IB_WIDTH_1X;
  319. *active_speed = IB_SPEED_HDR;
  320. break;
  321. case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
  322. *active_width = IB_WIDTH_4X;
  323. *active_speed = IB_SPEED_FDR;
  324. break;
  325. case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
  326. case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
  327. case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
  328. case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
  329. *active_width = IB_WIDTH_4X;
  330. *active_speed = IB_SPEED_EDR;
  331. break;
  332. default:
  333. return -EINVAL;
  334. }
  335. return 0;
  336. }
  337. static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
  338. struct ib_port_attr *props)
  339. {
  340. struct mlx5_ib_dev *dev = to_mdev(device);
  341. struct mlx5_core_dev *mdev;
  342. struct net_device *ndev, *upper;
  343. enum ib_mtu ndev_ib_mtu;
  344. bool put_mdev = true;
  345. u16 qkey_viol_cntr;
  346. u32 eth_prot_oper;
  347. u8 mdev_port_num;
  348. int err;
  349. mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
  350. if (!mdev) {
  351. /* This means the port isn't affiliated yet. Get the
  352. * info for the master port instead.
  353. */
  354. put_mdev = false;
  355. mdev = dev->mdev;
  356. mdev_port_num = 1;
  357. port_num = 1;
  358. }
  359. /* Possible bad flows are checked before filling out props so in case
  360. * of an error it will still be zeroed out.
  361. */
  362. err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
  363. mdev_port_num);
  364. if (err)
  365. goto out;
  366. props->active_width = IB_WIDTH_4X;
  367. props->active_speed = IB_SPEED_QDR;
  368. translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
  369. &props->active_width);
  370. props->port_cap_flags |= IB_PORT_CM_SUP;
  371. props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
  372. props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
  373. roce_address_table_size);
  374. props->max_mtu = IB_MTU_4096;
  375. props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
  376. props->pkey_tbl_len = 1;
  377. props->state = IB_PORT_DOWN;
  378. props->phys_state = 3;
  379. mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
  380. props->qkey_viol_cntr = qkey_viol_cntr;
  381. /* If this is a stub query for an unaffiliated port stop here */
  382. if (!put_mdev)
  383. goto out;
  384. ndev = mlx5_ib_get_netdev(device, port_num);
  385. if (!ndev)
  386. goto out;
  387. if (mlx5_lag_is_active(dev->mdev)) {
  388. rcu_read_lock();
  389. upper = netdev_master_upper_dev_get_rcu(ndev);
  390. if (upper) {
  391. dev_put(ndev);
  392. ndev = upper;
  393. dev_hold(ndev);
  394. }
  395. rcu_read_unlock();
  396. }
  397. if (netif_running(ndev) && netif_carrier_ok(ndev)) {
  398. props->state = IB_PORT_ACTIVE;
  399. props->phys_state = 5;
  400. }
  401. ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
  402. dev_put(ndev);
  403. props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
  404. out:
  405. if (put_mdev)
  406. mlx5_ib_put_native_port_mdev(dev, port_num);
  407. return err;
  408. }
  409. static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
  410. unsigned int index, const union ib_gid *gid,
  411. const struct ib_gid_attr *attr)
  412. {
  413. enum ib_gid_type gid_type = IB_GID_TYPE_IB;
  414. u8 roce_version = 0;
  415. u8 roce_l3_type = 0;
  416. bool vlan = false;
  417. u8 mac[ETH_ALEN];
  418. u16 vlan_id = 0;
  419. if (gid) {
  420. gid_type = attr->gid_type;
  421. ether_addr_copy(mac, attr->ndev->dev_addr);
  422. if (is_vlan_dev(attr->ndev)) {
  423. vlan = true;
  424. vlan_id = vlan_dev_vlan_id(attr->ndev);
  425. }
  426. }
  427. switch (gid_type) {
  428. case IB_GID_TYPE_IB:
  429. roce_version = MLX5_ROCE_VERSION_1;
  430. break;
  431. case IB_GID_TYPE_ROCE_UDP_ENCAP:
  432. roce_version = MLX5_ROCE_VERSION_2;
  433. if (ipv6_addr_v4mapped((void *)gid))
  434. roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
  435. else
  436. roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
  437. break;
  438. default:
  439. mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
  440. }
  441. return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
  442. roce_l3_type, gid->raw, mac, vlan,
  443. vlan_id, port_num);
  444. }
  445. static int mlx5_ib_add_gid(const union ib_gid *gid,
  446. const struct ib_gid_attr *attr,
  447. __always_unused void **context)
  448. {
  449. return set_roce_addr(to_mdev(attr->device), attr->port_num,
  450. attr->index, gid, attr);
  451. }
  452. static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
  453. __always_unused void **context)
  454. {
  455. return set_roce_addr(to_mdev(attr->device), attr->port_num,
  456. attr->index, NULL, NULL);
  457. }
  458. __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
  459. int index)
  460. {
  461. struct ib_gid_attr attr;
  462. union ib_gid gid;
  463. if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
  464. return 0;
  465. dev_put(attr.ndev);
  466. if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
  467. return 0;
  468. return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
  469. }
  470. int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
  471. int index, enum ib_gid_type *gid_type)
  472. {
  473. struct ib_gid_attr attr;
  474. union ib_gid gid;
  475. int ret;
  476. ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
  477. if (ret)
  478. return ret;
  479. dev_put(attr.ndev);
  480. *gid_type = attr.gid_type;
  481. return 0;
  482. }
  483. static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
  484. {
  485. if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
  486. return !MLX5_CAP_GEN(dev->mdev, ib_virt);
  487. return 0;
  488. }
  489. enum {
  490. MLX5_VPORT_ACCESS_METHOD_MAD,
  491. MLX5_VPORT_ACCESS_METHOD_HCA,
  492. MLX5_VPORT_ACCESS_METHOD_NIC,
  493. };
  494. static int mlx5_get_vport_access_method(struct ib_device *ibdev)
  495. {
  496. if (mlx5_use_mad_ifc(to_mdev(ibdev)))
  497. return MLX5_VPORT_ACCESS_METHOD_MAD;
  498. if (mlx5_ib_port_link_layer(ibdev, 1) ==
  499. IB_LINK_LAYER_ETHERNET)
  500. return MLX5_VPORT_ACCESS_METHOD_NIC;
  501. return MLX5_VPORT_ACCESS_METHOD_HCA;
  502. }
  503. static void get_atomic_caps(struct mlx5_ib_dev *dev,
  504. u8 atomic_size_qp,
  505. struct ib_device_attr *props)
  506. {
  507. u8 tmp;
  508. u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
  509. u8 atomic_req_8B_endianness_mode =
  510. MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
  511. /* Check if HW supports 8 bytes standard atomic operations and capable
  512. * of host endianness respond
  513. */
  514. tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
  515. if (((atomic_operations & tmp) == tmp) &&
  516. (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
  517. (atomic_req_8B_endianness_mode)) {
  518. props->atomic_cap = IB_ATOMIC_HCA;
  519. } else {
  520. props->atomic_cap = IB_ATOMIC_NONE;
  521. }
  522. }
  523. static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
  524. struct ib_device_attr *props)
  525. {
  526. u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
  527. get_atomic_caps(dev, atomic_size_qp, props);
  528. }
  529. static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
  530. struct ib_device_attr *props)
  531. {
  532. u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
  533. get_atomic_caps(dev, atomic_size_qp, props);
  534. }
  535. bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
  536. {
  537. struct ib_device_attr props = {};
  538. get_atomic_caps_dc(dev, &props);
  539. return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
  540. }
  541. static int mlx5_query_system_image_guid(struct ib_device *ibdev,
  542. __be64 *sys_image_guid)
  543. {
  544. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  545. struct mlx5_core_dev *mdev = dev->mdev;
  546. u64 tmp;
  547. int err;
  548. switch (mlx5_get_vport_access_method(ibdev)) {
  549. case MLX5_VPORT_ACCESS_METHOD_MAD:
  550. return mlx5_query_mad_ifc_system_image_guid(ibdev,
  551. sys_image_guid);
  552. case MLX5_VPORT_ACCESS_METHOD_HCA:
  553. err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
  554. break;
  555. case MLX5_VPORT_ACCESS_METHOD_NIC:
  556. err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
  557. break;
  558. default:
  559. return -EINVAL;
  560. }
  561. if (!err)
  562. *sys_image_guid = cpu_to_be64(tmp);
  563. return err;
  564. }
  565. static int mlx5_query_max_pkeys(struct ib_device *ibdev,
  566. u16 *max_pkeys)
  567. {
  568. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  569. struct mlx5_core_dev *mdev = dev->mdev;
  570. switch (mlx5_get_vport_access_method(ibdev)) {
  571. case MLX5_VPORT_ACCESS_METHOD_MAD:
  572. return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
  573. case MLX5_VPORT_ACCESS_METHOD_HCA:
  574. case MLX5_VPORT_ACCESS_METHOD_NIC:
  575. *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
  576. pkey_table_size));
  577. return 0;
  578. default:
  579. return -EINVAL;
  580. }
  581. }
  582. static int mlx5_query_vendor_id(struct ib_device *ibdev,
  583. u32 *vendor_id)
  584. {
  585. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  586. switch (mlx5_get_vport_access_method(ibdev)) {
  587. case MLX5_VPORT_ACCESS_METHOD_MAD:
  588. return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
  589. case MLX5_VPORT_ACCESS_METHOD_HCA:
  590. case MLX5_VPORT_ACCESS_METHOD_NIC:
  591. return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
  592. default:
  593. return -EINVAL;
  594. }
  595. }
  596. static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
  597. __be64 *node_guid)
  598. {
  599. u64 tmp;
  600. int err;
  601. switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
  602. case MLX5_VPORT_ACCESS_METHOD_MAD:
  603. return mlx5_query_mad_ifc_node_guid(dev, node_guid);
  604. case MLX5_VPORT_ACCESS_METHOD_HCA:
  605. err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
  606. break;
  607. case MLX5_VPORT_ACCESS_METHOD_NIC:
  608. err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
  609. break;
  610. default:
  611. return -EINVAL;
  612. }
  613. if (!err)
  614. *node_guid = cpu_to_be64(tmp);
  615. return err;
  616. }
  617. struct mlx5_reg_node_desc {
  618. u8 desc[IB_DEVICE_NODE_DESC_MAX];
  619. };
  620. static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
  621. {
  622. struct mlx5_reg_node_desc in;
  623. if (mlx5_use_mad_ifc(dev))
  624. return mlx5_query_mad_ifc_node_desc(dev, node_desc);
  625. memset(&in, 0, sizeof(in));
  626. return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
  627. sizeof(struct mlx5_reg_node_desc),
  628. MLX5_REG_NODE_DESC, 0, 0);
  629. }
  630. static int mlx5_ib_query_device(struct ib_device *ibdev,
  631. struct ib_device_attr *props,
  632. struct ib_udata *uhw)
  633. {
  634. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  635. struct mlx5_core_dev *mdev = dev->mdev;
  636. int err = -ENOMEM;
  637. int max_sq_desc;
  638. int max_rq_sg;
  639. int max_sq_sg;
  640. u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
  641. bool raw_support = !mlx5_core_mp_enabled(mdev);
  642. struct mlx5_ib_query_device_resp resp = {};
  643. size_t resp_len;
  644. u64 max_tso;
  645. resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
  646. if (uhw->outlen && uhw->outlen < resp_len)
  647. return -EINVAL;
  648. else
  649. resp.response_length = resp_len;
  650. if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
  651. return -EINVAL;
  652. memset(props, 0, sizeof(*props));
  653. err = mlx5_query_system_image_guid(ibdev,
  654. &props->sys_image_guid);
  655. if (err)
  656. return err;
  657. err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
  658. if (err)
  659. return err;
  660. err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
  661. if (err)
  662. return err;
  663. props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
  664. (fw_rev_min(dev->mdev) << 16) |
  665. fw_rev_sub(dev->mdev);
  666. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  667. IB_DEVICE_PORT_ACTIVE_EVENT |
  668. IB_DEVICE_SYS_IMAGE_GUID |
  669. IB_DEVICE_RC_RNR_NAK_GEN;
  670. if (MLX5_CAP_GEN(mdev, pkv))
  671. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  672. if (MLX5_CAP_GEN(mdev, qkv))
  673. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  674. if (MLX5_CAP_GEN(mdev, apm))
  675. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  676. if (MLX5_CAP_GEN(mdev, xrc))
  677. props->device_cap_flags |= IB_DEVICE_XRC;
  678. if (MLX5_CAP_GEN(mdev, imaicl)) {
  679. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
  680. IB_DEVICE_MEM_WINDOW_TYPE_2B;
  681. props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
  682. /* We support 'Gappy' memory registration too */
  683. props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
  684. }
  685. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  686. if (MLX5_CAP_GEN(mdev, sho)) {
  687. props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
  688. /* At this stage no support for signature handover */
  689. props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
  690. IB_PROT_T10DIF_TYPE_2 |
  691. IB_PROT_T10DIF_TYPE_3;
  692. props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
  693. IB_GUARD_T10DIF_CSUM;
  694. }
  695. if (MLX5_CAP_GEN(mdev, block_lb_mc))
  696. props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  697. if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
  698. if (MLX5_CAP_ETH(mdev, csum_cap)) {
  699. /* Legacy bit to support old userspace libraries */
  700. props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
  701. props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
  702. }
  703. if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
  704. props->raw_packet_caps |=
  705. IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
  706. if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
  707. max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
  708. if (max_tso) {
  709. resp.tso_caps.max_tso = 1 << max_tso;
  710. resp.tso_caps.supported_qpts |=
  711. 1 << IB_QPT_RAW_PACKET;
  712. resp.response_length += sizeof(resp.tso_caps);
  713. }
  714. }
  715. if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
  716. resp.rss_caps.rx_hash_function =
  717. MLX5_RX_HASH_FUNC_TOEPLITZ;
  718. resp.rss_caps.rx_hash_fields_mask =
  719. MLX5_RX_HASH_SRC_IPV4 |
  720. MLX5_RX_HASH_DST_IPV4 |
  721. MLX5_RX_HASH_SRC_IPV6 |
  722. MLX5_RX_HASH_DST_IPV6 |
  723. MLX5_RX_HASH_SRC_PORT_TCP |
  724. MLX5_RX_HASH_DST_PORT_TCP |
  725. MLX5_RX_HASH_SRC_PORT_UDP |
  726. MLX5_RX_HASH_DST_PORT_UDP |
  727. MLX5_RX_HASH_INNER;
  728. if (mlx5_accel_ipsec_device_caps(dev->mdev) &
  729. MLX5_ACCEL_IPSEC_CAP_DEVICE)
  730. resp.rss_caps.rx_hash_fields_mask |=
  731. MLX5_RX_HASH_IPSEC_SPI;
  732. resp.response_length += sizeof(resp.rss_caps);
  733. }
  734. } else {
  735. if (field_avail(typeof(resp), tso_caps, uhw->outlen))
  736. resp.response_length += sizeof(resp.tso_caps);
  737. if (field_avail(typeof(resp), rss_caps, uhw->outlen))
  738. resp.response_length += sizeof(resp.rss_caps);
  739. }
  740. if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
  741. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  742. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  743. }
  744. if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
  745. MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
  746. raw_support)
  747. props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
  748. if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
  749. MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
  750. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  751. if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
  752. MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
  753. raw_support) {
  754. /* Legacy bit to support old userspace libraries */
  755. props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
  756. props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
  757. }
  758. if (MLX5_CAP_DEV_MEM(mdev, memic)) {
  759. props->max_dm_size =
  760. MLX5_CAP_DEV_MEM(mdev, max_memic_size);
  761. }
  762. if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
  763. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  764. if (MLX5_CAP_GEN(mdev, end_pad))
  765. props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
  766. props->vendor_part_id = mdev->pdev->device;
  767. props->hw_ver = mdev->pdev->revision;
  768. props->max_mr_size = ~0ull;
  769. props->page_size_cap = ~(min_page_size - 1);
  770. props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
  771. props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
  772. max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
  773. sizeof(struct mlx5_wqe_data_seg);
  774. max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
  775. max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
  776. sizeof(struct mlx5_wqe_raddr_seg)) /
  777. sizeof(struct mlx5_wqe_data_seg);
  778. props->max_sge = min(max_rq_sg, max_sq_sg);
  779. props->max_sge_rd = MLX5_MAX_SGE_RD;
  780. props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
  781. props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
  782. props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
  783. props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
  784. props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
  785. props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
  786. props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
  787. props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
  788. props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
  789. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  790. props->max_srq_sge = max_rq_sg - 1;
  791. props->max_fast_reg_page_list_len =
  792. 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
  793. get_atomic_caps_qp(dev, props);
  794. props->masked_atomic_cap = IB_ATOMIC_NONE;
  795. props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
  796. props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
  797. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  798. props->max_mcast_grp;
  799. props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
  800. props->max_ah = INT_MAX;
  801. props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
  802. props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
  803. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  804. if (MLX5_CAP_GEN(mdev, pg))
  805. props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
  806. props->odp_caps = dev->odp_caps;
  807. #endif
  808. if (MLX5_CAP_GEN(mdev, cd))
  809. props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
  810. if (!mlx5_core_is_pf(mdev))
  811. props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
  812. if (mlx5_ib_port_link_layer(ibdev, 1) ==
  813. IB_LINK_LAYER_ETHERNET && raw_support) {
  814. props->rss_caps.max_rwq_indirection_tables =
  815. 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
  816. props->rss_caps.max_rwq_indirection_table_size =
  817. 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
  818. props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
  819. props->max_wq_type_rq =
  820. 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
  821. }
  822. if (MLX5_CAP_GEN(mdev, tag_matching)) {
  823. props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
  824. props->tm_caps.max_num_tags =
  825. (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
  826. props->tm_caps.flags = IB_TM_CAP_RC;
  827. props->tm_caps.max_ops =
  828. 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
  829. props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
  830. }
  831. if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
  832. props->cq_caps.max_cq_moderation_count =
  833. MLX5_MAX_CQ_COUNT;
  834. props->cq_caps.max_cq_moderation_period =
  835. MLX5_MAX_CQ_PERIOD;
  836. }
  837. if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
  838. resp.cqe_comp_caps.max_num =
  839. MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
  840. MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
  841. resp.cqe_comp_caps.supported_format =
  842. MLX5_IB_CQE_RES_FORMAT_HASH |
  843. MLX5_IB_CQE_RES_FORMAT_CSUM;
  844. resp.response_length += sizeof(resp.cqe_comp_caps);
  845. }
  846. if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
  847. raw_support) {
  848. if (MLX5_CAP_QOS(mdev, packet_pacing) &&
  849. MLX5_CAP_GEN(mdev, qos)) {
  850. resp.packet_pacing_caps.qp_rate_limit_max =
  851. MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
  852. resp.packet_pacing_caps.qp_rate_limit_min =
  853. MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
  854. resp.packet_pacing_caps.supported_qpts |=
  855. 1 << IB_QPT_RAW_PACKET;
  856. if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
  857. MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
  858. resp.packet_pacing_caps.cap_flags |=
  859. MLX5_IB_PP_SUPPORT_BURST;
  860. }
  861. resp.response_length += sizeof(resp.packet_pacing_caps);
  862. }
  863. if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
  864. uhw->outlen)) {
  865. if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
  866. resp.mlx5_ib_support_multi_pkt_send_wqes =
  867. MLX5_IB_ALLOW_MPW;
  868. if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
  869. resp.mlx5_ib_support_multi_pkt_send_wqes |=
  870. MLX5_IB_SUPPORT_EMPW;
  871. resp.response_length +=
  872. sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
  873. }
  874. if (field_avail(typeof(resp), flags, uhw->outlen)) {
  875. resp.response_length += sizeof(resp.flags);
  876. if (MLX5_CAP_GEN(mdev, cqe_compression_128))
  877. resp.flags |=
  878. MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
  879. if (MLX5_CAP_GEN(mdev, cqe_128_always))
  880. resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
  881. }
  882. if (field_avail(typeof(resp), sw_parsing_caps,
  883. uhw->outlen)) {
  884. resp.response_length += sizeof(resp.sw_parsing_caps);
  885. if (MLX5_CAP_ETH(mdev, swp)) {
  886. resp.sw_parsing_caps.sw_parsing_offloads |=
  887. MLX5_IB_SW_PARSING;
  888. if (MLX5_CAP_ETH(mdev, swp_csum))
  889. resp.sw_parsing_caps.sw_parsing_offloads |=
  890. MLX5_IB_SW_PARSING_CSUM;
  891. if (MLX5_CAP_ETH(mdev, swp_lso))
  892. resp.sw_parsing_caps.sw_parsing_offloads |=
  893. MLX5_IB_SW_PARSING_LSO;
  894. if (resp.sw_parsing_caps.sw_parsing_offloads)
  895. resp.sw_parsing_caps.supported_qpts =
  896. BIT(IB_QPT_RAW_PACKET);
  897. }
  898. }
  899. if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
  900. raw_support) {
  901. resp.response_length += sizeof(resp.striding_rq_caps);
  902. if (MLX5_CAP_GEN(mdev, striding_rq)) {
  903. resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
  904. MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
  905. resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
  906. MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
  907. resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
  908. MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
  909. resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
  910. MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
  911. resp.striding_rq_caps.supported_qpts =
  912. BIT(IB_QPT_RAW_PACKET);
  913. }
  914. }
  915. if (field_avail(typeof(resp), tunnel_offloads_caps,
  916. uhw->outlen)) {
  917. resp.response_length += sizeof(resp.tunnel_offloads_caps);
  918. if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
  919. resp.tunnel_offloads_caps |=
  920. MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
  921. if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
  922. resp.tunnel_offloads_caps |=
  923. MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
  924. if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
  925. resp.tunnel_offloads_caps |=
  926. MLX5_IB_TUNNELED_OFFLOADS_GRE;
  927. }
  928. if (uhw->outlen) {
  929. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  930. if (err)
  931. return err;
  932. }
  933. return 0;
  934. }
  935. enum mlx5_ib_width {
  936. MLX5_IB_WIDTH_1X = 1 << 0,
  937. MLX5_IB_WIDTH_2X = 1 << 1,
  938. MLX5_IB_WIDTH_4X = 1 << 2,
  939. MLX5_IB_WIDTH_8X = 1 << 3,
  940. MLX5_IB_WIDTH_12X = 1 << 4
  941. };
  942. static int translate_active_width(struct ib_device *ibdev, u8 active_width,
  943. u8 *ib_width)
  944. {
  945. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  946. int err = 0;
  947. if (active_width & MLX5_IB_WIDTH_1X) {
  948. *ib_width = IB_WIDTH_1X;
  949. } else if (active_width & MLX5_IB_WIDTH_2X) {
  950. mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
  951. (int)active_width);
  952. err = -EINVAL;
  953. } else if (active_width & MLX5_IB_WIDTH_4X) {
  954. *ib_width = IB_WIDTH_4X;
  955. } else if (active_width & MLX5_IB_WIDTH_8X) {
  956. *ib_width = IB_WIDTH_8X;
  957. } else if (active_width & MLX5_IB_WIDTH_12X) {
  958. *ib_width = IB_WIDTH_12X;
  959. } else {
  960. mlx5_ib_dbg(dev, "Invalid active_width %d\n",
  961. (int)active_width);
  962. err = -EINVAL;
  963. }
  964. return err;
  965. }
  966. static int mlx5_mtu_to_ib_mtu(int mtu)
  967. {
  968. switch (mtu) {
  969. case 256: return 1;
  970. case 512: return 2;
  971. case 1024: return 3;
  972. case 2048: return 4;
  973. case 4096: return 5;
  974. default:
  975. pr_warn("invalid mtu\n");
  976. return -1;
  977. }
  978. }
  979. enum ib_max_vl_num {
  980. __IB_MAX_VL_0 = 1,
  981. __IB_MAX_VL_0_1 = 2,
  982. __IB_MAX_VL_0_3 = 3,
  983. __IB_MAX_VL_0_7 = 4,
  984. __IB_MAX_VL_0_14 = 5,
  985. };
  986. enum mlx5_vl_hw_cap {
  987. MLX5_VL_HW_0 = 1,
  988. MLX5_VL_HW_0_1 = 2,
  989. MLX5_VL_HW_0_2 = 3,
  990. MLX5_VL_HW_0_3 = 4,
  991. MLX5_VL_HW_0_4 = 5,
  992. MLX5_VL_HW_0_5 = 6,
  993. MLX5_VL_HW_0_6 = 7,
  994. MLX5_VL_HW_0_7 = 8,
  995. MLX5_VL_HW_0_14 = 15
  996. };
  997. static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
  998. u8 *max_vl_num)
  999. {
  1000. switch (vl_hw_cap) {
  1001. case MLX5_VL_HW_0:
  1002. *max_vl_num = __IB_MAX_VL_0;
  1003. break;
  1004. case MLX5_VL_HW_0_1:
  1005. *max_vl_num = __IB_MAX_VL_0_1;
  1006. break;
  1007. case MLX5_VL_HW_0_3:
  1008. *max_vl_num = __IB_MAX_VL_0_3;
  1009. break;
  1010. case MLX5_VL_HW_0_7:
  1011. *max_vl_num = __IB_MAX_VL_0_7;
  1012. break;
  1013. case MLX5_VL_HW_0_14:
  1014. *max_vl_num = __IB_MAX_VL_0_14;
  1015. break;
  1016. default:
  1017. return -EINVAL;
  1018. }
  1019. return 0;
  1020. }
  1021. static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
  1022. struct ib_port_attr *props)
  1023. {
  1024. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1025. struct mlx5_core_dev *mdev = dev->mdev;
  1026. struct mlx5_hca_vport_context *rep;
  1027. u16 max_mtu;
  1028. u16 oper_mtu;
  1029. int err;
  1030. u8 ib_link_width_oper;
  1031. u8 vl_hw_cap;
  1032. rep = kzalloc(sizeof(*rep), GFP_KERNEL);
  1033. if (!rep) {
  1034. err = -ENOMEM;
  1035. goto out;
  1036. }
  1037. /* props being zeroed by the caller, avoid zeroing it here */
  1038. err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
  1039. if (err)
  1040. goto out;
  1041. props->lid = rep->lid;
  1042. props->lmc = rep->lmc;
  1043. props->sm_lid = rep->sm_lid;
  1044. props->sm_sl = rep->sm_sl;
  1045. props->state = rep->vport_state;
  1046. props->phys_state = rep->port_physical_state;
  1047. props->port_cap_flags = rep->cap_mask1;
  1048. props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
  1049. props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
  1050. props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
  1051. props->bad_pkey_cntr = rep->pkey_violation_counter;
  1052. props->qkey_viol_cntr = rep->qkey_violation_counter;
  1053. props->subnet_timeout = rep->subnet_timeout;
  1054. props->init_type_reply = rep->init_type_reply;
  1055. props->grh_required = rep->grh_required;
  1056. err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
  1057. if (err)
  1058. goto out;
  1059. err = translate_active_width(ibdev, ib_link_width_oper,
  1060. &props->active_width);
  1061. if (err)
  1062. goto out;
  1063. err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
  1064. if (err)
  1065. goto out;
  1066. mlx5_query_port_max_mtu(mdev, &max_mtu, port);
  1067. props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
  1068. mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
  1069. props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
  1070. err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
  1071. if (err)
  1072. goto out;
  1073. err = translate_max_vl_num(ibdev, vl_hw_cap,
  1074. &props->max_vl_num);
  1075. out:
  1076. kfree(rep);
  1077. return err;
  1078. }
  1079. int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
  1080. struct ib_port_attr *props)
  1081. {
  1082. unsigned int count;
  1083. int ret;
  1084. switch (mlx5_get_vport_access_method(ibdev)) {
  1085. case MLX5_VPORT_ACCESS_METHOD_MAD:
  1086. ret = mlx5_query_mad_ifc_port(ibdev, port, props);
  1087. break;
  1088. case MLX5_VPORT_ACCESS_METHOD_HCA:
  1089. ret = mlx5_query_hca_port(ibdev, port, props);
  1090. break;
  1091. case MLX5_VPORT_ACCESS_METHOD_NIC:
  1092. ret = mlx5_query_port_roce(ibdev, port, props);
  1093. break;
  1094. default:
  1095. ret = -EINVAL;
  1096. }
  1097. if (!ret && props) {
  1098. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1099. struct mlx5_core_dev *mdev;
  1100. bool put_mdev = true;
  1101. mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
  1102. if (!mdev) {
  1103. /* If the port isn't affiliated yet query the master.
  1104. * The master and slave will have the same values.
  1105. */
  1106. mdev = dev->mdev;
  1107. port = 1;
  1108. put_mdev = false;
  1109. }
  1110. count = mlx5_core_reserved_gids_count(mdev);
  1111. if (put_mdev)
  1112. mlx5_ib_put_native_port_mdev(dev, port);
  1113. props->gid_tbl_len -= count;
  1114. }
  1115. return ret;
  1116. }
  1117. static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
  1118. struct ib_port_attr *props)
  1119. {
  1120. int ret;
  1121. /* Only link layer == ethernet is valid for representors */
  1122. ret = mlx5_query_port_roce(ibdev, port, props);
  1123. if (ret || !props)
  1124. return ret;
  1125. /* We don't support GIDS */
  1126. props->gid_tbl_len = 0;
  1127. return ret;
  1128. }
  1129. static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  1130. union ib_gid *gid)
  1131. {
  1132. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1133. struct mlx5_core_dev *mdev = dev->mdev;
  1134. switch (mlx5_get_vport_access_method(ibdev)) {
  1135. case MLX5_VPORT_ACCESS_METHOD_MAD:
  1136. return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
  1137. case MLX5_VPORT_ACCESS_METHOD_HCA:
  1138. return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
  1139. default:
  1140. return -EINVAL;
  1141. }
  1142. }
  1143. static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
  1144. u16 index, u16 *pkey)
  1145. {
  1146. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1147. struct mlx5_core_dev *mdev;
  1148. bool put_mdev = true;
  1149. u8 mdev_port_num;
  1150. int err;
  1151. mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
  1152. if (!mdev) {
  1153. /* The port isn't affiliated yet, get the PKey from the master
  1154. * port. For RoCE the PKey tables will be the same.
  1155. */
  1156. put_mdev = false;
  1157. mdev = dev->mdev;
  1158. mdev_port_num = 1;
  1159. }
  1160. err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
  1161. index, pkey);
  1162. if (put_mdev)
  1163. mlx5_ib_put_native_port_mdev(dev, port);
  1164. return err;
  1165. }
  1166. static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  1167. u16 *pkey)
  1168. {
  1169. switch (mlx5_get_vport_access_method(ibdev)) {
  1170. case MLX5_VPORT_ACCESS_METHOD_MAD:
  1171. return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
  1172. case MLX5_VPORT_ACCESS_METHOD_HCA:
  1173. case MLX5_VPORT_ACCESS_METHOD_NIC:
  1174. return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
  1175. default:
  1176. return -EINVAL;
  1177. }
  1178. }
  1179. static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
  1180. struct ib_device_modify *props)
  1181. {
  1182. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1183. struct mlx5_reg_node_desc in;
  1184. struct mlx5_reg_node_desc out;
  1185. int err;
  1186. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  1187. return -EOPNOTSUPP;
  1188. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  1189. return 0;
  1190. /*
  1191. * If possible, pass node desc to FW, so it can generate
  1192. * a 144 trap. If cmd fails, just ignore.
  1193. */
  1194. memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  1195. err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
  1196. sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
  1197. if (err)
  1198. return err;
  1199. memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  1200. return err;
  1201. }
  1202. static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
  1203. u32 value)
  1204. {
  1205. struct mlx5_hca_vport_context ctx = {};
  1206. struct mlx5_core_dev *mdev;
  1207. u8 mdev_port_num;
  1208. int err;
  1209. mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
  1210. if (!mdev)
  1211. return -ENODEV;
  1212. err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
  1213. if (err)
  1214. goto out;
  1215. if (~ctx.cap_mask1_perm & mask) {
  1216. mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
  1217. mask, ctx.cap_mask1_perm);
  1218. err = -EINVAL;
  1219. goto out;
  1220. }
  1221. ctx.cap_mask1 = value;
  1222. ctx.cap_mask1_perm = mask;
  1223. err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
  1224. 0, &ctx);
  1225. out:
  1226. mlx5_ib_put_native_port_mdev(dev, port_num);
  1227. return err;
  1228. }
  1229. static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  1230. struct ib_port_modify *props)
  1231. {
  1232. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1233. struct ib_port_attr attr;
  1234. u32 tmp;
  1235. int err;
  1236. u32 change_mask;
  1237. u32 value;
  1238. bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
  1239. IB_LINK_LAYER_INFINIBAND);
  1240. /* CM layer calls ib_modify_port() regardless of the link layer. For
  1241. * Ethernet ports, qkey violation and Port capabilities are meaningless.
  1242. */
  1243. if (!is_ib)
  1244. return 0;
  1245. if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
  1246. change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
  1247. value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
  1248. return set_port_caps_atomic(dev, port, change_mask, value);
  1249. }
  1250. mutex_lock(&dev->cap_mask_mutex);
  1251. err = ib_query_port(ibdev, port, &attr);
  1252. if (err)
  1253. goto out;
  1254. tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
  1255. ~props->clr_port_cap_mask;
  1256. err = mlx5_set_port_caps(dev->mdev, port, tmp);
  1257. out:
  1258. mutex_unlock(&dev->cap_mask_mutex);
  1259. return err;
  1260. }
  1261. static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
  1262. {
  1263. mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
  1264. caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
  1265. }
  1266. static u16 calc_dynamic_bfregs(int uars_per_sys_page)
  1267. {
  1268. /* Large page with non 4k uar support might limit the dynamic size */
  1269. if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
  1270. return MLX5_MIN_DYN_BFREGS;
  1271. return MLX5_MAX_DYN_BFREGS;
  1272. }
  1273. static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
  1274. struct mlx5_ib_alloc_ucontext_req_v2 *req,
  1275. struct mlx5_bfreg_info *bfregi)
  1276. {
  1277. int uars_per_sys_page;
  1278. int bfregs_per_sys_page;
  1279. int ref_bfregs = req->total_num_bfregs;
  1280. if (req->total_num_bfregs == 0)
  1281. return -EINVAL;
  1282. BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
  1283. BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
  1284. if (req->total_num_bfregs > MLX5_MAX_BFREGS)
  1285. return -ENOMEM;
  1286. uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
  1287. bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
  1288. /* This holds the required static allocation asked by the user */
  1289. req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
  1290. if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
  1291. return -EINVAL;
  1292. bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
  1293. bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
  1294. bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
  1295. bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
  1296. mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
  1297. MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
  1298. lib_uar_4k ? "yes" : "no", ref_bfregs,
  1299. req->total_num_bfregs, bfregi->total_num_bfregs,
  1300. bfregi->num_sys_pages);
  1301. return 0;
  1302. }
  1303. static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
  1304. {
  1305. struct mlx5_bfreg_info *bfregi;
  1306. int err;
  1307. int i;
  1308. bfregi = &context->bfregi;
  1309. for (i = 0; i < bfregi->num_static_sys_pages; i++) {
  1310. err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
  1311. if (err)
  1312. goto error;
  1313. mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
  1314. }
  1315. for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
  1316. bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
  1317. return 0;
  1318. error:
  1319. for (--i; i >= 0; i--)
  1320. if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
  1321. mlx5_ib_warn(dev, "failed to free uar %d\n", i);
  1322. return err;
  1323. }
  1324. static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
  1325. {
  1326. struct mlx5_bfreg_info *bfregi;
  1327. int err;
  1328. int i;
  1329. bfregi = &context->bfregi;
  1330. for (i = 0; i < bfregi->num_sys_pages; i++) {
  1331. if (i < bfregi->num_static_sys_pages ||
  1332. bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
  1333. err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
  1334. if (err) {
  1335. mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
  1336. return err;
  1337. }
  1338. }
  1339. }
  1340. return 0;
  1341. }
  1342. static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
  1343. {
  1344. int err;
  1345. err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
  1346. if (err)
  1347. return err;
  1348. if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
  1349. (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
  1350. !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
  1351. return err;
  1352. mutex_lock(&dev->lb_mutex);
  1353. dev->user_td++;
  1354. if (dev->user_td == 2)
  1355. err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
  1356. mutex_unlock(&dev->lb_mutex);
  1357. return err;
  1358. }
  1359. static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
  1360. {
  1361. mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
  1362. if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
  1363. (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
  1364. !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
  1365. return;
  1366. mutex_lock(&dev->lb_mutex);
  1367. dev->user_td--;
  1368. if (dev->user_td < 2)
  1369. mlx5_nic_vport_update_local_lb(dev->mdev, false);
  1370. mutex_unlock(&dev->lb_mutex);
  1371. }
  1372. static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
  1373. struct ib_udata *udata)
  1374. {
  1375. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  1376. struct mlx5_ib_alloc_ucontext_req_v2 req = {};
  1377. struct mlx5_ib_alloc_ucontext_resp resp = {};
  1378. struct mlx5_core_dev *mdev = dev->mdev;
  1379. struct mlx5_ib_ucontext *context;
  1380. struct mlx5_bfreg_info *bfregi;
  1381. int ver;
  1382. int err;
  1383. size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
  1384. max_cqe_version);
  1385. bool lib_uar_4k;
  1386. if (!dev->ib_active)
  1387. return ERR_PTR(-EAGAIN);
  1388. if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
  1389. ver = 0;
  1390. else if (udata->inlen >= min_req_v2)
  1391. ver = 2;
  1392. else
  1393. return ERR_PTR(-EINVAL);
  1394. err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
  1395. if (err)
  1396. return ERR_PTR(err);
  1397. if (req.flags)
  1398. return ERR_PTR(-EINVAL);
  1399. if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
  1400. return ERR_PTR(-EOPNOTSUPP);
  1401. req.total_num_bfregs = ALIGN(req.total_num_bfregs,
  1402. MLX5_NON_FP_BFREGS_PER_UAR);
  1403. if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
  1404. return ERR_PTR(-EINVAL);
  1405. resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
  1406. if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
  1407. resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
  1408. resp.cache_line_size = cache_line_size();
  1409. resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
  1410. resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
  1411. resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
  1412. resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
  1413. resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
  1414. resp.cqe_version = min_t(__u8,
  1415. (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
  1416. req.max_cqe_version);
  1417. resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
  1418. MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
  1419. resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
  1420. MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
  1421. resp.response_length = min(offsetof(typeof(resp), response_length) +
  1422. sizeof(resp.response_length), udata->outlen);
  1423. if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
  1424. if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
  1425. resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
  1426. if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
  1427. resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
  1428. if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
  1429. resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
  1430. if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
  1431. resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
  1432. /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
  1433. }
  1434. context = kzalloc(sizeof(*context), GFP_KERNEL);
  1435. if (!context)
  1436. return ERR_PTR(-ENOMEM);
  1437. lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
  1438. bfregi = &context->bfregi;
  1439. /* updates req->total_num_bfregs */
  1440. err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
  1441. if (err)
  1442. goto out_ctx;
  1443. mutex_init(&bfregi->lock);
  1444. bfregi->lib_uar_4k = lib_uar_4k;
  1445. bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
  1446. GFP_KERNEL);
  1447. if (!bfregi->count) {
  1448. err = -ENOMEM;
  1449. goto out_ctx;
  1450. }
  1451. bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
  1452. sizeof(*bfregi->sys_pages),
  1453. GFP_KERNEL);
  1454. if (!bfregi->sys_pages) {
  1455. err = -ENOMEM;
  1456. goto out_count;
  1457. }
  1458. err = allocate_uars(dev, context);
  1459. if (err)
  1460. goto out_sys_pages;
  1461. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  1462. context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
  1463. #endif
  1464. if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
  1465. err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
  1466. if (err)
  1467. goto out_uars;
  1468. }
  1469. INIT_LIST_HEAD(&context->vma_private_list);
  1470. mutex_init(&context->vma_private_list_mutex);
  1471. INIT_LIST_HEAD(&context->db_page_list);
  1472. mutex_init(&context->db_page_mutex);
  1473. resp.tot_bfregs = req.total_num_bfregs;
  1474. resp.num_ports = dev->num_ports;
  1475. if (field_avail(typeof(resp), cqe_version, udata->outlen))
  1476. resp.response_length += sizeof(resp.cqe_version);
  1477. if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
  1478. resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
  1479. MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
  1480. resp.response_length += sizeof(resp.cmds_supp_uhw);
  1481. }
  1482. if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
  1483. if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
  1484. mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
  1485. resp.eth_min_inline++;
  1486. }
  1487. resp.response_length += sizeof(resp.eth_min_inline);
  1488. }
  1489. if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
  1490. if (mdev->clock_info)
  1491. resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
  1492. resp.response_length += sizeof(resp.clock_info_versions);
  1493. }
  1494. /*
  1495. * We don't want to expose information from the PCI bar that is located
  1496. * after 4096 bytes, so if the arch only supports larger pages, let's
  1497. * pretend we don't support reading the HCA's core clock. This is also
  1498. * forced by mmap function.
  1499. */
  1500. if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
  1501. if (PAGE_SIZE <= 4096) {
  1502. resp.comp_mask |=
  1503. MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
  1504. resp.hca_core_clock_offset =
  1505. offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
  1506. }
  1507. resp.response_length += sizeof(resp.hca_core_clock_offset);
  1508. }
  1509. if (field_avail(typeof(resp), log_uar_size, udata->outlen))
  1510. resp.response_length += sizeof(resp.log_uar_size);
  1511. if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
  1512. resp.response_length += sizeof(resp.num_uars_per_page);
  1513. if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
  1514. resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
  1515. resp.response_length += sizeof(resp.num_dyn_bfregs);
  1516. }
  1517. err = ib_copy_to_udata(udata, &resp, resp.response_length);
  1518. if (err)
  1519. goto out_td;
  1520. bfregi->ver = ver;
  1521. bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
  1522. context->cqe_version = resp.cqe_version;
  1523. context->lib_caps = req.lib_caps;
  1524. print_lib_caps(dev, context->lib_caps);
  1525. return &context->ibucontext;
  1526. out_td:
  1527. if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
  1528. mlx5_ib_dealloc_transport_domain(dev, context->tdn);
  1529. out_uars:
  1530. deallocate_uars(dev, context);
  1531. out_sys_pages:
  1532. kfree(bfregi->sys_pages);
  1533. out_count:
  1534. kfree(bfregi->count);
  1535. out_ctx:
  1536. kfree(context);
  1537. return ERR_PTR(err);
  1538. }
  1539. static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  1540. {
  1541. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  1542. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  1543. struct mlx5_bfreg_info *bfregi;
  1544. bfregi = &context->bfregi;
  1545. if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
  1546. mlx5_ib_dealloc_transport_domain(dev, context->tdn);
  1547. deallocate_uars(dev, context);
  1548. kfree(bfregi->sys_pages);
  1549. kfree(bfregi->count);
  1550. kfree(context);
  1551. return 0;
  1552. }
  1553. static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
  1554. int uar_idx)
  1555. {
  1556. int fw_uars_per_page;
  1557. fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
  1558. return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
  1559. }
  1560. static int get_command(unsigned long offset)
  1561. {
  1562. return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
  1563. }
  1564. static int get_arg(unsigned long offset)
  1565. {
  1566. return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
  1567. }
  1568. static int get_index(unsigned long offset)
  1569. {
  1570. return get_arg(offset);
  1571. }
  1572. /* Index resides in an extra byte to enable larger values than 255 */
  1573. static int get_extended_index(unsigned long offset)
  1574. {
  1575. return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
  1576. }
  1577. static void mlx5_ib_vma_open(struct vm_area_struct *area)
  1578. {
  1579. /* vma_open is called when a new VMA is created on top of our VMA. This
  1580. * is done through either mremap flow or split_vma (usually due to
  1581. * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
  1582. * as this VMA is strongly hardware related. Therefore we set the
  1583. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  1584. * calling us again and trying to do incorrect actions. We assume that
  1585. * the original VMA size is exactly a single page, and therefore all
  1586. * "splitting" operation will not happen to it.
  1587. */
  1588. area->vm_ops = NULL;
  1589. }
  1590. static void mlx5_ib_vma_close(struct vm_area_struct *area)
  1591. {
  1592. struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
  1593. /* It's guaranteed that all VMAs opened on a FD are closed before the
  1594. * file itself is closed, therefore no sync is needed with the regular
  1595. * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
  1596. * However need a sync with accessing the vma as part of
  1597. * mlx5_ib_disassociate_ucontext.
  1598. * The close operation is usually called under mm->mmap_sem except when
  1599. * process is exiting.
  1600. * The exiting case is handled explicitly as part of
  1601. * mlx5_ib_disassociate_ucontext.
  1602. */
  1603. mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
  1604. /* setting the vma context pointer to null in the mlx5_ib driver's
  1605. * private data, to protect a race condition in
  1606. * mlx5_ib_disassociate_ucontext().
  1607. */
  1608. mlx5_ib_vma_priv_data->vma = NULL;
  1609. mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
  1610. list_del(&mlx5_ib_vma_priv_data->list);
  1611. mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
  1612. kfree(mlx5_ib_vma_priv_data);
  1613. }
  1614. static const struct vm_operations_struct mlx5_ib_vm_ops = {
  1615. .open = mlx5_ib_vma_open,
  1616. .close = mlx5_ib_vma_close
  1617. };
  1618. static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
  1619. struct mlx5_ib_ucontext *ctx)
  1620. {
  1621. struct mlx5_ib_vma_private_data *vma_prv;
  1622. struct list_head *vma_head = &ctx->vma_private_list;
  1623. vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
  1624. if (!vma_prv)
  1625. return -ENOMEM;
  1626. vma_prv->vma = vma;
  1627. vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
  1628. vma->vm_private_data = vma_prv;
  1629. vma->vm_ops = &mlx5_ib_vm_ops;
  1630. mutex_lock(&ctx->vma_private_list_mutex);
  1631. list_add(&vma_prv->list, vma_head);
  1632. mutex_unlock(&ctx->vma_private_list_mutex);
  1633. return 0;
  1634. }
  1635. static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  1636. {
  1637. int ret;
  1638. struct vm_area_struct *vma;
  1639. struct mlx5_ib_vma_private_data *vma_private, *n;
  1640. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  1641. struct task_struct *owning_process = NULL;
  1642. struct mm_struct *owning_mm = NULL;
  1643. owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
  1644. if (!owning_process)
  1645. return;
  1646. owning_mm = get_task_mm(owning_process);
  1647. if (!owning_mm) {
  1648. pr_info("no mm, disassociate ucontext is pending task termination\n");
  1649. while (1) {
  1650. put_task_struct(owning_process);
  1651. usleep_range(1000, 2000);
  1652. owning_process = get_pid_task(ibcontext->tgid,
  1653. PIDTYPE_PID);
  1654. if (!owning_process ||
  1655. owning_process->state == TASK_DEAD) {
  1656. pr_info("disassociate ucontext done, task was terminated\n");
  1657. /* in case task was dead need to release the
  1658. * task struct.
  1659. */
  1660. if (owning_process)
  1661. put_task_struct(owning_process);
  1662. return;
  1663. }
  1664. }
  1665. }
  1666. /* need to protect from a race on closing the vma as part of
  1667. * mlx5_ib_vma_close.
  1668. */
  1669. down_write(&owning_mm->mmap_sem);
  1670. mutex_lock(&context->vma_private_list_mutex);
  1671. list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
  1672. list) {
  1673. vma = vma_private->vma;
  1674. ret = zap_vma_ptes(vma, vma->vm_start,
  1675. PAGE_SIZE);
  1676. WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
  1677. /* context going to be destroyed, should
  1678. * not access ops any more.
  1679. */
  1680. vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
  1681. vma->vm_ops = NULL;
  1682. list_del(&vma_private->list);
  1683. kfree(vma_private);
  1684. }
  1685. mutex_unlock(&context->vma_private_list_mutex);
  1686. up_write(&owning_mm->mmap_sem);
  1687. mmput(owning_mm);
  1688. put_task_struct(owning_process);
  1689. }
  1690. static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
  1691. {
  1692. switch (cmd) {
  1693. case MLX5_IB_MMAP_WC_PAGE:
  1694. return "WC";
  1695. case MLX5_IB_MMAP_REGULAR_PAGE:
  1696. return "best effort WC";
  1697. case MLX5_IB_MMAP_NC_PAGE:
  1698. return "NC";
  1699. case MLX5_IB_MMAP_DEVICE_MEM:
  1700. return "Device Memory";
  1701. default:
  1702. return NULL;
  1703. }
  1704. }
  1705. static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
  1706. struct vm_area_struct *vma,
  1707. struct mlx5_ib_ucontext *context)
  1708. {
  1709. phys_addr_t pfn;
  1710. int err;
  1711. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  1712. return -EINVAL;
  1713. if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
  1714. return -EOPNOTSUPP;
  1715. if (vma->vm_flags & VM_WRITE)
  1716. return -EPERM;
  1717. if (!dev->mdev->clock_info_page)
  1718. return -EOPNOTSUPP;
  1719. pfn = page_to_pfn(dev->mdev->clock_info_page);
  1720. err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
  1721. vma->vm_page_prot);
  1722. if (err)
  1723. return err;
  1724. mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
  1725. vma->vm_start,
  1726. (unsigned long long)pfn << PAGE_SHIFT);
  1727. return mlx5_ib_set_vma_data(vma, context);
  1728. }
  1729. static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
  1730. struct vm_area_struct *vma,
  1731. struct mlx5_ib_ucontext *context)
  1732. {
  1733. struct mlx5_bfreg_info *bfregi = &context->bfregi;
  1734. int err;
  1735. unsigned long idx;
  1736. phys_addr_t pfn, pa;
  1737. pgprot_t prot;
  1738. u32 bfreg_dyn_idx = 0;
  1739. u32 uar_index;
  1740. int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
  1741. int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
  1742. bfregi->num_static_sys_pages;
  1743. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  1744. return -EINVAL;
  1745. if (dyn_uar)
  1746. idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
  1747. else
  1748. idx = get_index(vma->vm_pgoff);
  1749. if (idx >= max_valid_idx) {
  1750. mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
  1751. idx, max_valid_idx);
  1752. return -EINVAL;
  1753. }
  1754. switch (cmd) {
  1755. case MLX5_IB_MMAP_WC_PAGE:
  1756. case MLX5_IB_MMAP_ALLOC_WC:
  1757. /* Some architectures don't support WC memory */
  1758. #if defined(CONFIG_X86)
  1759. if (!pat_enabled())
  1760. return -EPERM;
  1761. #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
  1762. return -EPERM;
  1763. #endif
  1764. /* fall through */
  1765. case MLX5_IB_MMAP_REGULAR_PAGE:
  1766. /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
  1767. prot = pgprot_writecombine(vma->vm_page_prot);
  1768. break;
  1769. case MLX5_IB_MMAP_NC_PAGE:
  1770. prot = pgprot_noncached(vma->vm_page_prot);
  1771. break;
  1772. default:
  1773. return -EINVAL;
  1774. }
  1775. if (dyn_uar) {
  1776. int uars_per_page;
  1777. uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
  1778. bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
  1779. if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
  1780. mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
  1781. bfreg_dyn_idx, bfregi->total_num_bfregs);
  1782. return -EINVAL;
  1783. }
  1784. mutex_lock(&bfregi->lock);
  1785. /* Fail if uar already allocated, first bfreg index of each
  1786. * page holds its count.
  1787. */
  1788. if (bfregi->count[bfreg_dyn_idx]) {
  1789. mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
  1790. mutex_unlock(&bfregi->lock);
  1791. return -EINVAL;
  1792. }
  1793. bfregi->count[bfreg_dyn_idx]++;
  1794. mutex_unlock(&bfregi->lock);
  1795. err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
  1796. if (err) {
  1797. mlx5_ib_warn(dev, "UAR alloc failed\n");
  1798. goto free_bfreg;
  1799. }
  1800. } else {
  1801. uar_index = bfregi->sys_pages[idx];
  1802. }
  1803. pfn = uar_index2pfn(dev, uar_index);
  1804. mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
  1805. vma->vm_page_prot = prot;
  1806. err = io_remap_pfn_range(vma, vma->vm_start, pfn,
  1807. PAGE_SIZE, vma->vm_page_prot);
  1808. if (err) {
  1809. mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
  1810. err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
  1811. err = -EAGAIN;
  1812. goto err;
  1813. }
  1814. pa = pfn << PAGE_SHIFT;
  1815. mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
  1816. vma->vm_start, &pa);
  1817. err = mlx5_ib_set_vma_data(vma, context);
  1818. if (err)
  1819. goto err;
  1820. if (dyn_uar)
  1821. bfregi->sys_pages[idx] = uar_index;
  1822. return 0;
  1823. err:
  1824. if (!dyn_uar)
  1825. return err;
  1826. mlx5_cmd_free_uar(dev->mdev, idx);
  1827. free_bfreg:
  1828. mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
  1829. return err;
  1830. }
  1831. static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  1832. {
  1833. struct mlx5_ib_ucontext *mctx = to_mucontext(context);
  1834. struct mlx5_ib_dev *dev = to_mdev(context->device);
  1835. u16 page_idx = get_extended_index(vma->vm_pgoff);
  1836. size_t map_size = vma->vm_end - vma->vm_start;
  1837. u32 npages = map_size >> PAGE_SHIFT;
  1838. phys_addr_t pfn;
  1839. pgprot_t prot;
  1840. if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
  1841. page_idx + npages)
  1842. return -EINVAL;
  1843. pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
  1844. MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
  1845. PAGE_SHIFT) +
  1846. page_idx;
  1847. prot = pgprot_writecombine(vma->vm_page_prot);
  1848. vma->vm_page_prot = prot;
  1849. if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
  1850. vma->vm_page_prot))
  1851. return -EAGAIN;
  1852. return mlx5_ib_set_vma_data(vma, mctx);
  1853. }
  1854. static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
  1855. {
  1856. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  1857. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  1858. unsigned long command;
  1859. phys_addr_t pfn;
  1860. command = get_command(vma->vm_pgoff);
  1861. switch (command) {
  1862. case MLX5_IB_MMAP_WC_PAGE:
  1863. case MLX5_IB_MMAP_NC_PAGE:
  1864. case MLX5_IB_MMAP_REGULAR_PAGE:
  1865. case MLX5_IB_MMAP_ALLOC_WC:
  1866. return uar_mmap(dev, command, vma, context);
  1867. case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
  1868. return -ENOSYS;
  1869. case MLX5_IB_MMAP_CORE_CLOCK:
  1870. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  1871. return -EINVAL;
  1872. if (vma->vm_flags & VM_WRITE)
  1873. return -EPERM;
  1874. /* Don't expose to user-space information it shouldn't have */
  1875. if (PAGE_SIZE > 4096)
  1876. return -EOPNOTSUPP;
  1877. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1878. pfn = (dev->mdev->iseg_base +
  1879. offsetof(struct mlx5_init_seg, internal_timer_h)) >>
  1880. PAGE_SHIFT;
  1881. if (io_remap_pfn_range(vma, vma->vm_start, pfn,
  1882. PAGE_SIZE, vma->vm_page_prot))
  1883. return -EAGAIN;
  1884. mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
  1885. vma->vm_start,
  1886. (unsigned long long)pfn << PAGE_SHIFT);
  1887. break;
  1888. case MLX5_IB_MMAP_CLOCK_INFO:
  1889. return mlx5_ib_mmap_clock_info_page(dev, vma, context);
  1890. case MLX5_IB_MMAP_DEVICE_MEM:
  1891. return dm_mmap(ibcontext, vma);
  1892. default:
  1893. return -EINVAL;
  1894. }
  1895. return 0;
  1896. }
  1897. struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
  1898. struct ib_ucontext *context,
  1899. struct ib_dm_alloc_attr *attr,
  1900. struct uverbs_attr_bundle *attrs)
  1901. {
  1902. u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
  1903. struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
  1904. phys_addr_t memic_addr;
  1905. struct mlx5_ib_dm *dm;
  1906. u64 start_offset;
  1907. u32 page_idx;
  1908. int err;
  1909. dm = kzalloc(sizeof(*dm), GFP_KERNEL);
  1910. if (!dm)
  1911. return ERR_PTR(-ENOMEM);
  1912. mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
  1913. attr->length, act_size, attr->alignment);
  1914. err = mlx5_cmd_alloc_memic(memic, &memic_addr,
  1915. act_size, attr->alignment);
  1916. if (err)
  1917. goto err_free;
  1918. start_offset = memic_addr & ~PAGE_MASK;
  1919. page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
  1920. MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
  1921. PAGE_SHIFT;
  1922. err = uverbs_copy_to(attrs,
  1923. MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
  1924. &start_offset, sizeof(start_offset));
  1925. if (err)
  1926. goto err_dealloc;
  1927. err = uverbs_copy_to(attrs,
  1928. MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
  1929. &page_idx, sizeof(page_idx));
  1930. if (err)
  1931. goto err_dealloc;
  1932. bitmap_set(to_mucontext(context)->dm_pages, page_idx,
  1933. DIV_ROUND_UP(act_size, PAGE_SIZE));
  1934. dm->dev_addr = memic_addr;
  1935. return &dm->ibdm;
  1936. err_dealloc:
  1937. mlx5_cmd_dealloc_memic(memic, memic_addr,
  1938. act_size);
  1939. err_free:
  1940. kfree(dm);
  1941. return ERR_PTR(err);
  1942. }
  1943. int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
  1944. {
  1945. struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
  1946. struct mlx5_ib_dm *dm = to_mdm(ibdm);
  1947. u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
  1948. u32 page_idx;
  1949. int ret;
  1950. ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
  1951. if (ret)
  1952. return ret;
  1953. page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
  1954. MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
  1955. PAGE_SHIFT;
  1956. bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
  1957. page_idx,
  1958. DIV_ROUND_UP(act_size, PAGE_SIZE));
  1959. kfree(dm);
  1960. return 0;
  1961. }
  1962. static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
  1963. struct ib_ucontext *context,
  1964. struct ib_udata *udata)
  1965. {
  1966. struct mlx5_ib_alloc_pd_resp resp;
  1967. struct mlx5_ib_pd *pd;
  1968. int err;
  1969. pd = kmalloc(sizeof(*pd), GFP_KERNEL);
  1970. if (!pd)
  1971. return ERR_PTR(-ENOMEM);
  1972. err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
  1973. if (err) {
  1974. kfree(pd);
  1975. return ERR_PTR(err);
  1976. }
  1977. if (context) {
  1978. resp.pdn = pd->pdn;
  1979. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  1980. mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
  1981. kfree(pd);
  1982. return ERR_PTR(-EFAULT);
  1983. }
  1984. }
  1985. return &pd->ibpd;
  1986. }
  1987. static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
  1988. {
  1989. struct mlx5_ib_dev *mdev = to_mdev(pd->device);
  1990. struct mlx5_ib_pd *mpd = to_mpd(pd);
  1991. mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
  1992. kfree(mpd);
  1993. return 0;
  1994. }
  1995. enum {
  1996. MATCH_CRITERIA_ENABLE_OUTER_BIT,
  1997. MATCH_CRITERIA_ENABLE_MISC_BIT,
  1998. MATCH_CRITERIA_ENABLE_INNER_BIT
  1999. };
  2000. #define HEADER_IS_ZERO(match_criteria, headers) \
  2001. !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
  2002. 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
  2003. static u8 get_match_criteria_enable(u32 *match_criteria)
  2004. {
  2005. u8 match_criteria_enable;
  2006. match_criteria_enable =
  2007. (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
  2008. MATCH_CRITERIA_ENABLE_OUTER_BIT;
  2009. match_criteria_enable |=
  2010. (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
  2011. MATCH_CRITERIA_ENABLE_MISC_BIT;
  2012. match_criteria_enable |=
  2013. (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
  2014. MATCH_CRITERIA_ENABLE_INNER_BIT;
  2015. return match_criteria_enable;
  2016. }
  2017. static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
  2018. {
  2019. MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
  2020. MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
  2021. }
  2022. static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
  2023. bool inner)
  2024. {
  2025. if (inner) {
  2026. MLX5_SET(fte_match_set_misc,
  2027. misc_c, inner_ipv6_flow_label, mask);
  2028. MLX5_SET(fte_match_set_misc,
  2029. misc_v, inner_ipv6_flow_label, val);
  2030. } else {
  2031. MLX5_SET(fte_match_set_misc,
  2032. misc_c, outer_ipv6_flow_label, mask);
  2033. MLX5_SET(fte_match_set_misc,
  2034. misc_v, outer_ipv6_flow_label, val);
  2035. }
  2036. }
  2037. static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
  2038. {
  2039. MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
  2040. MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
  2041. MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
  2042. MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
  2043. }
  2044. #define LAST_ETH_FIELD vlan_tag
  2045. #define LAST_IB_FIELD sl
  2046. #define LAST_IPV4_FIELD tos
  2047. #define LAST_IPV6_FIELD traffic_class
  2048. #define LAST_TCP_UDP_FIELD src_port
  2049. #define LAST_TUNNEL_FIELD tunnel_id
  2050. #define LAST_FLOW_TAG_FIELD tag_id
  2051. #define LAST_DROP_FIELD size
  2052. /* Field is the last supported field */
  2053. #define FIELDS_NOT_SUPPORTED(filter, field)\
  2054. memchr_inv((void *)&filter.field +\
  2055. sizeof(filter.field), 0,\
  2056. sizeof(filter) -\
  2057. offsetof(typeof(filter), field) -\
  2058. sizeof(filter.field))
  2059. static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
  2060. const struct ib_flow_attr *flow_attr,
  2061. struct mlx5_flow_act *action)
  2062. {
  2063. struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
  2064. switch (maction->ib_action.type) {
  2065. case IB_FLOW_ACTION_ESP:
  2066. /* Currently only AES_GCM keymat is supported by the driver */
  2067. action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
  2068. action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
  2069. MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
  2070. MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
  2071. return 0;
  2072. default:
  2073. return -EOPNOTSUPP;
  2074. }
  2075. }
  2076. static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
  2077. u32 *match_v, const union ib_flow_spec *ib_spec,
  2078. const struct ib_flow_attr *flow_attr,
  2079. struct mlx5_flow_act *action)
  2080. {
  2081. void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
  2082. misc_parameters);
  2083. void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
  2084. misc_parameters);
  2085. void *headers_c;
  2086. void *headers_v;
  2087. int match_ipv;
  2088. int ret;
  2089. if (ib_spec->type & IB_FLOW_SPEC_INNER) {
  2090. headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
  2091. inner_headers);
  2092. headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
  2093. inner_headers);
  2094. match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
  2095. ft_field_support.inner_ip_version);
  2096. } else {
  2097. headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
  2098. outer_headers);
  2099. headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
  2100. outer_headers);
  2101. match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
  2102. ft_field_support.outer_ip_version);
  2103. }
  2104. switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
  2105. case IB_FLOW_SPEC_ETH:
  2106. if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
  2107. return -EOPNOTSUPP;
  2108. ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
  2109. dmac_47_16),
  2110. ib_spec->eth.mask.dst_mac);
  2111. ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
  2112. dmac_47_16),
  2113. ib_spec->eth.val.dst_mac);
  2114. ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
  2115. smac_47_16),
  2116. ib_spec->eth.mask.src_mac);
  2117. ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
  2118. smac_47_16),
  2119. ib_spec->eth.val.src_mac);
  2120. if (ib_spec->eth.mask.vlan_tag) {
  2121. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2122. cvlan_tag, 1);
  2123. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2124. cvlan_tag, 1);
  2125. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2126. first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
  2127. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2128. first_vid, ntohs(ib_spec->eth.val.vlan_tag));
  2129. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2130. first_cfi,
  2131. ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
  2132. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2133. first_cfi,
  2134. ntohs(ib_spec->eth.val.vlan_tag) >> 12);
  2135. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2136. first_prio,
  2137. ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
  2138. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2139. first_prio,
  2140. ntohs(ib_spec->eth.val.vlan_tag) >> 13);
  2141. }
  2142. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2143. ethertype, ntohs(ib_spec->eth.mask.ether_type));
  2144. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2145. ethertype, ntohs(ib_spec->eth.val.ether_type));
  2146. break;
  2147. case IB_FLOW_SPEC_IPV4:
  2148. if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
  2149. return -EOPNOTSUPP;
  2150. if (match_ipv) {
  2151. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2152. ip_version, 0xf);
  2153. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2154. ip_version, MLX5_FS_IPV4_VERSION);
  2155. } else {
  2156. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2157. ethertype, 0xffff);
  2158. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2159. ethertype, ETH_P_IP);
  2160. }
  2161. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
  2162. src_ipv4_src_ipv6.ipv4_layout.ipv4),
  2163. &ib_spec->ipv4.mask.src_ip,
  2164. sizeof(ib_spec->ipv4.mask.src_ip));
  2165. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
  2166. src_ipv4_src_ipv6.ipv4_layout.ipv4),
  2167. &ib_spec->ipv4.val.src_ip,
  2168. sizeof(ib_spec->ipv4.val.src_ip));
  2169. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
  2170. dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
  2171. &ib_spec->ipv4.mask.dst_ip,
  2172. sizeof(ib_spec->ipv4.mask.dst_ip));
  2173. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
  2174. dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
  2175. &ib_spec->ipv4.val.dst_ip,
  2176. sizeof(ib_spec->ipv4.val.dst_ip));
  2177. set_tos(headers_c, headers_v,
  2178. ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
  2179. set_proto(headers_c, headers_v,
  2180. ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
  2181. break;
  2182. case IB_FLOW_SPEC_IPV6:
  2183. if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
  2184. return -EOPNOTSUPP;
  2185. if (match_ipv) {
  2186. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2187. ip_version, 0xf);
  2188. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2189. ip_version, MLX5_FS_IPV6_VERSION);
  2190. } else {
  2191. MLX5_SET(fte_match_set_lyr_2_4, headers_c,
  2192. ethertype, 0xffff);
  2193. MLX5_SET(fte_match_set_lyr_2_4, headers_v,
  2194. ethertype, ETH_P_IPV6);
  2195. }
  2196. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
  2197. src_ipv4_src_ipv6.ipv6_layout.ipv6),
  2198. &ib_spec->ipv6.mask.src_ip,
  2199. sizeof(ib_spec->ipv6.mask.src_ip));
  2200. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
  2201. src_ipv4_src_ipv6.ipv6_layout.ipv6),
  2202. &ib_spec->ipv6.val.src_ip,
  2203. sizeof(ib_spec->ipv6.val.src_ip));
  2204. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
  2205. dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
  2206. &ib_spec->ipv6.mask.dst_ip,
  2207. sizeof(ib_spec->ipv6.mask.dst_ip));
  2208. memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
  2209. dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
  2210. &ib_spec->ipv6.val.dst_ip,
  2211. sizeof(ib_spec->ipv6.val.dst_ip));
  2212. set_tos(headers_c, headers_v,
  2213. ib_spec->ipv6.mask.traffic_class,
  2214. ib_spec->ipv6.val.traffic_class);
  2215. set_proto(headers_c, headers_v,
  2216. ib_spec->ipv6.mask.next_hdr,
  2217. ib_spec->ipv6.val.next_hdr);
  2218. set_flow_label(misc_params_c, misc_params_v,
  2219. ntohl(ib_spec->ipv6.mask.flow_label),
  2220. ntohl(ib_spec->ipv6.val.flow_label),
  2221. ib_spec->type & IB_FLOW_SPEC_INNER);
  2222. break;
  2223. case IB_FLOW_SPEC_ESP:
  2224. if (ib_spec->esp.mask.seq)
  2225. return -EOPNOTSUPP;
  2226. MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
  2227. ntohl(ib_spec->esp.mask.spi));
  2228. MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
  2229. ntohl(ib_spec->esp.val.spi));
  2230. break;
  2231. case IB_FLOW_SPEC_TCP:
  2232. if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
  2233. LAST_TCP_UDP_FIELD))
  2234. return -EOPNOTSUPP;
  2235. MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
  2236. 0xff);
  2237. MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
  2238. IPPROTO_TCP);
  2239. MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
  2240. ntohs(ib_spec->tcp_udp.mask.src_port));
  2241. MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
  2242. ntohs(ib_spec->tcp_udp.val.src_port));
  2243. MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
  2244. ntohs(ib_spec->tcp_udp.mask.dst_port));
  2245. MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
  2246. ntohs(ib_spec->tcp_udp.val.dst_port));
  2247. break;
  2248. case IB_FLOW_SPEC_UDP:
  2249. if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
  2250. LAST_TCP_UDP_FIELD))
  2251. return -EOPNOTSUPP;
  2252. MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
  2253. 0xff);
  2254. MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
  2255. IPPROTO_UDP);
  2256. MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
  2257. ntohs(ib_spec->tcp_udp.mask.src_port));
  2258. MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
  2259. ntohs(ib_spec->tcp_udp.val.src_port));
  2260. MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
  2261. ntohs(ib_spec->tcp_udp.mask.dst_port));
  2262. MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
  2263. ntohs(ib_spec->tcp_udp.val.dst_port));
  2264. break;
  2265. case IB_FLOW_SPEC_VXLAN_TUNNEL:
  2266. if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
  2267. LAST_TUNNEL_FIELD))
  2268. return -EOPNOTSUPP;
  2269. MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
  2270. ntohl(ib_spec->tunnel.mask.tunnel_id));
  2271. MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
  2272. ntohl(ib_spec->tunnel.val.tunnel_id));
  2273. break;
  2274. case IB_FLOW_SPEC_ACTION_TAG:
  2275. if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
  2276. LAST_FLOW_TAG_FIELD))
  2277. return -EOPNOTSUPP;
  2278. if (ib_spec->flow_tag.tag_id >= BIT(24))
  2279. return -EINVAL;
  2280. action->flow_tag = ib_spec->flow_tag.tag_id;
  2281. action->has_flow_tag = true;
  2282. break;
  2283. case IB_FLOW_SPEC_ACTION_DROP:
  2284. if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
  2285. LAST_DROP_FIELD))
  2286. return -EOPNOTSUPP;
  2287. action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
  2288. break;
  2289. case IB_FLOW_SPEC_ACTION_HANDLE:
  2290. ret = parse_flow_flow_action(ib_spec, flow_attr, action);
  2291. if (ret)
  2292. return ret;
  2293. break;
  2294. default:
  2295. return -EINVAL;
  2296. }
  2297. return 0;
  2298. }
  2299. /* If a flow could catch both multicast and unicast packets,
  2300. * it won't fall into the multicast flow steering table and this rule
  2301. * could steal other multicast packets.
  2302. */
  2303. static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
  2304. {
  2305. union ib_flow_spec *flow_spec;
  2306. if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
  2307. ib_attr->num_of_specs < 1)
  2308. return false;
  2309. flow_spec = (union ib_flow_spec *)(ib_attr + 1);
  2310. if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
  2311. struct ib_flow_spec_ipv4 *ipv4_spec;
  2312. ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
  2313. if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
  2314. return true;
  2315. return false;
  2316. }
  2317. if (flow_spec->type == IB_FLOW_SPEC_ETH) {
  2318. struct ib_flow_spec_eth *eth_spec;
  2319. eth_spec = (struct ib_flow_spec_eth *)flow_spec;
  2320. return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
  2321. is_multicast_ether_addr(eth_spec->val.dst_mac);
  2322. }
  2323. return false;
  2324. }
  2325. enum valid_spec {
  2326. VALID_SPEC_INVALID,
  2327. VALID_SPEC_VALID,
  2328. VALID_SPEC_NA,
  2329. };
  2330. static enum valid_spec
  2331. is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
  2332. const struct mlx5_flow_spec *spec,
  2333. const struct mlx5_flow_act *flow_act,
  2334. bool egress)
  2335. {
  2336. const u32 *match_c = spec->match_criteria;
  2337. bool is_crypto =
  2338. (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
  2339. MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
  2340. bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
  2341. bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
  2342. /*
  2343. * Currently only crypto is supported in egress, when regular egress
  2344. * rules would be supported, always return VALID_SPEC_NA.
  2345. */
  2346. if (!is_crypto)
  2347. return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
  2348. return is_crypto && is_ipsec &&
  2349. (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
  2350. VALID_SPEC_VALID : VALID_SPEC_INVALID;
  2351. }
  2352. static bool is_valid_spec(struct mlx5_core_dev *mdev,
  2353. const struct mlx5_flow_spec *spec,
  2354. const struct mlx5_flow_act *flow_act,
  2355. bool egress)
  2356. {
  2357. /* We curretly only support ipsec egress flow */
  2358. return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
  2359. }
  2360. static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
  2361. const struct ib_flow_attr *flow_attr,
  2362. bool check_inner)
  2363. {
  2364. union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
  2365. int match_ipv = check_inner ?
  2366. MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
  2367. ft_field_support.inner_ip_version) :
  2368. MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
  2369. ft_field_support.outer_ip_version);
  2370. int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
  2371. bool ipv4_spec_valid, ipv6_spec_valid;
  2372. unsigned int ip_spec_type = 0;
  2373. bool has_ethertype = false;
  2374. unsigned int spec_index;
  2375. bool mask_valid = true;
  2376. u16 eth_type = 0;
  2377. bool type_valid;
  2378. /* Validate that ethertype is correct */
  2379. for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
  2380. if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
  2381. ib_spec->eth.mask.ether_type) {
  2382. mask_valid = (ib_spec->eth.mask.ether_type ==
  2383. htons(0xffff));
  2384. has_ethertype = true;
  2385. eth_type = ntohs(ib_spec->eth.val.ether_type);
  2386. } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
  2387. (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
  2388. ip_spec_type = ib_spec->type;
  2389. }
  2390. ib_spec = (void *)ib_spec + ib_spec->size;
  2391. }
  2392. type_valid = (!has_ethertype) || (!ip_spec_type);
  2393. if (!type_valid && mask_valid) {
  2394. ipv4_spec_valid = (eth_type == ETH_P_IP) &&
  2395. (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
  2396. ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
  2397. (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
  2398. type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
  2399. (((eth_type == ETH_P_MPLS_UC) ||
  2400. (eth_type == ETH_P_MPLS_MC)) && match_ipv);
  2401. }
  2402. return type_valid;
  2403. }
  2404. static bool is_valid_attr(struct mlx5_core_dev *mdev,
  2405. const struct ib_flow_attr *flow_attr)
  2406. {
  2407. return is_valid_ethertype(mdev, flow_attr, false) &&
  2408. is_valid_ethertype(mdev, flow_attr, true);
  2409. }
  2410. static void put_flow_table(struct mlx5_ib_dev *dev,
  2411. struct mlx5_ib_flow_prio *prio, bool ft_added)
  2412. {
  2413. prio->refcount -= !!ft_added;
  2414. if (!prio->refcount) {
  2415. mlx5_destroy_flow_table(prio->flow_table);
  2416. prio->flow_table = NULL;
  2417. }
  2418. }
  2419. static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
  2420. {
  2421. struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
  2422. struct mlx5_ib_flow_handler *handler = container_of(flow_id,
  2423. struct mlx5_ib_flow_handler,
  2424. ibflow);
  2425. struct mlx5_ib_flow_handler *iter, *tmp;
  2426. mutex_lock(&dev->flow_db->lock);
  2427. list_for_each_entry_safe(iter, tmp, &handler->list, list) {
  2428. mlx5_del_flow_rules(iter->rule);
  2429. put_flow_table(dev, iter->prio, true);
  2430. list_del(&iter->list);
  2431. kfree(iter);
  2432. }
  2433. mlx5_del_flow_rules(handler->rule);
  2434. put_flow_table(dev, handler->prio, true);
  2435. mutex_unlock(&dev->flow_db->lock);
  2436. kfree(handler);
  2437. return 0;
  2438. }
  2439. static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
  2440. {
  2441. priority *= 2;
  2442. if (!dont_trap)
  2443. priority++;
  2444. return priority;
  2445. }
  2446. enum flow_table_type {
  2447. MLX5_IB_FT_RX,
  2448. MLX5_IB_FT_TX
  2449. };
  2450. #define MLX5_FS_MAX_TYPES 6
  2451. #define MLX5_FS_MAX_ENTRIES BIT(16)
  2452. static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
  2453. struct ib_flow_attr *flow_attr,
  2454. enum flow_table_type ft_type)
  2455. {
  2456. bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
  2457. struct mlx5_flow_namespace *ns = NULL;
  2458. struct mlx5_ib_flow_prio *prio;
  2459. struct mlx5_flow_table *ft;
  2460. int max_table_size;
  2461. int num_entries;
  2462. int num_groups;
  2463. int priority;
  2464. int err = 0;
  2465. max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
  2466. log_max_ft_size));
  2467. if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  2468. if (ft_type == MLX5_IB_FT_TX)
  2469. priority = 0;
  2470. else if (flow_is_multicast_only(flow_attr) &&
  2471. !dont_trap)
  2472. priority = MLX5_IB_FLOW_MCAST_PRIO;
  2473. else
  2474. priority = ib_prio_to_core_prio(flow_attr->priority,
  2475. dont_trap);
  2476. ns = mlx5_get_flow_namespace(dev->mdev,
  2477. ft_type == MLX5_IB_FT_TX ?
  2478. MLX5_FLOW_NAMESPACE_EGRESS :
  2479. MLX5_FLOW_NAMESPACE_BYPASS);
  2480. num_entries = MLX5_FS_MAX_ENTRIES;
  2481. num_groups = MLX5_FS_MAX_TYPES;
  2482. prio = &dev->flow_db->prios[priority];
  2483. } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
  2484. flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
  2485. ns = mlx5_get_flow_namespace(dev->mdev,
  2486. MLX5_FLOW_NAMESPACE_LEFTOVERS);
  2487. build_leftovers_ft_param(&priority,
  2488. &num_entries,
  2489. &num_groups);
  2490. prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
  2491. } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
  2492. if (!MLX5_CAP_FLOWTABLE(dev->mdev,
  2493. allow_sniffer_and_nic_rx_shared_tir))
  2494. return ERR_PTR(-ENOTSUPP);
  2495. ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
  2496. MLX5_FLOW_NAMESPACE_SNIFFER_RX :
  2497. MLX5_FLOW_NAMESPACE_SNIFFER_TX);
  2498. prio = &dev->flow_db->sniffer[ft_type];
  2499. priority = 0;
  2500. num_entries = 1;
  2501. num_groups = 1;
  2502. }
  2503. if (!ns)
  2504. return ERR_PTR(-ENOTSUPP);
  2505. if (num_entries > max_table_size)
  2506. return ERR_PTR(-ENOMEM);
  2507. ft = prio->flow_table;
  2508. if (!ft) {
  2509. ft = mlx5_create_auto_grouped_flow_table(ns, priority,
  2510. num_entries,
  2511. num_groups,
  2512. 0, 0);
  2513. if (!IS_ERR(ft)) {
  2514. prio->refcount = 0;
  2515. prio->flow_table = ft;
  2516. } else {
  2517. err = PTR_ERR(ft);
  2518. }
  2519. }
  2520. return err ? ERR_PTR(err) : prio;
  2521. }
  2522. static void set_underlay_qp(struct mlx5_ib_dev *dev,
  2523. struct mlx5_flow_spec *spec,
  2524. u32 underlay_qpn)
  2525. {
  2526. void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
  2527. spec->match_criteria,
  2528. misc_parameters);
  2529. void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
  2530. misc_parameters);
  2531. if (underlay_qpn &&
  2532. MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
  2533. ft_field_support.bth_dst_qp)) {
  2534. MLX5_SET(fte_match_set_misc,
  2535. misc_params_v, bth_dst_qp, underlay_qpn);
  2536. MLX5_SET(fte_match_set_misc,
  2537. misc_params_c, bth_dst_qp, 0xffffff);
  2538. }
  2539. }
  2540. static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
  2541. struct mlx5_ib_flow_prio *ft_prio,
  2542. const struct ib_flow_attr *flow_attr,
  2543. struct mlx5_flow_destination *dst,
  2544. u32 underlay_qpn)
  2545. {
  2546. struct mlx5_flow_table *ft = ft_prio->flow_table;
  2547. struct mlx5_ib_flow_handler *handler;
  2548. struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
  2549. struct mlx5_flow_spec *spec;
  2550. struct mlx5_flow_destination *rule_dst = dst;
  2551. const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
  2552. unsigned int spec_index;
  2553. int err = 0;
  2554. int dest_num = 1;
  2555. bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
  2556. if (!is_valid_attr(dev->mdev, flow_attr))
  2557. return ERR_PTR(-EINVAL);
  2558. spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
  2559. handler = kzalloc(sizeof(*handler), GFP_KERNEL);
  2560. if (!handler || !spec) {
  2561. err = -ENOMEM;
  2562. goto free;
  2563. }
  2564. INIT_LIST_HEAD(&handler->list);
  2565. for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
  2566. err = parse_flow_attr(dev->mdev, spec->match_criteria,
  2567. spec->match_value,
  2568. ib_flow, flow_attr, &flow_act);
  2569. if (err < 0)
  2570. goto free;
  2571. ib_flow += ((union ib_flow_spec *)ib_flow)->size;
  2572. }
  2573. if (!flow_is_multicast_only(flow_attr))
  2574. set_underlay_qp(dev, spec, underlay_qpn);
  2575. if (dev->rep) {
  2576. void *misc;
  2577. misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
  2578. misc_parameters);
  2579. MLX5_SET(fte_match_set_misc, misc, source_port,
  2580. dev->rep->vport);
  2581. misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
  2582. misc_parameters);
  2583. MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
  2584. }
  2585. spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
  2586. if (is_egress &&
  2587. !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
  2588. err = -EINVAL;
  2589. goto free;
  2590. }
  2591. if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
  2592. rule_dst = NULL;
  2593. dest_num = 0;
  2594. } else {
  2595. if (is_egress)
  2596. flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
  2597. else
  2598. flow_act.action |=
  2599. dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
  2600. MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
  2601. }
  2602. if (flow_act.has_flow_tag &&
  2603. (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
  2604. flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
  2605. mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
  2606. flow_act.flow_tag, flow_attr->type);
  2607. err = -EINVAL;
  2608. goto free;
  2609. }
  2610. handler->rule = mlx5_add_flow_rules(ft, spec,
  2611. &flow_act,
  2612. rule_dst, dest_num);
  2613. if (IS_ERR(handler->rule)) {
  2614. err = PTR_ERR(handler->rule);
  2615. goto free;
  2616. }
  2617. ft_prio->refcount++;
  2618. handler->prio = ft_prio;
  2619. ft_prio->flow_table = ft;
  2620. free:
  2621. if (err)
  2622. kfree(handler);
  2623. kvfree(spec);
  2624. return err ? ERR_PTR(err) : handler;
  2625. }
  2626. static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
  2627. struct mlx5_ib_flow_prio *ft_prio,
  2628. const struct ib_flow_attr *flow_attr,
  2629. struct mlx5_flow_destination *dst)
  2630. {
  2631. return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
  2632. }
  2633. static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
  2634. struct mlx5_ib_flow_prio *ft_prio,
  2635. struct ib_flow_attr *flow_attr,
  2636. struct mlx5_flow_destination *dst)
  2637. {
  2638. struct mlx5_ib_flow_handler *handler_dst = NULL;
  2639. struct mlx5_ib_flow_handler *handler = NULL;
  2640. handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
  2641. if (!IS_ERR(handler)) {
  2642. handler_dst = create_flow_rule(dev, ft_prio,
  2643. flow_attr, dst);
  2644. if (IS_ERR(handler_dst)) {
  2645. mlx5_del_flow_rules(handler->rule);
  2646. ft_prio->refcount--;
  2647. kfree(handler);
  2648. handler = handler_dst;
  2649. } else {
  2650. list_add(&handler_dst->list, &handler->list);
  2651. }
  2652. }
  2653. return handler;
  2654. }
  2655. enum {
  2656. LEFTOVERS_MC,
  2657. LEFTOVERS_UC,
  2658. };
  2659. static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
  2660. struct mlx5_ib_flow_prio *ft_prio,
  2661. struct ib_flow_attr *flow_attr,
  2662. struct mlx5_flow_destination *dst)
  2663. {
  2664. struct mlx5_ib_flow_handler *handler_ucast = NULL;
  2665. struct mlx5_ib_flow_handler *handler = NULL;
  2666. static struct {
  2667. struct ib_flow_attr flow_attr;
  2668. struct ib_flow_spec_eth eth_flow;
  2669. } leftovers_specs[] = {
  2670. [LEFTOVERS_MC] = {
  2671. .flow_attr = {
  2672. .num_of_specs = 1,
  2673. .size = sizeof(leftovers_specs[0])
  2674. },
  2675. .eth_flow = {
  2676. .type = IB_FLOW_SPEC_ETH,
  2677. .size = sizeof(struct ib_flow_spec_eth),
  2678. .mask = {.dst_mac = {0x1} },
  2679. .val = {.dst_mac = {0x1} }
  2680. }
  2681. },
  2682. [LEFTOVERS_UC] = {
  2683. .flow_attr = {
  2684. .num_of_specs = 1,
  2685. .size = sizeof(leftovers_specs[0])
  2686. },
  2687. .eth_flow = {
  2688. .type = IB_FLOW_SPEC_ETH,
  2689. .size = sizeof(struct ib_flow_spec_eth),
  2690. .mask = {.dst_mac = {0x1} },
  2691. .val = {.dst_mac = {} }
  2692. }
  2693. }
  2694. };
  2695. handler = create_flow_rule(dev, ft_prio,
  2696. &leftovers_specs[LEFTOVERS_MC].flow_attr,
  2697. dst);
  2698. if (!IS_ERR(handler) &&
  2699. flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
  2700. handler_ucast = create_flow_rule(dev, ft_prio,
  2701. &leftovers_specs[LEFTOVERS_UC].flow_attr,
  2702. dst);
  2703. if (IS_ERR(handler_ucast)) {
  2704. mlx5_del_flow_rules(handler->rule);
  2705. ft_prio->refcount--;
  2706. kfree(handler);
  2707. handler = handler_ucast;
  2708. } else {
  2709. list_add(&handler_ucast->list, &handler->list);
  2710. }
  2711. }
  2712. return handler;
  2713. }
  2714. static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
  2715. struct mlx5_ib_flow_prio *ft_rx,
  2716. struct mlx5_ib_flow_prio *ft_tx,
  2717. struct mlx5_flow_destination *dst)
  2718. {
  2719. struct mlx5_ib_flow_handler *handler_rx;
  2720. struct mlx5_ib_flow_handler *handler_tx;
  2721. int err;
  2722. static const struct ib_flow_attr flow_attr = {
  2723. .num_of_specs = 0,
  2724. .size = sizeof(flow_attr)
  2725. };
  2726. handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
  2727. if (IS_ERR(handler_rx)) {
  2728. err = PTR_ERR(handler_rx);
  2729. goto err;
  2730. }
  2731. handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
  2732. if (IS_ERR(handler_tx)) {
  2733. err = PTR_ERR(handler_tx);
  2734. goto err_tx;
  2735. }
  2736. list_add(&handler_tx->list, &handler_rx->list);
  2737. return handler_rx;
  2738. err_tx:
  2739. mlx5_del_flow_rules(handler_rx->rule);
  2740. ft_rx->refcount--;
  2741. kfree(handler_rx);
  2742. err:
  2743. return ERR_PTR(err);
  2744. }
  2745. static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
  2746. struct ib_flow_attr *flow_attr,
  2747. int domain)
  2748. {
  2749. struct mlx5_ib_dev *dev = to_mdev(qp->device);
  2750. struct mlx5_ib_qp *mqp = to_mqp(qp);
  2751. struct mlx5_ib_flow_handler *handler = NULL;
  2752. struct mlx5_flow_destination *dst = NULL;
  2753. struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
  2754. struct mlx5_ib_flow_prio *ft_prio;
  2755. bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
  2756. int err;
  2757. int underlay_qpn;
  2758. if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
  2759. return ERR_PTR(-ENOMEM);
  2760. if (domain != IB_FLOW_DOMAIN_USER ||
  2761. flow_attr->port > dev->num_ports ||
  2762. (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
  2763. IB_FLOW_ATTR_FLAGS_EGRESS)))
  2764. return ERR_PTR(-EINVAL);
  2765. if (is_egress &&
  2766. (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
  2767. flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
  2768. return ERR_PTR(-EINVAL);
  2769. dst = kzalloc(sizeof(*dst), GFP_KERNEL);
  2770. if (!dst)
  2771. return ERR_PTR(-ENOMEM);
  2772. mutex_lock(&dev->flow_db->lock);
  2773. ft_prio = get_flow_table(dev, flow_attr,
  2774. is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
  2775. if (IS_ERR(ft_prio)) {
  2776. err = PTR_ERR(ft_prio);
  2777. goto unlock;
  2778. }
  2779. if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
  2780. ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
  2781. if (IS_ERR(ft_prio_tx)) {
  2782. err = PTR_ERR(ft_prio_tx);
  2783. ft_prio_tx = NULL;
  2784. goto destroy_ft;
  2785. }
  2786. }
  2787. if (is_egress) {
  2788. dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
  2789. } else {
  2790. dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
  2791. if (mqp->flags & MLX5_IB_QP_RSS)
  2792. dst->tir_num = mqp->rss_qp.tirn;
  2793. else
  2794. dst->tir_num = mqp->raw_packet_qp.rq.tirn;
  2795. }
  2796. if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  2797. if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
  2798. handler = create_dont_trap_rule(dev, ft_prio,
  2799. flow_attr, dst);
  2800. } else {
  2801. underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
  2802. mqp->underlay_qpn : 0;
  2803. handler = _create_flow_rule(dev, ft_prio, flow_attr,
  2804. dst, underlay_qpn);
  2805. }
  2806. } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
  2807. flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
  2808. handler = create_leftovers_rule(dev, ft_prio, flow_attr,
  2809. dst);
  2810. } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
  2811. handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
  2812. } else {
  2813. err = -EINVAL;
  2814. goto destroy_ft;
  2815. }
  2816. if (IS_ERR(handler)) {
  2817. err = PTR_ERR(handler);
  2818. handler = NULL;
  2819. goto destroy_ft;
  2820. }
  2821. mutex_unlock(&dev->flow_db->lock);
  2822. kfree(dst);
  2823. return &handler->ibflow;
  2824. destroy_ft:
  2825. put_flow_table(dev, ft_prio, false);
  2826. if (ft_prio_tx)
  2827. put_flow_table(dev, ft_prio_tx, false);
  2828. unlock:
  2829. mutex_unlock(&dev->flow_db->lock);
  2830. kfree(dst);
  2831. kfree(handler);
  2832. return ERR_PTR(err);
  2833. }
  2834. static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
  2835. {
  2836. u32 flags = 0;
  2837. if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
  2838. flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
  2839. return flags;
  2840. }
  2841. #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
  2842. static struct ib_flow_action *
  2843. mlx5_ib_create_flow_action_esp(struct ib_device *device,
  2844. const struct ib_flow_action_attrs_esp *attr,
  2845. struct uverbs_attr_bundle *attrs)
  2846. {
  2847. struct mlx5_ib_dev *mdev = to_mdev(device);
  2848. struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
  2849. struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
  2850. struct mlx5_ib_flow_action *action;
  2851. u64 action_flags;
  2852. u64 flags;
  2853. int err = 0;
  2854. if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
  2855. MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
  2856. return ERR_PTR(-EFAULT);
  2857. if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
  2858. return ERR_PTR(-EOPNOTSUPP);
  2859. flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
  2860. /* We current only support a subset of the standard features. Only a
  2861. * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
  2862. * (with overlap). Full offload mode isn't supported.
  2863. */
  2864. if (!attr->keymat || attr->replay || attr->encap ||
  2865. attr->spi || attr->seq || attr->tfc_pad ||
  2866. attr->hard_limit_pkts ||
  2867. (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
  2868. IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
  2869. return ERR_PTR(-EOPNOTSUPP);
  2870. if (attr->keymat->protocol !=
  2871. IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
  2872. return ERR_PTR(-EOPNOTSUPP);
  2873. aes_gcm = &attr->keymat->keymat.aes_gcm;
  2874. if (aes_gcm->icv_len != 16 ||
  2875. aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
  2876. return ERR_PTR(-EOPNOTSUPP);
  2877. action = kmalloc(sizeof(*action), GFP_KERNEL);
  2878. if (!action)
  2879. return ERR_PTR(-ENOMEM);
  2880. action->esp_aes_gcm.ib_flags = attr->flags;
  2881. memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
  2882. sizeof(accel_attrs.keymat.aes_gcm.aes_key));
  2883. accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
  2884. memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
  2885. sizeof(accel_attrs.keymat.aes_gcm.salt));
  2886. memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
  2887. sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
  2888. accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
  2889. accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
  2890. accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
  2891. accel_attrs.esn = attr->esn;
  2892. if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
  2893. accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
  2894. if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
  2895. accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
  2896. if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
  2897. accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
  2898. action->esp_aes_gcm.ctx =
  2899. mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
  2900. if (IS_ERR(action->esp_aes_gcm.ctx)) {
  2901. err = PTR_ERR(action->esp_aes_gcm.ctx);
  2902. goto err_parse;
  2903. }
  2904. action->esp_aes_gcm.ib_flags = attr->flags;
  2905. return &action->ib_action;
  2906. err_parse:
  2907. kfree(action);
  2908. return ERR_PTR(err);
  2909. }
  2910. static int
  2911. mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
  2912. const struct ib_flow_action_attrs_esp *attr,
  2913. struct uverbs_attr_bundle *attrs)
  2914. {
  2915. struct mlx5_ib_flow_action *maction = to_mflow_act(action);
  2916. struct mlx5_accel_esp_xfrm_attrs accel_attrs;
  2917. int err = 0;
  2918. if (attr->keymat || attr->replay || attr->encap ||
  2919. attr->spi || attr->seq || attr->tfc_pad ||
  2920. attr->hard_limit_pkts ||
  2921. (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
  2922. IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
  2923. IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
  2924. return -EOPNOTSUPP;
  2925. /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
  2926. * be modified.
  2927. */
  2928. if (!(maction->esp_aes_gcm.ib_flags &
  2929. IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
  2930. attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
  2931. IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
  2932. return -EINVAL;
  2933. memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
  2934. sizeof(accel_attrs));
  2935. accel_attrs.esn = attr->esn;
  2936. if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
  2937. accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
  2938. else
  2939. accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
  2940. err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
  2941. &accel_attrs);
  2942. if (err)
  2943. return err;
  2944. maction->esp_aes_gcm.ib_flags &=
  2945. ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
  2946. maction->esp_aes_gcm.ib_flags |=
  2947. attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
  2948. return 0;
  2949. }
  2950. static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
  2951. {
  2952. struct mlx5_ib_flow_action *maction = to_mflow_act(action);
  2953. switch (action->type) {
  2954. case IB_FLOW_ACTION_ESP:
  2955. /*
  2956. * We only support aes_gcm by now, so we implicitly know this is
  2957. * the underline crypto.
  2958. */
  2959. mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
  2960. break;
  2961. default:
  2962. WARN_ON(true);
  2963. break;
  2964. }
  2965. kfree(maction);
  2966. return 0;
  2967. }
  2968. static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  2969. {
  2970. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  2971. struct mlx5_ib_qp *mqp = to_mqp(ibqp);
  2972. int err;
  2973. if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
  2974. mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
  2975. return -EOPNOTSUPP;
  2976. }
  2977. err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
  2978. if (err)
  2979. mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
  2980. ibqp->qp_num, gid->raw);
  2981. return err;
  2982. }
  2983. static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  2984. {
  2985. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  2986. int err;
  2987. err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
  2988. if (err)
  2989. mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
  2990. ibqp->qp_num, gid->raw);
  2991. return err;
  2992. }
  2993. static int init_node_data(struct mlx5_ib_dev *dev)
  2994. {
  2995. int err;
  2996. err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
  2997. if (err)
  2998. return err;
  2999. dev->mdev->rev_id = dev->mdev->pdev->revision;
  3000. return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
  3001. }
  3002. static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
  3003. char *buf)
  3004. {
  3005. struct mlx5_ib_dev *dev =
  3006. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  3007. return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
  3008. }
  3009. static ssize_t show_reg_pages(struct device *device,
  3010. struct device_attribute *attr, char *buf)
  3011. {
  3012. struct mlx5_ib_dev *dev =
  3013. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  3014. return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
  3015. }
  3016. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  3017. char *buf)
  3018. {
  3019. struct mlx5_ib_dev *dev =
  3020. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  3021. return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
  3022. }
  3023. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  3024. char *buf)
  3025. {
  3026. struct mlx5_ib_dev *dev =
  3027. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  3028. return sprintf(buf, "%x\n", dev->mdev->rev_id);
  3029. }
  3030. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  3031. char *buf)
  3032. {
  3033. struct mlx5_ib_dev *dev =
  3034. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  3035. return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
  3036. dev->mdev->board_id);
  3037. }
  3038. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  3039. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  3040. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  3041. static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
  3042. static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
  3043. static struct device_attribute *mlx5_class_attributes[] = {
  3044. &dev_attr_hw_rev,
  3045. &dev_attr_hca_type,
  3046. &dev_attr_board_id,
  3047. &dev_attr_fw_pages,
  3048. &dev_attr_reg_pages,
  3049. };
  3050. static void pkey_change_handler(struct work_struct *work)
  3051. {
  3052. struct mlx5_ib_port_resources *ports =
  3053. container_of(work, struct mlx5_ib_port_resources,
  3054. pkey_change_work);
  3055. mutex_lock(&ports->devr->mutex);
  3056. mlx5_ib_gsi_pkey_change(ports->gsi);
  3057. mutex_unlock(&ports->devr->mutex);
  3058. }
  3059. static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
  3060. {
  3061. struct mlx5_ib_qp *mqp;
  3062. struct mlx5_ib_cq *send_mcq, *recv_mcq;
  3063. struct mlx5_core_cq *mcq;
  3064. struct list_head cq_armed_list;
  3065. unsigned long flags_qp;
  3066. unsigned long flags_cq;
  3067. unsigned long flags;
  3068. INIT_LIST_HEAD(&cq_armed_list);
  3069. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  3070. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  3071. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  3072. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  3073. if (mqp->sq.tail != mqp->sq.head) {
  3074. send_mcq = to_mcq(mqp->ibqp.send_cq);
  3075. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  3076. if (send_mcq->mcq.comp &&
  3077. mqp->ibqp.send_cq->comp_handler) {
  3078. if (!send_mcq->mcq.reset_notify_added) {
  3079. send_mcq->mcq.reset_notify_added = 1;
  3080. list_add_tail(&send_mcq->mcq.reset_notify,
  3081. &cq_armed_list);
  3082. }
  3083. }
  3084. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  3085. }
  3086. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  3087. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  3088. /* no handling is needed for SRQ */
  3089. if (!mqp->ibqp.srq) {
  3090. if (mqp->rq.tail != mqp->rq.head) {
  3091. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  3092. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  3093. if (recv_mcq->mcq.comp &&
  3094. mqp->ibqp.recv_cq->comp_handler) {
  3095. if (!recv_mcq->mcq.reset_notify_added) {
  3096. recv_mcq->mcq.reset_notify_added = 1;
  3097. list_add_tail(&recv_mcq->mcq.reset_notify,
  3098. &cq_armed_list);
  3099. }
  3100. }
  3101. spin_unlock_irqrestore(&recv_mcq->lock,
  3102. flags_cq);
  3103. }
  3104. }
  3105. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  3106. }
  3107. /*At that point all inflight post send were put to be executed as of we
  3108. * lock/unlock above locks Now need to arm all involved CQs.
  3109. */
  3110. list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
  3111. mcq->comp(mcq);
  3112. }
  3113. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  3114. }
  3115. static void delay_drop_handler(struct work_struct *work)
  3116. {
  3117. int err;
  3118. struct mlx5_ib_delay_drop *delay_drop =
  3119. container_of(work, struct mlx5_ib_delay_drop,
  3120. delay_drop_work);
  3121. atomic_inc(&delay_drop->events_cnt);
  3122. mutex_lock(&delay_drop->lock);
  3123. err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
  3124. delay_drop->timeout);
  3125. if (err) {
  3126. mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
  3127. delay_drop->timeout);
  3128. delay_drop->activate = false;
  3129. }
  3130. mutex_unlock(&delay_drop->lock);
  3131. }
  3132. static void mlx5_ib_handle_event(struct work_struct *_work)
  3133. {
  3134. struct mlx5_ib_event_work *work =
  3135. container_of(_work, struct mlx5_ib_event_work, work);
  3136. struct mlx5_ib_dev *ibdev;
  3137. struct ib_event ibev;
  3138. bool fatal = false;
  3139. u8 port = (u8)work->param;
  3140. if (mlx5_core_is_mp_slave(work->dev)) {
  3141. ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
  3142. if (!ibdev)
  3143. goto out;
  3144. } else {
  3145. ibdev = work->context;
  3146. }
  3147. switch (work->event) {
  3148. case MLX5_DEV_EVENT_SYS_ERROR:
  3149. ibev.event = IB_EVENT_DEVICE_FATAL;
  3150. mlx5_ib_handle_internal_error(ibdev);
  3151. fatal = true;
  3152. break;
  3153. case MLX5_DEV_EVENT_PORT_UP:
  3154. case MLX5_DEV_EVENT_PORT_DOWN:
  3155. case MLX5_DEV_EVENT_PORT_INITIALIZED:
  3156. /* In RoCE, port up/down events are handled in
  3157. * mlx5_netdev_event().
  3158. */
  3159. if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
  3160. IB_LINK_LAYER_ETHERNET)
  3161. goto out;
  3162. ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
  3163. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  3164. break;
  3165. case MLX5_DEV_EVENT_LID_CHANGE:
  3166. ibev.event = IB_EVENT_LID_CHANGE;
  3167. break;
  3168. case MLX5_DEV_EVENT_PKEY_CHANGE:
  3169. ibev.event = IB_EVENT_PKEY_CHANGE;
  3170. schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
  3171. break;
  3172. case MLX5_DEV_EVENT_GUID_CHANGE:
  3173. ibev.event = IB_EVENT_GID_CHANGE;
  3174. break;
  3175. case MLX5_DEV_EVENT_CLIENT_REREG:
  3176. ibev.event = IB_EVENT_CLIENT_REREGISTER;
  3177. break;
  3178. case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
  3179. schedule_work(&ibdev->delay_drop.delay_drop_work);
  3180. goto out;
  3181. default:
  3182. goto out;
  3183. }
  3184. ibev.device = &ibdev->ib_dev;
  3185. ibev.element.port_num = port;
  3186. if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
  3187. mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
  3188. goto out;
  3189. }
  3190. if (ibdev->ib_active)
  3191. ib_dispatch_event(&ibev);
  3192. if (fatal)
  3193. ibdev->ib_active = false;
  3194. out:
  3195. kfree(work);
  3196. }
  3197. static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
  3198. enum mlx5_dev_event event, unsigned long param)
  3199. {
  3200. struct mlx5_ib_event_work *work;
  3201. work = kmalloc(sizeof(*work), GFP_ATOMIC);
  3202. if (!work)
  3203. return;
  3204. INIT_WORK(&work->work, mlx5_ib_handle_event);
  3205. work->dev = dev;
  3206. work->param = param;
  3207. work->context = context;
  3208. work->event = event;
  3209. queue_work(mlx5_ib_event_wq, &work->work);
  3210. }
  3211. static int set_has_smi_cap(struct mlx5_ib_dev *dev)
  3212. {
  3213. struct mlx5_hca_vport_context vport_ctx;
  3214. int err;
  3215. int port;
  3216. for (port = 1; port <= dev->num_ports; port++) {
  3217. dev->mdev->port_caps[port - 1].has_smi = false;
  3218. if (MLX5_CAP_GEN(dev->mdev, port_type) ==
  3219. MLX5_CAP_PORT_TYPE_IB) {
  3220. if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
  3221. err = mlx5_query_hca_vport_context(dev->mdev, 0,
  3222. port, 0,
  3223. &vport_ctx);
  3224. if (err) {
  3225. mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
  3226. port, err);
  3227. return err;
  3228. }
  3229. dev->mdev->port_caps[port - 1].has_smi =
  3230. vport_ctx.has_smi;
  3231. } else {
  3232. dev->mdev->port_caps[port - 1].has_smi = true;
  3233. }
  3234. }
  3235. }
  3236. return 0;
  3237. }
  3238. static void get_ext_port_caps(struct mlx5_ib_dev *dev)
  3239. {
  3240. int port;
  3241. for (port = 1; port <= dev->num_ports; port++)
  3242. mlx5_query_ext_port_caps(dev, port);
  3243. }
  3244. static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
  3245. {
  3246. struct ib_device_attr *dprops = NULL;
  3247. struct ib_port_attr *pprops = NULL;
  3248. int err = -ENOMEM;
  3249. struct ib_udata uhw = {.inlen = 0, .outlen = 0};
  3250. pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
  3251. if (!pprops)
  3252. goto out;
  3253. dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
  3254. if (!dprops)
  3255. goto out;
  3256. err = set_has_smi_cap(dev);
  3257. if (err)
  3258. goto out;
  3259. err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
  3260. if (err) {
  3261. mlx5_ib_warn(dev, "query_device failed %d\n", err);
  3262. goto out;
  3263. }
  3264. memset(pprops, 0, sizeof(*pprops));
  3265. err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
  3266. if (err) {
  3267. mlx5_ib_warn(dev, "query_port %d failed %d\n",
  3268. port, err);
  3269. goto out;
  3270. }
  3271. dev->mdev->port_caps[port - 1].pkey_table_len =
  3272. dprops->max_pkeys;
  3273. dev->mdev->port_caps[port - 1].gid_table_len =
  3274. pprops->gid_tbl_len;
  3275. mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
  3276. port, dprops->max_pkeys, pprops->gid_tbl_len);
  3277. out:
  3278. kfree(pprops);
  3279. kfree(dprops);
  3280. return err;
  3281. }
  3282. static void destroy_umrc_res(struct mlx5_ib_dev *dev)
  3283. {
  3284. int err;
  3285. err = mlx5_mr_cache_cleanup(dev);
  3286. if (err)
  3287. mlx5_ib_warn(dev, "mr cache cleanup failed\n");
  3288. if (dev->umrc.qp)
  3289. mlx5_ib_destroy_qp(dev->umrc.qp);
  3290. if (dev->umrc.cq)
  3291. ib_free_cq(dev->umrc.cq);
  3292. if (dev->umrc.pd)
  3293. ib_dealloc_pd(dev->umrc.pd);
  3294. }
  3295. enum {
  3296. MAX_UMR_WR = 128,
  3297. };
  3298. static int create_umr_res(struct mlx5_ib_dev *dev)
  3299. {
  3300. struct ib_qp_init_attr *init_attr = NULL;
  3301. struct ib_qp_attr *attr = NULL;
  3302. struct ib_pd *pd;
  3303. struct ib_cq *cq;
  3304. struct ib_qp *qp;
  3305. int ret;
  3306. attr = kzalloc(sizeof(*attr), GFP_KERNEL);
  3307. init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
  3308. if (!attr || !init_attr) {
  3309. ret = -ENOMEM;
  3310. goto error_0;
  3311. }
  3312. pd = ib_alloc_pd(&dev->ib_dev, 0);
  3313. if (IS_ERR(pd)) {
  3314. mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
  3315. ret = PTR_ERR(pd);
  3316. goto error_0;
  3317. }
  3318. cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
  3319. if (IS_ERR(cq)) {
  3320. mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
  3321. ret = PTR_ERR(cq);
  3322. goto error_2;
  3323. }
  3324. init_attr->send_cq = cq;
  3325. init_attr->recv_cq = cq;
  3326. init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
  3327. init_attr->cap.max_send_wr = MAX_UMR_WR;
  3328. init_attr->cap.max_send_sge = 1;
  3329. init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
  3330. init_attr->port_num = 1;
  3331. qp = mlx5_ib_create_qp(pd, init_attr, NULL);
  3332. if (IS_ERR(qp)) {
  3333. mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
  3334. ret = PTR_ERR(qp);
  3335. goto error_3;
  3336. }
  3337. qp->device = &dev->ib_dev;
  3338. qp->real_qp = qp;
  3339. qp->uobject = NULL;
  3340. qp->qp_type = MLX5_IB_QPT_REG_UMR;
  3341. qp->send_cq = init_attr->send_cq;
  3342. qp->recv_cq = init_attr->recv_cq;
  3343. attr->qp_state = IB_QPS_INIT;
  3344. attr->port_num = 1;
  3345. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
  3346. IB_QP_PORT, NULL);
  3347. if (ret) {
  3348. mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
  3349. goto error_4;
  3350. }
  3351. memset(attr, 0, sizeof(*attr));
  3352. attr->qp_state = IB_QPS_RTR;
  3353. attr->path_mtu = IB_MTU_256;
  3354. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  3355. if (ret) {
  3356. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
  3357. goto error_4;
  3358. }
  3359. memset(attr, 0, sizeof(*attr));
  3360. attr->qp_state = IB_QPS_RTS;
  3361. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  3362. if (ret) {
  3363. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
  3364. goto error_4;
  3365. }
  3366. dev->umrc.qp = qp;
  3367. dev->umrc.cq = cq;
  3368. dev->umrc.pd = pd;
  3369. sema_init(&dev->umrc.sem, MAX_UMR_WR);
  3370. ret = mlx5_mr_cache_init(dev);
  3371. if (ret) {
  3372. mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
  3373. goto error_4;
  3374. }
  3375. kfree(attr);
  3376. kfree(init_attr);
  3377. return 0;
  3378. error_4:
  3379. mlx5_ib_destroy_qp(qp);
  3380. dev->umrc.qp = NULL;
  3381. error_3:
  3382. ib_free_cq(cq);
  3383. dev->umrc.cq = NULL;
  3384. error_2:
  3385. ib_dealloc_pd(pd);
  3386. dev->umrc.pd = NULL;
  3387. error_0:
  3388. kfree(attr);
  3389. kfree(init_attr);
  3390. return ret;
  3391. }
  3392. static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
  3393. {
  3394. switch (umr_fence_cap) {
  3395. case MLX5_CAP_UMR_FENCE_NONE:
  3396. return MLX5_FENCE_MODE_NONE;
  3397. case MLX5_CAP_UMR_FENCE_SMALL:
  3398. return MLX5_FENCE_MODE_INITIATOR_SMALL;
  3399. default:
  3400. return MLX5_FENCE_MODE_STRONG_ORDERING;
  3401. }
  3402. }
  3403. static int create_dev_resources(struct mlx5_ib_resources *devr)
  3404. {
  3405. struct ib_srq_init_attr attr;
  3406. struct mlx5_ib_dev *dev;
  3407. struct ib_cq_init_attr cq_attr = {.cqe = 1};
  3408. int port;
  3409. int ret = 0;
  3410. dev = container_of(devr, struct mlx5_ib_dev, devr);
  3411. mutex_init(&devr->mutex);
  3412. devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
  3413. if (IS_ERR(devr->p0)) {
  3414. ret = PTR_ERR(devr->p0);
  3415. goto error0;
  3416. }
  3417. devr->p0->device = &dev->ib_dev;
  3418. devr->p0->uobject = NULL;
  3419. atomic_set(&devr->p0->usecnt, 0);
  3420. devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
  3421. if (IS_ERR(devr->c0)) {
  3422. ret = PTR_ERR(devr->c0);
  3423. goto error1;
  3424. }
  3425. devr->c0->device = &dev->ib_dev;
  3426. devr->c0->uobject = NULL;
  3427. devr->c0->comp_handler = NULL;
  3428. devr->c0->event_handler = NULL;
  3429. devr->c0->cq_context = NULL;
  3430. atomic_set(&devr->c0->usecnt, 0);
  3431. devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  3432. if (IS_ERR(devr->x0)) {
  3433. ret = PTR_ERR(devr->x0);
  3434. goto error2;
  3435. }
  3436. devr->x0->device = &dev->ib_dev;
  3437. devr->x0->inode = NULL;
  3438. atomic_set(&devr->x0->usecnt, 0);
  3439. mutex_init(&devr->x0->tgt_qp_mutex);
  3440. INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
  3441. devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  3442. if (IS_ERR(devr->x1)) {
  3443. ret = PTR_ERR(devr->x1);
  3444. goto error3;
  3445. }
  3446. devr->x1->device = &dev->ib_dev;
  3447. devr->x1->inode = NULL;
  3448. atomic_set(&devr->x1->usecnt, 0);
  3449. mutex_init(&devr->x1->tgt_qp_mutex);
  3450. INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
  3451. memset(&attr, 0, sizeof(attr));
  3452. attr.attr.max_sge = 1;
  3453. attr.attr.max_wr = 1;
  3454. attr.srq_type = IB_SRQT_XRC;
  3455. attr.ext.cq = devr->c0;
  3456. attr.ext.xrc.xrcd = devr->x0;
  3457. devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  3458. if (IS_ERR(devr->s0)) {
  3459. ret = PTR_ERR(devr->s0);
  3460. goto error4;
  3461. }
  3462. devr->s0->device = &dev->ib_dev;
  3463. devr->s0->pd = devr->p0;
  3464. devr->s0->uobject = NULL;
  3465. devr->s0->event_handler = NULL;
  3466. devr->s0->srq_context = NULL;
  3467. devr->s0->srq_type = IB_SRQT_XRC;
  3468. devr->s0->ext.xrc.xrcd = devr->x0;
  3469. devr->s0->ext.cq = devr->c0;
  3470. atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
  3471. atomic_inc(&devr->s0->ext.cq->usecnt);
  3472. atomic_inc(&devr->p0->usecnt);
  3473. atomic_set(&devr->s0->usecnt, 0);
  3474. memset(&attr, 0, sizeof(attr));
  3475. attr.attr.max_sge = 1;
  3476. attr.attr.max_wr = 1;
  3477. attr.srq_type = IB_SRQT_BASIC;
  3478. devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  3479. if (IS_ERR(devr->s1)) {
  3480. ret = PTR_ERR(devr->s1);
  3481. goto error5;
  3482. }
  3483. devr->s1->device = &dev->ib_dev;
  3484. devr->s1->pd = devr->p0;
  3485. devr->s1->uobject = NULL;
  3486. devr->s1->event_handler = NULL;
  3487. devr->s1->srq_context = NULL;
  3488. devr->s1->srq_type = IB_SRQT_BASIC;
  3489. devr->s1->ext.cq = devr->c0;
  3490. atomic_inc(&devr->p0->usecnt);
  3491. atomic_set(&devr->s1->usecnt, 0);
  3492. for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
  3493. INIT_WORK(&devr->ports[port].pkey_change_work,
  3494. pkey_change_handler);
  3495. devr->ports[port].devr = devr;
  3496. }
  3497. return 0;
  3498. error5:
  3499. mlx5_ib_destroy_srq(devr->s0);
  3500. error4:
  3501. mlx5_ib_dealloc_xrcd(devr->x1);
  3502. error3:
  3503. mlx5_ib_dealloc_xrcd(devr->x0);
  3504. error2:
  3505. mlx5_ib_destroy_cq(devr->c0);
  3506. error1:
  3507. mlx5_ib_dealloc_pd(devr->p0);
  3508. error0:
  3509. return ret;
  3510. }
  3511. static void destroy_dev_resources(struct mlx5_ib_resources *devr)
  3512. {
  3513. struct mlx5_ib_dev *dev =
  3514. container_of(devr, struct mlx5_ib_dev, devr);
  3515. int port;
  3516. mlx5_ib_destroy_srq(devr->s1);
  3517. mlx5_ib_destroy_srq(devr->s0);
  3518. mlx5_ib_dealloc_xrcd(devr->x0);
  3519. mlx5_ib_dealloc_xrcd(devr->x1);
  3520. mlx5_ib_destroy_cq(devr->c0);
  3521. mlx5_ib_dealloc_pd(devr->p0);
  3522. /* Make sure no change P_Key work items are still executing */
  3523. for (port = 0; port < dev->num_ports; ++port)
  3524. cancel_work_sync(&devr->ports[port].pkey_change_work);
  3525. }
  3526. static u32 get_core_cap_flags(struct ib_device *ibdev)
  3527. {
  3528. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  3529. enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
  3530. u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
  3531. u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
  3532. bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
  3533. u32 ret = 0;
  3534. if (ll == IB_LINK_LAYER_INFINIBAND)
  3535. return RDMA_CORE_PORT_IBA_IB;
  3536. if (raw_support)
  3537. ret = RDMA_CORE_PORT_RAW_PACKET;
  3538. if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
  3539. return ret;
  3540. if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
  3541. return ret;
  3542. if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
  3543. ret |= RDMA_CORE_PORT_IBA_ROCE;
  3544. if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
  3545. ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  3546. return ret;
  3547. }
  3548. static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
  3549. struct ib_port_immutable *immutable)
  3550. {
  3551. struct ib_port_attr attr;
  3552. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  3553. enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
  3554. int err;
  3555. immutable->core_cap_flags = get_core_cap_flags(ibdev);
  3556. err = ib_query_port(ibdev, port_num, &attr);
  3557. if (err)
  3558. return err;
  3559. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  3560. immutable->gid_tbl_len = attr.gid_tbl_len;
  3561. immutable->core_cap_flags = get_core_cap_flags(ibdev);
  3562. if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
  3563. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  3564. return 0;
  3565. }
  3566. static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
  3567. struct ib_port_immutable *immutable)
  3568. {
  3569. struct ib_port_attr attr;
  3570. int err;
  3571. immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
  3572. err = ib_query_port(ibdev, port_num, &attr);
  3573. if (err)
  3574. return err;
  3575. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  3576. immutable->gid_tbl_len = attr.gid_tbl_len;
  3577. immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
  3578. return 0;
  3579. }
  3580. static void get_dev_fw_str(struct ib_device *ibdev, char *str)
  3581. {
  3582. struct mlx5_ib_dev *dev =
  3583. container_of(ibdev, struct mlx5_ib_dev, ib_dev);
  3584. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
  3585. fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
  3586. fw_rev_sub(dev->mdev));
  3587. }
  3588. static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
  3589. {
  3590. struct mlx5_core_dev *mdev = dev->mdev;
  3591. struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
  3592. MLX5_FLOW_NAMESPACE_LAG);
  3593. struct mlx5_flow_table *ft;
  3594. int err;
  3595. if (!ns || !mlx5_lag_is_active(mdev))
  3596. return 0;
  3597. err = mlx5_cmd_create_vport_lag(mdev);
  3598. if (err)
  3599. return err;
  3600. ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
  3601. if (IS_ERR(ft)) {
  3602. err = PTR_ERR(ft);
  3603. goto err_destroy_vport_lag;
  3604. }
  3605. dev->flow_db->lag_demux_ft = ft;
  3606. return 0;
  3607. err_destroy_vport_lag:
  3608. mlx5_cmd_destroy_vport_lag(mdev);
  3609. return err;
  3610. }
  3611. static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
  3612. {
  3613. struct mlx5_core_dev *mdev = dev->mdev;
  3614. if (dev->flow_db->lag_demux_ft) {
  3615. mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
  3616. dev->flow_db->lag_demux_ft = NULL;
  3617. mlx5_cmd_destroy_vport_lag(mdev);
  3618. }
  3619. }
  3620. static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
  3621. {
  3622. int err;
  3623. dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
  3624. err = register_netdevice_notifier(&dev->roce[port_num].nb);
  3625. if (err) {
  3626. dev->roce[port_num].nb.notifier_call = NULL;
  3627. return err;
  3628. }
  3629. return 0;
  3630. }
  3631. static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
  3632. {
  3633. if (dev->roce[port_num].nb.notifier_call) {
  3634. unregister_netdevice_notifier(&dev->roce[port_num].nb);
  3635. dev->roce[port_num].nb.notifier_call = NULL;
  3636. }
  3637. }
  3638. static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
  3639. {
  3640. int err;
  3641. if (MLX5_CAP_GEN(dev->mdev, roce)) {
  3642. err = mlx5_nic_vport_enable_roce(dev->mdev);
  3643. if (err)
  3644. return err;
  3645. }
  3646. err = mlx5_eth_lag_init(dev);
  3647. if (err)
  3648. goto err_disable_roce;
  3649. return 0;
  3650. err_disable_roce:
  3651. if (MLX5_CAP_GEN(dev->mdev, roce))
  3652. mlx5_nic_vport_disable_roce(dev->mdev);
  3653. return err;
  3654. }
  3655. static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
  3656. {
  3657. mlx5_eth_lag_cleanup(dev);
  3658. if (MLX5_CAP_GEN(dev->mdev, roce))
  3659. mlx5_nic_vport_disable_roce(dev->mdev);
  3660. }
  3661. struct mlx5_ib_counter {
  3662. const char *name;
  3663. size_t offset;
  3664. };
  3665. #define INIT_Q_COUNTER(_name) \
  3666. { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
  3667. static const struct mlx5_ib_counter basic_q_cnts[] = {
  3668. INIT_Q_COUNTER(rx_write_requests),
  3669. INIT_Q_COUNTER(rx_read_requests),
  3670. INIT_Q_COUNTER(rx_atomic_requests),
  3671. INIT_Q_COUNTER(out_of_buffer),
  3672. };
  3673. static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
  3674. INIT_Q_COUNTER(out_of_sequence),
  3675. };
  3676. static const struct mlx5_ib_counter retrans_q_cnts[] = {
  3677. INIT_Q_COUNTER(duplicate_request),
  3678. INIT_Q_COUNTER(rnr_nak_retry_err),
  3679. INIT_Q_COUNTER(packet_seq_err),
  3680. INIT_Q_COUNTER(implied_nak_seq_err),
  3681. INIT_Q_COUNTER(local_ack_timeout_err),
  3682. };
  3683. #define INIT_CONG_COUNTER(_name) \
  3684. { .name = #_name, .offset = \
  3685. MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
  3686. static const struct mlx5_ib_counter cong_cnts[] = {
  3687. INIT_CONG_COUNTER(rp_cnp_ignored),
  3688. INIT_CONG_COUNTER(rp_cnp_handled),
  3689. INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
  3690. INIT_CONG_COUNTER(np_cnp_sent),
  3691. };
  3692. static const struct mlx5_ib_counter extended_err_cnts[] = {
  3693. INIT_Q_COUNTER(resp_local_length_error),
  3694. INIT_Q_COUNTER(resp_cqe_error),
  3695. INIT_Q_COUNTER(req_cqe_error),
  3696. INIT_Q_COUNTER(req_remote_invalid_request),
  3697. INIT_Q_COUNTER(req_remote_access_errors),
  3698. INIT_Q_COUNTER(resp_remote_access_errors),
  3699. INIT_Q_COUNTER(resp_cqe_flush_error),
  3700. INIT_Q_COUNTER(req_cqe_flush_error),
  3701. };
  3702. static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
  3703. {
  3704. int i;
  3705. for (i = 0; i < dev->num_ports; i++) {
  3706. if (dev->port[i].cnts.set_id)
  3707. mlx5_core_dealloc_q_counter(dev->mdev,
  3708. dev->port[i].cnts.set_id);
  3709. kfree(dev->port[i].cnts.names);
  3710. kfree(dev->port[i].cnts.offsets);
  3711. }
  3712. }
  3713. static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
  3714. struct mlx5_ib_counters *cnts)
  3715. {
  3716. u32 num_counters;
  3717. num_counters = ARRAY_SIZE(basic_q_cnts);
  3718. if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
  3719. num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
  3720. if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
  3721. num_counters += ARRAY_SIZE(retrans_q_cnts);
  3722. if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
  3723. num_counters += ARRAY_SIZE(extended_err_cnts);
  3724. cnts->num_q_counters = num_counters;
  3725. if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
  3726. cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
  3727. num_counters += ARRAY_SIZE(cong_cnts);
  3728. }
  3729. cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
  3730. if (!cnts->names)
  3731. return -ENOMEM;
  3732. cnts->offsets = kcalloc(num_counters,
  3733. sizeof(cnts->offsets), GFP_KERNEL);
  3734. if (!cnts->offsets)
  3735. goto err_names;
  3736. return 0;
  3737. err_names:
  3738. kfree(cnts->names);
  3739. cnts->names = NULL;
  3740. return -ENOMEM;
  3741. }
  3742. static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
  3743. const char **names,
  3744. size_t *offsets)
  3745. {
  3746. int i;
  3747. int j = 0;
  3748. for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
  3749. names[j] = basic_q_cnts[i].name;
  3750. offsets[j] = basic_q_cnts[i].offset;
  3751. }
  3752. if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
  3753. for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
  3754. names[j] = out_of_seq_q_cnts[i].name;
  3755. offsets[j] = out_of_seq_q_cnts[i].offset;
  3756. }
  3757. }
  3758. if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
  3759. for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
  3760. names[j] = retrans_q_cnts[i].name;
  3761. offsets[j] = retrans_q_cnts[i].offset;
  3762. }
  3763. }
  3764. if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
  3765. for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
  3766. names[j] = extended_err_cnts[i].name;
  3767. offsets[j] = extended_err_cnts[i].offset;
  3768. }
  3769. }
  3770. if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
  3771. for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
  3772. names[j] = cong_cnts[i].name;
  3773. offsets[j] = cong_cnts[i].offset;
  3774. }
  3775. }
  3776. }
  3777. static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
  3778. {
  3779. int err = 0;
  3780. int i;
  3781. for (i = 0; i < dev->num_ports; i++) {
  3782. err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
  3783. if (err)
  3784. goto err_alloc;
  3785. mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
  3786. dev->port[i].cnts.offsets);
  3787. err = mlx5_core_alloc_q_counter(dev->mdev,
  3788. &dev->port[i].cnts.set_id);
  3789. if (err) {
  3790. mlx5_ib_warn(dev,
  3791. "couldn't allocate queue counter for port %d, err %d\n",
  3792. i + 1, err);
  3793. goto err_alloc;
  3794. }
  3795. dev->port[i].cnts.set_id_valid = true;
  3796. }
  3797. return 0;
  3798. err_alloc:
  3799. mlx5_ib_dealloc_counters(dev);
  3800. return err;
  3801. }
  3802. static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
  3803. u8 port_num)
  3804. {
  3805. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  3806. struct mlx5_ib_port *port = &dev->port[port_num - 1];
  3807. /* We support only per port stats */
  3808. if (port_num == 0)
  3809. return NULL;
  3810. return rdma_alloc_hw_stats_struct(port->cnts.names,
  3811. port->cnts.num_q_counters +
  3812. port->cnts.num_cong_counters,
  3813. RDMA_HW_STATS_DEFAULT_LIFESPAN);
  3814. }
  3815. static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
  3816. struct mlx5_ib_port *port,
  3817. struct rdma_hw_stats *stats)
  3818. {
  3819. int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
  3820. void *out;
  3821. __be32 val;
  3822. int ret, i;
  3823. out = kvzalloc(outlen, GFP_KERNEL);
  3824. if (!out)
  3825. return -ENOMEM;
  3826. ret = mlx5_core_query_q_counter(mdev,
  3827. port->cnts.set_id, 0,
  3828. out, outlen);
  3829. if (ret)
  3830. goto free;
  3831. for (i = 0; i < port->cnts.num_q_counters; i++) {
  3832. val = *(__be32 *)(out + port->cnts.offsets[i]);
  3833. stats->value[i] = (u64)be32_to_cpu(val);
  3834. }
  3835. free:
  3836. kvfree(out);
  3837. return ret;
  3838. }
  3839. static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
  3840. struct rdma_hw_stats *stats,
  3841. u8 port_num, int index)
  3842. {
  3843. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  3844. struct mlx5_ib_port *port = &dev->port[port_num - 1];
  3845. struct mlx5_core_dev *mdev;
  3846. int ret, num_counters;
  3847. u8 mdev_port_num;
  3848. if (!stats)
  3849. return -EINVAL;
  3850. num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
  3851. /* q_counters are per IB device, query the master mdev */
  3852. ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
  3853. if (ret)
  3854. return ret;
  3855. if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
  3856. mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
  3857. &mdev_port_num);
  3858. if (!mdev) {
  3859. /* If port is not affiliated yet, its in down state
  3860. * which doesn't have any counters yet, so it would be
  3861. * zero. So no need to read from the HCA.
  3862. */
  3863. goto done;
  3864. }
  3865. ret = mlx5_lag_query_cong_counters(dev->mdev,
  3866. stats->value +
  3867. port->cnts.num_q_counters,
  3868. port->cnts.num_cong_counters,
  3869. port->cnts.offsets +
  3870. port->cnts.num_q_counters);
  3871. mlx5_ib_put_native_port_mdev(dev, port_num);
  3872. if (ret)
  3873. return ret;
  3874. }
  3875. done:
  3876. return num_counters;
  3877. }
  3878. static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
  3879. {
  3880. return mlx5_rdma_netdev_free(netdev);
  3881. }
  3882. static struct net_device*
  3883. mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
  3884. u8 port_num,
  3885. enum rdma_netdev_t type,
  3886. const char *name,
  3887. unsigned char name_assign_type,
  3888. void (*setup)(struct net_device *))
  3889. {
  3890. struct net_device *netdev;
  3891. struct rdma_netdev *rn;
  3892. if (type != RDMA_NETDEV_IPOIB)
  3893. return ERR_PTR(-EOPNOTSUPP);
  3894. netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
  3895. name, setup);
  3896. if (likely(!IS_ERR_OR_NULL(netdev))) {
  3897. rn = netdev_priv(netdev);
  3898. rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
  3899. }
  3900. return netdev;
  3901. }
  3902. static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
  3903. {
  3904. if (!dev->delay_drop.dbg)
  3905. return;
  3906. debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
  3907. kfree(dev->delay_drop.dbg);
  3908. dev->delay_drop.dbg = NULL;
  3909. }
  3910. static void cancel_delay_drop(struct mlx5_ib_dev *dev)
  3911. {
  3912. if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
  3913. return;
  3914. cancel_work_sync(&dev->delay_drop.delay_drop_work);
  3915. delay_drop_debugfs_cleanup(dev);
  3916. }
  3917. static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
  3918. size_t count, loff_t *pos)
  3919. {
  3920. struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
  3921. char lbuf[20];
  3922. int len;
  3923. len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
  3924. return simple_read_from_buffer(buf, count, pos, lbuf, len);
  3925. }
  3926. static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
  3927. size_t count, loff_t *pos)
  3928. {
  3929. struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
  3930. u32 timeout;
  3931. u32 var;
  3932. if (kstrtouint_from_user(buf, count, 0, &var))
  3933. return -EFAULT;
  3934. timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
  3935. 1000);
  3936. if (timeout != var)
  3937. mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
  3938. timeout);
  3939. delay_drop->timeout = timeout;
  3940. return count;
  3941. }
  3942. static const struct file_operations fops_delay_drop_timeout = {
  3943. .owner = THIS_MODULE,
  3944. .open = simple_open,
  3945. .write = delay_drop_timeout_write,
  3946. .read = delay_drop_timeout_read,
  3947. };
  3948. static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
  3949. {
  3950. struct mlx5_ib_dbg_delay_drop *dbg;
  3951. if (!mlx5_debugfs_root)
  3952. return 0;
  3953. dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
  3954. if (!dbg)
  3955. return -ENOMEM;
  3956. dev->delay_drop.dbg = dbg;
  3957. dbg->dir_debugfs =
  3958. debugfs_create_dir("delay_drop",
  3959. dev->mdev->priv.dbg_root);
  3960. if (!dbg->dir_debugfs)
  3961. goto out_debugfs;
  3962. dbg->events_cnt_debugfs =
  3963. debugfs_create_atomic_t("num_timeout_events", 0400,
  3964. dbg->dir_debugfs,
  3965. &dev->delay_drop.events_cnt);
  3966. if (!dbg->events_cnt_debugfs)
  3967. goto out_debugfs;
  3968. dbg->rqs_cnt_debugfs =
  3969. debugfs_create_atomic_t("num_rqs", 0400,
  3970. dbg->dir_debugfs,
  3971. &dev->delay_drop.rqs_cnt);
  3972. if (!dbg->rqs_cnt_debugfs)
  3973. goto out_debugfs;
  3974. dbg->timeout_debugfs =
  3975. debugfs_create_file("timeout", 0600,
  3976. dbg->dir_debugfs,
  3977. &dev->delay_drop,
  3978. &fops_delay_drop_timeout);
  3979. if (!dbg->timeout_debugfs)
  3980. goto out_debugfs;
  3981. return 0;
  3982. out_debugfs:
  3983. delay_drop_debugfs_cleanup(dev);
  3984. return -ENOMEM;
  3985. }
  3986. static void init_delay_drop(struct mlx5_ib_dev *dev)
  3987. {
  3988. if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
  3989. return;
  3990. mutex_init(&dev->delay_drop.lock);
  3991. dev->delay_drop.dev = dev;
  3992. dev->delay_drop.activate = false;
  3993. dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
  3994. INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
  3995. atomic_set(&dev->delay_drop.rqs_cnt, 0);
  3996. atomic_set(&dev->delay_drop.events_cnt, 0);
  3997. if (delay_drop_debugfs_init(dev))
  3998. mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
  3999. }
  4000. static const struct cpumask *
  4001. mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
  4002. {
  4003. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  4004. return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
  4005. }
  4006. /* The mlx5_ib_multiport_mutex should be held when calling this function */
  4007. static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
  4008. struct mlx5_ib_multiport_info *mpi)
  4009. {
  4010. u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
  4011. struct mlx5_ib_port *port = &ibdev->port[port_num];
  4012. int comps;
  4013. int err;
  4014. int i;
  4015. mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
  4016. spin_lock(&port->mp.mpi_lock);
  4017. if (!mpi->ibdev) {
  4018. spin_unlock(&port->mp.mpi_lock);
  4019. return;
  4020. }
  4021. mpi->ibdev = NULL;
  4022. spin_unlock(&port->mp.mpi_lock);
  4023. mlx5_remove_netdev_notifier(ibdev, port_num);
  4024. spin_lock(&port->mp.mpi_lock);
  4025. comps = mpi->mdev_refcnt;
  4026. if (comps) {
  4027. mpi->unaffiliate = true;
  4028. init_completion(&mpi->unref_comp);
  4029. spin_unlock(&port->mp.mpi_lock);
  4030. for (i = 0; i < comps; i++)
  4031. wait_for_completion(&mpi->unref_comp);
  4032. spin_lock(&port->mp.mpi_lock);
  4033. mpi->unaffiliate = false;
  4034. }
  4035. port->mp.mpi = NULL;
  4036. list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
  4037. spin_unlock(&port->mp.mpi_lock);
  4038. err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
  4039. mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
  4040. /* Log an error, still needed to cleanup the pointers and add
  4041. * it back to the list.
  4042. */
  4043. if (err)
  4044. mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
  4045. port_num + 1);
  4046. ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
  4047. }
  4048. /* The mlx5_ib_multiport_mutex should be held when calling this function */
  4049. static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
  4050. struct mlx5_ib_multiport_info *mpi)
  4051. {
  4052. u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
  4053. int err;
  4054. spin_lock(&ibdev->port[port_num].mp.mpi_lock);
  4055. if (ibdev->port[port_num].mp.mpi) {
  4056. mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
  4057. port_num + 1);
  4058. spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
  4059. return false;
  4060. }
  4061. ibdev->port[port_num].mp.mpi = mpi;
  4062. mpi->ibdev = ibdev;
  4063. spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
  4064. err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
  4065. if (err)
  4066. goto unbind;
  4067. err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
  4068. if (err)
  4069. goto unbind;
  4070. err = mlx5_add_netdev_notifier(ibdev, port_num);
  4071. if (err) {
  4072. mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
  4073. port_num + 1);
  4074. goto unbind;
  4075. }
  4076. err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
  4077. if (err)
  4078. goto unbind;
  4079. return true;
  4080. unbind:
  4081. mlx5_ib_unbind_slave_port(ibdev, mpi);
  4082. return false;
  4083. }
  4084. static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
  4085. {
  4086. int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
  4087. enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
  4088. port_num + 1);
  4089. struct mlx5_ib_multiport_info *mpi;
  4090. int err;
  4091. int i;
  4092. if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
  4093. return 0;
  4094. err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
  4095. &dev->sys_image_guid);
  4096. if (err)
  4097. return err;
  4098. err = mlx5_nic_vport_enable_roce(dev->mdev);
  4099. if (err)
  4100. return err;
  4101. mutex_lock(&mlx5_ib_multiport_mutex);
  4102. for (i = 0; i < dev->num_ports; i++) {
  4103. bool bound = false;
  4104. /* build a stub multiport info struct for the native port. */
  4105. if (i == port_num) {
  4106. mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
  4107. if (!mpi) {
  4108. mutex_unlock(&mlx5_ib_multiport_mutex);
  4109. mlx5_nic_vport_disable_roce(dev->mdev);
  4110. return -ENOMEM;
  4111. }
  4112. mpi->is_master = true;
  4113. mpi->mdev = dev->mdev;
  4114. mpi->sys_image_guid = dev->sys_image_guid;
  4115. dev->port[i].mp.mpi = mpi;
  4116. mpi->ibdev = dev;
  4117. mpi = NULL;
  4118. continue;
  4119. }
  4120. list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
  4121. list) {
  4122. if (dev->sys_image_guid == mpi->sys_image_guid &&
  4123. (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
  4124. bound = mlx5_ib_bind_slave_port(dev, mpi);
  4125. }
  4126. if (bound) {
  4127. dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
  4128. mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
  4129. list_del(&mpi->list);
  4130. break;
  4131. }
  4132. }
  4133. if (!bound) {
  4134. get_port_caps(dev, i + 1);
  4135. mlx5_ib_dbg(dev, "no free port found for port %d\n",
  4136. i + 1);
  4137. }
  4138. }
  4139. list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
  4140. mutex_unlock(&mlx5_ib_multiport_mutex);
  4141. return err;
  4142. }
  4143. static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
  4144. {
  4145. int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
  4146. enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
  4147. port_num + 1);
  4148. int i;
  4149. if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
  4150. return;
  4151. mutex_lock(&mlx5_ib_multiport_mutex);
  4152. for (i = 0; i < dev->num_ports; i++) {
  4153. if (dev->port[i].mp.mpi) {
  4154. /* Destroy the native port stub */
  4155. if (i == port_num) {
  4156. kfree(dev->port[i].mp.mpi);
  4157. dev->port[i].mp.mpi = NULL;
  4158. } else {
  4159. mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
  4160. mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
  4161. }
  4162. }
  4163. }
  4164. mlx5_ib_dbg(dev, "removing from devlist\n");
  4165. list_del(&dev->ib_dev_list);
  4166. mutex_unlock(&mlx5_ib_multiport_mutex);
  4167. mlx5_nic_vport_disable_roce(dev->mdev);
  4168. }
  4169. ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
  4170. UVERBS_METHOD_DM_ALLOC,
  4171. &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
  4172. UVERBS_ATTR_TYPE(u64),
  4173. UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
  4174. &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
  4175. UVERBS_ATTR_TYPE(u16),
  4176. UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
  4177. ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
  4178. UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
  4179. &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
  4180. UVERBS_ATTR_TYPE(u64),
  4181. UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
  4182. #define NUM_TREES 2
  4183. static int populate_specs_root(struct mlx5_ib_dev *dev)
  4184. {
  4185. const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
  4186. uverbs_default_get_objects()};
  4187. size_t num_trees = 1;
  4188. if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
  4189. !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
  4190. default_root[num_trees++] = &mlx5_ib_flow_action;
  4191. if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
  4192. !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
  4193. default_root[num_trees++] = &mlx5_ib_dm;
  4194. dev->ib_dev.specs_root =
  4195. uverbs_alloc_spec_tree(num_trees, default_root);
  4196. return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
  4197. }
  4198. static void depopulate_specs_root(struct mlx5_ib_dev *dev)
  4199. {
  4200. uverbs_free_spec_tree(dev->ib_dev.specs_root);
  4201. }
  4202. void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
  4203. {
  4204. mlx5_ib_cleanup_multiport_master(dev);
  4205. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  4206. cleanup_srcu_struct(&dev->mr_srcu);
  4207. #endif
  4208. kfree(dev->port);
  4209. }
  4210. int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
  4211. {
  4212. struct mlx5_core_dev *mdev = dev->mdev;
  4213. const char *name;
  4214. int err;
  4215. int i;
  4216. dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
  4217. GFP_KERNEL);
  4218. if (!dev->port)
  4219. return -ENOMEM;
  4220. for (i = 0; i < dev->num_ports; i++) {
  4221. spin_lock_init(&dev->port[i].mp.mpi_lock);
  4222. rwlock_init(&dev->roce[i].netdev_lock);
  4223. }
  4224. err = mlx5_ib_init_multiport_master(dev);
  4225. if (err)
  4226. goto err_free_port;
  4227. if (!mlx5_core_mp_enabled(mdev)) {
  4228. for (i = 1; i <= dev->num_ports; i++) {
  4229. err = get_port_caps(dev, i);
  4230. if (err)
  4231. break;
  4232. }
  4233. } else {
  4234. err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
  4235. }
  4236. if (err)
  4237. goto err_mp;
  4238. if (mlx5_use_mad_ifc(dev))
  4239. get_ext_port_caps(dev);
  4240. if (!mlx5_lag_is_active(mdev))
  4241. name = "mlx5_%d";
  4242. else
  4243. name = "mlx5_bond_%d";
  4244. strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
  4245. dev->ib_dev.owner = THIS_MODULE;
  4246. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  4247. dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
  4248. dev->ib_dev.phys_port_cnt = dev->num_ports;
  4249. dev->ib_dev.num_comp_vectors =
  4250. dev->mdev->priv.eq_table.num_comp_vectors;
  4251. dev->ib_dev.dev.parent = &mdev->pdev->dev;
  4252. mutex_init(&dev->cap_mask_mutex);
  4253. INIT_LIST_HEAD(&dev->qp_list);
  4254. spin_lock_init(&dev->reset_flow_resource_lock);
  4255. spin_lock_init(&dev->memic.memic_lock);
  4256. dev->memic.dev = mdev;
  4257. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  4258. err = init_srcu_struct(&dev->mr_srcu);
  4259. if (err)
  4260. goto err_free_port;
  4261. #endif
  4262. return 0;
  4263. err_mp:
  4264. mlx5_ib_cleanup_multiport_master(dev);
  4265. err_free_port:
  4266. kfree(dev->port);
  4267. return -ENOMEM;
  4268. }
  4269. static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
  4270. {
  4271. dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
  4272. if (!dev->flow_db)
  4273. return -ENOMEM;
  4274. mutex_init(&dev->flow_db->lock);
  4275. return 0;
  4276. }
  4277. int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
  4278. {
  4279. struct mlx5_ib_dev *nic_dev;
  4280. nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
  4281. if (!nic_dev)
  4282. return -EINVAL;
  4283. dev->flow_db = nic_dev->flow_db;
  4284. return 0;
  4285. }
  4286. static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
  4287. {
  4288. kfree(dev->flow_db);
  4289. }
  4290. int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
  4291. {
  4292. struct mlx5_core_dev *mdev = dev->mdev;
  4293. int err;
  4294. dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
  4295. dev->ib_dev.uverbs_cmd_mask =
  4296. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  4297. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  4298. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  4299. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  4300. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  4301. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  4302. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  4303. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  4304. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  4305. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  4306. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  4307. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  4308. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  4309. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  4310. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  4311. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  4312. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  4313. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  4314. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  4315. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  4316. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  4317. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  4318. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  4319. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  4320. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  4321. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  4322. dev->ib_dev.uverbs_ex_cmd_mask =
  4323. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  4324. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
  4325. (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
  4326. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
  4327. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
  4328. dev->ib_dev.query_device = mlx5_ib_query_device;
  4329. dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
  4330. dev->ib_dev.query_gid = mlx5_ib_query_gid;
  4331. dev->ib_dev.add_gid = mlx5_ib_add_gid;
  4332. dev->ib_dev.del_gid = mlx5_ib_del_gid;
  4333. dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
  4334. dev->ib_dev.modify_device = mlx5_ib_modify_device;
  4335. dev->ib_dev.modify_port = mlx5_ib_modify_port;
  4336. dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
  4337. dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
  4338. dev->ib_dev.mmap = mlx5_ib_mmap;
  4339. dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
  4340. dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
  4341. dev->ib_dev.create_ah = mlx5_ib_create_ah;
  4342. dev->ib_dev.query_ah = mlx5_ib_query_ah;
  4343. dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
  4344. dev->ib_dev.create_srq = mlx5_ib_create_srq;
  4345. dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
  4346. dev->ib_dev.query_srq = mlx5_ib_query_srq;
  4347. dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
  4348. dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
  4349. dev->ib_dev.create_qp = mlx5_ib_create_qp;
  4350. dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
  4351. dev->ib_dev.query_qp = mlx5_ib_query_qp;
  4352. dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
  4353. dev->ib_dev.post_send = mlx5_ib_post_send;
  4354. dev->ib_dev.post_recv = mlx5_ib_post_recv;
  4355. dev->ib_dev.create_cq = mlx5_ib_create_cq;
  4356. dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
  4357. dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
  4358. dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
  4359. dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
  4360. dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
  4361. dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
  4362. dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
  4363. dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
  4364. dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
  4365. dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
  4366. dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
  4367. dev->ib_dev.process_mad = mlx5_ib_process_mad;
  4368. dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
  4369. dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
  4370. dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
  4371. dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
  4372. dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
  4373. if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
  4374. dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
  4375. if (mlx5_core_is_pf(mdev)) {
  4376. dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
  4377. dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
  4378. dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
  4379. dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
  4380. }
  4381. dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
  4382. dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
  4383. if (MLX5_CAP_GEN(mdev, imaicl)) {
  4384. dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
  4385. dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
  4386. dev->ib_dev.uverbs_cmd_mask |=
  4387. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  4388. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  4389. }
  4390. if (MLX5_CAP_GEN(mdev, xrc)) {
  4391. dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
  4392. dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
  4393. dev->ib_dev.uverbs_cmd_mask |=
  4394. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  4395. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  4396. }
  4397. if (MLX5_CAP_DEV_MEM(mdev, memic)) {
  4398. dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
  4399. dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
  4400. dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
  4401. }
  4402. dev->ib_dev.create_flow = mlx5_ib_create_flow;
  4403. dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
  4404. dev->ib_dev.uverbs_ex_cmd_mask |=
  4405. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  4406. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  4407. dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
  4408. dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
  4409. dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
  4410. dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
  4411. err = init_node_data(dev);
  4412. if (err)
  4413. return err;
  4414. if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
  4415. (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
  4416. MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
  4417. mutex_init(&dev->lb_mutex);
  4418. return 0;
  4419. }
  4420. static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
  4421. {
  4422. dev->ib_dev.get_port_immutable = mlx5_port_immutable;
  4423. dev->ib_dev.query_port = mlx5_ib_query_port;
  4424. return 0;
  4425. }
  4426. int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
  4427. {
  4428. dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
  4429. dev->ib_dev.query_port = mlx5_ib_rep_query_port;
  4430. return 0;
  4431. }
  4432. static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
  4433. u8 port_num)
  4434. {
  4435. int i;
  4436. for (i = 0; i < dev->num_ports; i++) {
  4437. dev->roce[i].dev = dev;
  4438. dev->roce[i].native_port_num = i + 1;
  4439. dev->roce[i].last_port_state = IB_PORT_DOWN;
  4440. }
  4441. dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
  4442. dev->ib_dev.create_wq = mlx5_ib_create_wq;
  4443. dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
  4444. dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
  4445. dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
  4446. dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
  4447. dev->ib_dev.uverbs_ex_cmd_mask |=
  4448. (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
  4449. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
  4450. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
  4451. (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
  4452. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
  4453. return mlx5_add_netdev_notifier(dev, port_num);
  4454. }
  4455. static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
  4456. {
  4457. u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
  4458. mlx5_remove_netdev_notifier(dev, port_num);
  4459. }
  4460. int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
  4461. {
  4462. struct mlx5_core_dev *mdev = dev->mdev;
  4463. enum rdma_link_layer ll;
  4464. int port_type_cap;
  4465. int err = 0;
  4466. u8 port_num;
  4467. port_num = mlx5_core_native_port_num(dev->mdev) - 1;
  4468. port_type_cap = MLX5_CAP_GEN(mdev, port_type);
  4469. ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  4470. if (ll == IB_LINK_LAYER_ETHERNET)
  4471. err = mlx5_ib_stage_common_roce_init(dev, port_num);
  4472. return err;
  4473. }
  4474. void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
  4475. {
  4476. mlx5_ib_stage_common_roce_cleanup(dev);
  4477. }
  4478. static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
  4479. {
  4480. struct mlx5_core_dev *mdev = dev->mdev;
  4481. enum rdma_link_layer ll;
  4482. int port_type_cap;
  4483. u8 port_num;
  4484. int err;
  4485. port_num = mlx5_core_native_port_num(dev->mdev) - 1;
  4486. port_type_cap = MLX5_CAP_GEN(mdev, port_type);
  4487. ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  4488. if (ll == IB_LINK_LAYER_ETHERNET) {
  4489. err = mlx5_ib_stage_common_roce_init(dev, port_num);
  4490. if (err)
  4491. return err;
  4492. err = mlx5_enable_eth(dev, port_num);
  4493. if (err)
  4494. goto cleanup;
  4495. }
  4496. return 0;
  4497. cleanup:
  4498. mlx5_ib_stage_common_roce_cleanup(dev);
  4499. return err;
  4500. }
  4501. static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
  4502. {
  4503. struct mlx5_core_dev *mdev = dev->mdev;
  4504. enum rdma_link_layer ll;
  4505. int port_type_cap;
  4506. u8 port_num;
  4507. port_num = mlx5_core_native_port_num(dev->mdev) - 1;
  4508. port_type_cap = MLX5_CAP_GEN(mdev, port_type);
  4509. ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  4510. if (ll == IB_LINK_LAYER_ETHERNET) {
  4511. mlx5_disable_eth(dev);
  4512. mlx5_ib_stage_common_roce_cleanup(dev);
  4513. }
  4514. }
  4515. int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
  4516. {
  4517. return create_dev_resources(&dev->devr);
  4518. }
  4519. void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
  4520. {
  4521. destroy_dev_resources(&dev->devr);
  4522. }
  4523. static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
  4524. {
  4525. mlx5_ib_internal_fill_odp_caps(dev);
  4526. return mlx5_ib_odp_init_one(dev);
  4527. }
  4528. int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
  4529. {
  4530. if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
  4531. dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
  4532. dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
  4533. return mlx5_ib_alloc_counters(dev);
  4534. }
  4535. return 0;
  4536. }
  4537. void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
  4538. {
  4539. if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
  4540. mlx5_ib_dealloc_counters(dev);
  4541. }
  4542. static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
  4543. {
  4544. return mlx5_ib_init_cong_debugfs(dev,
  4545. mlx5_core_native_port_num(dev->mdev) - 1);
  4546. }
  4547. static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
  4548. {
  4549. mlx5_ib_cleanup_cong_debugfs(dev,
  4550. mlx5_core_native_port_num(dev->mdev) - 1);
  4551. }
  4552. static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
  4553. {
  4554. dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
  4555. return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
  4556. }
  4557. static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
  4558. {
  4559. mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
  4560. }
  4561. int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
  4562. {
  4563. int err;
  4564. err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
  4565. if (err)
  4566. return err;
  4567. err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
  4568. if (err)
  4569. mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
  4570. return err;
  4571. }
  4572. void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
  4573. {
  4574. mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
  4575. mlx5_free_bfreg(dev->mdev, &dev->bfreg);
  4576. }
  4577. static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
  4578. {
  4579. return populate_specs_root(dev);
  4580. }
  4581. int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
  4582. {
  4583. return ib_register_device(&dev->ib_dev, NULL);
  4584. }
  4585. static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
  4586. {
  4587. depopulate_specs_root(dev);
  4588. }
  4589. void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
  4590. {
  4591. destroy_umrc_res(dev);
  4592. }
  4593. void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
  4594. {
  4595. ib_unregister_device(&dev->ib_dev);
  4596. }
  4597. int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
  4598. {
  4599. return create_umr_res(dev);
  4600. }
  4601. static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
  4602. {
  4603. init_delay_drop(dev);
  4604. return 0;
  4605. }
  4606. static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
  4607. {
  4608. cancel_delay_drop(dev);
  4609. }
  4610. int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
  4611. {
  4612. int err;
  4613. int i;
  4614. for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
  4615. err = device_create_file(&dev->ib_dev.dev,
  4616. mlx5_class_attributes[i]);
  4617. if (err)
  4618. return err;
  4619. }
  4620. return 0;
  4621. }
  4622. static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
  4623. {
  4624. mlx5_ib_register_vport_reps(dev);
  4625. return 0;
  4626. }
  4627. static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
  4628. {
  4629. mlx5_ib_unregister_vport_reps(dev);
  4630. }
  4631. void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
  4632. const struct mlx5_ib_profile *profile,
  4633. int stage)
  4634. {
  4635. /* Number of stages to cleanup */
  4636. while (stage) {
  4637. stage--;
  4638. if (profile->stage[stage].cleanup)
  4639. profile->stage[stage].cleanup(dev);
  4640. }
  4641. ib_dealloc_device((struct ib_device *)dev);
  4642. }
  4643. static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
  4644. void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
  4645. const struct mlx5_ib_profile *profile)
  4646. {
  4647. int err;
  4648. int i;
  4649. printk_once(KERN_INFO "%s", mlx5_version);
  4650. for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
  4651. if (profile->stage[i].init) {
  4652. err = profile->stage[i].init(dev);
  4653. if (err)
  4654. goto err_out;
  4655. }
  4656. }
  4657. dev->profile = profile;
  4658. dev->ib_active = true;
  4659. return dev;
  4660. err_out:
  4661. __mlx5_ib_remove(dev, profile, i);
  4662. return NULL;
  4663. }
  4664. static const struct mlx5_ib_profile pf_profile = {
  4665. STAGE_CREATE(MLX5_IB_STAGE_INIT,
  4666. mlx5_ib_stage_init_init,
  4667. mlx5_ib_stage_init_cleanup),
  4668. STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
  4669. mlx5_ib_stage_flow_db_init,
  4670. mlx5_ib_stage_flow_db_cleanup),
  4671. STAGE_CREATE(MLX5_IB_STAGE_CAPS,
  4672. mlx5_ib_stage_caps_init,
  4673. NULL),
  4674. STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
  4675. mlx5_ib_stage_non_default_cb,
  4676. NULL),
  4677. STAGE_CREATE(MLX5_IB_STAGE_ROCE,
  4678. mlx5_ib_stage_roce_init,
  4679. mlx5_ib_stage_roce_cleanup),
  4680. STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
  4681. mlx5_ib_stage_dev_res_init,
  4682. mlx5_ib_stage_dev_res_cleanup),
  4683. STAGE_CREATE(MLX5_IB_STAGE_ODP,
  4684. mlx5_ib_stage_odp_init,
  4685. NULL),
  4686. STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
  4687. mlx5_ib_stage_counters_init,
  4688. mlx5_ib_stage_counters_cleanup),
  4689. STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
  4690. mlx5_ib_stage_cong_debugfs_init,
  4691. mlx5_ib_stage_cong_debugfs_cleanup),
  4692. STAGE_CREATE(MLX5_IB_STAGE_UAR,
  4693. mlx5_ib_stage_uar_init,
  4694. mlx5_ib_stage_uar_cleanup),
  4695. STAGE_CREATE(MLX5_IB_STAGE_BFREG,
  4696. mlx5_ib_stage_bfrag_init,
  4697. mlx5_ib_stage_bfrag_cleanup),
  4698. STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
  4699. NULL,
  4700. mlx5_ib_stage_pre_ib_reg_umr_cleanup),
  4701. STAGE_CREATE(MLX5_IB_STAGE_SPECS,
  4702. mlx5_ib_stage_populate_specs,
  4703. mlx5_ib_stage_depopulate_specs),
  4704. STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
  4705. mlx5_ib_stage_ib_reg_init,
  4706. mlx5_ib_stage_ib_reg_cleanup),
  4707. STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
  4708. mlx5_ib_stage_post_ib_reg_umr_init,
  4709. NULL),
  4710. STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
  4711. mlx5_ib_stage_delay_drop_init,
  4712. mlx5_ib_stage_delay_drop_cleanup),
  4713. STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
  4714. mlx5_ib_stage_class_attr_init,
  4715. NULL),
  4716. };
  4717. static const struct mlx5_ib_profile nic_rep_profile = {
  4718. STAGE_CREATE(MLX5_IB_STAGE_INIT,
  4719. mlx5_ib_stage_init_init,
  4720. mlx5_ib_stage_init_cleanup),
  4721. STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
  4722. mlx5_ib_stage_flow_db_init,
  4723. mlx5_ib_stage_flow_db_cleanup),
  4724. STAGE_CREATE(MLX5_IB_STAGE_CAPS,
  4725. mlx5_ib_stage_caps_init,
  4726. NULL),
  4727. STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
  4728. mlx5_ib_stage_rep_non_default_cb,
  4729. NULL),
  4730. STAGE_CREATE(MLX5_IB_STAGE_ROCE,
  4731. mlx5_ib_stage_rep_roce_init,
  4732. mlx5_ib_stage_rep_roce_cleanup),
  4733. STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
  4734. mlx5_ib_stage_dev_res_init,
  4735. mlx5_ib_stage_dev_res_cleanup),
  4736. STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
  4737. mlx5_ib_stage_counters_init,
  4738. mlx5_ib_stage_counters_cleanup),
  4739. STAGE_CREATE(MLX5_IB_STAGE_UAR,
  4740. mlx5_ib_stage_uar_init,
  4741. mlx5_ib_stage_uar_cleanup),
  4742. STAGE_CREATE(MLX5_IB_STAGE_BFREG,
  4743. mlx5_ib_stage_bfrag_init,
  4744. mlx5_ib_stage_bfrag_cleanup),
  4745. STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
  4746. NULL,
  4747. mlx5_ib_stage_pre_ib_reg_umr_cleanup),
  4748. STAGE_CREATE(MLX5_IB_STAGE_SPECS,
  4749. mlx5_ib_stage_populate_specs,
  4750. mlx5_ib_stage_depopulate_specs),
  4751. STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
  4752. mlx5_ib_stage_ib_reg_init,
  4753. mlx5_ib_stage_ib_reg_cleanup),
  4754. STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
  4755. mlx5_ib_stage_post_ib_reg_umr_init,
  4756. NULL),
  4757. STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
  4758. mlx5_ib_stage_class_attr_init,
  4759. NULL),
  4760. STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
  4761. mlx5_ib_stage_rep_reg_init,
  4762. mlx5_ib_stage_rep_reg_cleanup),
  4763. };
  4764. static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
  4765. {
  4766. struct mlx5_ib_multiport_info *mpi;
  4767. struct mlx5_ib_dev *dev;
  4768. bool bound = false;
  4769. int err;
  4770. mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
  4771. if (!mpi)
  4772. return NULL;
  4773. mpi->mdev = mdev;
  4774. err = mlx5_query_nic_vport_system_image_guid(mdev,
  4775. &mpi->sys_image_guid);
  4776. if (err) {
  4777. kfree(mpi);
  4778. return NULL;
  4779. }
  4780. mutex_lock(&mlx5_ib_multiport_mutex);
  4781. list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
  4782. if (dev->sys_image_guid == mpi->sys_image_guid)
  4783. bound = mlx5_ib_bind_slave_port(dev, mpi);
  4784. if (bound) {
  4785. rdma_roce_rescan_device(&dev->ib_dev);
  4786. break;
  4787. }
  4788. }
  4789. if (!bound) {
  4790. list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
  4791. dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
  4792. } else {
  4793. mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
  4794. }
  4795. mutex_unlock(&mlx5_ib_multiport_mutex);
  4796. return mpi;
  4797. }
  4798. static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
  4799. {
  4800. enum rdma_link_layer ll;
  4801. struct mlx5_ib_dev *dev;
  4802. int port_type_cap;
  4803. printk_once(KERN_INFO "%s", mlx5_version);
  4804. port_type_cap = MLX5_CAP_GEN(mdev, port_type);
  4805. ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  4806. if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
  4807. u8 port_num = mlx5_core_native_port_num(mdev) - 1;
  4808. return mlx5_ib_add_slave_port(mdev, port_num);
  4809. }
  4810. dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
  4811. if (!dev)
  4812. return NULL;
  4813. dev->mdev = mdev;
  4814. dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
  4815. MLX5_CAP_GEN(mdev, num_vhca_ports));
  4816. if (MLX5_VPORT_MANAGER(mdev) &&
  4817. mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
  4818. dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
  4819. return __mlx5_ib_add(dev, &nic_rep_profile);
  4820. }
  4821. return __mlx5_ib_add(dev, &pf_profile);
  4822. }
  4823. static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
  4824. {
  4825. struct mlx5_ib_multiport_info *mpi;
  4826. struct mlx5_ib_dev *dev;
  4827. if (mlx5_core_is_mp_slave(mdev)) {
  4828. mpi = context;
  4829. mutex_lock(&mlx5_ib_multiport_mutex);
  4830. if (mpi->ibdev)
  4831. mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
  4832. list_del(&mpi->list);
  4833. mutex_unlock(&mlx5_ib_multiport_mutex);
  4834. return;
  4835. }
  4836. dev = context;
  4837. __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
  4838. }
  4839. static struct mlx5_interface mlx5_ib_interface = {
  4840. .add = mlx5_ib_add,
  4841. .remove = mlx5_ib_remove,
  4842. .event = mlx5_ib_event,
  4843. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  4844. .pfault = mlx5_ib_pfault,
  4845. #endif
  4846. .protocol = MLX5_INTERFACE_PROTOCOL_IB,
  4847. };
  4848. unsigned long mlx5_ib_get_xlt_emergency_page(void)
  4849. {
  4850. mutex_lock(&xlt_emergency_page_mutex);
  4851. return xlt_emergency_page;
  4852. }
  4853. void mlx5_ib_put_xlt_emergency_page(void)
  4854. {
  4855. mutex_unlock(&xlt_emergency_page_mutex);
  4856. }
  4857. static int __init mlx5_ib_init(void)
  4858. {
  4859. int err;
  4860. xlt_emergency_page = __get_free_page(GFP_KERNEL);
  4861. if (!xlt_emergency_page)
  4862. return -ENOMEM;
  4863. mutex_init(&xlt_emergency_page_mutex);
  4864. mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
  4865. if (!mlx5_ib_event_wq) {
  4866. free_page(xlt_emergency_page);
  4867. return -ENOMEM;
  4868. }
  4869. mlx5_ib_odp_init();
  4870. err = mlx5_register_interface(&mlx5_ib_interface);
  4871. return err;
  4872. }
  4873. static void __exit mlx5_ib_cleanup(void)
  4874. {
  4875. mlx5_unregister_interface(&mlx5_ib_interface);
  4876. destroy_workqueue(mlx5_ib_event_wq);
  4877. mutex_destroy(&xlt_emergency_page_mutex);
  4878. free_page(xlt_emergency_page);
  4879. }
  4880. module_init(mlx5_ib_init);
  4881. module_exit(mlx5_ib_cleanup);