i40iw.h 16 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #ifndef I40IW_IW_H
  35. #define I40IW_IW_H
  36. #include <linux/netdevice.h>
  37. #include <linux/inetdevice.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/kernel.h>
  40. #include <linux/delay.h>
  41. #include <linux/pci.h>
  42. #include <linux/dma-mapping.h>
  43. #include <linux/workqueue.h>
  44. #include <linux/slab.h>
  45. #include <linux/io.h>
  46. #include <linux/crc32c.h>
  47. #include <rdma/ib_smi.h>
  48. #include <rdma/ib_verbs.h>
  49. #include <rdma/ib_pack.h>
  50. #include <rdma/rdma_cm.h>
  51. #include <rdma/iw_cm.h>
  52. #include <crypto/hash.h>
  53. #include "i40iw_status.h"
  54. #include "i40iw_osdep.h"
  55. #include "i40iw_d.h"
  56. #include "i40iw_hmc.h"
  57. #include <i40e_client.h>
  58. #include "i40iw_type.h"
  59. #include "i40iw_p.h"
  60. #include <rdma/i40iw-abi.h>
  61. #include "i40iw_pble.h"
  62. #include "i40iw_verbs.h"
  63. #include "i40iw_cm.h"
  64. #include "i40iw_user.h"
  65. #include "i40iw_puda.h"
  66. #define I40IW_FW_VERSION 2
  67. #define I40IW_HW_VERSION 2
  68. #define I40IW_ARP_ADD 1
  69. #define I40IW_ARP_DELETE 2
  70. #define I40IW_ARP_RESOLVE 3
  71. #define I40IW_MACIP_ADD 1
  72. #define I40IW_MACIP_DELETE 2
  73. #define IW_CCQ_SIZE (I40IW_CQP_SW_SQSIZE_2048 + 1)
  74. #define IW_CEQ_SIZE 2048
  75. #define IW_AEQ_SIZE 2048
  76. #define RX_BUF_SIZE (1536 + 8)
  77. #define IW_REG0_SIZE (4 * 1024)
  78. #define IW_TX_TIMEOUT (6 * HZ)
  79. #define IW_FIRST_QPN 1
  80. #define IW_SW_CONTEXT_ALIGN 1024
  81. #define MAX_DPC_ITERATIONS 128
  82. #define I40IW_EVENT_TIMEOUT 100000
  83. #define I40IW_VCHNL_EVENT_TIMEOUT 100000
  84. #define I40IW_NO_VLAN 0xffff
  85. #define I40IW_NO_QSET 0xffff
  86. /* access to mcast filter list */
  87. #define IW_ADD_MCAST false
  88. #define IW_DEL_MCAST true
  89. #define I40IW_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
  90. #define I40IW_DRV_OPT_DISABLE_MPA_CRC 0x00000002
  91. #define I40IW_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
  92. #define I40IW_DRV_OPT_DISABLE_INTF 0x00000008
  93. #define I40IW_DRV_OPT_ENABLE_MSI 0x00000010
  94. #define I40IW_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
  95. #define I40IW_DRV_OPT_NO_INLINE_DATA 0x00000080
  96. #define I40IW_DRV_OPT_DISABLE_INT_MOD 0x00000100
  97. #define I40IW_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
  98. #define I40IW_DRV_OPT_ENABLE_PAU 0x00000400
  99. #define I40IW_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800
  100. #define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types)
  101. #define IW_CFG_FPM_QP_COUNT 32768
  102. #define I40IW_MAX_PAGES_PER_FMR 512
  103. #define I40IW_MIN_PAGES_PER_FMR 1
  104. #define I40IW_CQP_COMPL_RQ_WQE_FLUSHED 2
  105. #define I40IW_CQP_COMPL_SQ_WQE_FLUSHED 3
  106. #define I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED 4
  107. struct i40iw_cqp_compl_info {
  108. u32 op_ret_val;
  109. u16 maj_err_code;
  110. u16 min_err_code;
  111. bool error;
  112. u8 op_code;
  113. };
  114. #define i40iw_pr_err(fmt, args ...) pr_err("%s: "fmt, __func__, ## args)
  115. #define i40iw_pr_info(fmt, args ...) pr_info("%s: " fmt, __func__, ## args)
  116. #define i40iw_pr_warn(fmt, args ...) pr_warn("%s: " fmt, __func__, ## args)
  117. struct i40iw_cqp_request {
  118. struct cqp_commands_info info;
  119. wait_queue_head_t waitq;
  120. struct list_head list;
  121. atomic_t refcount;
  122. void (*callback_fcn)(struct i40iw_cqp_request*, u32);
  123. void *param;
  124. struct i40iw_cqp_compl_info compl_info;
  125. bool waiting;
  126. bool request_done;
  127. bool dynamic;
  128. };
  129. struct i40iw_cqp {
  130. struct i40iw_sc_cqp sc_cqp;
  131. spinlock_t req_lock; /*cqp request list */
  132. wait_queue_head_t waitq;
  133. struct i40iw_dma_mem sq;
  134. struct i40iw_dma_mem host_ctx;
  135. u64 *scratch_array;
  136. struct i40iw_cqp_request *cqp_requests;
  137. struct list_head cqp_avail_reqs;
  138. struct list_head cqp_pending_reqs;
  139. };
  140. struct i40iw_device;
  141. struct i40iw_ccq {
  142. struct i40iw_sc_cq sc_cq;
  143. spinlock_t lock; /* ccq control */
  144. wait_queue_head_t waitq;
  145. struct i40iw_dma_mem mem_cq;
  146. struct i40iw_dma_mem shadow_area;
  147. };
  148. struct i40iw_ceq {
  149. struct i40iw_sc_ceq sc_ceq;
  150. struct i40iw_dma_mem mem;
  151. u32 irq;
  152. u32 msix_idx;
  153. struct i40iw_device *iwdev;
  154. struct tasklet_struct dpc_tasklet;
  155. };
  156. struct i40iw_aeq {
  157. struct i40iw_sc_aeq sc_aeq;
  158. struct i40iw_dma_mem mem;
  159. };
  160. struct i40iw_arp_entry {
  161. u32 ip_addr[4];
  162. u8 mac_addr[ETH_ALEN];
  163. };
  164. enum init_completion_state {
  165. INVALID_STATE = 0,
  166. INITIAL_STATE,
  167. CQP_CREATED,
  168. HMC_OBJS_CREATED,
  169. PBLE_CHUNK_MEM,
  170. CCQ_CREATED,
  171. AEQ_CREATED,
  172. CEQ_CREATED,
  173. ILQ_CREATED,
  174. IEQ_CREATED,
  175. IP_ADDR_REGISTERED,
  176. RDMA_DEV_REGISTERED
  177. };
  178. struct i40iw_msix_vector {
  179. u32 idx;
  180. u32 irq;
  181. u32 cpu_affinity;
  182. u32 ceq_id;
  183. };
  184. struct l2params_work {
  185. struct work_struct work;
  186. struct i40iw_device *iwdev;
  187. struct i40iw_l2params l2params;
  188. };
  189. #define I40IW_MSIX_TABLE_SIZE 65
  190. struct virtchnl_work {
  191. struct work_struct work;
  192. union {
  193. struct i40iw_cqp_request *cqp_request;
  194. struct i40iw_virtchnl_work_info work_info;
  195. };
  196. };
  197. struct i40e_qvlist_info;
  198. struct i40iw_device {
  199. struct i40iw_ib_device *iwibdev;
  200. struct net_device *netdev;
  201. wait_queue_head_t vchnl_waitq;
  202. struct i40iw_sc_dev sc_dev;
  203. struct i40iw_sc_vsi vsi;
  204. struct i40iw_handler *hdl;
  205. struct i40e_info *ldev;
  206. struct i40e_client *client;
  207. struct i40iw_hw hw;
  208. struct i40iw_cm_core cm_core;
  209. u8 *mem_resources;
  210. unsigned long *allocated_qps;
  211. unsigned long *allocated_cqs;
  212. unsigned long *allocated_mrs;
  213. unsigned long *allocated_pds;
  214. unsigned long *allocated_arps;
  215. struct i40iw_qp **qp_table;
  216. bool msix_shared;
  217. u32 msix_count;
  218. struct i40iw_msix_vector *iw_msixtbl;
  219. struct i40e_qvlist_info *iw_qvlist;
  220. struct i40iw_hmc_pble_rsrc *pble_rsrc;
  221. struct i40iw_arp_entry *arp_table;
  222. struct i40iw_cqp cqp;
  223. struct i40iw_ccq ccq;
  224. u32 ceqs_count;
  225. struct i40iw_ceq *ceqlist;
  226. struct i40iw_aeq aeq;
  227. u32 arp_table_size;
  228. u32 next_arp_index;
  229. spinlock_t resource_lock; /* hw resource access */
  230. spinlock_t qptable_lock;
  231. u32 vendor_id;
  232. u32 vendor_part_id;
  233. u32 of_device_registered;
  234. u32 device_cap_flags;
  235. unsigned long db_start;
  236. u8 resource_profile;
  237. u8 max_rdma_vfs;
  238. u8 max_enabled_vfs;
  239. u8 max_sge;
  240. u8 iw_status;
  241. u8 send_term_ok;
  242. bool push_mode; /* Initialized from parameter passed to driver */
  243. /* x710 specific */
  244. struct mutex pbl_mutex;
  245. struct tasklet_struct dpc_tasklet;
  246. struct workqueue_struct *virtchnl_wq;
  247. struct virtchnl_work virtchnl_w[I40IW_MAX_PE_ENABLED_VF_COUNT];
  248. struct i40iw_dma_mem obj_mem;
  249. struct i40iw_dma_mem obj_next;
  250. u8 *hmc_info_mem;
  251. u32 sd_type;
  252. struct workqueue_struct *param_wq;
  253. atomic_t params_busy;
  254. enum init_completion_state init_state;
  255. u16 mac_ip_table_idx;
  256. atomic_t vchnl_msgs;
  257. u32 max_mr;
  258. u32 max_qp;
  259. u32 max_cq;
  260. u32 max_pd;
  261. u32 next_qp;
  262. u32 next_cq;
  263. u32 next_pd;
  264. u32 max_mr_size;
  265. u32 max_qp_wr;
  266. u32 max_cqe;
  267. u32 mr_stagmask;
  268. u32 mpa_version;
  269. bool dcb;
  270. bool closing;
  271. bool reset;
  272. u32 used_pds;
  273. u32 used_cqs;
  274. u32 used_mrs;
  275. u32 used_qps;
  276. wait_queue_head_t close_wq;
  277. atomic64_t use_count;
  278. };
  279. struct i40iw_ib_device {
  280. struct ib_device ibdev;
  281. struct i40iw_device *iwdev;
  282. };
  283. struct i40iw_handler {
  284. struct list_head list;
  285. struct i40e_client *client;
  286. struct i40iw_device device;
  287. struct i40e_info ldev;
  288. };
  289. /**
  290. * to_iwdev - get device
  291. * @ibdev: ib device
  292. **/
  293. static inline struct i40iw_device *to_iwdev(struct ib_device *ibdev)
  294. {
  295. return container_of(ibdev, struct i40iw_ib_device, ibdev)->iwdev;
  296. }
  297. /**
  298. * to_ucontext - get user context
  299. * @ibucontext: ib user context
  300. **/
  301. static inline struct i40iw_ucontext *to_ucontext(struct ib_ucontext *ibucontext)
  302. {
  303. return container_of(ibucontext, struct i40iw_ucontext, ibucontext);
  304. }
  305. /**
  306. * to_iwpd - get protection domain
  307. * @ibpd: ib pd
  308. **/
  309. static inline struct i40iw_pd *to_iwpd(struct ib_pd *ibpd)
  310. {
  311. return container_of(ibpd, struct i40iw_pd, ibpd);
  312. }
  313. /**
  314. * to_iwmr - get device memory region
  315. * @ibdev: ib memory region
  316. **/
  317. static inline struct i40iw_mr *to_iwmr(struct ib_mr *ibmr)
  318. {
  319. return container_of(ibmr, struct i40iw_mr, ibmr);
  320. }
  321. /**
  322. * to_iwmr_from_ibfmr - get device memory region
  323. * @ibfmr: ib fmr
  324. **/
  325. static inline struct i40iw_mr *to_iwmr_from_ibfmr(struct ib_fmr *ibfmr)
  326. {
  327. return container_of(ibfmr, struct i40iw_mr, ibfmr);
  328. }
  329. /**
  330. * to_iwmw - get device memory window
  331. * @ibmw: ib memory window
  332. **/
  333. static inline struct i40iw_mr *to_iwmw(struct ib_mw *ibmw)
  334. {
  335. return container_of(ibmw, struct i40iw_mr, ibmw);
  336. }
  337. /**
  338. * to_iwcq - get completion queue
  339. * @ibcq: ib cqdevice
  340. **/
  341. static inline struct i40iw_cq *to_iwcq(struct ib_cq *ibcq)
  342. {
  343. return container_of(ibcq, struct i40iw_cq, ibcq);
  344. }
  345. /**
  346. * to_iwqp - get device qp
  347. * @ibqp: ib qp
  348. **/
  349. static inline struct i40iw_qp *to_iwqp(struct ib_qp *ibqp)
  350. {
  351. return container_of(ibqp, struct i40iw_qp, ibqp);
  352. }
  353. /* i40iw.c */
  354. void i40iw_add_ref(struct ib_qp *);
  355. void i40iw_rem_ref(struct ib_qp *);
  356. struct ib_qp *i40iw_get_qp(struct ib_device *, int);
  357. void i40iw_flush_wqes(struct i40iw_device *iwdev,
  358. struct i40iw_qp *qp);
  359. void i40iw_manage_arp_cache(struct i40iw_device *iwdev,
  360. unsigned char *mac_addr,
  361. u32 *ip_addr,
  362. bool ipv4,
  363. u32 action);
  364. int i40iw_manage_apbvt(struct i40iw_device *iwdev,
  365. u16 accel_local_port,
  366. bool add_port);
  367. struct i40iw_cqp_request *i40iw_get_cqp_request(struct i40iw_cqp *cqp, bool wait);
  368. void i40iw_free_cqp_request(struct i40iw_cqp *cqp, struct i40iw_cqp_request *cqp_request);
  369. void i40iw_put_cqp_request(struct i40iw_cqp *cqp, struct i40iw_cqp_request *cqp_request);
  370. /**
  371. * i40iw_alloc_resource - allocate a resource
  372. * @iwdev: device pointer
  373. * @resource_array: resource bit array:
  374. * @max_resources: maximum resource number
  375. * @req_resources_num: Allocated resource number
  376. * @next: next free id
  377. **/
  378. static inline int i40iw_alloc_resource(struct i40iw_device *iwdev,
  379. unsigned long *resource_array,
  380. u32 max_resources,
  381. u32 *req_resource_num,
  382. u32 *next)
  383. {
  384. u32 resource_num;
  385. unsigned long flags;
  386. spin_lock_irqsave(&iwdev->resource_lock, flags);
  387. resource_num = find_next_zero_bit(resource_array, max_resources, *next);
  388. if (resource_num >= max_resources) {
  389. resource_num = find_first_zero_bit(resource_array, max_resources);
  390. if (resource_num >= max_resources) {
  391. spin_unlock_irqrestore(&iwdev->resource_lock, flags);
  392. return -EOVERFLOW;
  393. }
  394. }
  395. set_bit(resource_num, resource_array);
  396. *next = resource_num + 1;
  397. if (*next == max_resources)
  398. *next = 0;
  399. *req_resource_num = resource_num;
  400. spin_unlock_irqrestore(&iwdev->resource_lock, flags);
  401. return 0;
  402. }
  403. /**
  404. * i40iw_is_resource_allocated - detrmine if resource is
  405. * allocated
  406. * @iwdev: device pointer
  407. * @resource_array: resource array for the resource_num
  408. * @resource_num: resource number to check
  409. **/
  410. static inline bool i40iw_is_resource_allocated(struct i40iw_device *iwdev,
  411. unsigned long *resource_array,
  412. u32 resource_num)
  413. {
  414. bool bit_is_set;
  415. unsigned long flags;
  416. spin_lock_irqsave(&iwdev->resource_lock, flags);
  417. bit_is_set = test_bit(resource_num, resource_array);
  418. spin_unlock_irqrestore(&iwdev->resource_lock, flags);
  419. return bit_is_set;
  420. }
  421. /**
  422. * i40iw_free_resource - free a resource
  423. * @iwdev: device pointer
  424. * @resource_array: resource array for the resource_num
  425. * @resource_num: resource number to free
  426. **/
  427. static inline void i40iw_free_resource(struct i40iw_device *iwdev,
  428. unsigned long *resource_array,
  429. u32 resource_num)
  430. {
  431. unsigned long flags;
  432. spin_lock_irqsave(&iwdev->resource_lock, flags);
  433. clear_bit(resource_num, resource_array);
  434. spin_unlock_irqrestore(&iwdev->resource_lock, flags);
  435. }
  436. /**
  437. * to_iwhdl - Get the handler from the device pointer
  438. * @iwdev: device pointer
  439. **/
  440. static inline struct i40iw_handler *to_iwhdl(struct i40iw_device *iw_dev)
  441. {
  442. return container_of(iw_dev, struct i40iw_handler, device);
  443. }
  444. struct i40iw_handler *i40iw_find_netdev(struct net_device *netdev);
  445. /**
  446. * iw_init_resources -
  447. */
  448. u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev);
  449. int i40iw_register_rdma_device(struct i40iw_device *iwdev);
  450. void i40iw_port_ibevent(struct i40iw_device *iwdev);
  451. void i40iw_cm_disconn(struct i40iw_qp *iwqp);
  452. void i40iw_cm_disconn_worker(void *);
  453. int mini_cm_recv_pkt(struct i40iw_cm_core *, struct i40iw_device *,
  454. struct sk_buff *);
  455. enum i40iw_status_code i40iw_handle_cqp_op(struct i40iw_device *iwdev,
  456. struct i40iw_cqp_request *cqp_request);
  457. enum i40iw_status_code i40iw_add_mac_addr(struct i40iw_device *iwdev,
  458. u8 *mac_addr, u8 *mac_index);
  459. int i40iw_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
  460. void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq);
  461. void i40iw_cleanup_pending_cqp_op(struct i40iw_device *iwdev);
  462. void i40iw_rem_pdusecount(struct i40iw_pd *iwpd, struct i40iw_device *iwdev);
  463. void i40iw_add_pdusecount(struct i40iw_pd *iwpd);
  464. void i40iw_rem_devusecount(struct i40iw_device *iwdev);
  465. void i40iw_add_devusecount(struct i40iw_device *iwdev);
  466. void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
  467. struct i40iw_modify_qp_info *info, bool wait);
  468. void i40iw_qp_suspend_resume(struct i40iw_sc_dev *dev,
  469. struct i40iw_sc_qp *qp,
  470. bool suspend);
  471. enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
  472. struct i40iw_cm_info *cminfo,
  473. enum i40iw_quad_entry_type etype,
  474. enum i40iw_quad_hash_manage_type mtype,
  475. void *cmnode,
  476. bool wait);
  477. void i40iw_receive_ilq(struct i40iw_sc_vsi *vsi, struct i40iw_puda_buf *rbuf);
  478. void i40iw_free_sqbuf(struct i40iw_sc_vsi *vsi, void *bufp);
  479. void i40iw_free_qp_resources(struct i40iw_device *iwdev,
  480. struct i40iw_qp *iwqp,
  481. u32 qp_num);
  482. enum i40iw_status_code i40iw_obj_aligned_mem(struct i40iw_device *iwdev,
  483. struct i40iw_dma_mem *memptr,
  484. u32 size, u32 mask);
  485. void i40iw_request_reset(struct i40iw_device *iwdev);
  486. void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev);
  487. void i40iw_setup_cm_core(struct i40iw_device *iwdev);
  488. void i40iw_cleanup_cm_core(struct i40iw_cm_core *cm_core);
  489. void i40iw_process_ceq(struct i40iw_device *, struct i40iw_ceq *iwceq);
  490. void i40iw_process_aeq(struct i40iw_device *);
  491. void i40iw_next_iw_state(struct i40iw_qp *iwqp,
  492. u8 state, u8 del_hash,
  493. u8 term, u8 term_len);
  494. int i40iw_send_syn(struct i40iw_cm_node *cm_node, u32 sendack);
  495. int i40iw_send_reset(struct i40iw_cm_node *cm_node);
  496. struct i40iw_cm_node *i40iw_find_node(struct i40iw_cm_core *cm_core,
  497. u16 rem_port,
  498. u32 *rem_addr,
  499. u16 loc_port,
  500. u32 *loc_addr,
  501. bool add_refcnt,
  502. bool accelerated_list);
  503. enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
  504. struct i40iw_sc_qp *qp,
  505. struct i40iw_qp_flush_info *info,
  506. bool wait);
  507. void i40iw_gen_ae(struct i40iw_device *iwdev,
  508. struct i40iw_sc_qp *qp,
  509. struct i40iw_gen_ae_info *info,
  510. bool wait);
  511. void i40iw_copy_ip_ntohl(u32 *dst, __be32 *src);
  512. struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *ib_pd,
  513. u64 addr,
  514. u64 size,
  515. int acc,
  516. u64 *iova_start);
  517. int i40iw_inetaddr_event(struct notifier_block *notifier,
  518. unsigned long event,
  519. void *ptr);
  520. int i40iw_inet6addr_event(struct notifier_block *notifier,
  521. unsigned long event,
  522. void *ptr);
  523. int i40iw_net_event(struct notifier_block *notifier,
  524. unsigned long event,
  525. void *ptr);
  526. int i40iw_netdevice_event(struct notifier_block *notifier,
  527. unsigned long event,
  528. void *ptr);
  529. #endif