hns_roce_qp.c 28 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/platform_device.h>
  34. #include <rdma/ib_addr.h>
  35. #include <rdma/ib_umem.h>
  36. #include "hns_roce_common.h"
  37. #include "hns_roce_device.h"
  38. #include "hns_roce_hem.h"
  39. #include <rdma/hns-abi.h>
  40. #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS)
  41. void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
  42. {
  43. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  44. struct device *dev = hr_dev->dev;
  45. struct hns_roce_qp *qp;
  46. spin_lock(&qp_table->lock);
  47. qp = __hns_roce_qp_lookup(hr_dev, qpn);
  48. if (qp)
  49. atomic_inc(&qp->refcount);
  50. spin_unlock(&qp_table->lock);
  51. if (!qp) {
  52. dev_warn(dev, "Async event for bogus QP %08x\n", qpn);
  53. return;
  54. }
  55. qp->event(qp, (enum hns_roce_event)event_type);
  56. if (atomic_dec_and_test(&qp->refcount))
  57. complete(&qp->free);
  58. }
  59. EXPORT_SYMBOL_GPL(hns_roce_qp_event);
  60. static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
  61. enum hns_roce_event type)
  62. {
  63. struct ib_event event;
  64. struct ib_qp *ibqp = &hr_qp->ibqp;
  65. if (ibqp->event_handler) {
  66. event.device = ibqp->device;
  67. event.element.qp = ibqp;
  68. switch (type) {
  69. case HNS_ROCE_EVENT_TYPE_PATH_MIG:
  70. event.event = IB_EVENT_PATH_MIG;
  71. break;
  72. case HNS_ROCE_EVENT_TYPE_COMM_EST:
  73. event.event = IB_EVENT_COMM_EST;
  74. break;
  75. case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
  76. event.event = IB_EVENT_SQ_DRAINED;
  77. break;
  78. case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
  79. event.event = IB_EVENT_QP_LAST_WQE_REACHED;
  80. break;
  81. case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
  82. event.event = IB_EVENT_QP_FATAL;
  83. break;
  84. case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
  85. event.event = IB_EVENT_PATH_MIG_ERR;
  86. break;
  87. case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
  88. event.event = IB_EVENT_QP_REQ_ERR;
  89. break;
  90. case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
  91. event.event = IB_EVENT_QP_ACCESS_ERR;
  92. break;
  93. default:
  94. dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
  95. type, hr_qp->qpn);
  96. return;
  97. }
  98. ibqp->event_handler(&event, ibqp->qp_context);
  99. }
  100. }
  101. static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt,
  102. int align, unsigned long *base)
  103. {
  104. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  105. return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align, base);
  106. }
  107. enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
  108. {
  109. switch (state) {
  110. case IB_QPS_RESET:
  111. return HNS_ROCE_QP_STATE_RST;
  112. case IB_QPS_INIT:
  113. return HNS_ROCE_QP_STATE_INIT;
  114. case IB_QPS_RTR:
  115. return HNS_ROCE_QP_STATE_RTR;
  116. case IB_QPS_RTS:
  117. return HNS_ROCE_QP_STATE_RTS;
  118. case IB_QPS_SQD:
  119. return HNS_ROCE_QP_STATE_SQD;
  120. case IB_QPS_ERR:
  121. return HNS_ROCE_QP_STATE_ERR;
  122. default:
  123. return HNS_ROCE_QP_NUM_STATE;
  124. }
  125. }
  126. EXPORT_SYMBOL_GPL(to_hns_roce_state);
  127. static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
  128. struct hns_roce_qp *hr_qp)
  129. {
  130. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  131. int ret;
  132. if (!qpn)
  133. return -EINVAL;
  134. hr_qp->qpn = qpn;
  135. spin_lock_irq(&qp_table->lock);
  136. ret = radix_tree_insert(&hr_dev->qp_table_tree,
  137. hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
  138. spin_unlock_irq(&qp_table->lock);
  139. if (ret) {
  140. dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n");
  141. goto err_put_irrl;
  142. }
  143. atomic_set(&hr_qp->refcount, 1);
  144. init_completion(&hr_qp->free);
  145. return 0;
  146. err_put_irrl:
  147. return ret;
  148. }
  149. static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
  150. struct hns_roce_qp *hr_qp)
  151. {
  152. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  153. struct device *dev = hr_dev->dev;
  154. int ret;
  155. if (!qpn)
  156. return -EINVAL;
  157. hr_qp->qpn = qpn;
  158. /* Alloc memory for QPC */
  159. ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  160. if (ret) {
  161. dev_err(dev, "QPC table get failed\n");
  162. goto err_out;
  163. }
  164. /* Alloc memory for IRRL */
  165. ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  166. if (ret) {
  167. dev_err(dev, "IRRL table get failed\n");
  168. goto err_put_qp;
  169. }
  170. if (hr_dev->caps.trrl_entry_sz) {
  171. /* Alloc memory for TRRL */
  172. ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
  173. hr_qp->qpn);
  174. if (ret) {
  175. dev_err(dev, "TRRL table get failed\n");
  176. goto err_put_irrl;
  177. }
  178. }
  179. spin_lock_irq(&qp_table->lock);
  180. ret = radix_tree_insert(&hr_dev->qp_table_tree,
  181. hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
  182. spin_unlock_irq(&qp_table->lock);
  183. if (ret) {
  184. dev_err(dev, "QPC radix_tree_insert failed\n");
  185. goto err_put_trrl;
  186. }
  187. atomic_set(&hr_qp->refcount, 1);
  188. init_completion(&hr_qp->free);
  189. return 0;
  190. err_put_trrl:
  191. if (hr_dev->caps.trrl_entry_sz)
  192. hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
  193. err_put_irrl:
  194. hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  195. err_put_qp:
  196. hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  197. err_out:
  198. return ret;
  199. }
  200. void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  201. {
  202. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  203. unsigned long flags;
  204. spin_lock_irqsave(&qp_table->lock, flags);
  205. radix_tree_delete(&hr_dev->qp_table_tree,
  206. hr_qp->qpn & (hr_dev->caps.num_qps - 1));
  207. spin_unlock_irqrestore(&qp_table->lock, flags);
  208. }
  209. EXPORT_SYMBOL_GPL(hns_roce_qp_remove);
  210. void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  211. {
  212. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  213. if (atomic_dec_and_test(&hr_qp->refcount))
  214. complete(&hr_qp->free);
  215. wait_for_completion(&hr_qp->free);
  216. if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) {
  217. if (hr_dev->caps.trrl_entry_sz)
  218. hns_roce_table_put(hr_dev, &qp_table->trrl_table,
  219. hr_qp->qpn);
  220. hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  221. hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  222. }
  223. }
  224. EXPORT_SYMBOL_GPL(hns_roce_qp_free);
  225. void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
  226. int cnt)
  227. {
  228. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  229. if (base_qpn < SQP_NUM)
  230. return;
  231. hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR);
  232. }
  233. EXPORT_SYMBOL_GPL(hns_roce_release_range_qp);
  234. static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
  235. struct ib_qp_cap *cap, int is_user, int has_srq,
  236. struct hns_roce_qp *hr_qp)
  237. {
  238. struct device *dev = hr_dev->dev;
  239. u32 max_cnt;
  240. /* Check the validity of QP support capacity */
  241. if (cap->max_recv_wr > hr_dev->caps.max_wqes ||
  242. cap->max_recv_sge > hr_dev->caps.max_rq_sg) {
  243. dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n",
  244. cap->max_recv_wr, cap->max_recv_sge);
  245. return -EINVAL;
  246. }
  247. /* If srq exit, set zero for relative number of rq */
  248. if (has_srq) {
  249. if (cap->max_recv_wr) {
  250. dev_dbg(dev, "srq no need config max_recv_wr\n");
  251. return -EINVAL;
  252. }
  253. hr_qp->rq.wqe_cnt = hr_qp->rq.max_gs = 0;
  254. } else {
  255. if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) {
  256. dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n");
  257. return -EINVAL;
  258. }
  259. if (hr_dev->caps.min_wqes)
  260. max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes);
  261. else
  262. max_cnt = cap->max_recv_wr;
  263. hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
  264. if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
  265. dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n");
  266. return -EINVAL;
  267. }
  268. max_cnt = max(1U, cap->max_recv_sge);
  269. hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
  270. if (hr_dev->caps.max_rq_sg <= 2)
  271. hr_qp->rq.wqe_shift =
  272. ilog2(hr_dev->caps.max_rq_desc_sz);
  273. else
  274. hr_qp->rq.wqe_shift =
  275. ilog2(hr_dev->caps.max_rq_desc_sz
  276. * hr_qp->rq.max_gs);
  277. }
  278. cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt;
  279. cap->max_recv_sge = hr_qp->rq.max_gs;
  280. return 0;
  281. }
  282. static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
  283. struct ib_qp_cap *cap,
  284. struct hns_roce_qp *hr_qp,
  285. struct hns_roce_ib_create_qp *ucmd)
  286. {
  287. u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
  288. u8 max_sq_stride = ilog2(roundup_sq_stride);
  289. u32 page_size;
  290. u32 max_cnt;
  291. /* Sanity check SQ size before proceeding */
  292. if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
  293. ucmd->log_sq_stride > max_sq_stride ||
  294. ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
  295. dev_err(hr_dev->dev, "check SQ size error!\n");
  296. return -EINVAL;
  297. }
  298. if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
  299. dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n",
  300. cap->max_send_sge);
  301. return -EINVAL;
  302. }
  303. hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
  304. hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
  305. max_cnt = max(1U, cap->max_send_sge);
  306. if (hr_dev->caps.max_sq_sg <= 2)
  307. hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
  308. else
  309. hr_qp->sq.max_gs = max_cnt;
  310. if (hr_qp->sq.max_gs > 2)
  311. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  312. (hr_qp->sq.max_gs - 2));
  313. hr_qp->sge.sge_shift = 4;
  314. /* Get buf size, SQ and RQ are aligned to page_szie */
  315. if (hr_dev->caps.max_sq_sg <= 2) {
  316. hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
  317. hr_qp->rq.wqe_shift), PAGE_SIZE) +
  318. HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  319. hr_qp->sq.wqe_shift), PAGE_SIZE);
  320. hr_qp->sq.offset = 0;
  321. hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  322. hr_qp->sq.wqe_shift), PAGE_SIZE);
  323. } else {
  324. page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
  325. hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
  326. hr_qp->rq.wqe_shift), page_size) +
  327. HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
  328. hr_qp->sge.sge_shift), page_size) +
  329. HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  330. hr_qp->sq.wqe_shift), page_size);
  331. hr_qp->sq.offset = 0;
  332. if (hr_qp->sge.sge_cnt) {
  333. hr_qp->sge.offset = HNS_ROCE_ALOGN_UP(
  334. (hr_qp->sq.wqe_cnt <<
  335. hr_qp->sq.wqe_shift),
  336. page_size);
  337. hr_qp->rq.offset = hr_qp->sge.offset +
  338. HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
  339. hr_qp->sge.sge_shift),
  340. page_size);
  341. } else {
  342. hr_qp->rq.offset = HNS_ROCE_ALOGN_UP(
  343. (hr_qp->sq.wqe_cnt <<
  344. hr_qp->sq.wqe_shift),
  345. page_size);
  346. }
  347. }
  348. return 0;
  349. }
  350. static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
  351. struct ib_qp_cap *cap,
  352. struct hns_roce_qp *hr_qp)
  353. {
  354. struct device *dev = hr_dev->dev;
  355. u32 page_size;
  356. u32 max_cnt;
  357. int size;
  358. if (cap->max_send_wr > hr_dev->caps.max_wqes ||
  359. cap->max_send_sge > hr_dev->caps.max_sq_sg ||
  360. cap->max_inline_data > hr_dev->caps.max_sq_inline) {
  361. dev_err(dev, "SQ WR or sge or inline data error!\n");
  362. return -EINVAL;
  363. }
  364. hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
  365. hr_qp->sq_max_wqes_per_wr = 1;
  366. hr_qp->sq_spare_wqes = 0;
  367. if (hr_dev->caps.min_wqes)
  368. max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes);
  369. else
  370. max_cnt = cap->max_send_wr;
  371. hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt);
  372. if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) {
  373. dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n");
  374. return -EINVAL;
  375. }
  376. /* Get data_seg numbers */
  377. max_cnt = max(1U, cap->max_send_sge);
  378. if (hr_dev->caps.max_sq_sg <= 2)
  379. hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
  380. else
  381. hr_qp->sq.max_gs = max_cnt;
  382. if (hr_qp->sq.max_gs > 2) {
  383. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  384. (hr_qp->sq.max_gs - 2));
  385. hr_qp->sge.sge_shift = 4;
  386. }
  387. /* ud sqwqe's sge use extend sge */
  388. if (hr_dev->caps.max_sq_sg > 2 && hr_qp->ibqp.qp_type == IB_QPT_GSI) {
  389. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  390. hr_qp->sq.max_gs);
  391. hr_qp->sge.sge_shift = 4;
  392. }
  393. /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */
  394. page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
  395. hr_qp->sq.offset = 0;
  396. size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift,
  397. page_size);
  398. if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) {
  399. hr_qp->sge.offset = size;
  400. size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt <<
  401. hr_qp->sge.sge_shift, page_size);
  402. }
  403. hr_qp->rq.offset = size;
  404. size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift),
  405. page_size);
  406. hr_qp->buff_size = size;
  407. /* Get wr and sge number which send */
  408. cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt;
  409. cap->max_send_sge = hr_qp->sq.max_gs;
  410. /* We don't support inline sends for kernel QPs (yet) */
  411. cap->max_inline_data = 0;
  412. return 0;
  413. }
  414. static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
  415. {
  416. if (attr->qp_type == IB_QPT_XRC_INI ||
  417. attr->qp_type == IB_QPT_XRC_TGT || attr->srq)
  418. return 0;
  419. return 1;
  420. }
  421. static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
  422. struct ib_pd *ib_pd,
  423. struct ib_qp_init_attr *init_attr,
  424. struct ib_udata *udata, unsigned long sqpn,
  425. struct hns_roce_qp *hr_qp)
  426. {
  427. struct device *dev = hr_dev->dev;
  428. struct hns_roce_ib_create_qp ucmd;
  429. struct hns_roce_ib_create_qp_resp resp = {};
  430. unsigned long qpn = 0;
  431. int ret = 0;
  432. u32 page_shift;
  433. u32 npages;
  434. int i;
  435. mutex_init(&hr_qp->mutex);
  436. spin_lock_init(&hr_qp->sq.lock);
  437. spin_lock_init(&hr_qp->rq.lock);
  438. hr_qp->state = IB_QPS_RESET;
  439. hr_qp->ibqp.qp_type = init_attr->qp_type;
  440. if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
  441. hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_ALL_WR);
  442. else
  443. hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_REQ_WR);
  444. ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, !!ib_pd->uobject,
  445. !!init_attr->srq, hr_qp);
  446. if (ret) {
  447. dev_err(dev, "hns_roce_set_rq_size failed\n");
  448. goto err_out;
  449. }
  450. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
  451. /* allocate recv inline buf */
  452. hr_qp->rq_inl_buf.wqe_list = kcalloc(hr_qp->rq.wqe_cnt,
  453. sizeof(struct hns_roce_rinl_wqe),
  454. GFP_KERNEL);
  455. if (!hr_qp->rq_inl_buf.wqe_list) {
  456. ret = -ENOMEM;
  457. goto err_out;
  458. }
  459. hr_qp->rq_inl_buf.wqe_cnt = hr_qp->rq.wqe_cnt;
  460. /* Firstly, allocate a list of sge space buffer */
  461. hr_qp->rq_inl_buf.wqe_list[0].sg_list =
  462. kcalloc(hr_qp->rq_inl_buf.wqe_cnt,
  463. init_attr->cap.max_recv_sge *
  464. sizeof(struct hns_roce_rinl_sge),
  465. GFP_KERNEL);
  466. if (!hr_qp->rq_inl_buf.wqe_list[0].sg_list) {
  467. ret = -ENOMEM;
  468. goto err_wqe_list;
  469. }
  470. for (i = 1; i < hr_qp->rq_inl_buf.wqe_cnt; i++)
  471. /* Secondly, reallocate the buffer */
  472. hr_qp->rq_inl_buf.wqe_list[i].sg_list =
  473. &hr_qp->rq_inl_buf.wqe_list[0].sg_list[i *
  474. init_attr->cap.max_recv_sge];
  475. }
  476. if (ib_pd->uobject) {
  477. if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
  478. dev_err(dev, "ib_copy_from_udata error for create qp\n");
  479. ret = -EFAULT;
  480. goto err_rq_sge_list;
  481. }
  482. ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp,
  483. &ucmd);
  484. if (ret) {
  485. dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n");
  486. goto err_rq_sge_list;
  487. }
  488. hr_qp->umem = ib_umem_get(ib_pd->uobject->context,
  489. ucmd.buf_addr, hr_qp->buff_size, 0,
  490. 0);
  491. if (IS_ERR(hr_qp->umem)) {
  492. dev_err(dev, "ib_umem_get error for create qp\n");
  493. ret = PTR_ERR(hr_qp->umem);
  494. goto err_rq_sge_list;
  495. }
  496. hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
  497. if (hr_dev->caps.mtt_buf_pg_sz) {
  498. npages = (ib_umem_page_count(hr_qp->umem) +
  499. (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) /
  500. (1 << hr_dev->caps.mtt_buf_pg_sz);
  501. page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
  502. ret = hns_roce_mtt_init(hr_dev, npages,
  503. page_shift,
  504. &hr_qp->mtt);
  505. } else {
  506. ret = hns_roce_mtt_init(hr_dev,
  507. ib_umem_page_count(hr_qp->umem),
  508. hr_qp->umem->page_shift,
  509. &hr_qp->mtt);
  510. }
  511. if (ret) {
  512. dev_err(dev, "hns_roce_mtt_init error for create qp\n");
  513. goto err_buf;
  514. }
  515. ret = hns_roce_ib_umem_write_mtt(hr_dev, &hr_qp->mtt,
  516. hr_qp->umem);
  517. if (ret) {
  518. dev_err(dev, "hns_roce_ib_umem_write_mtt error for create qp\n");
  519. goto err_mtt;
  520. }
  521. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  522. (udata->outlen >= sizeof(resp)) &&
  523. hns_roce_qp_has_rq(init_attr)) {
  524. ret = hns_roce_db_map_user(
  525. to_hr_ucontext(ib_pd->uobject->context),
  526. ucmd.db_addr, &hr_qp->rdb);
  527. if (ret) {
  528. dev_err(dev, "rq record doorbell map failed!\n");
  529. goto err_mtt;
  530. }
  531. }
  532. } else {
  533. if (init_attr->create_flags &
  534. IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
  535. dev_err(dev, "init_attr->create_flags error!\n");
  536. ret = -EINVAL;
  537. goto err_rq_sge_list;
  538. }
  539. if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) {
  540. dev_err(dev, "init_attr->create_flags error!\n");
  541. ret = -EINVAL;
  542. goto err_rq_sge_list;
  543. }
  544. /* Set SQ size */
  545. ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap,
  546. hr_qp);
  547. if (ret) {
  548. dev_err(dev, "hns_roce_set_kernel_sq_size error!\n");
  549. goto err_rq_sge_list;
  550. }
  551. /* QP doorbell register address */
  552. hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset +
  553. DB_REG_OFFSET * hr_dev->priv_uar.index;
  554. hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset +
  555. DB_REG_OFFSET * hr_dev->priv_uar.index;
  556. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  557. hns_roce_qp_has_rq(init_attr)) {
  558. ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
  559. if (ret) {
  560. dev_err(dev, "rq record doorbell alloc failed!\n");
  561. goto err_rq_sge_list;
  562. }
  563. *hr_qp->rdb.db_record = 0;
  564. }
  565. /* Allocate QP buf */
  566. page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
  567. if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size,
  568. (1 << page_shift) * 2,
  569. &hr_qp->hr_buf, page_shift)) {
  570. dev_err(dev, "hns_roce_buf_alloc error!\n");
  571. ret = -ENOMEM;
  572. goto err_db;
  573. }
  574. hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
  575. /* Write MTT */
  576. ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages,
  577. hr_qp->hr_buf.page_shift, &hr_qp->mtt);
  578. if (ret) {
  579. dev_err(dev, "hns_roce_mtt_init error for kernel create qp\n");
  580. goto err_buf;
  581. }
  582. ret = hns_roce_buf_write_mtt(hr_dev, &hr_qp->mtt,
  583. &hr_qp->hr_buf);
  584. if (ret) {
  585. dev_err(dev, "hns_roce_buf_write_mtt error for kernel create qp\n");
  586. goto err_mtt;
  587. }
  588. hr_qp->sq.wrid = kmalloc_array(hr_qp->sq.wqe_cnt, sizeof(u64),
  589. GFP_KERNEL);
  590. hr_qp->rq.wrid = kmalloc_array(hr_qp->rq.wqe_cnt, sizeof(u64),
  591. GFP_KERNEL);
  592. if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) {
  593. ret = -ENOMEM;
  594. goto err_wrid;
  595. }
  596. }
  597. if (sqpn) {
  598. qpn = sqpn;
  599. } else {
  600. /* Get QPN */
  601. ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn);
  602. if (ret) {
  603. dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n");
  604. goto err_wrid;
  605. }
  606. }
  607. if (init_attr->qp_type == IB_QPT_GSI &&
  608. hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
  609. /* In v1 engine, GSI QP context in RoCE engine's register */
  610. ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp);
  611. if (ret) {
  612. dev_err(dev, "hns_roce_qp_alloc failed!\n");
  613. goto err_qpn;
  614. }
  615. } else {
  616. ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp);
  617. if (ret) {
  618. dev_err(dev, "hns_roce_qp_alloc failed!\n");
  619. goto err_qpn;
  620. }
  621. }
  622. if (sqpn)
  623. hr_qp->doorbell_qpn = 1;
  624. else
  625. hr_qp->doorbell_qpn = cpu_to_le64(hr_qp->qpn);
  626. if (ib_pd->uobject && (udata->outlen >= sizeof(resp)) &&
  627. (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) {
  628. /* indicate kernel supports record db */
  629. resp.cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB;
  630. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  631. if (ret)
  632. goto err_qp;
  633. hr_qp->rdb_en = 1;
  634. }
  635. hr_qp->event = hns_roce_ib_qp_event;
  636. return 0;
  637. err_qp:
  638. if (init_attr->qp_type == IB_QPT_GSI &&
  639. hr_dev->hw_rev == HNS_ROCE_HW_VER1)
  640. hns_roce_qp_remove(hr_dev, hr_qp);
  641. else
  642. hns_roce_qp_free(hr_dev, hr_qp);
  643. err_qpn:
  644. if (!sqpn)
  645. hns_roce_release_range_qp(hr_dev, qpn, 1);
  646. err_wrid:
  647. if (ib_pd->uobject) {
  648. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  649. (udata->outlen >= sizeof(resp)) &&
  650. hns_roce_qp_has_rq(init_attr))
  651. hns_roce_db_unmap_user(
  652. to_hr_ucontext(ib_pd->uobject->context),
  653. &hr_qp->rdb);
  654. } else {
  655. kfree(hr_qp->sq.wrid);
  656. kfree(hr_qp->rq.wrid);
  657. }
  658. err_mtt:
  659. hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
  660. err_buf:
  661. if (ib_pd->uobject)
  662. ib_umem_release(hr_qp->umem);
  663. else
  664. hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
  665. err_db:
  666. if (!ib_pd->uobject && hns_roce_qp_has_rq(init_attr) &&
  667. (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB))
  668. hns_roce_free_db(hr_dev, &hr_qp->rdb);
  669. err_rq_sge_list:
  670. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
  671. kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
  672. err_wqe_list:
  673. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
  674. kfree(hr_qp->rq_inl_buf.wqe_list);
  675. err_out:
  676. return ret;
  677. }
  678. struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
  679. struct ib_qp_init_attr *init_attr,
  680. struct ib_udata *udata)
  681. {
  682. struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
  683. struct device *dev = hr_dev->dev;
  684. struct hns_roce_sqp *hr_sqp;
  685. struct hns_roce_qp *hr_qp;
  686. int ret;
  687. switch (init_attr->qp_type) {
  688. case IB_QPT_RC: {
  689. hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
  690. if (!hr_qp)
  691. return ERR_PTR(-ENOMEM);
  692. ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0,
  693. hr_qp);
  694. if (ret) {
  695. dev_err(dev, "Create RC QP failed\n");
  696. kfree(hr_qp);
  697. return ERR_PTR(ret);
  698. }
  699. hr_qp->ibqp.qp_num = hr_qp->qpn;
  700. break;
  701. }
  702. case IB_QPT_GSI: {
  703. /* Userspace is not allowed to create special QPs: */
  704. if (pd->uobject) {
  705. dev_err(dev, "not support usr space GSI\n");
  706. return ERR_PTR(-EINVAL);
  707. }
  708. hr_sqp = kzalloc(sizeof(*hr_sqp), GFP_KERNEL);
  709. if (!hr_sqp)
  710. return ERR_PTR(-ENOMEM);
  711. hr_qp = &hr_sqp->hr_qp;
  712. hr_qp->port = init_attr->port_num - 1;
  713. hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
  714. /* when hw version is v1, the sqpn is allocated */
  715. if (hr_dev->caps.max_sq_sg <= 2)
  716. hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS +
  717. hr_dev->iboe.phy_port[hr_qp->port];
  718. else
  719. hr_qp->ibqp.qp_num = 1;
  720. ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
  721. hr_qp->ibqp.qp_num, hr_qp);
  722. if (ret) {
  723. dev_err(dev, "Create GSI QP failed!\n");
  724. kfree(hr_sqp);
  725. return ERR_PTR(ret);
  726. }
  727. break;
  728. }
  729. default:{
  730. dev_err(dev, "not support QP type %d\n", init_attr->qp_type);
  731. return ERR_PTR(-EINVAL);
  732. }
  733. }
  734. return &hr_qp->ibqp;
  735. }
  736. EXPORT_SYMBOL_GPL(hns_roce_create_qp);
  737. int to_hr_qp_type(int qp_type)
  738. {
  739. int transport_type;
  740. if (qp_type == IB_QPT_RC)
  741. transport_type = SERV_TYPE_RC;
  742. else if (qp_type == IB_QPT_UC)
  743. transport_type = SERV_TYPE_UC;
  744. else if (qp_type == IB_QPT_UD)
  745. transport_type = SERV_TYPE_UD;
  746. else if (qp_type == IB_QPT_GSI)
  747. transport_type = SERV_TYPE_UD;
  748. else
  749. transport_type = -1;
  750. return transport_type;
  751. }
  752. EXPORT_SYMBOL_GPL(to_hr_qp_type);
  753. int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  754. int attr_mask, struct ib_udata *udata)
  755. {
  756. struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  757. struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
  758. enum ib_qp_state cur_state, new_state;
  759. struct device *dev = hr_dev->dev;
  760. int ret = -EINVAL;
  761. int p;
  762. enum ib_mtu active_mtu;
  763. mutex_lock(&hr_qp->mutex);
  764. cur_state = attr_mask & IB_QP_CUR_STATE ?
  765. attr->cur_qp_state : (enum ib_qp_state)hr_qp->state;
  766. new_state = attr_mask & IB_QP_STATE ?
  767. attr->qp_state : cur_state;
  768. if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
  769. IB_LINK_LAYER_ETHERNET)) {
  770. dev_err(dev, "ib_modify_qp_is_ok failed\n");
  771. goto out;
  772. }
  773. if ((attr_mask & IB_QP_PORT) &&
  774. (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
  775. dev_err(dev, "attr port_num invalid.attr->port_num=%d\n",
  776. attr->port_num);
  777. goto out;
  778. }
  779. if (attr_mask & IB_QP_PKEY_INDEX) {
  780. p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
  781. if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
  782. dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n",
  783. attr->pkey_index);
  784. goto out;
  785. }
  786. }
  787. if (attr_mask & IB_QP_PATH_MTU) {
  788. p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
  789. active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
  790. if ((hr_dev->caps.max_mtu == IB_MTU_4096 &&
  791. attr->path_mtu > IB_MTU_4096) ||
  792. (hr_dev->caps.max_mtu == IB_MTU_2048 &&
  793. attr->path_mtu > IB_MTU_2048) ||
  794. attr->path_mtu < IB_MTU_256 ||
  795. attr->path_mtu > active_mtu) {
  796. dev_err(dev, "attr path_mtu(%d)invalid while modify qp",
  797. attr->path_mtu);
  798. goto out;
  799. }
  800. }
  801. if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
  802. attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
  803. dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n",
  804. attr->max_rd_atomic);
  805. goto out;
  806. }
  807. if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
  808. attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
  809. dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n",
  810. attr->max_dest_rd_atomic);
  811. goto out;
  812. }
  813. if (cur_state == new_state && cur_state == IB_QPS_RESET) {
  814. ret = 0;
  815. goto out;
  816. }
  817. ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
  818. new_state);
  819. out:
  820. mutex_unlock(&hr_qp->mutex);
  821. return ret;
  822. }
  823. void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
  824. __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
  825. {
  826. if (send_cq == recv_cq) {
  827. spin_lock_irq(&send_cq->lock);
  828. __acquire(&recv_cq->lock);
  829. } else if (send_cq->cqn < recv_cq->cqn) {
  830. spin_lock_irq(&send_cq->lock);
  831. spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
  832. } else {
  833. spin_lock_irq(&recv_cq->lock);
  834. spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
  835. }
  836. }
  837. EXPORT_SYMBOL_GPL(hns_roce_lock_cqs);
  838. void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
  839. struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
  840. __releases(&recv_cq->lock)
  841. {
  842. if (send_cq == recv_cq) {
  843. __release(&recv_cq->lock);
  844. spin_unlock_irq(&send_cq->lock);
  845. } else if (send_cq->cqn < recv_cq->cqn) {
  846. spin_unlock(&recv_cq->lock);
  847. spin_unlock_irq(&send_cq->lock);
  848. } else {
  849. spin_unlock(&send_cq->lock);
  850. spin_unlock_irq(&recv_cq->lock);
  851. }
  852. }
  853. EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs);
  854. static void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
  855. {
  856. return hns_roce_buf_offset(&hr_qp->hr_buf, offset);
  857. }
  858. void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
  859. {
  860. return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
  861. }
  862. EXPORT_SYMBOL_GPL(get_recv_wqe);
  863. void *get_send_wqe(struct hns_roce_qp *hr_qp, int n)
  864. {
  865. return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
  866. }
  867. EXPORT_SYMBOL_GPL(get_send_wqe);
  868. void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n)
  869. {
  870. return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset +
  871. (n << hr_qp->sge.sge_shift));
  872. }
  873. EXPORT_SYMBOL_GPL(get_send_extend_sge);
  874. bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
  875. struct ib_cq *ib_cq)
  876. {
  877. struct hns_roce_cq *hr_cq;
  878. u32 cur;
  879. cur = hr_wq->head - hr_wq->tail;
  880. if (likely(cur + nreq < hr_wq->max_post))
  881. return false;
  882. hr_cq = to_hr_cq(ib_cq);
  883. spin_lock(&hr_cq->lock);
  884. cur = hr_wq->head - hr_wq->tail;
  885. spin_unlock(&hr_cq->lock);
  886. return cur + nreq >= hr_wq->max_post;
  887. }
  888. EXPORT_SYMBOL_GPL(hns_roce_wq_overflow);
  889. int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
  890. {
  891. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  892. int reserved_from_top = 0;
  893. int ret;
  894. spin_lock_init(&qp_table->lock);
  895. INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC);
  896. /* A port include two SQP, six port total 12 */
  897. ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps,
  898. hr_dev->caps.num_qps - 1, SQP_NUM,
  899. reserved_from_top);
  900. if (ret) {
  901. dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n",
  902. ret);
  903. return ret;
  904. }
  905. return 0;
  906. }
  907. void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
  908. {
  909. hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap);
  910. }