hns_roce_main.c 22 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/acpi.h>
  34. #include <linux/of_platform.h>
  35. #include <linux/module.h>
  36. #include <rdma/ib_addr.h>
  37. #include <rdma/ib_smi.h>
  38. #include <rdma/ib_user_verbs.h>
  39. #include <rdma/ib_cache.h>
  40. #include "hns_roce_common.h"
  41. #include "hns_roce_device.h"
  42. #include <rdma/hns-abi.h>
  43. #include "hns_roce_hem.h"
  44. /**
  45. * hns_get_gid_index - Get gid index.
  46. * @hr_dev: pointer to structure hns_roce_dev.
  47. * @port: port, value range: 0 ~ MAX
  48. * @gid_index: gid_index, value range: 0 ~ MAX
  49. * Description:
  50. * N ports shared gids, allocation method as follow:
  51. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  52. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  53. * And so on
  54. */
  55. int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  56. {
  57. return gid_index * hr_dev->caps.num_ports + port;
  58. }
  59. EXPORT_SYMBOL_GPL(hns_get_gid_index);
  60. static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  61. {
  62. u8 phy_port;
  63. u32 i = 0;
  64. if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
  65. return 0;
  66. for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
  67. hr_dev->dev_addr[port][i] = addr[i];
  68. phy_port = hr_dev->iboe.phy_port[port];
  69. return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  70. }
  71. static int hns_roce_add_gid(const union ib_gid *gid,
  72. const struct ib_gid_attr *attr, void **context)
  73. {
  74. struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  75. u8 port = attr->port_num - 1;
  76. unsigned long flags;
  77. int ret;
  78. if (port >= hr_dev->caps.num_ports)
  79. return -EINVAL;
  80. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  81. ret = hr_dev->hw->set_gid(hr_dev, port, attr->index,
  82. (union ib_gid *)gid, attr);
  83. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  84. return ret;
  85. }
  86. static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  87. {
  88. struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  89. struct ib_gid_attr zattr = { };
  90. union ib_gid zgid = { {0} };
  91. u8 port = attr->port_num - 1;
  92. unsigned long flags;
  93. int ret;
  94. if (port >= hr_dev->caps.num_ports)
  95. return -EINVAL;
  96. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  97. ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
  98. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  99. return ret;
  100. }
  101. static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
  102. unsigned long event)
  103. {
  104. struct device *dev = hr_dev->dev;
  105. struct net_device *netdev;
  106. int ret = 0;
  107. netdev = hr_dev->iboe.netdevs[port];
  108. if (!netdev) {
  109. dev_err(dev, "port(%d) can't find netdev\n", port);
  110. return -ENODEV;
  111. }
  112. switch (event) {
  113. case NETDEV_UP:
  114. case NETDEV_CHANGE:
  115. case NETDEV_REGISTER:
  116. case NETDEV_CHANGEADDR:
  117. ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
  118. break;
  119. case NETDEV_DOWN:
  120. /*
  121. * In v1 engine, only support all ports closed together.
  122. */
  123. break;
  124. default:
  125. dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
  126. break;
  127. }
  128. return ret;
  129. }
  130. static int hns_roce_netdev_event(struct notifier_block *self,
  131. unsigned long event, void *ptr)
  132. {
  133. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  134. struct hns_roce_ib_iboe *iboe = NULL;
  135. struct hns_roce_dev *hr_dev = NULL;
  136. u8 port = 0;
  137. int ret = 0;
  138. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
  139. iboe = &hr_dev->iboe;
  140. for (port = 0; port < hr_dev->caps.num_ports; port++) {
  141. if (dev == iboe->netdevs[port]) {
  142. ret = handle_en_event(hr_dev, port, event);
  143. if (ret)
  144. return NOTIFY_DONE;
  145. break;
  146. }
  147. }
  148. return NOTIFY_DONE;
  149. }
  150. static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
  151. {
  152. int ret;
  153. u8 i;
  154. for (i = 0; i < hr_dev->caps.num_ports; i++) {
  155. if (hr_dev->hw->set_mtu)
  156. hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
  157. hr_dev->caps.max_mtu);
  158. ret = hns_roce_set_mac(hr_dev, i,
  159. hr_dev->iboe.netdevs[i]->dev_addr);
  160. if (ret)
  161. return ret;
  162. }
  163. return 0;
  164. }
  165. static int hns_roce_query_device(struct ib_device *ib_dev,
  166. struct ib_device_attr *props,
  167. struct ib_udata *uhw)
  168. {
  169. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  170. memset(props, 0, sizeof(*props));
  171. props->sys_image_guid = cpu_to_be32(hr_dev->sys_image_guid);
  172. props->max_mr_size = (u64)(~(0ULL));
  173. props->page_size_cap = hr_dev->caps.page_size_cap;
  174. props->vendor_id = hr_dev->vendor_id;
  175. props->vendor_part_id = hr_dev->vendor_part_id;
  176. props->hw_ver = hr_dev->hw_rev;
  177. props->max_qp = hr_dev->caps.num_qps;
  178. props->max_qp_wr = hr_dev->caps.max_wqes;
  179. props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
  180. IB_DEVICE_RC_RNR_NAK_GEN;
  181. props->max_sge = max(hr_dev->caps.max_sq_sg, hr_dev->caps.max_rq_sg);
  182. props->max_sge_rd = 1;
  183. props->max_cq = hr_dev->caps.num_cqs;
  184. props->max_cqe = hr_dev->caps.max_cqes;
  185. props->max_mr = hr_dev->caps.num_mtpts;
  186. props->max_pd = hr_dev->caps.num_pds;
  187. props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
  188. props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
  189. props->atomic_cap = IB_ATOMIC_NONE;
  190. props->max_pkeys = 1;
  191. props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
  192. return 0;
  193. }
  194. static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
  195. u8 port_num)
  196. {
  197. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  198. struct net_device *ndev;
  199. if (port_num < 1 || port_num > hr_dev->caps.num_ports)
  200. return NULL;
  201. rcu_read_lock();
  202. ndev = hr_dev->iboe.netdevs[port_num - 1];
  203. if (ndev)
  204. dev_hold(ndev);
  205. rcu_read_unlock();
  206. return ndev;
  207. }
  208. static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
  209. struct ib_port_attr *props)
  210. {
  211. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  212. struct device *dev = hr_dev->dev;
  213. struct net_device *net_dev;
  214. unsigned long flags;
  215. enum ib_mtu mtu;
  216. u8 port;
  217. assert(port_num > 0);
  218. port = port_num - 1;
  219. /* props being zeroed by the caller, avoid zeroing it here */
  220. props->max_mtu = hr_dev->caps.max_mtu;
  221. props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
  222. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  223. IB_PORT_VENDOR_CLASS_SUP |
  224. IB_PORT_BOOT_MGMT_SUP;
  225. props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
  226. props->pkey_tbl_len = 1;
  227. props->active_width = IB_WIDTH_4X;
  228. props->active_speed = 1;
  229. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  230. net_dev = hr_dev->iboe.netdevs[port];
  231. if (!net_dev) {
  232. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  233. dev_err(dev, "find netdev %d failed!\r\n", port);
  234. return -EINVAL;
  235. }
  236. mtu = iboe_get_mtu(net_dev->mtu);
  237. props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
  238. props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
  239. IB_PORT_ACTIVE : IB_PORT_DOWN;
  240. props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
  241. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  242. return 0;
  243. }
  244. static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
  245. u8 port_num)
  246. {
  247. return IB_LINK_LAYER_ETHERNET;
  248. }
  249. static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
  250. u16 *pkey)
  251. {
  252. *pkey = PKEY_ID;
  253. return 0;
  254. }
  255. static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
  256. struct ib_device_modify *props)
  257. {
  258. unsigned long flags;
  259. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  260. return -EOPNOTSUPP;
  261. if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
  262. spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
  263. memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
  264. spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
  265. }
  266. return 0;
  267. }
  268. static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
  269. struct ib_port_modify *props)
  270. {
  271. return 0;
  272. }
  273. static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
  274. struct ib_udata *udata)
  275. {
  276. int ret = 0;
  277. struct hns_roce_ucontext *context;
  278. struct hns_roce_ib_alloc_ucontext_resp resp = {};
  279. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  280. resp.qp_tab_size = hr_dev->caps.num_qps;
  281. context = kmalloc(sizeof(*context), GFP_KERNEL);
  282. if (!context)
  283. return ERR_PTR(-ENOMEM);
  284. ret = hns_roce_uar_alloc(hr_dev, &context->uar);
  285. if (ret)
  286. goto error_fail_uar_alloc;
  287. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  288. INIT_LIST_HEAD(&context->page_list);
  289. mutex_init(&context->page_mutex);
  290. }
  291. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  292. if (ret)
  293. goto error_fail_copy_to_udata;
  294. return &context->ibucontext;
  295. error_fail_copy_to_udata:
  296. hns_roce_uar_free(hr_dev, &context->uar);
  297. error_fail_uar_alloc:
  298. kfree(context);
  299. return ERR_PTR(ret);
  300. }
  301. static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
  302. {
  303. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  304. hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
  305. kfree(context);
  306. return 0;
  307. }
  308. static int hns_roce_mmap(struct ib_ucontext *context,
  309. struct vm_area_struct *vma)
  310. {
  311. struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
  312. if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
  313. return -EINVAL;
  314. if (vma->vm_pgoff == 0) {
  315. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  316. if (io_remap_pfn_range(vma, vma->vm_start,
  317. to_hr_ucontext(context)->uar.pfn,
  318. PAGE_SIZE, vma->vm_page_prot))
  319. return -EAGAIN;
  320. } else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
  321. hr_dev->tptr_size) {
  322. /* vm_pgoff: 1 -- TPTR */
  323. if (io_remap_pfn_range(vma, vma->vm_start,
  324. hr_dev->tptr_dma_addr >> PAGE_SHIFT,
  325. hr_dev->tptr_size,
  326. vma->vm_page_prot))
  327. return -EAGAIN;
  328. } else
  329. return -EINVAL;
  330. return 0;
  331. }
  332. static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
  333. struct ib_port_immutable *immutable)
  334. {
  335. struct ib_port_attr attr;
  336. int ret;
  337. ret = ib_query_port(ib_dev, port_num, &attr);
  338. if (ret)
  339. return ret;
  340. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  341. immutable->gid_tbl_len = attr.gid_tbl_len;
  342. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  343. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  344. if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
  345. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  346. return 0;
  347. }
  348. static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
  349. {
  350. struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
  351. unregister_netdevice_notifier(&iboe->nb);
  352. ib_unregister_device(&hr_dev->ib_dev);
  353. }
  354. static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
  355. {
  356. int ret;
  357. struct hns_roce_ib_iboe *iboe = NULL;
  358. struct ib_device *ib_dev = NULL;
  359. struct device *dev = hr_dev->dev;
  360. iboe = &hr_dev->iboe;
  361. spin_lock_init(&iboe->lock);
  362. ib_dev = &hr_dev->ib_dev;
  363. strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
  364. ib_dev->owner = THIS_MODULE;
  365. ib_dev->node_type = RDMA_NODE_IB_CA;
  366. ib_dev->dev.parent = dev;
  367. ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
  368. ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
  369. ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
  370. ib_dev->uverbs_abi_ver = 1;
  371. ib_dev->uverbs_cmd_mask =
  372. (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
  373. (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  374. (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
  375. (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
  376. (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
  377. (1ULL << IB_USER_VERBS_CMD_REG_MR) |
  378. (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
  379. (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  380. (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
  381. (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
  382. (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
  383. (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
  384. (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
  385. (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
  386. /* HCA||device||port */
  387. ib_dev->modify_device = hns_roce_modify_device;
  388. ib_dev->query_device = hns_roce_query_device;
  389. ib_dev->query_port = hns_roce_query_port;
  390. ib_dev->modify_port = hns_roce_modify_port;
  391. ib_dev->get_link_layer = hns_roce_get_link_layer;
  392. ib_dev->get_netdev = hns_roce_get_netdev;
  393. ib_dev->add_gid = hns_roce_add_gid;
  394. ib_dev->del_gid = hns_roce_del_gid;
  395. ib_dev->query_pkey = hns_roce_query_pkey;
  396. ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
  397. ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
  398. ib_dev->mmap = hns_roce_mmap;
  399. /* PD */
  400. ib_dev->alloc_pd = hns_roce_alloc_pd;
  401. ib_dev->dealloc_pd = hns_roce_dealloc_pd;
  402. /* AH */
  403. ib_dev->create_ah = hns_roce_create_ah;
  404. ib_dev->query_ah = hns_roce_query_ah;
  405. ib_dev->destroy_ah = hns_roce_destroy_ah;
  406. /* QP */
  407. ib_dev->create_qp = hns_roce_create_qp;
  408. ib_dev->modify_qp = hns_roce_modify_qp;
  409. ib_dev->query_qp = hr_dev->hw->query_qp;
  410. ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
  411. ib_dev->post_send = hr_dev->hw->post_send;
  412. ib_dev->post_recv = hr_dev->hw->post_recv;
  413. /* CQ */
  414. ib_dev->create_cq = hns_roce_ib_create_cq;
  415. ib_dev->modify_cq = hr_dev->hw->modify_cq;
  416. ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
  417. ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
  418. ib_dev->poll_cq = hr_dev->hw->poll_cq;
  419. /* MR */
  420. ib_dev->get_dma_mr = hns_roce_get_dma_mr;
  421. ib_dev->reg_user_mr = hns_roce_reg_user_mr;
  422. ib_dev->dereg_mr = hns_roce_dereg_mr;
  423. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
  424. ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
  425. ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
  426. }
  427. /* OTHERS */
  428. ib_dev->get_port_immutable = hns_roce_port_immutable;
  429. ib_dev->driver_id = RDMA_DRIVER_HNS;
  430. ret = ib_register_device(ib_dev, NULL);
  431. if (ret) {
  432. dev_err(dev, "ib_register_device failed!\n");
  433. return ret;
  434. }
  435. ret = hns_roce_setup_mtu_mac(hr_dev);
  436. if (ret) {
  437. dev_err(dev, "setup_mtu_mac failed!\n");
  438. goto error_failed_setup_mtu_mac;
  439. }
  440. iboe->nb.notifier_call = hns_roce_netdev_event;
  441. ret = register_netdevice_notifier(&iboe->nb);
  442. if (ret) {
  443. dev_err(dev, "register_netdevice_notifier failed!\n");
  444. goto error_failed_setup_mtu_mac;
  445. }
  446. return 0;
  447. error_failed_setup_mtu_mac:
  448. ib_unregister_device(ib_dev);
  449. return ret;
  450. }
  451. static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
  452. {
  453. int ret;
  454. struct device *dev = hr_dev->dev;
  455. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
  456. HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
  457. hr_dev->caps.num_mtt_segs, 1);
  458. if (ret) {
  459. dev_err(dev, "Failed to init MTT context memory, aborting.\n");
  460. return ret;
  461. }
  462. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
  463. ret = hns_roce_init_hem_table(hr_dev,
  464. &hr_dev->mr_table.mtt_cqe_table,
  465. HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
  466. hr_dev->caps.num_cqe_segs, 1);
  467. if (ret) {
  468. dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
  469. goto err_unmap_cqe;
  470. }
  471. }
  472. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
  473. HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
  474. hr_dev->caps.num_mtpts, 1);
  475. if (ret) {
  476. dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
  477. goto err_unmap_mtt;
  478. }
  479. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
  480. HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
  481. hr_dev->caps.num_qps, 1);
  482. if (ret) {
  483. dev_err(dev, "Failed to init QP context memory, aborting.\n");
  484. goto err_unmap_dmpt;
  485. }
  486. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
  487. HEM_TYPE_IRRL,
  488. hr_dev->caps.irrl_entry_sz *
  489. hr_dev->caps.max_qp_init_rdma,
  490. hr_dev->caps.num_qps, 1);
  491. if (ret) {
  492. dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
  493. goto err_unmap_qp;
  494. }
  495. if (hr_dev->caps.trrl_entry_sz) {
  496. ret = hns_roce_init_hem_table(hr_dev,
  497. &hr_dev->qp_table.trrl_table,
  498. HEM_TYPE_TRRL,
  499. hr_dev->caps.trrl_entry_sz *
  500. hr_dev->caps.max_qp_dest_rdma,
  501. hr_dev->caps.num_qps, 1);
  502. if (ret) {
  503. dev_err(dev,
  504. "Failed to init trrl_table memory, aborting.\n");
  505. goto err_unmap_irrl;
  506. }
  507. }
  508. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
  509. HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
  510. hr_dev->caps.num_cqs, 1);
  511. if (ret) {
  512. dev_err(dev, "Failed to init CQ context memory, aborting.\n");
  513. goto err_unmap_trrl;
  514. }
  515. return 0;
  516. err_unmap_trrl:
  517. if (hr_dev->caps.trrl_entry_sz)
  518. hns_roce_cleanup_hem_table(hr_dev,
  519. &hr_dev->qp_table.trrl_table);
  520. err_unmap_irrl:
  521. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
  522. err_unmap_qp:
  523. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
  524. err_unmap_dmpt:
  525. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
  526. err_unmap_mtt:
  527. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
  528. hns_roce_cleanup_hem_table(hr_dev,
  529. &hr_dev->mr_table.mtt_cqe_table);
  530. err_unmap_cqe:
  531. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
  532. return ret;
  533. }
  534. /**
  535. * hns_roce_setup_hca - setup host channel adapter
  536. * @hr_dev: pointer to hns roce device
  537. * Return : int
  538. */
  539. static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
  540. {
  541. int ret;
  542. struct device *dev = hr_dev->dev;
  543. spin_lock_init(&hr_dev->sm_lock);
  544. spin_lock_init(&hr_dev->bt_cmd_lock);
  545. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  546. INIT_LIST_HEAD(&hr_dev->pgdir_list);
  547. mutex_init(&hr_dev->pgdir_mutex);
  548. }
  549. ret = hns_roce_init_uar_table(hr_dev);
  550. if (ret) {
  551. dev_err(dev, "Failed to initialize uar table. aborting\n");
  552. return ret;
  553. }
  554. ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
  555. if (ret) {
  556. dev_err(dev, "Failed to allocate priv_uar.\n");
  557. goto err_uar_table_free;
  558. }
  559. ret = hns_roce_init_pd_table(hr_dev);
  560. if (ret) {
  561. dev_err(dev, "Failed to init protected domain table.\n");
  562. goto err_uar_alloc_free;
  563. }
  564. ret = hns_roce_init_mr_table(hr_dev);
  565. if (ret) {
  566. dev_err(dev, "Failed to init memory region table.\n");
  567. goto err_pd_table_free;
  568. }
  569. ret = hns_roce_init_cq_table(hr_dev);
  570. if (ret) {
  571. dev_err(dev, "Failed to init completion queue table.\n");
  572. goto err_mr_table_free;
  573. }
  574. ret = hns_roce_init_qp_table(hr_dev);
  575. if (ret) {
  576. dev_err(dev, "Failed to init queue pair table.\n");
  577. goto err_cq_table_free;
  578. }
  579. return 0;
  580. err_cq_table_free:
  581. hns_roce_cleanup_cq_table(hr_dev);
  582. err_mr_table_free:
  583. hns_roce_cleanup_mr_table(hr_dev);
  584. err_pd_table_free:
  585. hns_roce_cleanup_pd_table(hr_dev);
  586. err_uar_alloc_free:
  587. hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
  588. err_uar_table_free:
  589. hns_roce_cleanup_uar_table(hr_dev);
  590. return ret;
  591. }
  592. int hns_roce_init(struct hns_roce_dev *hr_dev)
  593. {
  594. int ret;
  595. struct device *dev = hr_dev->dev;
  596. if (hr_dev->hw->reset) {
  597. ret = hr_dev->hw->reset(hr_dev, true);
  598. if (ret) {
  599. dev_err(dev, "Reset RoCE engine failed!\n");
  600. return ret;
  601. }
  602. }
  603. if (hr_dev->hw->cmq_init) {
  604. ret = hr_dev->hw->cmq_init(hr_dev);
  605. if (ret) {
  606. dev_err(dev, "Init RoCE Command Queue failed!\n");
  607. goto error_failed_cmq_init;
  608. }
  609. }
  610. ret = hr_dev->hw->hw_profile(hr_dev);
  611. if (ret) {
  612. dev_err(dev, "Get RoCE engine profile failed!\n");
  613. goto error_failed_cmd_init;
  614. }
  615. ret = hns_roce_cmd_init(hr_dev);
  616. if (ret) {
  617. dev_err(dev, "cmd init failed!\n");
  618. goto error_failed_cmd_init;
  619. }
  620. ret = hr_dev->hw->init_eq(hr_dev);
  621. if (ret) {
  622. dev_err(dev, "eq init failed!\n");
  623. goto error_failed_eq_table;
  624. }
  625. if (hr_dev->cmd_mod) {
  626. ret = hns_roce_cmd_use_events(hr_dev);
  627. if (ret) {
  628. dev_err(dev, "Switch to event-driven cmd failed!\n");
  629. goto error_failed_use_event;
  630. }
  631. }
  632. ret = hns_roce_init_hem(hr_dev);
  633. if (ret) {
  634. dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
  635. goto error_failed_init_hem;
  636. }
  637. ret = hns_roce_setup_hca(hr_dev);
  638. if (ret) {
  639. dev_err(dev, "setup hca failed!\n");
  640. goto error_failed_setup_hca;
  641. }
  642. if (hr_dev->hw->hw_init) {
  643. ret = hr_dev->hw->hw_init(hr_dev);
  644. if (ret) {
  645. dev_err(dev, "hw_init failed!\n");
  646. goto error_failed_engine_init;
  647. }
  648. }
  649. ret = hns_roce_register_device(hr_dev);
  650. if (ret)
  651. goto error_failed_register_device;
  652. return 0;
  653. error_failed_register_device:
  654. if (hr_dev->hw->hw_exit)
  655. hr_dev->hw->hw_exit(hr_dev);
  656. error_failed_engine_init:
  657. hns_roce_cleanup_bitmap(hr_dev);
  658. error_failed_setup_hca:
  659. hns_roce_cleanup_hem(hr_dev);
  660. error_failed_init_hem:
  661. if (hr_dev->cmd_mod)
  662. hns_roce_cmd_use_polling(hr_dev);
  663. error_failed_use_event:
  664. hr_dev->hw->cleanup_eq(hr_dev);
  665. error_failed_eq_table:
  666. hns_roce_cmd_cleanup(hr_dev);
  667. error_failed_cmd_init:
  668. if (hr_dev->hw->cmq_exit)
  669. hr_dev->hw->cmq_exit(hr_dev);
  670. error_failed_cmq_init:
  671. if (hr_dev->hw->reset) {
  672. ret = hr_dev->hw->reset(hr_dev, false);
  673. if (ret)
  674. dev_err(dev, "Dereset RoCE engine failed!\n");
  675. }
  676. return ret;
  677. }
  678. EXPORT_SYMBOL_GPL(hns_roce_init);
  679. void hns_roce_exit(struct hns_roce_dev *hr_dev)
  680. {
  681. hns_roce_unregister_device(hr_dev);
  682. if (hr_dev->hw->hw_exit)
  683. hr_dev->hw->hw_exit(hr_dev);
  684. hns_roce_cleanup_bitmap(hr_dev);
  685. hns_roce_cleanup_hem(hr_dev);
  686. if (hr_dev->cmd_mod)
  687. hns_roce_cmd_use_polling(hr_dev);
  688. hr_dev->hw->cleanup_eq(hr_dev);
  689. hns_roce_cmd_cleanup(hr_dev);
  690. if (hr_dev->hw->cmq_exit)
  691. hr_dev->hw->cmq_exit(hr_dev);
  692. if (hr_dev->hw->reset)
  693. hr_dev->hw->reset(hr_dev, false);
  694. }
  695. EXPORT_SYMBOL_GPL(hns_roce_exit);
  696. MODULE_LICENSE("Dual BSD/GPL");
  697. MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
  698. MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
  699. MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
  700. MODULE_DESCRIPTION("HNS RoCE Driver");