device.c 42 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. static int allow_db_fc_on_t5;
  44. module_param(allow_db_fc_on_t5, int, 0644);
  45. MODULE_PARM_DESC(allow_db_fc_on_t5,
  46. "Allow DB Flow Control on T5 (default = 0)");
  47. static int allow_db_coalescing_on_t5;
  48. module_param(allow_db_coalescing_on_t5, int, 0644);
  49. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  50. "Allow DB Coalescing on T5 (default = 0)");
  51. int c4iw_wr_log = 0;
  52. module_param(c4iw_wr_log, int, 0444);
  53. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  54. static int c4iw_wr_log_size_order = 12;
  55. module_param(c4iw_wr_log_size_order, int, 0444);
  56. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  57. "Number of entries (log2) in the work request timing log.");
  58. static LIST_HEAD(uld_ctx_list);
  59. static DEFINE_MUTEX(dev_mutex);
  60. static struct workqueue_struct *reg_workq;
  61. #define DB_FC_RESUME_SIZE 64
  62. #define DB_FC_RESUME_DELAY 1
  63. #define DB_FC_DRAIN_THRESH 0
  64. static struct dentry *c4iw_debugfs_root;
  65. struct c4iw_debugfs_data {
  66. struct c4iw_dev *devp;
  67. char *buf;
  68. int bufsize;
  69. int pos;
  70. };
  71. static int count_idrs(int id, void *p, void *data)
  72. {
  73. int *countp = data;
  74. *countp = *countp + 1;
  75. return 0;
  76. }
  77. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  78. loff_t *ppos)
  79. {
  80. struct c4iw_debugfs_data *d = file->private_data;
  81. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  82. }
  83. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  84. {
  85. struct wr_log_entry le;
  86. int idx;
  87. if (!wq->rdev->wr_log)
  88. return;
  89. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  90. (wq->rdev->wr_log_size - 1);
  91. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  92. le.poll_host_time = ktime_get();
  93. le.valid = 1;
  94. le.cqe_sge_ts = CQE_TS(cqe);
  95. if (SQ_TYPE(cqe)) {
  96. le.qid = wq->sq.qid;
  97. le.opcode = CQE_OPCODE(cqe);
  98. le.post_host_time = wq->sq.sw_sq[wq->sq.cidx].host_time;
  99. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  100. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  101. } else {
  102. le.qid = wq->rq.qid;
  103. le.opcode = FW_RI_RECEIVE;
  104. le.post_host_time = wq->rq.sw_rq[wq->rq.cidx].host_time;
  105. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  106. le.wr_id = CQE_WRID_MSN(cqe);
  107. }
  108. wq->rdev->wr_log[idx] = le;
  109. }
  110. static int wr_log_show(struct seq_file *seq, void *v)
  111. {
  112. struct c4iw_dev *dev = seq->private;
  113. ktime_t prev_time;
  114. struct wr_log_entry *lep;
  115. int prev_time_set = 0;
  116. int idx, end;
  117. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  118. idx = atomic_read(&dev->rdev.wr_log_idx) &
  119. (dev->rdev.wr_log_size - 1);
  120. end = idx - 1;
  121. if (end < 0)
  122. end = dev->rdev.wr_log_size - 1;
  123. lep = &dev->rdev.wr_log[idx];
  124. while (idx != end) {
  125. if (lep->valid) {
  126. if (!prev_time_set) {
  127. prev_time_set = 1;
  128. prev_time = lep->poll_host_time;
  129. }
  130. seq_printf(seq, "%04u: nsec %llu qid %u opcode "
  131. "%u %s 0x%x host_wr_delta nsec %llu "
  132. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  133. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  134. "cqe_poll_delta_ns %llu\n",
  135. idx,
  136. ktime_to_ns(ktime_sub(lep->poll_host_time,
  137. prev_time)),
  138. lep->qid, lep->opcode,
  139. lep->opcode == FW_RI_RECEIVE ?
  140. "msn" : "wrid",
  141. lep->wr_id,
  142. ktime_to_ns(ktime_sub(lep->poll_host_time,
  143. lep->post_host_time)),
  144. lep->post_sge_ts, lep->cqe_sge_ts,
  145. lep->poll_sge_ts,
  146. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  147. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  148. prev_time = lep->poll_host_time;
  149. }
  150. idx++;
  151. if (idx > (dev->rdev.wr_log_size - 1))
  152. idx = 0;
  153. lep = &dev->rdev.wr_log[idx];
  154. }
  155. #undef ts2ns
  156. return 0;
  157. }
  158. static int wr_log_open(struct inode *inode, struct file *file)
  159. {
  160. return single_open(file, wr_log_show, inode->i_private);
  161. }
  162. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  163. size_t count, loff_t *pos)
  164. {
  165. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  166. int i;
  167. if (dev->rdev.wr_log)
  168. for (i = 0; i < dev->rdev.wr_log_size; i++)
  169. dev->rdev.wr_log[i].valid = 0;
  170. return count;
  171. }
  172. static const struct file_operations wr_log_debugfs_fops = {
  173. .owner = THIS_MODULE,
  174. .open = wr_log_open,
  175. .release = single_release,
  176. .read = seq_read,
  177. .llseek = seq_lseek,
  178. .write = wr_log_clear,
  179. };
  180. static struct sockaddr_in zero_sin = {
  181. .sin_family = AF_INET,
  182. };
  183. static struct sockaddr_in6 zero_sin6 = {
  184. .sin6_family = AF_INET6,
  185. };
  186. static void set_ep_sin_addrs(struct c4iw_ep *ep,
  187. struct sockaddr_in **lsin,
  188. struct sockaddr_in **rsin,
  189. struct sockaddr_in **m_lsin,
  190. struct sockaddr_in **m_rsin)
  191. {
  192. struct iw_cm_id *id = ep->com.cm_id;
  193. *m_lsin = (struct sockaddr_in *)&ep->com.local_addr;
  194. *m_rsin = (struct sockaddr_in *)&ep->com.remote_addr;
  195. if (id) {
  196. *lsin = (struct sockaddr_in *)&id->local_addr;
  197. *rsin = (struct sockaddr_in *)&id->remote_addr;
  198. } else {
  199. *lsin = &zero_sin;
  200. *rsin = &zero_sin;
  201. }
  202. }
  203. static void set_ep_sin6_addrs(struct c4iw_ep *ep,
  204. struct sockaddr_in6 **lsin6,
  205. struct sockaddr_in6 **rsin6,
  206. struct sockaddr_in6 **m_lsin6,
  207. struct sockaddr_in6 **m_rsin6)
  208. {
  209. struct iw_cm_id *id = ep->com.cm_id;
  210. *m_lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
  211. *m_rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
  212. if (id) {
  213. *lsin6 = (struct sockaddr_in6 *)&id->local_addr;
  214. *rsin6 = (struct sockaddr_in6 *)&id->remote_addr;
  215. } else {
  216. *lsin6 = &zero_sin6;
  217. *rsin6 = &zero_sin6;
  218. }
  219. }
  220. static int dump_qp(int id, void *p, void *data)
  221. {
  222. struct c4iw_qp *qp = p;
  223. struct c4iw_debugfs_data *qpd = data;
  224. int space;
  225. int cc;
  226. if (id != qp->wq.sq.qid)
  227. return 0;
  228. space = qpd->bufsize - qpd->pos - 1;
  229. if (space == 0)
  230. return 1;
  231. if (qp->ep) {
  232. struct c4iw_ep *ep = qp->ep;
  233. if (ep->com.local_addr.ss_family == AF_INET) {
  234. struct sockaddr_in *lsin;
  235. struct sockaddr_in *rsin;
  236. struct sockaddr_in *m_lsin;
  237. struct sockaddr_in *m_rsin;
  238. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  239. cc = snprintf(qpd->buf + qpd->pos, space,
  240. "rc qp sq id %u rq id %u state %u "
  241. "onchip %u ep tid %u state %u "
  242. "%pI4:%u/%u->%pI4:%u/%u\n",
  243. qp->wq.sq.qid, qp->wq.rq.qid,
  244. (int)qp->attr.state,
  245. qp->wq.sq.flags & T4_SQ_ONCHIP,
  246. ep->hwtid, (int)ep->com.state,
  247. &lsin->sin_addr, ntohs(lsin->sin_port),
  248. ntohs(m_lsin->sin_port),
  249. &rsin->sin_addr, ntohs(rsin->sin_port),
  250. ntohs(m_rsin->sin_port));
  251. } else {
  252. struct sockaddr_in6 *lsin6;
  253. struct sockaddr_in6 *rsin6;
  254. struct sockaddr_in6 *m_lsin6;
  255. struct sockaddr_in6 *m_rsin6;
  256. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
  257. &m_rsin6);
  258. cc = snprintf(qpd->buf + qpd->pos, space,
  259. "rc qp sq id %u rq id %u state %u "
  260. "onchip %u ep tid %u state %u "
  261. "%pI6:%u/%u->%pI6:%u/%u\n",
  262. qp->wq.sq.qid, qp->wq.rq.qid,
  263. (int)qp->attr.state,
  264. qp->wq.sq.flags & T4_SQ_ONCHIP,
  265. ep->hwtid, (int)ep->com.state,
  266. &lsin6->sin6_addr,
  267. ntohs(lsin6->sin6_port),
  268. ntohs(m_lsin6->sin6_port),
  269. &rsin6->sin6_addr,
  270. ntohs(rsin6->sin6_port),
  271. ntohs(m_rsin6->sin6_port));
  272. }
  273. } else
  274. cc = snprintf(qpd->buf + qpd->pos, space,
  275. "qp sq id %u rq id %u state %u onchip %u\n",
  276. qp->wq.sq.qid, qp->wq.rq.qid,
  277. (int)qp->attr.state,
  278. qp->wq.sq.flags & T4_SQ_ONCHIP);
  279. if (cc < space)
  280. qpd->pos += cc;
  281. return 0;
  282. }
  283. static int qp_release(struct inode *inode, struct file *file)
  284. {
  285. struct c4iw_debugfs_data *qpd = file->private_data;
  286. if (!qpd) {
  287. pr_info("%s null qpd?\n", __func__);
  288. return 0;
  289. }
  290. vfree(qpd->buf);
  291. kfree(qpd);
  292. return 0;
  293. }
  294. static int qp_open(struct inode *inode, struct file *file)
  295. {
  296. struct c4iw_debugfs_data *qpd;
  297. int count = 1;
  298. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  299. if (!qpd)
  300. return -ENOMEM;
  301. qpd->devp = inode->i_private;
  302. qpd->pos = 0;
  303. spin_lock_irq(&qpd->devp->lock);
  304. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  305. spin_unlock_irq(&qpd->devp->lock);
  306. qpd->bufsize = count * 180;
  307. qpd->buf = vmalloc(qpd->bufsize);
  308. if (!qpd->buf) {
  309. kfree(qpd);
  310. return -ENOMEM;
  311. }
  312. spin_lock_irq(&qpd->devp->lock);
  313. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  314. spin_unlock_irq(&qpd->devp->lock);
  315. qpd->buf[qpd->pos++] = 0;
  316. file->private_data = qpd;
  317. return 0;
  318. }
  319. static const struct file_operations qp_debugfs_fops = {
  320. .owner = THIS_MODULE,
  321. .open = qp_open,
  322. .release = qp_release,
  323. .read = debugfs_read,
  324. .llseek = default_llseek,
  325. };
  326. static int dump_stag(int id, void *p, void *data)
  327. {
  328. struct c4iw_debugfs_data *stagd = data;
  329. int space;
  330. int cc;
  331. struct fw_ri_tpte tpte;
  332. int ret;
  333. space = stagd->bufsize - stagd->pos - 1;
  334. if (space == 0)
  335. return 1;
  336. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  337. (__be32 *)&tpte);
  338. if (ret) {
  339. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  340. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  341. return ret;
  342. }
  343. cc = snprintf(stagd->buf + stagd->pos, space,
  344. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  345. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  346. (u32)id<<8,
  347. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  348. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  349. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  350. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  351. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  352. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  353. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  354. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  355. if (cc < space)
  356. stagd->pos += cc;
  357. return 0;
  358. }
  359. static int stag_release(struct inode *inode, struct file *file)
  360. {
  361. struct c4iw_debugfs_data *stagd = file->private_data;
  362. if (!stagd) {
  363. pr_info("%s null stagd?\n", __func__);
  364. return 0;
  365. }
  366. vfree(stagd->buf);
  367. kfree(stagd);
  368. return 0;
  369. }
  370. static int stag_open(struct inode *inode, struct file *file)
  371. {
  372. struct c4iw_debugfs_data *stagd;
  373. int ret = 0;
  374. int count = 1;
  375. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  376. if (!stagd) {
  377. ret = -ENOMEM;
  378. goto out;
  379. }
  380. stagd->devp = inode->i_private;
  381. stagd->pos = 0;
  382. spin_lock_irq(&stagd->devp->lock);
  383. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  384. spin_unlock_irq(&stagd->devp->lock);
  385. stagd->bufsize = count * 256;
  386. stagd->buf = vmalloc(stagd->bufsize);
  387. if (!stagd->buf) {
  388. ret = -ENOMEM;
  389. goto err1;
  390. }
  391. spin_lock_irq(&stagd->devp->lock);
  392. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  393. spin_unlock_irq(&stagd->devp->lock);
  394. stagd->buf[stagd->pos++] = 0;
  395. file->private_data = stagd;
  396. goto out;
  397. err1:
  398. kfree(stagd);
  399. out:
  400. return ret;
  401. }
  402. static const struct file_operations stag_debugfs_fops = {
  403. .owner = THIS_MODULE,
  404. .open = stag_open,
  405. .release = stag_release,
  406. .read = debugfs_read,
  407. .llseek = default_llseek,
  408. };
  409. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  410. static int stats_show(struct seq_file *seq, void *v)
  411. {
  412. struct c4iw_dev *dev = seq->private;
  413. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  414. "Max", "Fail");
  415. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  416. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  417. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  418. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  419. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  420. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  421. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  422. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  423. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  424. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  425. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  426. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  427. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  428. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  429. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  430. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  431. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  432. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  433. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  434. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  435. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  436. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  437. db_state_str[dev->db_state],
  438. dev->rdev.stats.db_state_transitions,
  439. dev->rdev.stats.db_fc_interruptions);
  440. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  441. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  442. dev->rdev.stats.act_ofld_conn_fails);
  443. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  444. dev->rdev.stats.pas_ofld_conn_fails);
  445. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  446. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  447. return 0;
  448. }
  449. static int stats_open(struct inode *inode, struct file *file)
  450. {
  451. return single_open(file, stats_show, inode->i_private);
  452. }
  453. static ssize_t stats_clear(struct file *file, const char __user *buf,
  454. size_t count, loff_t *pos)
  455. {
  456. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  457. mutex_lock(&dev->rdev.stats.lock);
  458. dev->rdev.stats.pd.max = 0;
  459. dev->rdev.stats.pd.fail = 0;
  460. dev->rdev.stats.qid.max = 0;
  461. dev->rdev.stats.qid.fail = 0;
  462. dev->rdev.stats.stag.max = 0;
  463. dev->rdev.stats.stag.fail = 0;
  464. dev->rdev.stats.pbl.max = 0;
  465. dev->rdev.stats.pbl.fail = 0;
  466. dev->rdev.stats.rqt.max = 0;
  467. dev->rdev.stats.rqt.fail = 0;
  468. dev->rdev.stats.ocqp.max = 0;
  469. dev->rdev.stats.ocqp.fail = 0;
  470. dev->rdev.stats.db_full = 0;
  471. dev->rdev.stats.db_empty = 0;
  472. dev->rdev.stats.db_drop = 0;
  473. dev->rdev.stats.db_state_transitions = 0;
  474. dev->rdev.stats.tcam_full = 0;
  475. dev->rdev.stats.act_ofld_conn_fails = 0;
  476. dev->rdev.stats.pas_ofld_conn_fails = 0;
  477. mutex_unlock(&dev->rdev.stats.lock);
  478. return count;
  479. }
  480. static const struct file_operations stats_debugfs_fops = {
  481. .owner = THIS_MODULE,
  482. .open = stats_open,
  483. .release = single_release,
  484. .read = seq_read,
  485. .llseek = seq_lseek,
  486. .write = stats_clear,
  487. };
  488. static int dump_ep(int id, void *p, void *data)
  489. {
  490. struct c4iw_ep *ep = p;
  491. struct c4iw_debugfs_data *epd = data;
  492. int space;
  493. int cc;
  494. space = epd->bufsize - epd->pos - 1;
  495. if (space == 0)
  496. return 1;
  497. if (ep->com.local_addr.ss_family == AF_INET) {
  498. struct sockaddr_in *lsin;
  499. struct sockaddr_in *rsin;
  500. struct sockaddr_in *m_lsin;
  501. struct sockaddr_in *m_rsin;
  502. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  503. cc = snprintf(epd->buf + epd->pos, space,
  504. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  505. "history 0x%lx hwtid %d atid %d "
  506. "conn_na %u abort_na %u "
  507. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  508. ep, ep->com.cm_id, ep->com.qp,
  509. (int)ep->com.state, ep->com.flags,
  510. ep->com.history, ep->hwtid, ep->atid,
  511. ep->stats.connect_neg_adv,
  512. ep->stats.abort_neg_adv,
  513. &lsin->sin_addr, ntohs(lsin->sin_port),
  514. ntohs(m_lsin->sin_port),
  515. &rsin->sin_addr, ntohs(rsin->sin_port),
  516. ntohs(m_rsin->sin_port));
  517. } else {
  518. struct sockaddr_in6 *lsin6;
  519. struct sockaddr_in6 *rsin6;
  520. struct sockaddr_in6 *m_lsin6;
  521. struct sockaddr_in6 *m_rsin6;
  522. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
  523. cc = snprintf(epd->buf + epd->pos, space,
  524. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  525. "history 0x%lx hwtid %d atid %d "
  526. "conn_na %u abort_na %u "
  527. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  528. ep, ep->com.cm_id, ep->com.qp,
  529. (int)ep->com.state, ep->com.flags,
  530. ep->com.history, ep->hwtid, ep->atid,
  531. ep->stats.connect_neg_adv,
  532. ep->stats.abort_neg_adv,
  533. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  534. ntohs(m_lsin6->sin6_port),
  535. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  536. ntohs(m_rsin6->sin6_port));
  537. }
  538. if (cc < space)
  539. epd->pos += cc;
  540. return 0;
  541. }
  542. static int dump_listen_ep(int id, void *p, void *data)
  543. {
  544. struct c4iw_listen_ep *ep = p;
  545. struct c4iw_debugfs_data *epd = data;
  546. int space;
  547. int cc;
  548. space = epd->bufsize - epd->pos - 1;
  549. if (space == 0)
  550. return 1;
  551. if (ep->com.local_addr.ss_family == AF_INET) {
  552. struct sockaddr_in *lsin = (struct sockaddr_in *)
  553. &ep->com.cm_id->local_addr;
  554. struct sockaddr_in *m_lsin = (struct sockaddr_in *)
  555. &ep->com.cm_id->m_local_addr;
  556. cc = snprintf(epd->buf + epd->pos, space,
  557. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  558. "backlog %d %pI4:%d/%d\n",
  559. ep, ep->com.cm_id, (int)ep->com.state,
  560. ep->com.flags, ep->stid, ep->backlog,
  561. &lsin->sin_addr, ntohs(lsin->sin_port),
  562. ntohs(m_lsin->sin_port));
  563. } else {
  564. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  565. &ep->com.cm_id->local_addr;
  566. struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
  567. &ep->com.cm_id->m_local_addr;
  568. cc = snprintf(epd->buf + epd->pos, space,
  569. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  570. "backlog %d %pI6:%d/%d\n",
  571. ep, ep->com.cm_id, (int)ep->com.state,
  572. ep->com.flags, ep->stid, ep->backlog,
  573. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  574. ntohs(m_lsin6->sin6_port));
  575. }
  576. if (cc < space)
  577. epd->pos += cc;
  578. return 0;
  579. }
  580. static int ep_release(struct inode *inode, struct file *file)
  581. {
  582. struct c4iw_debugfs_data *epd = file->private_data;
  583. if (!epd) {
  584. pr_info("%s null qpd?\n", __func__);
  585. return 0;
  586. }
  587. vfree(epd->buf);
  588. kfree(epd);
  589. return 0;
  590. }
  591. static int ep_open(struct inode *inode, struct file *file)
  592. {
  593. struct c4iw_debugfs_data *epd;
  594. int ret = 0;
  595. int count = 1;
  596. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  597. if (!epd) {
  598. ret = -ENOMEM;
  599. goto out;
  600. }
  601. epd->devp = inode->i_private;
  602. epd->pos = 0;
  603. spin_lock_irq(&epd->devp->lock);
  604. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  605. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  606. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  607. spin_unlock_irq(&epd->devp->lock);
  608. epd->bufsize = count * 240;
  609. epd->buf = vmalloc(epd->bufsize);
  610. if (!epd->buf) {
  611. ret = -ENOMEM;
  612. goto err1;
  613. }
  614. spin_lock_irq(&epd->devp->lock);
  615. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  616. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  617. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  618. spin_unlock_irq(&epd->devp->lock);
  619. file->private_data = epd;
  620. goto out;
  621. err1:
  622. kfree(epd);
  623. out:
  624. return ret;
  625. }
  626. static const struct file_operations ep_debugfs_fops = {
  627. .owner = THIS_MODULE,
  628. .open = ep_open,
  629. .release = ep_release,
  630. .read = debugfs_read,
  631. };
  632. static int setup_debugfs(struct c4iw_dev *devp)
  633. {
  634. if (!devp->debugfs_root)
  635. return -1;
  636. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  637. (void *)devp, &qp_debugfs_fops, 4096);
  638. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  639. (void *)devp, &stag_debugfs_fops, 4096);
  640. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  641. (void *)devp, &stats_debugfs_fops, 4096);
  642. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  643. (void *)devp, &ep_debugfs_fops, 4096);
  644. if (c4iw_wr_log)
  645. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  646. (void *)devp, &wr_log_debugfs_fops, 4096);
  647. return 0;
  648. }
  649. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  650. struct c4iw_dev_ucontext *uctx)
  651. {
  652. struct list_head *pos, *nxt;
  653. struct c4iw_qid_list *entry;
  654. mutex_lock(&uctx->lock);
  655. list_for_each_safe(pos, nxt, &uctx->qpids) {
  656. entry = list_entry(pos, struct c4iw_qid_list, entry);
  657. list_del_init(&entry->entry);
  658. if (!(entry->qid & rdev->qpmask)) {
  659. c4iw_put_resource(&rdev->resource.qid_table,
  660. entry->qid);
  661. mutex_lock(&rdev->stats.lock);
  662. rdev->stats.qid.cur -= rdev->qpmask + 1;
  663. mutex_unlock(&rdev->stats.lock);
  664. }
  665. kfree(entry);
  666. }
  667. list_for_each_safe(pos, nxt, &uctx->cqids) {
  668. entry = list_entry(pos, struct c4iw_qid_list, entry);
  669. list_del_init(&entry->entry);
  670. kfree(entry);
  671. }
  672. mutex_unlock(&uctx->lock);
  673. }
  674. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  675. struct c4iw_dev_ucontext *uctx)
  676. {
  677. INIT_LIST_HEAD(&uctx->qpids);
  678. INIT_LIST_HEAD(&uctx->cqids);
  679. mutex_init(&uctx->lock);
  680. }
  681. /* Caller takes care of locking if needed */
  682. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  683. {
  684. int err;
  685. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  686. /*
  687. * This implementation assumes udb_density == ucq_density! Eventually
  688. * we might need to support this but for now fail the open. Also the
  689. * cqid and qpid range must match for now.
  690. */
  691. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  692. pr_err("%s: unsupported udb/ucq densities %u/%u\n",
  693. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  694. rdev->lldi.ucq_density);
  695. return -EINVAL;
  696. }
  697. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  698. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  699. pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
  700. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  701. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  702. rdev->lldi.vr->cq.size);
  703. return -EINVAL;
  704. }
  705. rdev->qpmask = rdev->lldi.udb_density - 1;
  706. rdev->cqmask = rdev->lldi.ucq_density - 1;
  707. pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n",
  708. pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  709. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  710. rdev->lldi.vr->pbl.start,
  711. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  712. rdev->lldi.vr->rq.size,
  713. rdev->lldi.vr->qp.start,
  714. rdev->lldi.vr->qp.size,
  715. rdev->lldi.vr->cq.start,
  716. rdev->lldi.vr->cq.size);
  717. pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
  718. &rdev->lldi.pdev->resource[2],
  719. rdev->lldi.db_reg, rdev->lldi.gts_reg,
  720. rdev->qpmask, rdev->cqmask);
  721. if (c4iw_num_stags(rdev) == 0)
  722. return -EINVAL;
  723. rdev->stats.pd.total = T4_MAX_NUM_PD;
  724. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  725. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  726. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  727. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  728. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  729. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  730. if (err) {
  731. pr_err("error %d initializing resources\n", err);
  732. return err;
  733. }
  734. err = c4iw_pblpool_create(rdev);
  735. if (err) {
  736. pr_err("error %d initializing pbl pool\n", err);
  737. goto destroy_resource;
  738. }
  739. err = c4iw_rqtpool_create(rdev);
  740. if (err) {
  741. pr_err("error %d initializing rqt pool\n", err);
  742. goto destroy_pblpool;
  743. }
  744. err = c4iw_ocqp_pool_create(rdev);
  745. if (err) {
  746. pr_err("error %d initializing ocqp pool\n", err);
  747. goto destroy_rqtpool;
  748. }
  749. rdev->status_page = (struct t4_dev_status_page *)
  750. __get_free_page(GFP_KERNEL);
  751. if (!rdev->status_page) {
  752. err = -ENOMEM;
  753. goto destroy_ocqp_pool;
  754. }
  755. rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
  756. rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
  757. rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
  758. rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
  759. if (c4iw_wr_log) {
  760. rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
  761. sizeof(*rdev->wr_log), GFP_KERNEL);
  762. if (rdev->wr_log) {
  763. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  764. atomic_set(&rdev->wr_log_idx, 0);
  765. }
  766. }
  767. rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
  768. if (!rdev->free_workq) {
  769. err = -ENOMEM;
  770. goto err_free_status_page_and_wr_log;
  771. }
  772. rdev->status_page->db_off = 0;
  773. init_completion(&rdev->rqt_compl);
  774. init_completion(&rdev->pbl_compl);
  775. kref_init(&rdev->rqt_kref);
  776. kref_init(&rdev->pbl_kref);
  777. return 0;
  778. err_free_status_page_and_wr_log:
  779. if (c4iw_wr_log && rdev->wr_log)
  780. kfree(rdev->wr_log);
  781. free_page((unsigned long)rdev->status_page);
  782. destroy_ocqp_pool:
  783. c4iw_ocqp_pool_destroy(rdev);
  784. destroy_rqtpool:
  785. c4iw_rqtpool_destroy(rdev);
  786. destroy_pblpool:
  787. c4iw_pblpool_destroy(rdev);
  788. destroy_resource:
  789. c4iw_destroy_resource(&rdev->resource);
  790. return err;
  791. }
  792. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  793. {
  794. kfree(rdev->wr_log);
  795. c4iw_release_dev_ucontext(rdev, &rdev->uctx);
  796. free_page((unsigned long)rdev->status_page);
  797. c4iw_pblpool_destroy(rdev);
  798. c4iw_rqtpool_destroy(rdev);
  799. wait_for_completion(&rdev->pbl_compl);
  800. wait_for_completion(&rdev->rqt_compl);
  801. c4iw_ocqp_pool_destroy(rdev);
  802. destroy_workqueue(rdev->free_workq);
  803. c4iw_destroy_resource(&rdev->resource);
  804. }
  805. void c4iw_dealloc(struct uld_ctx *ctx)
  806. {
  807. c4iw_rdev_close(&ctx->dev->rdev);
  808. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
  809. idr_destroy(&ctx->dev->cqidr);
  810. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
  811. idr_destroy(&ctx->dev->qpidr);
  812. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
  813. idr_destroy(&ctx->dev->mmidr);
  814. wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
  815. idr_destroy(&ctx->dev->hwtid_idr);
  816. idr_destroy(&ctx->dev->stid_idr);
  817. idr_destroy(&ctx->dev->atid_idr);
  818. if (ctx->dev->rdev.bar2_kva)
  819. iounmap(ctx->dev->rdev.bar2_kva);
  820. if (ctx->dev->rdev.oc_mw_kva)
  821. iounmap(ctx->dev->rdev.oc_mw_kva);
  822. ib_dealloc_device(&ctx->dev->ibdev);
  823. ctx->dev = NULL;
  824. }
  825. static void c4iw_remove(struct uld_ctx *ctx)
  826. {
  827. pr_debug("c4iw_dev %p\n", ctx->dev);
  828. c4iw_unregister_device(ctx->dev);
  829. c4iw_dealloc(ctx);
  830. }
  831. static int rdma_supported(const struct cxgb4_lld_info *infop)
  832. {
  833. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  834. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  835. infop->vr->cq.size > 0;
  836. }
  837. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  838. {
  839. struct c4iw_dev *devp;
  840. int ret;
  841. if (!rdma_supported(infop)) {
  842. pr_info("%s: RDMA not supported on this device\n",
  843. pci_name(infop->pdev));
  844. return ERR_PTR(-ENOSYS);
  845. }
  846. if (!ocqp_supported(infop))
  847. pr_info("%s: On-Chip Queues not supported on this device\n",
  848. pci_name(infop->pdev));
  849. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  850. if (!devp) {
  851. pr_err("Cannot allocate ib device\n");
  852. return ERR_PTR(-ENOMEM);
  853. }
  854. devp->rdev.lldi = *infop;
  855. /* init various hw-queue params based on lld info */
  856. pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  857. devp->rdev.lldi.sge_ingpadboundary,
  858. devp->rdev.lldi.sge_egrstatuspagesize);
  859. devp->rdev.hw_queue.t4_eq_status_entries =
  860. devp->rdev.lldi.sge_egrstatuspagesize / 64;
  861. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  862. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  863. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  864. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  865. devp->rdev.hw_queue.t4_max_sq_size =
  866. devp->rdev.hw_queue.t4_max_eq_size -
  867. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  868. devp->rdev.hw_queue.t4_max_qp_depth =
  869. devp->rdev.hw_queue.t4_max_rq_size;
  870. devp->rdev.hw_queue.t4_max_cq_depth =
  871. devp->rdev.hw_queue.t4_max_iq_size - 2;
  872. devp->rdev.hw_queue.t4_stat_len =
  873. devp->rdev.lldi.sge_egrstatuspagesize;
  874. /*
  875. * For T5/T6 devices, we map all of BAR2 with WC.
  876. * For T4 devices with onchip qp mem, we map only that part
  877. * of BAR2 with WC.
  878. */
  879. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  880. if (!is_t4(devp->rdev.lldi.adapter_type)) {
  881. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  882. pci_resource_len(devp->rdev.lldi.pdev, 2));
  883. if (!devp->rdev.bar2_kva) {
  884. pr_err("Unable to ioremap BAR2\n");
  885. ib_dealloc_device(&devp->ibdev);
  886. return ERR_PTR(-EINVAL);
  887. }
  888. } else if (ocqp_supported(infop)) {
  889. devp->rdev.oc_mw_pa =
  890. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  891. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  892. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  893. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  894. devp->rdev.lldi.vr->ocq.size);
  895. if (!devp->rdev.oc_mw_kva) {
  896. pr_err("Unable to ioremap onchip mem\n");
  897. ib_dealloc_device(&devp->ibdev);
  898. return ERR_PTR(-EINVAL);
  899. }
  900. }
  901. pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  902. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  903. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  904. ret = c4iw_rdev_open(&devp->rdev);
  905. if (ret) {
  906. pr_err("Unable to open CXIO rdev err %d\n", ret);
  907. ib_dealloc_device(&devp->ibdev);
  908. return ERR_PTR(ret);
  909. }
  910. idr_init(&devp->cqidr);
  911. idr_init(&devp->qpidr);
  912. idr_init(&devp->mmidr);
  913. idr_init(&devp->hwtid_idr);
  914. idr_init(&devp->stid_idr);
  915. idr_init(&devp->atid_idr);
  916. spin_lock_init(&devp->lock);
  917. mutex_init(&devp->rdev.stats.lock);
  918. mutex_init(&devp->db_mutex);
  919. INIT_LIST_HEAD(&devp->db_fc_list);
  920. init_waitqueue_head(&devp->wait);
  921. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  922. if (c4iw_debugfs_root) {
  923. devp->debugfs_root = debugfs_create_dir(
  924. pci_name(devp->rdev.lldi.pdev),
  925. c4iw_debugfs_root);
  926. setup_debugfs(devp);
  927. }
  928. return devp;
  929. }
  930. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  931. {
  932. struct uld_ctx *ctx;
  933. static int vers_printed;
  934. int i;
  935. if (!vers_printed++)
  936. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  937. DRV_VERSION);
  938. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  939. if (!ctx) {
  940. ctx = ERR_PTR(-ENOMEM);
  941. goto out;
  942. }
  943. ctx->lldi = *infop;
  944. pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  945. pci_name(ctx->lldi.pdev),
  946. ctx->lldi.nchan, ctx->lldi.nrxq,
  947. ctx->lldi.ntxq, ctx->lldi.nports);
  948. mutex_lock(&dev_mutex);
  949. list_add_tail(&ctx->entry, &uld_ctx_list);
  950. mutex_unlock(&dev_mutex);
  951. for (i = 0; i < ctx->lldi.nrxq; i++)
  952. pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  953. out:
  954. return ctx;
  955. }
  956. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  957. const __be64 *rsp,
  958. u32 pktshift)
  959. {
  960. struct sk_buff *skb;
  961. /*
  962. * Allocate space for cpl_pass_accept_req which will be synthesized by
  963. * driver. Once the driver synthesizes the request the skb will go
  964. * through the regular cpl_pass_accept_req processing.
  965. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  966. * cpl_rx_pkt.
  967. */
  968. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  969. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  970. if (unlikely(!skb))
  971. return NULL;
  972. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  973. sizeof(struct rss_header) - pktshift);
  974. /*
  975. * This skb will contain:
  976. * rss_header from the rspq descriptor (1 flit)
  977. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  978. * space for the difference between the size of an
  979. * rx_pkt and pass_accept_req cpl (1 flit)
  980. * the packet data from the gl
  981. */
  982. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  983. sizeof(struct rss_header));
  984. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  985. sizeof(struct cpl_pass_accept_req),
  986. gl->va + pktshift,
  987. gl->tot_len - pktshift);
  988. return skb;
  989. }
  990. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  991. const __be64 *rsp)
  992. {
  993. unsigned int opcode = *(u8 *)rsp;
  994. struct sk_buff *skb;
  995. if (opcode != CPL_RX_PKT)
  996. goto out;
  997. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  998. if (skb == NULL)
  999. goto out;
  1000. if (c4iw_handlers[opcode] == NULL) {
  1001. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1002. kfree_skb(skb);
  1003. goto out;
  1004. }
  1005. c4iw_handlers[opcode](dev, skb);
  1006. return 1;
  1007. out:
  1008. return 0;
  1009. }
  1010. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  1011. const struct pkt_gl *gl)
  1012. {
  1013. struct uld_ctx *ctx = handle;
  1014. struct c4iw_dev *dev = ctx->dev;
  1015. struct sk_buff *skb;
  1016. u8 opcode;
  1017. if (gl == NULL) {
  1018. /* omit RSS and rsp_ctrl at end of descriptor */
  1019. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  1020. skb = alloc_skb(256, GFP_ATOMIC);
  1021. if (!skb)
  1022. goto nomem;
  1023. __skb_put(skb, len);
  1024. skb_copy_to_linear_data(skb, &rsp[1], len);
  1025. } else if (gl == CXGB4_MSG_AN) {
  1026. const struct rsp_ctrl *rc = (void *)rsp;
  1027. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1028. c4iw_ev_handler(dev, qid);
  1029. return 0;
  1030. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1031. if (recv_rx_pkt(dev, gl, rsp))
  1032. return 0;
  1033. pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
  1034. pci_name(ctx->lldi.pdev), gl->va,
  1035. be64_to_cpu(*rsp),
  1036. be64_to_cpu(*(__force __be64 *)gl->va),
  1037. gl->tot_len);
  1038. return 0;
  1039. } else {
  1040. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1041. if (unlikely(!skb))
  1042. goto nomem;
  1043. }
  1044. opcode = *(u8 *)rsp;
  1045. if (c4iw_handlers[opcode]) {
  1046. c4iw_handlers[opcode](dev, skb);
  1047. } else {
  1048. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1049. kfree_skb(skb);
  1050. }
  1051. return 0;
  1052. nomem:
  1053. return -1;
  1054. }
  1055. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1056. {
  1057. struct uld_ctx *ctx = handle;
  1058. pr_debug("new_state %u\n", new_state);
  1059. switch (new_state) {
  1060. case CXGB4_STATE_UP:
  1061. pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
  1062. if (!ctx->dev) {
  1063. ctx->dev = c4iw_alloc(&ctx->lldi);
  1064. if (IS_ERR(ctx->dev)) {
  1065. pr_err("%s: initialization failed: %ld\n",
  1066. pci_name(ctx->lldi.pdev),
  1067. PTR_ERR(ctx->dev));
  1068. ctx->dev = NULL;
  1069. break;
  1070. }
  1071. INIT_WORK(&ctx->reg_work, c4iw_register_device);
  1072. queue_work(reg_workq, &ctx->reg_work);
  1073. }
  1074. break;
  1075. case CXGB4_STATE_DOWN:
  1076. pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
  1077. if (ctx->dev)
  1078. c4iw_remove(ctx);
  1079. break;
  1080. case CXGB4_STATE_FATAL_ERROR:
  1081. case CXGB4_STATE_START_RECOVERY:
  1082. pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
  1083. if (ctx->dev) {
  1084. struct ib_event event;
  1085. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1086. memset(&event, 0, sizeof event);
  1087. event.event = IB_EVENT_DEVICE_FATAL;
  1088. event.device = &ctx->dev->ibdev;
  1089. ib_dispatch_event(&event);
  1090. c4iw_remove(ctx);
  1091. }
  1092. break;
  1093. case CXGB4_STATE_DETACH:
  1094. pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
  1095. if (ctx->dev)
  1096. c4iw_remove(ctx);
  1097. break;
  1098. }
  1099. return 0;
  1100. }
  1101. static int disable_qp_db(int id, void *p, void *data)
  1102. {
  1103. struct c4iw_qp *qp = p;
  1104. t4_disable_wq_db(&qp->wq);
  1105. return 0;
  1106. }
  1107. static void stop_queues(struct uld_ctx *ctx)
  1108. {
  1109. unsigned long flags;
  1110. spin_lock_irqsave(&ctx->dev->lock, flags);
  1111. ctx->dev->rdev.stats.db_state_transitions++;
  1112. ctx->dev->db_state = STOPPED;
  1113. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1114. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1115. else
  1116. ctx->dev->rdev.status_page->db_off = 1;
  1117. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1118. }
  1119. static int enable_qp_db(int id, void *p, void *data)
  1120. {
  1121. struct c4iw_qp *qp = p;
  1122. t4_enable_wq_db(&qp->wq);
  1123. return 0;
  1124. }
  1125. static void resume_rc_qp(struct c4iw_qp *qp)
  1126. {
  1127. spin_lock(&qp->lock);
  1128. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
  1129. qp->wq.sq.wq_pidx_inc = 0;
  1130. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
  1131. qp->wq.rq.wq_pidx_inc = 0;
  1132. spin_unlock(&qp->lock);
  1133. }
  1134. static void resume_a_chunk(struct uld_ctx *ctx)
  1135. {
  1136. int i;
  1137. struct c4iw_qp *qp;
  1138. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1139. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1140. db_fc_entry);
  1141. list_del_init(&qp->db_fc_entry);
  1142. resume_rc_qp(qp);
  1143. if (list_empty(&ctx->dev->db_fc_list))
  1144. break;
  1145. }
  1146. }
  1147. static void resume_queues(struct uld_ctx *ctx)
  1148. {
  1149. spin_lock_irq(&ctx->dev->lock);
  1150. if (ctx->dev->db_state != STOPPED)
  1151. goto out;
  1152. ctx->dev->db_state = FLOW_CONTROL;
  1153. while (1) {
  1154. if (list_empty(&ctx->dev->db_fc_list)) {
  1155. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1156. ctx->dev->db_state = NORMAL;
  1157. ctx->dev->rdev.stats.db_state_transitions++;
  1158. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1159. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1160. NULL);
  1161. } else {
  1162. ctx->dev->rdev.status_page->db_off = 0;
  1163. }
  1164. break;
  1165. } else {
  1166. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1167. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1168. DB_FC_DRAIN_THRESH)) {
  1169. resume_a_chunk(ctx);
  1170. }
  1171. if (!list_empty(&ctx->dev->db_fc_list)) {
  1172. spin_unlock_irq(&ctx->dev->lock);
  1173. if (DB_FC_RESUME_DELAY) {
  1174. set_current_state(TASK_UNINTERRUPTIBLE);
  1175. schedule_timeout(DB_FC_RESUME_DELAY);
  1176. }
  1177. spin_lock_irq(&ctx->dev->lock);
  1178. if (ctx->dev->db_state != FLOW_CONTROL)
  1179. break;
  1180. }
  1181. }
  1182. }
  1183. out:
  1184. if (ctx->dev->db_state != NORMAL)
  1185. ctx->dev->rdev.stats.db_fc_interruptions++;
  1186. spin_unlock_irq(&ctx->dev->lock);
  1187. }
  1188. struct qp_list {
  1189. unsigned idx;
  1190. struct c4iw_qp **qps;
  1191. };
  1192. static int add_and_ref_qp(int id, void *p, void *data)
  1193. {
  1194. struct qp_list *qp_listp = data;
  1195. struct c4iw_qp *qp = p;
  1196. c4iw_qp_add_ref(&qp->ibqp);
  1197. qp_listp->qps[qp_listp->idx++] = qp;
  1198. return 0;
  1199. }
  1200. static int count_qps(int id, void *p, void *data)
  1201. {
  1202. unsigned *countp = data;
  1203. (*countp)++;
  1204. return 0;
  1205. }
  1206. static void deref_qps(struct qp_list *qp_list)
  1207. {
  1208. int idx;
  1209. for (idx = 0; idx < qp_list->idx; idx++)
  1210. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1211. }
  1212. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1213. {
  1214. int idx;
  1215. int ret;
  1216. for (idx = 0; idx < qp_list->idx; idx++) {
  1217. struct c4iw_qp *qp = qp_list->qps[idx];
  1218. spin_lock_irq(&qp->rhp->lock);
  1219. spin_lock(&qp->lock);
  1220. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1221. qp->wq.sq.qid,
  1222. t4_sq_host_wq_pidx(&qp->wq),
  1223. t4_sq_wq_size(&qp->wq));
  1224. if (ret) {
  1225. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
  1226. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1227. spin_unlock(&qp->lock);
  1228. spin_unlock_irq(&qp->rhp->lock);
  1229. return;
  1230. }
  1231. qp->wq.sq.wq_pidx_inc = 0;
  1232. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1233. qp->wq.rq.qid,
  1234. t4_rq_host_wq_pidx(&qp->wq),
  1235. t4_rq_wq_size(&qp->wq));
  1236. if (ret) {
  1237. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
  1238. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1239. spin_unlock(&qp->lock);
  1240. spin_unlock_irq(&qp->rhp->lock);
  1241. return;
  1242. }
  1243. qp->wq.rq.wq_pidx_inc = 0;
  1244. spin_unlock(&qp->lock);
  1245. spin_unlock_irq(&qp->rhp->lock);
  1246. /* Wait for the dbfifo to drain */
  1247. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1248. set_current_state(TASK_UNINTERRUPTIBLE);
  1249. schedule_timeout(usecs_to_jiffies(10));
  1250. }
  1251. }
  1252. }
  1253. static void recover_queues(struct uld_ctx *ctx)
  1254. {
  1255. int count = 0;
  1256. struct qp_list qp_list;
  1257. int ret;
  1258. /* slow everybody down */
  1259. set_current_state(TASK_UNINTERRUPTIBLE);
  1260. schedule_timeout(usecs_to_jiffies(1000));
  1261. /* flush the SGE contexts */
  1262. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1263. if (ret) {
  1264. pr_err("%s: Fatal error - DB overflow recovery failed\n",
  1265. pci_name(ctx->lldi.pdev));
  1266. return;
  1267. }
  1268. /* Count active queues so we can build a list of queues to recover */
  1269. spin_lock_irq(&ctx->dev->lock);
  1270. WARN_ON(ctx->dev->db_state != STOPPED);
  1271. ctx->dev->db_state = RECOVERY;
  1272. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1273. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1274. if (!qp_list.qps) {
  1275. spin_unlock_irq(&ctx->dev->lock);
  1276. return;
  1277. }
  1278. qp_list.idx = 0;
  1279. /* add and ref each qp so it doesn't get freed */
  1280. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1281. spin_unlock_irq(&ctx->dev->lock);
  1282. /* now traverse the list in a safe context to recover the db state*/
  1283. recover_lost_dbs(ctx, &qp_list);
  1284. /* we're almost done! deref the qps and clean up */
  1285. deref_qps(&qp_list);
  1286. kfree(qp_list.qps);
  1287. spin_lock_irq(&ctx->dev->lock);
  1288. WARN_ON(ctx->dev->db_state != RECOVERY);
  1289. ctx->dev->db_state = STOPPED;
  1290. spin_unlock_irq(&ctx->dev->lock);
  1291. }
  1292. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1293. {
  1294. struct uld_ctx *ctx = handle;
  1295. switch (control) {
  1296. case CXGB4_CONTROL_DB_FULL:
  1297. stop_queues(ctx);
  1298. ctx->dev->rdev.stats.db_full++;
  1299. break;
  1300. case CXGB4_CONTROL_DB_EMPTY:
  1301. resume_queues(ctx);
  1302. mutex_lock(&ctx->dev->rdev.stats.lock);
  1303. ctx->dev->rdev.stats.db_empty++;
  1304. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1305. break;
  1306. case CXGB4_CONTROL_DB_DROP:
  1307. recover_queues(ctx);
  1308. mutex_lock(&ctx->dev->rdev.stats.lock);
  1309. ctx->dev->rdev.stats.db_drop++;
  1310. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1311. break;
  1312. default:
  1313. pr_warn("%s: unknown control cmd %u\n",
  1314. pci_name(ctx->lldi.pdev), control);
  1315. break;
  1316. }
  1317. return 0;
  1318. }
  1319. static struct cxgb4_uld_info c4iw_uld_info = {
  1320. .name = DRV_NAME,
  1321. .nrxq = MAX_ULD_QSETS,
  1322. .ntxq = MAX_ULD_QSETS,
  1323. .rxq_size = 511,
  1324. .ciq = true,
  1325. .lro = false,
  1326. .add = c4iw_uld_add,
  1327. .rx_handler = c4iw_uld_rx_handler,
  1328. .state_change = c4iw_uld_state_change,
  1329. .control = c4iw_uld_control,
  1330. };
  1331. void _c4iw_free_wr_wait(struct kref *kref)
  1332. {
  1333. struct c4iw_wr_wait *wr_waitp;
  1334. wr_waitp = container_of(kref, struct c4iw_wr_wait, kref);
  1335. pr_debug("Free wr_wait %p\n", wr_waitp);
  1336. kfree(wr_waitp);
  1337. }
  1338. struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp)
  1339. {
  1340. struct c4iw_wr_wait *wr_waitp;
  1341. wr_waitp = kzalloc(sizeof(*wr_waitp), gfp);
  1342. if (wr_waitp) {
  1343. kref_init(&wr_waitp->kref);
  1344. pr_debug("wr_wait %p\n", wr_waitp);
  1345. }
  1346. return wr_waitp;
  1347. }
  1348. static int __init c4iw_init_module(void)
  1349. {
  1350. int err;
  1351. err = c4iw_cm_init();
  1352. if (err)
  1353. return err;
  1354. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1355. if (!c4iw_debugfs_root)
  1356. pr_warn("could not create debugfs entry, continuing\n");
  1357. reg_workq = create_singlethread_workqueue("Register_iWARP_device");
  1358. if (!reg_workq) {
  1359. pr_err("Failed creating workqueue to register iwarp device\n");
  1360. return -ENOMEM;
  1361. }
  1362. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1363. return 0;
  1364. }
  1365. static void __exit c4iw_exit_module(void)
  1366. {
  1367. struct uld_ctx *ctx, *tmp;
  1368. mutex_lock(&dev_mutex);
  1369. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1370. if (ctx->dev)
  1371. c4iw_remove(ctx);
  1372. kfree(ctx);
  1373. }
  1374. mutex_unlock(&dev_mutex);
  1375. flush_workqueue(reg_workq);
  1376. destroy_workqueue(reg_workq);
  1377. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1378. c4iw_cm_term();
  1379. debugfs_remove_recursive(c4iw_debugfs_root);
  1380. }
  1381. module_init(c4iw_init_module);
  1382. module_exit(c4iw_exit_module);