i2c-qup.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2014, Sony Mobile Communications AB.
  5. *
  6. */
  7. #include <linux/acpi.h>
  8. #include <linux/atomic.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/err.h>
  15. #include <linux/i2c.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/scatterlist.h>
  23. /* QUP Registers */
  24. #define QUP_CONFIG 0x000
  25. #define QUP_STATE 0x004
  26. #define QUP_IO_MODE 0x008
  27. #define QUP_SW_RESET 0x00c
  28. #define QUP_OPERATIONAL 0x018
  29. #define QUP_ERROR_FLAGS 0x01c
  30. #define QUP_ERROR_FLAGS_EN 0x020
  31. #define QUP_OPERATIONAL_MASK 0x028
  32. #define QUP_HW_VERSION 0x030
  33. #define QUP_MX_OUTPUT_CNT 0x100
  34. #define QUP_OUT_FIFO_BASE 0x110
  35. #define QUP_MX_WRITE_CNT 0x150
  36. #define QUP_MX_INPUT_CNT 0x200
  37. #define QUP_MX_READ_CNT 0x208
  38. #define QUP_IN_FIFO_BASE 0x218
  39. #define QUP_I2C_CLK_CTL 0x400
  40. #define QUP_I2C_STATUS 0x404
  41. #define QUP_I2C_MASTER_GEN 0x408
  42. /* QUP States and reset values */
  43. #define QUP_RESET_STATE 0
  44. #define QUP_RUN_STATE 1
  45. #define QUP_PAUSE_STATE 3
  46. #define QUP_STATE_MASK 3
  47. #define QUP_STATE_VALID BIT(2)
  48. #define QUP_I2C_MAST_GEN BIT(4)
  49. #define QUP_I2C_FLUSH BIT(6)
  50. #define QUP_OPERATIONAL_RESET 0x000ff0
  51. #define QUP_I2C_STATUS_RESET 0xfffffc
  52. /* QUP OPERATIONAL FLAGS */
  53. #define QUP_I2C_NACK_FLAG BIT(3)
  54. #define QUP_OUT_NOT_EMPTY BIT(4)
  55. #define QUP_IN_NOT_EMPTY BIT(5)
  56. #define QUP_OUT_FULL BIT(6)
  57. #define QUP_OUT_SVC_FLAG BIT(8)
  58. #define QUP_IN_SVC_FLAG BIT(9)
  59. #define QUP_MX_OUTPUT_DONE BIT(10)
  60. #define QUP_MX_INPUT_DONE BIT(11)
  61. #define OUT_BLOCK_WRITE_REQ BIT(12)
  62. #define IN_BLOCK_READ_REQ BIT(13)
  63. /* I2C mini core related values */
  64. #define QUP_NO_INPUT BIT(7)
  65. #define QUP_CLOCK_AUTO_GATE BIT(13)
  66. #define I2C_MINI_CORE (2 << 8)
  67. #define I2C_N_VAL 15
  68. #define I2C_N_VAL_V2 7
  69. /* Most significant word offset in FIFO port */
  70. #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
  71. /* Packing/Unpacking words in FIFOs, and IO modes */
  72. #define QUP_OUTPUT_BLK_MODE (1 << 10)
  73. #define QUP_OUTPUT_BAM_MODE (3 << 10)
  74. #define QUP_INPUT_BLK_MODE (1 << 12)
  75. #define QUP_INPUT_BAM_MODE (3 << 12)
  76. #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
  77. #define QUP_UNPACK_EN BIT(14)
  78. #define QUP_PACK_EN BIT(15)
  79. #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
  80. #define QUP_V2_TAGS_EN 1
  81. #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
  82. #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
  83. #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
  84. #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
  85. /* QUP tags */
  86. #define QUP_TAG_START (1 << 8)
  87. #define QUP_TAG_DATA (2 << 8)
  88. #define QUP_TAG_STOP (3 << 8)
  89. #define QUP_TAG_REC (4 << 8)
  90. #define QUP_BAM_INPUT_EOT 0x93
  91. #define QUP_BAM_FLUSH_STOP 0x96
  92. /* QUP v2 tags */
  93. #define QUP_TAG_V2_START 0x81
  94. #define QUP_TAG_V2_DATAWR 0x82
  95. #define QUP_TAG_V2_DATAWR_STOP 0x83
  96. #define QUP_TAG_V2_DATARD 0x85
  97. #define QUP_TAG_V2_DATARD_NACK 0x86
  98. #define QUP_TAG_V2_DATARD_STOP 0x87
  99. /* Status, Error flags */
  100. #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
  101. #define I2C_STATUS_BUS_ACTIVE BIT(8)
  102. #define I2C_STATUS_ERROR_MASK 0x38000fc
  103. #define QUP_STATUS_ERROR_FLAGS 0x7c
  104. #define QUP_READ_LIMIT 256
  105. #define SET_BIT 0x1
  106. #define RESET_BIT 0x0
  107. #define ONE_BYTE 0x1
  108. #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
  109. /* Maximum transfer length for single DMA descriptor */
  110. #define MX_TX_RX_LEN SZ_64K
  111. #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
  112. /* Maximum transfer length for all DMA descriptors */
  113. #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
  114. #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
  115. /*
  116. * Minimum transfer timeout for i2c transfers in seconds. It will be added on
  117. * the top of maximum transfer time calculated from i2c bus speed to compensate
  118. * the overheads.
  119. */
  120. #define TOUT_MIN 2
  121. /* Default values. Use these if FW query fails */
  122. #define DEFAULT_CLK_FREQ 100000
  123. #define DEFAULT_SRC_CLK 20000000
  124. /*
  125. * Max tags length (start, stop and maximum 2 bytes address) for each QUP
  126. * data transfer
  127. */
  128. #define QUP_MAX_TAGS_LEN 4
  129. /* Max data length for each DATARD tags */
  130. #define RECV_MAX_DATA_LEN 254
  131. /* TAG length for DATA READ in RX FIFO */
  132. #define READ_RX_TAGS_LEN 2
  133. /*
  134. * count: no of blocks
  135. * pos: current block number
  136. * tx_tag_len: tx tag length for current block
  137. * rx_tag_len: rx tag length for current block
  138. * data_len: remaining data length for current message
  139. * cur_blk_len: data length for current block
  140. * total_tx_len: total tx length including tag bytes for current QUP transfer
  141. * total_rx_len: total rx length including tag bytes for current QUP transfer
  142. * tx_fifo_data_pos: current byte number in TX FIFO word
  143. * tx_fifo_free: number of free bytes in current QUP block write.
  144. * rx_fifo_data_pos: current byte number in RX FIFO word
  145. * fifo_available: number of available bytes in RX FIFO for current
  146. * QUP block read
  147. * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
  148. * to TX FIFO will be appended in this data and will be written to
  149. * TX FIFO when all the 4 bytes are available.
  150. * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
  151. * contains the 4 bytes of RX data.
  152. * cur_data: pointer to tell cur data position for current message
  153. * cur_tx_tags: pointer to tell cur position in tags
  154. * tx_tags_sent: all tx tag bytes have been written in FIFO word
  155. * send_last_word: for tx FIFO, last word send is pending in current block
  156. * rx_bytes_read: if all the bytes have been read from rx FIFO.
  157. * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
  158. * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
  159. * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
  160. * tags: contains tx tag bytes for current QUP transfer
  161. */
  162. struct qup_i2c_block {
  163. int count;
  164. int pos;
  165. int tx_tag_len;
  166. int rx_tag_len;
  167. int data_len;
  168. int cur_blk_len;
  169. int total_tx_len;
  170. int total_rx_len;
  171. int tx_fifo_data_pos;
  172. int tx_fifo_free;
  173. int rx_fifo_data_pos;
  174. int fifo_available;
  175. u32 tx_fifo_data;
  176. u32 rx_fifo_data;
  177. u8 *cur_data;
  178. u8 *cur_tx_tags;
  179. bool tx_tags_sent;
  180. bool send_last_word;
  181. bool rx_tags_fetched;
  182. bool rx_bytes_read;
  183. bool is_tx_blk_mode;
  184. bool is_rx_blk_mode;
  185. u8 tags[6];
  186. };
  187. struct qup_i2c_tag {
  188. u8 *start;
  189. dma_addr_t addr;
  190. };
  191. struct qup_i2c_bam {
  192. struct qup_i2c_tag tag;
  193. struct dma_chan *dma;
  194. struct scatterlist *sg;
  195. unsigned int sg_cnt;
  196. };
  197. struct qup_i2c_dev {
  198. struct device *dev;
  199. void __iomem *base;
  200. int irq;
  201. struct clk *clk;
  202. struct clk *pclk;
  203. struct i2c_adapter adap;
  204. int clk_ctl;
  205. int out_fifo_sz;
  206. int in_fifo_sz;
  207. int out_blk_sz;
  208. int in_blk_sz;
  209. int blk_xfer_limit;
  210. unsigned long one_byte_t;
  211. unsigned long xfer_timeout;
  212. struct qup_i2c_block blk;
  213. struct i2c_msg *msg;
  214. /* Current posion in user message buffer */
  215. int pos;
  216. /* I2C protocol errors */
  217. u32 bus_err;
  218. /* QUP core errors */
  219. u32 qup_err;
  220. /* To check if this is the last msg */
  221. bool is_last;
  222. bool is_smbus_read;
  223. /* To configure when bus is in run state */
  224. u32 config_run;
  225. /* dma parameters */
  226. bool is_dma;
  227. /* To check if the current transfer is using DMA */
  228. bool use_dma;
  229. unsigned int max_xfer_sg_len;
  230. unsigned int tag_buf_pos;
  231. /* The threshold length above which block mode will be used */
  232. unsigned int blk_mode_threshold;
  233. struct dma_pool *dpool;
  234. struct qup_i2c_tag start_tag;
  235. struct qup_i2c_bam brx;
  236. struct qup_i2c_bam btx;
  237. struct completion xfer;
  238. /* function to write data in tx fifo */
  239. void (*write_tx_fifo)(struct qup_i2c_dev *qup);
  240. /* function to read data from rx fifo */
  241. void (*read_rx_fifo)(struct qup_i2c_dev *qup);
  242. /* function to write tags in tx fifo for i2c read transfer */
  243. void (*write_rx_tags)(struct qup_i2c_dev *qup);
  244. };
  245. static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
  246. {
  247. struct qup_i2c_dev *qup = dev;
  248. struct qup_i2c_block *blk = &qup->blk;
  249. u32 bus_err;
  250. u32 qup_err;
  251. u32 opflags;
  252. bus_err = readl(qup->base + QUP_I2C_STATUS);
  253. qup_err = readl(qup->base + QUP_ERROR_FLAGS);
  254. opflags = readl(qup->base + QUP_OPERATIONAL);
  255. if (!qup->msg) {
  256. /* Clear Error interrupt */
  257. writel(QUP_RESET_STATE, qup->base + QUP_STATE);
  258. return IRQ_HANDLED;
  259. }
  260. bus_err &= I2C_STATUS_ERROR_MASK;
  261. qup_err &= QUP_STATUS_ERROR_FLAGS;
  262. /* Clear the error bits in QUP_ERROR_FLAGS */
  263. if (qup_err)
  264. writel(qup_err, qup->base + QUP_ERROR_FLAGS);
  265. /* Clear the error bits in QUP_I2C_STATUS */
  266. if (bus_err)
  267. writel(bus_err, qup->base + QUP_I2C_STATUS);
  268. /*
  269. * Check for BAM mode and returns if already error has come for current
  270. * transfer. In Error case, sometimes, QUP generates more than one
  271. * interrupt.
  272. */
  273. if (qup->use_dma && (qup->qup_err || qup->bus_err))
  274. return IRQ_HANDLED;
  275. /* Reset the QUP State in case of error */
  276. if (qup_err || bus_err) {
  277. /*
  278. * Don’t reset the QUP state in case of BAM mode. The BAM
  279. * flush operation needs to be scheduled in transfer function
  280. * which will clear the remaining schedule descriptors in BAM
  281. * HW FIFO and generates the BAM interrupt.
  282. */
  283. if (!qup->use_dma)
  284. writel(QUP_RESET_STATE, qup->base + QUP_STATE);
  285. goto done;
  286. }
  287. if (opflags & QUP_OUT_SVC_FLAG) {
  288. writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
  289. if (opflags & OUT_BLOCK_WRITE_REQ) {
  290. blk->tx_fifo_free += qup->out_blk_sz;
  291. if (qup->msg->flags & I2C_M_RD)
  292. qup->write_rx_tags(qup);
  293. else
  294. qup->write_tx_fifo(qup);
  295. }
  296. }
  297. if (opflags & QUP_IN_SVC_FLAG) {
  298. writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
  299. if (!blk->is_rx_blk_mode) {
  300. blk->fifo_available += qup->in_fifo_sz;
  301. qup->read_rx_fifo(qup);
  302. } else if (opflags & IN_BLOCK_READ_REQ) {
  303. blk->fifo_available += qup->in_blk_sz;
  304. qup->read_rx_fifo(qup);
  305. }
  306. }
  307. if (qup->msg->flags & I2C_M_RD) {
  308. if (!blk->rx_bytes_read)
  309. return IRQ_HANDLED;
  310. } else {
  311. /*
  312. * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
  313. * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
  314. * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
  315. * of interrupt for write message in FIFO mode is
  316. * QUP_MAX_OUTPUT_DONE_FLAG condition.
  317. */
  318. if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
  319. return IRQ_HANDLED;
  320. }
  321. done:
  322. qup->qup_err = qup_err;
  323. qup->bus_err = bus_err;
  324. complete(&qup->xfer);
  325. return IRQ_HANDLED;
  326. }
  327. static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
  328. u32 req_state, u32 req_mask)
  329. {
  330. int retries = 1;
  331. u32 state;
  332. /*
  333. * State transition takes 3 AHB clocks cycles + 3 I2C master clock
  334. * cycles. So retry once after a 1uS delay.
  335. */
  336. do {
  337. state = readl(qup->base + QUP_STATE);
  338. if (state & QUP_STATE_VALID &&
  339. (state & req_mask) == req_state)
  340. return 0;
  341. udelay(1);
  342. } while (retries--);
  343. return -ETIMEDOUT;
  344. }
  345. static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
  346. {
  347. return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
  348. }
  349. static void qup_i2c_flush(struct qup_i2c_dev *qup)
  350. {
  351. u32 val = readl(qup->base + QUP_STATE);
  352. val |= QUP_I2C_FLUSH;
  353. writel(val, qup->base + QUP_STATE);
  354. }
  355. static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
  356. {
  357. return qup_i2c_poll_state_mask(qup, 0, 0);
  358. }
  359. static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
  360. {
  361. return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
  362. }
  363. static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
  364. {
  365. if (qup_i2c_poll_state_valid(qup) != 0)
  366. return -EIO;
  367. writel(state, qup->base + QUP_STATE);
  368. if (qup_i2c_poll_state(qup, state) != 0)
  369. return -EIO;
  370. return 0;
  371. }
  372. /* Check if I2C bus returns to IDLE state */
  373. static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
  374. {
  375. unsigned long timeout;
  376. u32 status;
  377. int ret = 0;
  378. timeout = jiffies + len * 4;
  379. for (;;) {
  380. status = readl(qup->base + QUP_I2C_STATUS);
  381. if (!(status & I2C_STATUS_BUS_ACTIVE))
  382. break;
  383. if (time_after(jiffies, timeout))
  384. ret = -ETIMEDOUT;
  385. usleep_range(len, len * 2);
  386. }
  387. return ret;
  388. }
  389. static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
  390. {
  391. struct qup_i2c_block *blk = &qup->blk;
  392. struct i2c_msg *msg = qup->msg;
  393. u32 addr = msg->addr << 1;
  394. u32 qup_tag;
  395. int idx;
  396. u32 val;
  397. if (qup->pos == 0) {
  398. val = QUP_TAG_START | addr;
  399. idx = 1;
  400. blk->tx_fifo_free--;
  401. } else {
  402. val = 0;
  403. idx = 0;
  404. }
  405. while (blk->tx_fifo_free && qup->pos < msg->len) {
  406. if (qup->pos == msg->len - 1)
  407. qup_tag = QUP_TAG_STOP;
  408. else
  409. qup_tag = QUP_TAG_DATA;
  410. if (idx & 1)
  411. val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
  412. else
  413. val = qup_tag | msg->buf[qup->pos];
  414. /* Write out the pair and the last odd value */
  415. if (idx & 1 || qup->pos == msg->len - 1)
  416. writel(val, qup->base + QUP_OUT_FIFO_BASE);
  417. qup->pos++;
  418. idx++;
  419. blk->tx_fifo_free--;
  420. }
  421. }
  422. static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
  423. struct i2c_msg *msg)
  424. {
  425. qup->blk.pos = 0;
  426. qup->blk.data_len = msg->len;
  427. qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
  428. }
  429. static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
  430. {
  431. int data_len;
  432. if (qup->blk.data_len > qup->blk_xfer_limit)
  433. data_len = qup->blk_xfer_limit;
  434. else
  435. data_len = qup->blk.data_len;
  436. return data_len;
  437. }
  438. static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
  439. {
  440. return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
  441. }
  442. static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
  443. struct i2c_msg *msg)
  444. {
  445. int len = 0;
  446. if (qup->is_smbus_read) {
  447. tags[len++] = QUP_TAG_V2_DATARD_STOP;
  448. tags[len++] = qup_i2c_get_data_len(qup);
  449. } else {
  450. tags[len++] = QUP_TAG_V2_START;
  451. tags[len++] = addr & 0xff;
  452. if (msg->flags & I2C_M_TEN)
  453. tags[len++] = addr >> 8;
  454. tags[len++] = QUP_TAG_V2_DATARD;
  455. /* Read 1 byte indicating the length of the SMBus message */
  456. tags[len++] = 1;
  457. }
  458. return len;
  459. }
  460. static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
  461. struct i2c_msg *msg)
  462. {
  463. u16 addr = i2c_8bit_addr_from_msg(msg);
  464. int len = 0;
  465. int data_len;
  466. int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
  467. /* Handle tags for SMBus block read */
  468. if (qup_i2c_check_msg_len(msg))
  469. return qup_i2c_set_tags_smb(addr, tags, qup, msg);
  470. if (qup->blk.pos == 0) {
  471. tags[len++] = QUP_TAG_V2_START;
  472. tags[len++] = addr & 0xff;
  473. if (msg->flags & I2C_M_TEN)
  474. tags[len++] = addr >> 8;
  475. }
  476. /* Send _STOP commands for the last block */
  477. if (last) {
  478. if (msg->flags & I2C_M_RD)
  479. tags[len++] = QUP_TAG_V2_DATARD_STOP;
  480. else
  481. tags[len++] = QUP_TAG_V2_DATAWR_STOP;
  482. } else {
  483. if (msg->flags & I2C_M_RD)
  484. tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
  485. QUP_TAG_V2_DATARD_NACK :
  486. QUP_TAG_V2_DATARD;
  487. else
  488. tags[len++] = QUP_TAG_V2_DATAWR;
  489. }
  490. data_len = qup_i2c_get_data_len(qup);
  491. /* 0 implies 256 bytes */
  492. if (data_len == QUP_READ_LIMIT)
  493. tags[len++] = 0;
  494. else
  495. tags[len++] = data_len;
  496. return len;
  497. }
  498. static void qup_i2c_bam_cb(void *data)
  499. {
  500. struct qup_i2c_dev *qup = data;
  501. complete(&qup->xfer);
  502. }
  503. static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
  504. unsigned int buflen, struct qup_i2c_dev *qup,
  505. int dir)
  506. {
  507. int ret;
  508. sg_set_buf(sg, buf, buflen);
  509. ret = dma_map_sg(qup->dev, sg, 1, dir);
  510. if (!ret)
  511. return -EINVAL;
  512. return 0;
  513. }
  514. static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
  515. {
  516. if (qup->btx.dma)
  517. dma_release_channel(qup->btx.dma);
  518. if (qup->brx.dma)
  519. dma_release_channel(qup->brx.dma);
  520. qup->btx.dma = NULL;
  521. qup->brx.dma = NULL;
  522. }
  523. static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
  524. {
  525. int err;
  526. if (!qup->btx.dma) {
  527. qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
  528. if (IS_ERR(qup->btx.dma)) {
  529. err = PTR_ERR(qup->btx.dma);
  530. qup->btx.dma = NULL;
  531. dev_err(qup->dev, "\n tx channel not available");
  532. return err;
  533. }
  534. }
  535. if (!qup->brx.dma) {
  536. qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
  537. if (IS_ERR(qup->brx.dma)) {
  538. dev_err(qup->dev, "\n rx channel not available");
  539. err = PTR_ERR(qup->brx.dma);
  540. qup->brx.dma = NULL;
  541. qup_i2c_rel_dma(qup);
  542. return err;
  543. }
  544. }
  545. return 0;
  546. }
  547. static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
  548. {
  549. int ret = 0, limit = QUP_READ_LIMIT;
  550. u32 len = 0, blocks, rem;
  551. u32 i = 0, tlen, tx_len = 0;
  552. u8 *tags;
  553. qup->blk_xfer_limit = QUP_READ_LIMIT;
  554. qup_i2c_set_blk_data(qup, msg);
  555. blocks = qup->blk.count;
  556. rem = msg->len - (blocks - 1) * limit;
  557. if (msg->flags & I2C_M_RD) {
  558. while (qup->blk.pos < blocks) {
  559. tlen = (i == (blocks - 1)) ? rem : limit;
  560. tags = &qup->start_tag.start[qup->tag_buf_pos + len];
  561. len += qup_i2c_set_tags(tags, qup, msg);
  562. qup->blk.data_len -= tlen;
  563. /* scratch buf to read the start and len tags */
  564. ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
  565. &qup->brx.tag.start[0],
  566. 2, qup, DMA_FROM_DEVICE);
  567. if (ret)
  568. return ret;
  569. ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
  570. &msg->buf[limit * i],
  571. tlen, qup,
  572. DMA_FROM_DEVICE);
  573. if (ret)
  574. return ret;
  575. i++;
  576. qup->blk.pos = i;
  577. }
  578. ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
  579. &qup->start_tag.start[qup->tag_buf_pos],
  580. len, qup, DMA_TO_DEVICE);
  581. if (ret)
  582. return ret;
  583. qup->tag_buf_pos += len;
  584. } else {
  585. while (qup->blk.pos < blocks) {
  586. tlen = (i == (blocks - 1)) ? rem : limit;
  587. tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
  588. len = qup_i2c_set_tags(tags, qup, msg);
  589. qup->blk.data_len -= tlen;
  590. ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
  591. tags, len,
  592. qup, DMA_TO_DEVICE);
  593. if (ret)
  594. return ret;
  595. tx_len += len;
  596. ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
  597. &msg->buf[limit * i],
  598. tlen, qup, DMA_TO_DEVICE);
  599. if (ret)
  600. return ret;
  601. i++;
  602. qup->blk.pos = i;
  603. }
  604. qup->tag_buf_pos += tx_len;
  605. }
  606. return 0;
  607. }
  608. static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
  609. {
  610. struct dma_async_tx_descriptor *txd, *rxd = NULL;
  611. int ret = 0;
  612. dma_cookie_t cookie_rx, cookie_tx;
  613. u32 len = 0;
  614. u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
  615. /* schedule the EOT and FLUSH I2C tags */
  616. len = 1;
  617. if (rx_cnt) {
  618. qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
  619. len++;
  620. /* scratch buf to read the BAM EOT FLUSH tags */
  621. ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
  622. &qup->brx.tag.start[0],
  623. 1, qup, DMA_FROM_DEVICE);
  624. if (ret)
  625. return ret;
  626. }
  627. qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
  628. ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
  629. len, qup, DMA_TO_DEVICE);
  630. if (ret)
  631. return ret;
  632. txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
  633. DMA_MEM_TO_DEV,
  634. DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
  635. if (!txd) {
  636. dev_err(qup->dev, "failed to get tx desc\n");
  637. ret = -EINVAL;
  638. goto desc_err;
  639. }
  640. if (!rx_cnt) {
  641. txd->callback = qup_i2c_bam_cb;
  642. txd->callback_param = qup;
  643. }
  644. cookie_tx = dmaengine_submit(txd);
  645. if (dma_submit_error(cookie_tx)) {
  646. ret = -EINVAL;
  647. goto desc_err;
  648. }
  649. dma_async_issue_pending(qup->btx.dma);
  650. if (rx_cnt) {
  651. rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
  652. rx_cnt, DMA_DEV_TO_MEM,
  653. DMA_PREP_INTERRUPT);
  654. if (!rxd) {
  655. dev_err(qup->dev, "failed to get rx desc\n");
  656. ret = -EINVAL;
  657. /* abort TX descriptors */
  658. dmaengine_terminate_all(qup->btx.dma);
  659. goto desc_err;
  660. }
  661. rxd->callback = qup_i2c_bam_cb;
  662. rxd->callback_param = qup;
  663. cookie_rx = dmaengine_submit(rxd);
  664. if (dma_submit_error(cookie_rx)) {
  665. ret = -EINVAL;
  666. goto desc_err;
  667. }
  668. dma_async_issue_pending(qup->brx.dma);
  669. }
  670. if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
  671. dev_err(qup->dev, "normal trans timed out\n");
  672. ret = -ETIMEDOUT;
  673. }
  674. if (ret || qup->bus_err || qup->qup_err) {
  675. reinit_completion(&qup->xfer);
  676. if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
  677. dev_err(qup->dev, "change to run state timed out");
  678. goto desc_err;
  679. }
  680. qup_i2c_flush(qup);
  681. /* wait for remaining interrupts to occur */
  682. if (!wait_for_completion_timeout(&qup->xfer, HZ))
  683. dev_err(qup->dev, "flush timed out\n");
  684. ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
  685. }
  686. desc_err:
  687. dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
  688. if (rx_cnt)
  689. dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
  690. DMA_FROM_DEVICE);
  691. return ret;
  692. }
  693. static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
  694. {
  695. qup->btx.sg_cnt = 0;
  696. qup->brx.sg_cnt = 0;
  697. qup->tag_buf_pos = 0;
  698. }
  699. static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
  700. int num)
  701. {
  702. struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
  703. int ret = 0;
  704. int idx = 0;
  705. enable_irq(qup->irq);
  706. ret = qup_i2c_req_dma(qup);
  707. if (ret)
  708. goto out;
  709. writel(0, qup->base + QUP_MX_INPUT_CNT);
  710. writel(0, qup->base + QUP_MX_OUTPUT_CNT);
  711. /* set BAM mode */
  712. writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
  713. /* mask fifo irqs */
  714. writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
  715. /* set RUN STATE */
  716. ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
  717. if (ret)
  718. goto out;
  719. writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
  720. qup_i2c_bam_clear_tag_buffers(qup);
  721. for (idx = 0; idx < num; idx++) {
  722. qup->msg = msg + idx;
  723. qup->is_last = idx == (num - 1);
  724. ret = qup_i2c_bam_make_desc(qup, qup->msg);
  725. if (ret)
  726. break;
  727. /*
  728. * Make DMA descriptor and schedule the BAM transfer if its
  729. * already crossed the maximum length. Since the memory for all
  730. * tags buffers have been taken for 2 maximum possible
  731. * transfers length so it will never cross the buffer actual
  732. * length.
  733. */
  734. if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
  735. qup->brx.sg_cnt > qup->max_xfer_sg_len ||
  736. qup->is_last) {
  737. ret = qup_i2c_bam_schedule_desc(qup);
  738. if (ret)
  739. break;
  740. qup_i2c_bam_clear_tag_buffers(qup);
  741. }
  742. }
  743. out:
  744. disable_irq(qup->irq);
  745. qup->msg = NULL;
  746. return ret;
  747. }
  748. static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
  749. struct i2c_msg *msg)
  750. {
  751. unsigned long left;
  752. int ret = 0;
  753. left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
  754. if (!left) {
  755. writel(1, qup->base + QUP_SW_RESET);
  756. ret = -ETIMEDOUT;
  757. }
  758. if (qup->bus_err || qup->qup_err)
  759. ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
  760. return ret;
  761. }
  762. static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
  763. {
  764. struct qup_i2c_block *blk = &qup->blk;
  765. struct i2c_msg *msg = qup->msg;
  766. u32 val = 0;
  767. int idx = 0;
  768. while (blk->fifo_available && qup->pos < msg->len) {
  769. if ((idx & 1) == 0) {
  770. /* Reading 2 words at time */
  771. val = readl(qup->base + QUP_IN_FIFO_BASE);
  772. msg->buf[qup->pos++] = val & 0xFF;
  773. } else {
  774. msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
  775. }
  776. idx++;
  777. blk->fifo_available--;
  778. }
  779. if (qup->pos == msg->len)
  780. blk->rx_bytes_read = true;
  781. }
  782. static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
  783. {
  784. struct i2c_msg *msg = qup->msg;
  785. u32 addr, len, val;
  786. addr = i2c_8bit_addr_from_msg(msg);
  787. /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
  788. len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
  789. val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
  790. writel(val, qup->base + QUP_OUT_FIFO_BASE);
  791. }
  792. static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
  793. {
  794. struct qup_i2c_block *blk = &qup->blk;
  795. u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
  796. u32 io_mode = QUP_REPACK_EN;
  797. blk->is_tx_blk_mode =
  798. blk->total_tx_len > qup->out_fifo_sz ? true : false;
  799. blk->is_rx_blk_mode =
  800. blk->total_rx_len > qup->in_fifo_sz ? true : false;
  801. if (blk->is_tx_blk_mode) {
  802. io_mode |= QUP_OUTPUT_BLK_MODE;
  803. writel(0, qup->base + QUP_MX_WRITE_CNT);
  804. writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
  805. } else {
  806. writel(0, qup->base + QUP_MX_OUTPUT_CNT);
  807. writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
  808. }
  809. if (blk->total_rx_len) {
  810. if (blk->is_rx_blk_mode) {
  811. io_mode |= QUP_INPUT_BLK_MODE;
  812. writel(0, qup->base + QUP_MX_READ_CNT);
  813. writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
  814. } else {
  815. writel(0, qup->base + QUP_MX_INPUT_CNT);
  816. writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
  817. }
  818. } else {
  819. qup_config |= QUP_NO_INPUT;
  820. }
  821. writel(qup_config, qup->base + QUP_CONFIG);
  822. writel(io_mode, qup->base + QUP_IO_MODE);
  823. }
  824. static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
  825. {
  826. blk->tx_fifo_free = 0;
  827. blk->fifo_available = 0;
  828. blk->rx_bytes_read = false;
  829. }
  830. static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
  831. {
  832. struct qup_i2c_block *blk = &qup->blk;
  833. int ret;
  834. qup_i2c_clear_blk_v1(blk);
  835. qup_i2c_conf_v1(qup);
  836. ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
  837. if (ret)
  838. return ret;
  839. writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
  840. ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
  841. if (ret)
  842. return ret;
  843. reinit_completion(&qup->xfer);
  844. enable_irq(qup->irq);
  845. if (!blk->is_tx_blk_mode) {
  846. blk->tx_fifo_free = qup->out_fifo_sz;
  847. if (is_rx)
  848. qup_i2c_write_rx_tags_v1(qup);
  849. else
  850. qup_i2c_write_tx_fifo_v1(qup);
  851. }
  852. ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
  853. if (ret)
  854. goto err;
  855. ret = qup_i2c_wait_for_complete(qup, qup->msg);
  856. if (ret)
  857. goto err;
  858. ret = qup_i2c_bus_active(qup, ONE_BYTE);
  859. err:
  860. disable_irq(qup->irq);
  861. return ret;
  862. }
  863. static int qup_i2c_write_one(struct qup_i2c_dev *qup)
  864. {
  865. struct i2c_msg *msg = qup->msg;
  866. struct qup_i2c_block *blk = &qup->blk;
  867. qup->pos = 0;
  868. blk->total_tx_len = msg->len + 1;
  869. blk->total_rx_len = 0;
  870. return qup_i2c_conf_xfer_v1(qup, false);
  871. }
  872. static int qup_i2c_read_one(struct qup_i2c_dev *qup)
  873. {
  874. struct qup_i2c_block *blk = &qup->blk;
  875. qup->pos = 0;
  876. blk->total_tx_len = 2;
  877. blk->total_rx_len = qup->msg->len;
  878. return qup_i2c_conf_xfer_v1(qup, true);
  879. }
  880. static int qup_i2c_xfer(struct i2c_adapter *adap,
  881. struct i2c_msg msgs[],
  882. int num)
  883. {
  884. struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
  885. int ret, idx;
  886. ret = pm_runtime_get_sync(qup->dev);
  887. if (ret < 0)
  888. goto out;
  889. qup->bus_err = 0;
  890. qup->qup_err = 0;
  891. writel(1, qup->base + QUP_SW_RESET);
  892. ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
  893. if (ret)
  894. goto out;
  895. /* Configure QUP as I2C mini core */
  896. writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
  897. for (idx = 0; idx < num; idx++) {
  898. if (msgs[idx].len == 0) {
  899. ret = -EINVAL;
  900. goto out;
  901. }
  902. if (qup_i2c_poll_state_i2c_master(qup)) {
  903. ret = -EIO;
  904. goto out;
  905. }
  906. if (qup_i2c_check_msg_len(&msgs[idx])) {
  907. ret = -EINVAL;
  908. goto out;
  909. }
  910. qup->msg = &msgs[idx];
  911. if (msgs[idx].flags & I2C_M_RD)
  912. ret = qup_i2c_read_one(qup);
  913. else
  914. ret = qup_i2c_write_one(qup);
  915. if (ret)
  916. break;
  917. ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
  918. if (ret)
  919. break;
  920. }
  921. if (ret == 0)
  922. ret = num;
  923. out:
  924. pm_runtime_mark_last_busy(qup->dev);
  925. pm_runtime_put_autosuspend(qup->dev);
  926. return ret;
  927. }
  928. /*
  929. * Configure registers related with reconfiguration during run and call it
  930. * before each i2c sub transfer.
  931. */
  932. static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
  933. {
  934. struct qup_i2c_block *blk = &qup->blk;
  935. u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
  936. if (blk->is_tx_blk_mode)
  937. writel(qup->config_run | blk->total_tx_len,
  938. qup->base + QUP_MX_OUTPUT_CNT);
  939. else
  940. writel(qup->config_run | blk->total_tx_len,
  941. qup->base + QUP_MX_WRITE_CNT);
  942. if (blk->total_rx_len) {
  943. if (blk->is_rx_blk_mode)
  944. writel(qup->config_run | blk->total_rx_len,
  945. qup->base + QUP_MX_INPUT_CNT);
  946. else
  947. writel(qup->config_run | blk->total_rx_len,
  948. qup->base + QUP_MX_READ_CNT);
  949. } else {
  950. qup_config |= QUP_NO_INPUT;
  951. }
  952. writel(qup_config, qup->base + QUP_CONFIG);
  953. }
  954. /*
  955. * Configure registers related with transfer mode (FIFO/Block)
  956. * before starting of i2c transfer. It will be called only once in
  957. * QUP RESET state.
  958. */
  959. static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
  960. {
  961. struct qup_i2c_block *blk = &qup->blk;
  962. u32 io_mode = QUP_REPACK_EN;
  963. if (blk->is_tx_blk_mode) {
  964. io_mode |= QUP_OUTPUT_BLK_MODE;
  965. writel(0, qup->base + QUP_MX_WRITE_CNT);
  966. } else {
  967. writel(0, qup->base + QUP_MX_OUTPUT_CNT);
  968. }
  969. if (blk->is_rx_blk_mode) {
  970. io_mode |= QUP_INPUT_BLK_MODE;
  971. writel(0, qup->base + QUP_MX_READ_CNT);
  972. } else {
  973. writel(0, qup->base + QUP_MX_INPUT_CNT);
  974. }
  975. writel(io_mode, qup->base + QUP_IO_MODE);
  976. }
  977. /* Clear required variables before starting of any QUP v2 sub transfer. */
  978. static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
  979. {
  980. blk->send_last_word = false;
  981. blk->tx_tags_sent = false;
  982. blk->tx_fifo_data = 0;
  983. blk->tx_fifo_data_pos = 0;
  984. blk->tx_fifo_free = 0;
  985. blk->rx_tags_fetched = false;
  986. blk->rx_bytes_read = false;
  987. blk->rx_fifo_data = 0;
  988. blk->rx_fifo_data_pos = 0;
  989. blk->fifo_available = 0;
  990. }
  991. /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
  992. static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
  993. {
  994. struct qup_i2c_block *blk = &qup->blk;
  995. int j;
  996. for (j = blk->rx_fifo_data_pos;
  997. blk->cur_blk_len && blk->fifo_available;
  998. blk->cur_blk_len--, blk->fifo_available--) {
  999. if (j == 0)
  1000. blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
  1001. *(blk->cur_data++) = blk->rx_fifo_data;
  1002. blk->rx_fifo_data >>= 8;
  1003. if (j == 3)
  1004. j = 0;
  1005. else
  1006. j++;
  1007. }
  1008. blk->rx_fifo_data_pos = j;
  1009. }
  1010. /* Receive tags for read message in QUP v2 i2c transfer. */
  1011. static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
  1012. {
  1013. struct qup_i2c_block *blk = &qup->blk;
  1014. blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
  1015. blk->rx_fifo_data >>= blk->rx_tag_len * 8;
  1016. blk->rx_fifo_data_pos = blk->rx_tag_len;
  1017. blk->fifo_available -= blk->rx_tag_len;
  1018. }
  1019. /*
  1020. * Read the data and tags from RX FIFO. Since in read case, the tags will be
  1021. * preceded by received data bytes so
  1022. * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
  1023. * all tag bytes and discard that.
  1024. * 2. Read the data from RX FIFO. When all the data bytes have been read then
  1025. * set rx_bytes_read to true.
  1026. */
  1027. static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
  1028. {
  1029. struct qup_i2c_block *blk = &qup->blk;
  1030. if (!blk->rx_tags_fetched) {
  1031. qup_i2c_recv_tags(qup);
  1032. blk->rx_tags_fetched = true;
  1033. }
  1034. qup_i2c_recv_data(qup);
  1035. if (!blk->cur_blk_len)
  1036. blk->rx_bytes_read = true;
  1037. }
  1038. /*
  1039. * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
  1040. * write works on word basis (4 bytes). Append new data byte write for TX FIFO
  1041. * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
  1042. */
  1043. static void
  1044. qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
  1045. {
  1046. struct qup_i2c_block *blk = &qup->blk;
  1047. unsigned int j;
  1048. for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
  1049. (*len)--, blk->tx_fifo_free--) {
  1050. blk->tx_fifo_data |= *(*data)++ << (j * 8);
  1051. if (j == 3) {
  1052. writel(blk->tx_fifo_data,
  1053. qup->base + QUP_OUT_FIFO_BASE);
  1054. blk->tx_fifo_data = 0x0;
  1055. j = 0;
  1056. } else {
  1057. j++;
  1058. }
  1059. }
  1060. blk->tx_fifo_data_pos = j;
  1061. }
  1062. /* Transfer tags for read message in QUP v2 i2c transfer. */
  1063. static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
  1064. {
  1065. struct qup_i2c_block *blk = &qup->blk;
  1066. qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
  1067. if (blk->tx_fifo_data_pos)
  1068. writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
  1069. }
  1070. /*
  1071. * Write the data and tags in TX FIFO. Since in write case, both tags and data
  1072. * need to be written and QUP write tags can have maximum 256 data length, so
  1073. *
  1074. * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
  1075. * tags to TX FIFO and set tx_tags_sent to true.
  1076. * 2. Check if send_last_word is true. It will be set when last few data bytes
  1077. * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO
  1078. * space. All this data bytes are available in tx_fifo_data so write this
  1079. * in FIFO.
  1080. * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
  1081. * then more data is pending otherwise following 3 cases can be possible
  1082. * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
  1083. * have been written in TX FIFO so nothing else is required.
  1084. * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
  1085. * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
  1086. * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
  1087. * will be always greater than or equal to 4 bytes.
  1088. * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
  1089. * bytes) are copied to tx_fifo_data but couldn't be sent because of
  1090. * FIFO full so make send_last_word true.
  1091. */
  1092. static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
  1093. {
  1094. struct qup_i2c_block *blk = &qup->blk;
  1095. if (!blk->tx_tags_sent) {
  1096. qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
  1097. &blk->tx_tag_len);
  1098. blk->tx_tags_sent = true;
  1099. }
  1100. if (blk->send_last_word)
  1101. goto send_last_word;
  1102. qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
  1103. if (!blk->cur_blk_len) {
  1104. if (!blk->tx_fifo_data_pos)
  1105. return;
  1106. if (blk->tx_fifo_free)
  1107. goto send_last_word;
  1108. blk->send_last_word = true;
  1109. }
  1110. return;
  1111. send_last_word:
  1112. writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
  1113. }
  1114. /*
  1115. * Main transfer function which read or write i2c data.
  1116. * The QUP v2 supports reconfiguration during run in which multiple i2c sub
  1117. * transfers can be scheduled.
  1118. */
  1119. static int
  1120. qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
  1121. bool change_pause_state)
  1122. {
  1123. struct qup_i2c_block *blk = &qup->blk;
  1124. struct i2c_msg *msg = qup->msg;
  1125. int ret;
  1126. /*
  1127. * Check if its SMBus Block read for which the top level read will be
  1128. * done into 2 QUP reads. One with message length 1 while other one is
  1129. * with actual length.
  1130. */
  1131. if (qup_i2c_check_msg_len(msg)) {
  1132. if (qup->is_smbus_read) {
  1133. /*
  1134. * If the message length is already read in
  1135. * the first byte of the buffer, account for
  1136. * that by setting the offset
  1137. */
  1138. blk->cur_data += 1;
  1139. is_first = false;
  1140. } else {
  1141. change_pause_state = false;
  1142. }
  1143. }
  1144. qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
  1145. qup_i2c_clear_blk_v2(blk);
  1146. qup_i2c_conf_count_v2(qup);
  1147. /* If it is first sub transfer, then configure i2c bus clocks */
  1148. if (is_first) {
  1149. ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
  1150. if (ret)
  1151. return ret;
  1152. writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
  1153. ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
  1154. if (ret)
  1155. return ret;
  1156. }
  1157. reinit_completion(&qup->xfer);
  1158. enable_irq(qup->irq);
  1159. /*
  1160. * In FIFO mode, tx FIFO can be written directly while in block mode the
  1161. * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
  1162. */
  1163. if (!blk->is_tx_blk_mode) {
  1164. blk->tx_fifo_free = qup->out_fifo_sz;
  1165. if (is_rx)
  1166. qup_i2c_write_rx_tags_v2(qup);
  1167. else
  1168. qup_i2c_write_tx_fifo_v2(qup);
  1169. }
  1170. ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
  1171. if (ret)
  1172. goto err;
  1173. ret = qup_i2c_wait_for_complete(qup, msg);
  1174. if (ret)
  1175. goto err;
  1176. /* Move to pause state for all the transfers, except last one */
  1177. if (change_pause_state) {
  1178. ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
  1179. if (ret)
  1180. goto err;
  1181. }
  1182. err:
  1183. disable_irq(qup->irq);
  1184. return ret;
  1185. }
  1186. /*
  1187. * Transfer one read/write message in i2c transfer. It splits the message into
  1188. * multiple of blk_xfer_limit data length blocks and schedule each
  1189. * QUP block individually.
  1190. */
  1191. static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
  1192. {
  1193. int ret = 0;
  1194. unsigned int data_len, i;
  1195. struct i2c_msg *msg = qup->msg;
  1196. struct qup_i2c_block *blk = &qup->blk;
  1197. u8 *msg_buf = msg->buf;
  1198. qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
  1199. qup_i2c_set_blk_data(qup, msg);
  1200. for (i = 0; i < blk->count; i++) {
  1201. data_len = qup_i2c_get_data_len(qup);
  1202. blk->pos = i;
  1203. blk->cur_tx_tags = blk->tags;
  1204. blk->cur_blk_len = data_len;
  1205. blk->tx_tag_len =
  1206. qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
  1207. blk->cur_data = msg_buf;
  1208. if (is_rx) {
  1209. blk->total_tx_len = blk->tx_tag_len;
  1210. blk->rx_tag_len = 2;
  1211. blk->total_rx_len = blk->rx_tag_len + data_len;
  1212. } else {
  1213. blk->total_tx_len = blk->tx_tag_len + data_len;
  1214. blk->total_rx_len = 0;
  1215. }
  1216. ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
  1217. !qup->is_last || i < blk->count - 1);
  1218. if (ret)
  1219. return ret;
  1220. /* Handle SMBus block read length */
  1221. if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
  1222. !qup->is_smbus_read) {
  1223. if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
  1224. return -EPROTO;
  1225. msg->len = msg->buf[0];
  1226. qup->is_smbus_read = true;
  1227. ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
  1228. qup->is_smbus_read = false;
  1229. if (ret)
  1230. return ret;
  1231. msg->len += 1;
  1232. }
  1233. msg_buf += data_len;
  1234. blk->data_len -= qup->blk_xfer_limit;
  1235. }
  1236. return ret;
  1237. }
  1238. /*
  1239. * QUP v2 supports 3 modes
  1240. * Programmed IO using FIFO mode : Less than FIFO size
  1241. * Programmed IO using Block mode : Greater than FIFO size
  1242. * DMA using BAM : Appropriate for any transaction size but the address should
  1243. * be DMA applicable
  1244. *
  1245. * This function determines the mode which will be used for this transfer. An
  1246. * i2c transfer contains multiple message. Following are the rules to determine
  1247. * the mode used.
  1248. * 1. Determine complete length, maximum tx and rx length for complete transfer.
  1249. * 2. If complete transfer length is greater than fifo size then use the DMA
  1250. * mode.
  1251. * 3. In FIFO or block mode, tx and rx can operate in different mode so check
  1252. * for maximum tx and rx length to determine mode.
  1253. */
  1254. static int
  1255. qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
  1256. struct i2c_msg msgs[], int num)
  1257. {
  1258. int idx;
  1259. bool no_dma = false;
  1260. unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
  1261. /* All i2c_msgs should be transferred using either dma or cpu */
  1262. for (idx = 0; idx < num; idx++) {
  1263. if (msgs[idx].len == 0)
  1264. return -EINVAL;
  1265. if (msgs[idx].flags & I2C_M_RD)
  1266. max_rx_len = max_t(unsigned int, max_rx_len,
  1267. msgs[idx].len);
  1268. else
  1269. max_tx_len = max_t(unsigned int, max_tx_len,
  1270. msgs[idx].len);
  1271. if (is_vmalloc_addr(msgs[idx].buf))
  1272. no_dma = true;
  1273. total_len += msgs[idx].len;
  1274. }
  1275. if (!no_dma && qup->is_dma &&
  1276. (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
  1277. qup->use_dma = true;
  1278. } else {
  1279. qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
  1280. QUP_MAX_TAGS_LEN ? true : false;
  1281. qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
  1282. READ_RX_TAGS_LEN ? true : false;
  1283. }
  1284. return 0;
  1285. }
  1286. static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
  1287. struct i2c_msg msgs[],
  1288. int num)
  1289. {
  1290. struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
  1291. int ret, idx = 0;
  1292. qup->bus_err = 0;
  1293. qup->qup_err = 0;
  1294. ret = pm_runtime_get_sync(qup->dev);
  1295. if (ret < 0)
  1296. goto out;
  1297. ret = qup_i2c_determine_mode_v2(qup, msgs, num);
  1298. if (ret)
  1299. goto out;
  1300. writel(1, qup->base + QUP_SW_RESET);
  1301. ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
  1302. if (ret)
  1303. goto out;
  1304. /* Configure QUP as I2C mini core */
  1305. writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
  1306. writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
  1307. if (qup_i2c_poll_state_i2c_master(qup)) {
  1308. ret = -EIO;
  1309. goto out;
  1310. }
  1311. if (qup->use_dma) {
  1312. reinit_completion(&qup->xfer);
  1313. ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
  1314. qup->use_dma = false;
  1315. } else {
  1316. qup_i2c_conf_mode_v2(qup);
  1317. for (idx = 0; idx < num; idx++) {
  1318. qup->msg = &msgs[idx];
  1319. qup->is_last = idx == (num - 1);
  1320. ret = qup_i2c_xfer_v2_msg(qup, idx,
  1321. !!(msgs[idx].flags & I2C_M_RD));
  1322. if (ret)
  1323. break;
  1324. }
  1325. qup->msg = NULL;
  1326. }
  1327. if (!ret)
  1328. ret = qup_i2c_bus_active(qup, ONE_BYTE);
  1329. if (!ret)
  1330. qup_i2c_change_state(qup, QUP_RESET_STATE);
  1331. if (ret == 0)
  1332. ret = num;
  1333. out:
  1334. pm_runtime_mark_last_busy(qup->dev);
  1335. pm_runtime_put_autosuspend(qup->dev);
  1336. return ret;
  1337. }
  1338. static u32 qup_i2c_func(struct i2c_adapter *adap)
  1339. {
  1340. return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
  1341. }
  1342. static const struct i2c_algorithm qup_i2c_algo = {
  1343. .master_xfer = qup_i2c_xfer,
  1344. .functionality = qup_i2c_func,
  1345. };
  1346. static const struct i2c_algorithm qup_i2c_algo_v2 = {
  1347. .master_xfer = qup_i2c_xfer_v2,
  1348. .functionality = qup_i2c_func,
  1349. };
  1350. /*
  1351. * The QUP block will issue a NACK and STOP on the bus when reaching
  1352. * the end of the read, the length of the read is specified as one byte
  1353. * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
  1354. */
  1355. static const struct i2c_adapter_quirks qup_i2c_quirks = {
  1356. .max_read_len = QUP_READ_LIMIT,
  1357. };
  1358. static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
  1359. {
  1360. clk_prepare_enable(qup->clk);
  1361. clk_prepare_enable(qup->pclk);
  1362. }
  1363. static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
  1364. {
  1365. u32 config;
  1366. qup_i2c_change_state(qup, QUP_RESET_STATE);
  1367. clk_disable_unprepare(qup->clk);
  1368. config = readl(qup->base + QUP_CONFIG);
  1369. config |= QUP_CLOCK_AUTO_GATE;
  1370. writel(config, qup->base + QUP_CONFIG);
  1371. clk_disable_unprepare(qup->pclk);
  1372. }
  1373. static int qup_i2c_probe(struct platform_device *pdev)
  1374. {
  1375. static const int blk_sizes[] = {4, 16, 32};
  1376. struct qup_i2c_dev *qup;
  1377. unsigned long one_bit_t;
  1378. struct resource *res;
  1379. u32 io_mode, hw_ver, size;
  1380. int ret, fs_div, hs_div;
  1381. u32 src_clk_freq = DEFAULT_SRC_CLK;
  1382. u32 clk_freq = DEFAULT_CLK_FREQ;
  1383. int blocks;
  1384. bool is_qup_v1;
  1385. qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
  1386. if (!qup)
  1387. return -ENOMEM;
  1388. qup->dev = &pdev->dev;
  1389. init_completion(&qup->xfer);
  1390. platform_set_drvdata(pdev, qup);
  1391. ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
  1392. if (ret) {
  1393. dev_notice(qup->dev, "using default clock-frequency %d",
  1394. DEFAULT_CLK_FREQ);
  1395. }
  1396. if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
  1397. qup->adap.algo = &qup_i2c_algo;
  1398. qup->adap.quirks = &qup_i2c_quirks;
  1399. is_qup_v1 = true;
  1400. } else {
  1401. qup->adap.algo = &qup_i2c_algo_v2;
  1402. is_qup_v1 = false;
  1403. ret = qup_i2c_req_dma(qup);
  1404. if (ret == -EPROBE_DEFER)
  1405. goto fail_dma;
  1406. else if (ret != 0)
  1407. goto nodma;
  1408. qup->max_xfer_sg_len = (MX_BLOCKS << 1);
  1409. blocks = (MX_DMA_BLOCKS << 1) + 1;
  1410. qup->btx.sg = devm_kzalloc(&pdev->dev,
  1411. sizeof(*qup->btx.sg) * blocks,
  1412. GFP_KERNEL);
  1413. if (!qup->btx.sg) {
  1414. ret = -ENOMEM;
  1415. goto fail_dma;
  1416. }
  1417. sg_init_table(qup->btx.sg, blocks);
  1418. qup->brx.sg = devm_kzalloc(&pdev->dev,
  1419. sizeof(*qup->brx.sg) * blocks,
  1420. GFP_KERNEL);
  1421. if (!qup->brx.sg) {
  1422. ret = -ENOMEM;
  1423. goto fail_dma;
  1424. }
  1425. sg_init_table(qup->brx.sg, blocks);
  1426. /* 2 tag bytes for each block + 5 for start, stop tags */
  1427. size = blocks * 2 + 5;
  1428. qup->start_tag.start = devm_kzalloc(&pdev->dev,
  1429. size, GFP_KERNEL);
  1430. if (!qup->start_tag.start) {
  1431. ret = -ENOMEM;
  1432. goto fail_dma;
  1433. }
  1434. qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
  1435. if (!qup->brx.tag.start) {
  1436. ret = -ENOMEM;
  1437. goto fail_dma;
  1438. }
  1439. qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
  1440. if (!qup->btx.tag.start) {
  1441. ret = -ENOMEM;
  1442. goto fail_dma;
  1443. }
  1444. qup->is_dma = true;
  1445. }
  1446. nodma:
  1447. /* We support frequencies up to FAST Mode (400KHz) */
  1448. if (!clk_freq || clk_freq > 400000) {
  1449. dev_err(qup->dev, "clock frequency not supported %d\n",
  1450. clk_freq);
  1451. return -EINVAL;
  1452. }
  1453. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1454. qup->base = devm_ioremap_resource(qup->dev, res);
  1455. if (IS_ERR(qup->base))
  1456. return PTR_ERR(qup->base);
  1457. qup->irq = platform_get_irq(pdev, 0);
  1458. if (qup->irq < 0) {
  1459. dev_err(qup->dev, "No IRQ defined\n");
  1460. return qup->irq;
  1461. }
  1462. if (has_acpi_companion(qup->dev)) {
  1463. ret = device_property_read_u32(qup->dev,
  1464. "src-clock-hz", &src_clk_freq);
  1465. if (ret) {
  1466. dev_notice(qup->dev, "using default src-clock-hz %d",
  1467. DEFAULT_SRC_CLK);
  1468. }
  1469. ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
  1470. } else {
  1471. qup->clk = devm_clk_get(qup->dev, "core");
  1472. if (IS_ERR(qup->clk)) {
  1473. dev_err(qup->dev, "Could not get core clock\n");
  1474. return PTR_ERR(qup->clk);
  1475. }
  1476. qup->pclk = devm_clk_get(qup->dev, "iface");
  1477. if (IS_ERR(qup->pclk)) {
  1478. dev_err(qup->dev, "Could not get iface clock\n");
  1479. return PTR_ERR(qup->pclk);
  1480. }
  1481. qup_i2c_enable_clocks(qup);
  1482. src_clk_freq = clk_get_rate(qup->clk);
  1483. }
  1484. /*
  1485. * Bootloaders might leave a pending interrupt on certain QUP's,
  1486. * so we reset the core before registering for interrupts.
  1487. */
  1488. writel(1, qup->base + QUP_SW_RESET);
  1489. ret = qup_i2c_poll_state_valid(qup);
  1490. if (ret)
  1491. goto fail;
  1492. ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
  1493. IRQF_TRIGGER_HIGH, "i2c_qup", qup);
  1494. if (ret) {
  1495. dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
  1496. goto fail;
  1497. }
  1498. disable_irq(qup->irq);
  1499. hw_ver = readl(qup->base + QUP_HW_VERSION);
  1500. dev_dbg(qup->dev, "Revision %x\n", hw_ver);
  1501. io_mode = readl(qup->base + QUP_IO_MODE);
  1502. /*
  1503. * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
  1504. * associated with each byte written/received
  1505. */
  1506. size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
  1507. if (size >= ARRAY_SIZE(blk_sizes)) {
  1508. ret = -EIO;
  1509. goto fail;
  1510. }
  1511. qup->out_blk_sz = blk_sizes[size];
  1512. size = QUP_INPUT_BLOCK_SIZE(io_mode);
  1513. if (size >= ARRAY_SIZE(blk_sizes)) {
  1514. ret = -EIO;
  1515. goto fail;
  1516. }
  1517. qup->in_blk_sz = blk_sizes[size];
  1518. if (is_qup_v1) {
  1519. /*
  1520. * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
  1521. * single transfer but the block size is in bytes so divide the
  1522. * in_blk_sz and out_blk_sz by 2
  1523. */
  1524. qup->in_blk_sz /= 2;
  1525. qup->out_blk_sz /= 2;
  1526. qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
  1527. qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
  1528. qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
  1529. } else {
  1530. qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
  1531. qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
  1532. qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
  1533. }
  1534. size = QUP_OUTPUT_FIFO_SIZE(io_mode);
  1535. qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
  1536. size = QUP_INPUT_FIFO_SIZE(io_mode);
  1537. qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
  1538. fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
  1539. hs_div = 3;
  1540. qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
  1541. /*
  1542. * Time it takes for a byte to be clocked out on the bus.
  1543. * Each byte takes 9 clock cycles (8 bits + 1 ack).
  1544. */
  1545. one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
  1546. qup->one_byte_t = one_bit_t * 9;
  1547. qup->xfer_timeout = TOUT_MIN * HZ +
  1548. usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
  1549. dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
  1550. qup->in_blk_sz, qup->in_fifo_sz,
  1551. qup->out_blk_sz, qup->out_fifo_sz);
  1552. i2c_set_adapdata(&qup->adap, qup);
  1553. qup->adap.dev.parent = qup->dev;
  1554. qup->adap.dev.of_node = pdev->dev.of_node;
  1555. qup->is_last = true;
  1556. strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
  1557. pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
  1558. pm_runtime_use_autosuspend(qup->dev);
  1559. pm_runtime_set_active(qup->dev);
  1560. pm_runtime_enable(qup->dev);
  1561. ret = i2c_add_adapter(&qup->adap);
  1562. if (ret)
  1563. goto fail_runtime;
  1564. return 0;
  1565. fail_runtime:
  1566. pm_runtime_disable(qup->dev);
  1567. pm_runtime_set_suspended(qup->dev);
  1568. fail:
  1569. qup_i2c_disable_clocks(qup);
  1570. fail_dma:
  1571. if (qup->btx.dma)
  1572. dma_release_channel(qup->btx.dma);
  1573. if (qup->brx.dma)
  1574. dma_release_channel(qup->brx.dma);
  1575. return ret;
  1576. }
  1577. static int qup_i2c_remove(struct platform_device *pdev)
  1578. {
  1579. struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
  1580. if (qup->is_dma) {
  1581. dma_release_channel(qup->btx.dma);
  1582. dma_release_channel(qup->brx.dma);
  1583. }
  1584. disable_irq(qup->irq);
  1585. qup_i2c_disable_clocks(qup);
  1586. i2c_del_adapter(&qup->adap);
  1587. pm_runtime_disable(qup->dev);
  1588. pm_runtime_set_suspended(qup->dev);
  1589. return 0;
  1590. }
  1591. #ifdef CONFIG_PM
  1592. static int qup_i2c_pm_suspend_runtime(struct device *device)
  1593. {
  1594. struct qup_i2c_dev *qup = dev_get_drvdata(device);
  1595. dev_dbg(device, "pm_runtime: suspending...\n");
  1596. qup_i2c_disable_clocks(qup);
  1597. return 0;
  1598. }
  1599. static int qup_i2c_pm_resume_runtime(struct device *device)
  1600. {
  1601. struct qup_i2c_dev *qup = dev_get_drvdata(device);
  1602. dev_dbg(device, "pm_runtime: resuming...\n");
  1603. qup_i2c_enable_clocks(qup);
  1604. return 0;
  1605. }
  1606. #endif
  1607. #ifdef CONFIG_PM_SLEEP
  1608. static int qup_i2c_suspend(struct device *device)
  1609. {
  1610. if (!pm_runtime_suspended(device))
  1611. return qup_i2c_pm_suspend_runtime(device);
  1612. return 0;
  1613. }
  1614. static int qup_i2c_resume(struct device *device)
  1615. {
  1616. qup_i2c_pm_resume_runtime(device);
  1617. pm_runtime_mark_last_busy(device);
  1618. pm_request_autosuspend(device);
  1619. return 0;
  1620. }
  1621. #endif
  1622. static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
  1623. SET_SYSTEM_SLEEP_PM_OPS(
  1624. qup_i2c_suspend,
  1625. qup_i2c_resume)
  1626. SET_RUNTIME_PM_OPS(
  1627. qup_i2c_pm_suspend_runtime,
  1628. qup_i2c_pm_resume_runtime,
  1629. NULL)
  1630. };
  1631. static const struct of_device_id qup_i2c_dt_match[] = {
  1632. { .compatible = "qcom,i2c-qup-v1.1.1" },
  1633. { .compatible = "qcom,i2c-qup-v2.1.1" },
  1634. { .compatible = "qcom,i2c-qup-v2.2.1" },
  1635. {}
  1636. };
  1637. MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
  1638. #if IS_ENABLED(CONFIG_ACPI)
  1639. static const struct acpi_device_id qup_i2c_acpi_match[] = {
  1640. { "QCOM8010"},
  1641. { },
  1642. };
  1643. MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
  1644. #endif
  1645. static struct platform_driver qup_i2c_driver = {
  1646. .probe = qup_i2c_probe,
  1647. .remove = qup_i2c_remove,
  1648. .driver = {
  1649. .name = "i2c_qup",
  1650. .pm = &qup_i2c_qup_pm_ops,
  1651. .of_match_table = qup_i2c_dt_match,
  1652. .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
  1653. },
  1654. };
  1655. module_platform_driver(qup_i2c_driver);
  1656. MODULE_LICENSE("GPL v2");
  1657. MODULE_ALIAS("platform:i2c_qup");