vmwgfx_stdu.c 45 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631
  1. /******************************************************************************
  2. *
  3. * COPYRIGHT © 2014-2015 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. ******************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. #include "device_include/svga3d_surfacedefs.h"
  29. #include <drm/drm_plane_helper.h>
  30. #include <drm/drm_atomic.h>
  31. #include <drm/drm_atomic_helper.h>
  32. #define vmw_crtc_to_stdu(x) \
  33. container_of(x, struct vmw_screen_target_display_unit, base.crtc)
  34. #define vmw_encoder_to_stdu(x) \
  35. container_of(x, struct vmw_screen_target_display_unit, base.encoder)
  36. #define vmw_connector_to_stdu(x) \
  37. container_of(x, struct vmw_screen_target_display_unit, base.connector)
  38. enum stdu_content_type {
  39. SAME_AS_DISPLAY = 0,
  40. SEPARATE_SURFACE,
  41. SEPARATE_DMA
  42. };
  43. /**
  44. * struct vmw_stdu_dirty - closure structure for the update functions
  45. *
  46. * @base: The base type we derive from. Used by vmw_kms_helper_dirty().
  47. * @transfer: Transfer direction for DMA command.
  48. * @left: Left side of bounding box.
  49. * @right: Right side of bounding box.
  50. * @top: Top side of bounding box.
  51. * @bottom: Bottom side of bounding box.
  52. * @fb_left: Left side of the framebuffer/content bounding box
  53. * @fb_top: Top of the framebuffer/content bounding box
  54. * @buf: DMA buffer when DMA-ing between buffer and screen targets.
  55. * @sid: Surface ID when copying between surface and screen targets.
  56. */
  57. struct vmw_stdu_dirty {
  58. struct vmw_kms_dirty base;
  59. SVGA3dTransferType transfer;
  60. s32 left, right, top, bottom;
  61. s32 fb_left, fb_top;
  62. u32 pitch;
  63. union {
  64. struct vmw_dma_buffer *buf;
  65. u32 sid;
  66. };
  67. };
  68. /*
  69. * SVGA commands that are used by this code. Please see the device headers
  70. * for explanation.
  71. */
  72. struct vmw_stdu_update {
  73. SVGA3dCmdHeader header;
  74. SVGA3dCmdUpdateGBScreenTarget body;
  75. };
  76. struct vmw_stdu_dma {
  77. SVGA3dCmdHeader header;
  78. SVGA3dCmdSurfaceDMA body;
  79. };
  80. struct vmw_stdu_surface_copy {
  81. SVGA3dCmdHeader header;
  82. SVGA3dCmdSurfaceCopy body;
  83. };
  84. /**
  85. * struct vmw_screen_target_display_unit
  86. *
  87. * @base: VMW specific DU structure
  88. * @display_srf: surface to be displayed. The dimension of this will always
  89. * match the display mode. If the display mode matches
  90. * content_vfbs dimensions, then this is a pointer into the
  91. * corresponding field in content_vfbs. If not, then this
  92. * is a separate buffer to which content_vfbs will blit to.
  93. * @content_type: content_fb type
  94. * @defined: true if the current display unit has been initialized
  95. */
  96. struct vmw_screen_target_display_unit {
  97. struct vmw_display_unit base;
  98. const struct vmw_surface *display_srf;
  99. enum stdu_content_type content_fb_type;
  100. s32 display_width, display_height;
  101. bool defined;
  102. /* For CPU Blit */
  103. unsigned int cpp;
  104. };
  105. static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu);
  106. /******************************************************************************
  107. * Screen Target Display Unit CRTC Functions
  108. *****************************************************************************/
  109. /**
  110. * vmw_stdu_crtc_destroy - cleans up the STDU
  111. *
  112. * @crtc: used to get a reference to the containing STDU
  113. */
  114. static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc)
  115. {
  116. vmw_stdu_destroy(vmw_crtc_to_stdu(crtc));
  117. }
  118. /**
  119. * vmw_stdu_define_st - Defines a Screen Target
  120. *
  121. * @dev_priv: VMW DRM device
  122. * @stdu: display unit to create a Screen Target for
  123. * @mode: The mode to set.
  124. * @crtc_x: X coordinate of screen target relative to framebuffer origin.
  125. * @crtc_y: Y coordinate of screen target relative to framebuffer origin.
  126. *
  127. * Creates a STDU that we can used later. This function is called whenever the
  128. * framebuffer size changes.
  129. *
  130. * RETURNs:
  131. * 0 on success, error code on failure
  132. */
  133. static int vmw_stdu_define_st(struct vmw_private *dev_priv,
  134. struct vmw_screen_target_display_unit *stdu,
  135. struct drm_display_mode *mode,
  136. int crtc_x, int crtc_y)
  137. {
  138. struct {
  139. SVGA3dCmdHeader header;
  140. SVGA3dCmdDefineGBScreenTarget body;
  141. } *cmd;
  142. cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  143. if (unlikely(cmd == NULL)) {
  144. DRM_ERROR("Out of FIFO space defining Screen Target\n");
  145. return -ENOMEM;
  146. }
  147. cmd->header.id = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET;
  148. cmd->header.size = sizeof(cmd->body);
  149. cmd->body.stid = stdu->base.unit;
  150. cmd->body.width = mode->hdisplay;
  151. cmd->body.height = mode->vdisplay;
  152. cmd->body.flags = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0;
  153. cmd->body.dpi = 0;
  154. if (stdu->base.is_implicit) {
  155. cmd->body.xRoot = crtc_x;
  156. cmd->body.yRoot = crtc_y;
  157. } else {
  158. cmd->body.xRoot = stdu->base.gui_x;
  159. cmd->body.yRoot = stdu->base.gui_y;
  160. }
  161. stdu->base.set_gui_x = cmd->body.xRoot;
  162. stdu->base.set_gui_y = cmd->body.yRoot;
  163. vmw_fifo_commit(dev_priv, sizeof(*cmd));
  164. stdu->defined = true;
  165. stdu->display_width = mode->hdisplay;
  166. stdu->display_height = mode->vdisplay;
  167. return 0;
  168. }
  169. /**
  170. * vmw_stdu_bind_st - Binds a surface to a Screen Target
  171. *
  172. * @dev_priv: VMW DRM device
  173. * @stdu: display unit affected
  174. * @res: Buffer to bind to the screen target. Set to NULL to blank screen.
  175. *
  176. * Binding a surface to a Screen Target the same as flipping
  177. */
  178. static int vmw_stdu_bind_st(struct vmw_private *dev_priv,
  179. struct vmw_screen_target_display_unit *stdu,
  180. const struct vmw_resource *res)
  181. {
  182. SVGA3dSurfaceImageId image;
  183. struct {
  184. SVGA3dCmdHeader header;
  185. SVGA3dCmdBindGBScreenTarget body;
  186. } *cmd;
  187. if (!stdu->defined) {
  188. DRM_ERROR("No screen target defined\n");
  189. return -EINVAL;
  190. }
  191. /* Set up image using information in vfb */
  192. memset(&image, 0, sizeof(image));
  193. image.sid = res ? res->id : SVGA3D_INVALID_ID;
  194. cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  195. if (unlikely(cmd == NULL)) {
  196. DRM_ERROR("Out of FIFO space binding a screen target\n");
  197. return -ENOMEM;
  198. }
  199. cmd->header.id = SVGA_3D_CMD_BIND_GB_SCREENTARGET;
  200. cmd->header.size = sizeof(cmd->body);
  201. cmd->body.stid = stdu->base.unit;
  202. cmd->body.image = image;
  203. vmw_fifo_commit(dev_priv, sizeof(*cmd));
  204. return 0;
  205. }
  206. /**
  207. * vmw_stdu_populate_update - populate an UPDATE_GB_SCREENTARGET command with a
  208. * bounding box.
  209. *
  210. * @cmd: Pointer to command stream.
  211. * @unit: Screen target unit.
  212. * @left: Left side of bounding box.
  213. * @right: Right side of bounding box.
  214. * @top: Top side of bounding box.
  215. * @bottom: Bottom side of bounding box.
  216. */
  217. static void vmw_stdu_populate_update(void *cmd, int unit,
  218. s32 left, s32 right, s32 top, s32 bottom)
  219. {
  220. struct vmw_stdu_update *update = cmd;
  221. update->header.id = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET;
  222. update->header.size = sizeof(update->body);
  223. update->body.stid = unit;
  224. update->body.rect.x = left;
  225. update->body.rect.y = top;
  226. update->body.rect.w = right - left;
  227. update->body.rect.h = bottom - top;
  228. }
  229. /**
  230. * vmw_stdu_update_st - Full update of a Screen Target
  231. *
  232. * @dev_priv: VMW DRM device
  233. * @stdu: display unit affected
  234. *
  235. * This function needs to be called whenever the content of a screen
  236. * target has changed completely. Typically as a result of a backing
  237. * surface change.
  238. *
  239. * RETURNS:
  240. * 0 on success, error code on failure
  241. */
  242. static int vmw_stdu_update_st(struct vmw_private *dev_priv,
  243. struct vmw_screen_target_display_unit *stdu)
  244. {
  245. struct vmw_stdu_update *cmd;
  246. if (!stdu->defined) {
  247. DRM_ERROR("No screen target defined");
  248. return -EINVAL;
  249. }
  250. cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  251. if (unlikely(cmd == NULL)) {
  252. DRM_ERROR("Out of FIFO space updating a Screen Target\n");
  253. return -ENOMEM;
  254. }
  255. vmw_stdu_populate_update(cmd, stdu->base.unit,
  256. 0, stdu->display_width,
  257. 0, stdu->display_height);
  258. vmw_fifo_commit(dev_priv, sizeof(*cmd));
  259. return 0;
  260. }
  261. /**
  262. * vmw_stdu_destroy_st - Destroy a Screen Target
  263. *
  264. * @dev_priv: VMW DRM device
  265. * @stdu: display unit to destroy
  266. */
  267. static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,
  268. struct vmw_screen_target_display_unit *stdu)
  269. {
  270. int ret;
  271. struct {
  272. SVGA3dCmdHeader header;
  273. SVGA3dCmdDestroyGBScreenTarget body;
  274. } *cmd;
  275. /* Nothing to do if not successfully defined */
  276. if (unlikely(!stdu->defined))
  277. return 0;
  278. cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  279. if (unlikely(cmd == NULL)) {
  280. DRM_ERROR("Out of FIFO space, screen target not destroyed\n");
  281. return -ENOMEM;
  282. }
  283. cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET;
  284. cmd->header.size = sizeof(cmd->body);
  285. cmd->body.stid = stdu->base.unit;
  286. vmw_fifo_commit(dev_priv, sizeof(*cmd));
  287. /* Force sync */
  288. ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
  289. if (unlikely(ret != 0))
  290. DRM_ERROR("Failed to sync with HW");
  291. stdu->defined = false;
  292. stdu->display_width = 0;
  293. stdu->display_height = 0;
  294. return ret;
  295. }
  296. /**
  297. * vmw_stdu_crtc_mode_set_nofb - Updates screen target size
  298. *
  299. * @crtc: CRTC associated with the screen target
  300. *
  301. * This function defines/destroys a screen target
  302. *
  303. */
  304. static void vmw_stdu_crtc_mode_set_nofb(struct drm_crtc *crtc)
  305. {
  306. struct vmw_private *dev_priv;
  307. struct vmw_screen_target_display_unit *stdu;
  308. int ret;
  309. stdu = vmw_crtc_to_stdu(crtc);
  310. dev_priv = vmw_priv(crtc->dev);
  311. if (stdu->defined) {
  312. ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
  313. if (ret)
  314. DRM_ERROR("Failed to blank CRTC\n");
  315. (void) vmw_stdu_update_st(dev_priv, stdu);
  316. ret = vmw_stdu_destroy_st(dev_priv, stdu);
  317. if (ret)
  318. DRM_ERROR("Failed to destroy Screen Target\n");
  319. stdu->content_fb_type = SAME_AS_DISPLAY;
  320. }
  321. if (!crtc->state->enable)
  322. return;
  323. vmw_svga_enable(dev_priv);
  324. ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, crtc->x, crtc->y);
  325. if (ret)
  326. DRM_ERROR("Failed to define Screen Target of size %dx%d\n",
  327. crtc->x, crtc->y);
  328. }
  329. static void vmw_stdu_crtc_helper_prepare(struct drm_crtc *crtc)
  330. {
  331. }
  332. static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,
  333. struct drm_crtc_state *old_state)
  334. {
  335. struct vmw_private *dev_priv;
  336. struct vmw_screen_target_display_unit *stdu;
  337. struct vmw_framebuffer *vfb;
  338. struct drm_framebuffer *fb;
  339. stdu = vmw_crtc_to_stdu(crtc);
  340. dev_priv = vmw_priv(crtc->dev);
  341. fb = crtc->primary->fb;
  342. vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
  343. if (vfb)
  344. vmw_kms_add_active(dev_priv, &stdu->base, vfb);
  345. else
  346. vmw_kms_del_active(dev_priv, &stdu->base);
  347. }
  348. static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
  349. struct drm_crtc_state *old_state)
  350. {
  351. struct vmw_private *dev_priv;
  352. struct vmw_screen_target_display_unit *stdu;
  353. int ret;
  354. if (!crtc) {
  355. DRM_ERROR("CRTC is NULL\n");
  356. return;
  357. }
  358. stdu = vmw_crtc_to_stdu(crtc);
  359. dev_priv = vmw_priv(crtc->dev);
  360. if (stdu->defined) {
  361. ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
  362. if (ret)
  363. DRM_ERROR("Failed to blank CRTC\n");
  364. (void) vmw_stdu_update_st(dev_priv, stdu);
  365. ret = vmw_stdu_destroy_st(dev_priv, stdu);
  366. if (ret)
  367. DRM_ERROR("Failed to destroy Screen Target\n");
  368. stdu->content_fb_type = SAME_AS_DISPLAY;
  369. }
  370. }
  371. /**
  372. * vmw_stdu_crtc_page_flip - Binds a buffer to a screen target
  373. *
  374. * @crtc: CRTC to attach FB to
  375. * @fb: FB to attach
  376. * @event: Event to be posted. This event should've been alloced
  377. * using k[mz]alloc, and should've been completely initialized.
  378. * @page_flip_flags: Input flags.
  379. *
  380. * If the STDU uses the same display and content buffers, i.e. a true flip,
  381. * this function will replace the existing display buffer with the new content
  382. * buffer.
  383. *
  384. * If the STDU uses different display and content buffers, i.e. a blit, then
  385. * only the content buffer will be updated.
  386. *
  387. * RETURNS:
  388. * 0 on success, error code on failure
  389. */
  390. static int vmw_stdu_crtc_page_flip(struct drm_crtc *crtc,
  391. struct drm_framebuffer *new_fb,
  392. struct drm_pending_vblank_event *event,
  393. uint32_t flags,
  394. struct drm_modeset_acquire_ctx *ctx)
  395. {
  396. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  397. struct vmw_screen_target_display_unit *stdu = vmw_crtc_to_stdu(crtc);
  398. int ret;
  399. if (!stdu->defined || !vmw_kms_crtc_flippable(dev_priv, crtc))
  400. return -EINVAL;
  401. ret = drm_atomic_helper_page_flip(crtc, new_fb, event, flags, ctx);
  402. if (ret) {
  403. DRM_ERROR("Page flip error %d.\n", ret);
  404. return ret;
  405. }
  406. return 0;
  407. }
  408. /**
  409. * vmw_stdu_dmabuf_clip - Callback to encode a suface DMA command cliprect
  410. *
  411. * @dirty: The closure structure.
  412. *
  413. * Encodes a surface DMA command cliprect and updates the bounding box
  414. * for the DMA.
  415. */
  416. static void vmw_stdu_dmabuf_clip(struct vmw_kms_dirty *dirty)
  417. {
  418. struct vmw_stdu_dirty *ddirty =
  419. container_of(dirty, struct vmw_stdu_dirty, base);
  420. struct vmw_stdu_dma *cmd = dirty->cmd;
  421. struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
  422. blit += dirty->num_hits;
  423. blit->srcx = dirty->fb_x;
  424. blit->srcy = dirty->fb_y;
  425. blit->x = dirty->unit_x1;
  426. blit->y = dirty->unit_y1;
  427. blit->d = 1;
  428. blit->w = dirty->unit_x2 - dirty->unit_x1;
  429. blit->h = dirty->unit_y2 - dirty->unit_y1;
  430. dirty->num_hits++;
  431. if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM)
  432. return;
  433. /* Destination bounding box */
  434. ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
  435. ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
  436. ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
  437. ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
  438. }
  439. /**
  440. * vmw_stdu_dmabuf_fifo_commit - Callback to fill in and submit a DMA command.
  441. *
  442. * @dirty: The closure structure.
  443. *
  444. * Fills in the missing fields in a DMA command, and optionally encodes
  445. * a screen target update command, depending on transfer direction.
  446. */
  447. static void vmw_stdu_dmabuf_fifo_commit(struct vmw_kms_dirty *dirty)
  448. {
  449. struct vmw_stdu_dirty *ddirty =
  450. container_of(dirty, struct vmw_stdu_dirty, base);
  451. struct vmw_screen_target_display_unit *stdu =
  452. container_of(dirty->unit, typeof(*stdu), base);
  453. struct vmw_stdu_dma *cmd = dirty->cmd;
  454. struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
  455. SVGA3dCmdSurfaceDMASuffix *suffix =
  456. (SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits];
  457. size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix);
  458. if (!dirty->num_hits) {
  459. vmw_fifo_commit(dirty->dev_priv, 0);
  460. return;
  461. }
  462. cmd->header.id = SVGA_3D_CMD_SURFACE_DMA;
  463. cmd->header.size = sizeof(cmd->body) + blit_size;
  464. vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr);
  465. cmd->body.guest.pitch = ddirty->pitch;
  466. cmd->body.host.sid = stdu->display_srf->res.id;
  467. cmd->body.host.face = 0;
  468. cmd->body.host.mipmap = 0;
  469. cmd->body.transfer = ddirty->transfer;
  470. suffix->suffixSize = sizeof(*suffix);
  471. suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE;
  472. if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) {
  473. blit_size += sizeof(struct vmw_stdu_update);
  474. vmw_stdu_populate_update(&suffix[1], stdu->base.unit,
  475. ddirty->left, ddirty->right,
  476. ddirty->top, ddirty->bottom);
  477. }
  478. vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
  479. ddirty->left = ddirty->top = S32_MAX;
  480. ddirty->right = ddirty->bottom = S32_MIN;
  481. }
  482. /**
  483. * vmw_stdu_dmabuf_cpu_clip - Callback to encode a CPU blit
  484. *
  485. * @dirty: The closure structure.
  486. *
  487. * This function calculates the bounding box for all the incoming clips.
  488. */
  489. static void vmw_stdu_dmabuf_cpu_clip(struct vmw_kms_dirty *dirty)
  490. {
  491. struct vmw_stdu_dirty *ddirty =
  492. container_of(dirty, struct vmw_stdu_dirty, base);
  493. dirty->num_hits = 1;
  494. /* Calculate destination bounding box */
  495. ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
  496. ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
  497. ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
  498. ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
  499. /*
  500. * Calculate content bounding box. We only need the top-left
  501. * coordinate because width and height will be the same as the
  502. * destination bounding box above
  503. */
  504. ddirty->fb_left = min_t(s32, ddirty->fb_left, dirty->fb_x);
  505. ddirty->fb_top = min_t(s32, ddirty->fb_top, dirty->fb_y);
  506. }
  507. /**
  508. * vmw_stdu_dmabuf_cpu_commit - Callback to do a CPU blit from DMAbuf
  509. *
  510. * @dirty: The closure structure.
  511. *
  512. * For the special case when we cannot create a proxy surface in a
  513. * 2D VM, we have to do a CPU blit ourselves.
  514. */
  515. static void vmw_stdu_dmabuf_cpu_commit(struct vmw_kms_dirty *dirty)
  516. {
  517. struct vmw_stdu_dirty *ddirty =
  518. container_of(dirty, struct vmw_stdu_dirty, base);
  519. struct vmw_screen_target_display_unit *stdu =
  520. container_of(dirty->unit, typeof(*stdu), base);
  521. s32 width, height;
  522. s32 src_pitch, dst_pitch;
  523. struct ttm_buffer_object *src_bo, *dst_bo;
  524. u32 src_offset, dst_offset;
  525. struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(stdu->cpp);
  526. if (!dirty->num_hits)
  527. return;
  528. width = ddirty->right - ddirty->left;
  529. height = ddirty->bottom - ddirty->top;
  530. if (width == 0 || height == 0)
  531. return;
  532. /* Assume we are blitting from Guest (dmabuf) to Host (display_srf) */
  533. dst_pitch = stdu->display_srf->base_size.width * stdu->cpp;
  534. dst_bo = &stdu->display_srf->res.backup->base;
  535. dst_offset = ddirty->top * dst_pitch + ddirty->left * stdu->cpp;
  536. src_pitch = ddirty->pitch;
  537. src_bo = &ddirty->buf->base;
  538. src_offset = ddirty->fb_top * src_pitch + ddirty->fb_left * stdu->cpp;
  539. /* Swap src and dst if the assumption was wrong. */
  540. if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM) {
  541. swap(dst_pitch, src_pitch);
  542. swap(dst_bo, src_bo);
  543. swap(src_offset, dst_offset);
  544. }
  545. (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch,
  546. src_bo, src_offset, src_pitch,
  547. width * stdu->cpp, height, &diff);
  548. if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM &&
  549. drm_rect_visible(&diff.rect)) {
  550. struct vmw_private *dev_priv;
  551. struct vmw_stdu_update *cmd;
  552. struct drm_clip_rect region;
  553. int ret;
  554. /* We are updating the actual surface, not a proxy */
  555. region.x1 = diff.rect.x1;
  556. region.x2 = diff.rect.x2;
  557. region.y1 = diff.rect.y1;
  558. region.y2 = diff.rect.y2;
  559. ret = vmw_kms_update_proxy(
  560. (struct vmw_resource *) &stdu->display_srf->res,
  561. (const struct drm_clip_rect *) &region, 1, 1);
  562. if (ret)
  563. goto out_cleanup;
  564. dev_priv = vmw_priv(stdu->base.crtc.dev);
  565. cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  566. if (!cmd) {
  567. DRM_ERROR("Cannot reserve FIFO space to update STDU");
  568. goto out_cleanup;
  569. }
  570. vmw_stdu_populate_update(cmd, stdu->base.unit,
  571. region.x1, region.x2,
  572. region.y1, region.y2);
  573. vmw_fifo_commit(dev_priv, sizeof(*cmd));
  574. }
  575. out_cleanup:
  576. ddirty->left = ddirty->top = ddirty->fb_left = ddirty->fb_top = S32_MAX;
  577. ddirty->right = ddirty->bottom = S32_MIN;
  578. }
  579. /**
  580. * vmw_kms_stdu_dma - Perform a DMA transfer between a dma-buffer backed
  581. * framebuffer and the screen target system.
  582. *
  583. * @dev_priv: Pointer to the device private structure.
  584. * @file_priv: Pointer to a struct drm-file identifying the caller. May be
  585. * set to NULL, but then @user_fence_rep must also be set to NULL.
  586. * @vfb: Pointer to the dma-buffer backed framebuffer.
  587. * @clips: Array of clip rects. Either @clips or @vclips must be NULL.
  588. * @vclips: Alternate array of clip rects. Either @clips or @vclips must
  589. * be NULL.
  590. * @num_clips: Number of clip rects in @clips or @vclips.
  591. * @increment: Increment to use when looping over @clips or @vclips.
  592. * @to_surface: Whether to DMA to the screen target system as opposed to
  593. * from the screen target system.
  594. * @interruptible: Whether to perform waits interruptible if possible.
  595. * @crtc: If crtc is passed, perform stdu dma on that crtc only.
  596. *
  597. * If DMA-ing till the screen target system, the function will also notify
  598. * the screen target system that a bounding box of the cliprects has been
  599. * updated.
  600. * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
  601. * interrupted.
  602. */
  603. int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
  604. struct drm_file *file_priv,
  605. struct vmw_framebuffer *vfb,
  606. struct drm_vmw_fence_rep __user *user_fence_rep,
  607. struct drm_clip_rect *clips,
  608. struct drm_vmw_rect *vclips,
  609. uint32_t num_clips,
  610. int increment,
  611. bool to_surface,
  612. bool interruptible,
  613. struct drm_crtc *crtc)
  614. {
  615. struct vmw_dma_buffer *buf =
  616. container_of(vfb, struct vmw_framebuffer_dmabuf, base)->buffer;
  617. struct vmw_stdu_dirty ddirty;
  618. int ret;
  619. bool cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D);
  620. /*
  621. * VMs without 3D support don't have the surface DMA command and
  622. * we'll be using a CPU blit, and the framebuffer should be moved out
  623. * of VRAM.
  624. */
  625. ret = vmw_kms_helper_buffer_prepare(dev_priv, buf, interruptible,
  626. false, cpu_blit);
  627. if (ret)
  628. return ret;
  629. ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM :
  630. SVGA3D_READ_HOST_VRAM;
  631. ddirty.left = ddirty.top = S32_MAX;
  632. ddirty.right = ddirty.bottom = S32_MIN;
  633. ddirty.fb_left = ddirty.fb_top = S32_MAX;
  634. ddirty.pitch = vfb->base.pitches[0];
  635. ddirty.buf = buf;
  636. ddirty.base.fifo_commit = vmw_stdu_dmabuf_fifo_commit;
  637. ddirty.base.clip = vmw_stdu_dmabuf_clip;
  638. ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) +
  639. num_clips * sizeof(SVGA3dCopyBox) +
  640. sizeof(SVGA3dCmdSurfaceDMASuffix);
  641. if (to_surface)
  642. ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update);
  643. if (cpu_blit) {
  644. ddirty.base.fifo_commit = vmw_stdu_dmabuf_cpu_commit;
  645. ddirty.base.clip = vmw_stdu_dmabuf_cpu_clip;
  646. ddirty.base.fifo_reserve_size = 0;
  647. }
  648. ddirty.base.crtc = crtc;
  649. ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,
  650. 0, 0, num_clips, increment, &ddirty.base);
  651. vmw_kms_helper_buffer_finish(dev_priv, file_priv, buf, NULL,
  652. user_fence_rep);
  653. return ret;
  654. }
  655. /**
  656. * vmw_stdu_surface_clip - Callback to encode a surface copy command cliprect
  657. *
  658. * @dirty: The closure structure.
  659. *
  660. * Encodes a surface copy command cliprect and updates the bounding box
  661. * for the copy.
  662. */
  663. static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty)
  664. {
  665. struct vmw_stdu_dirty *sdirty =
  666. container_of(dirty, struct vmw_stdu_dirty, base);
  667. struct vmw_stdu_surface_copy *cmd = dirty->cmd;
  668. struct vmw_screen_target_display_unit *stdu =
  669. container_of(dirty->unit, typeof(*stdu), base);
  670. if (sdirty->sid != stdu->display_srf->res.id) {
  671. struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
  672. blit += dirty->num_hits;
  673. blit->srcx = dirty->fb_x;
  674. blit->srcy = dirty->fb_y;
  675. blit->x = dirty->unit_x1;
  676. blit->y = dirty->unit_y1;
  677. blit->d = 1;
  678. blit->w = dirty->unit_x2 - dirty->unit_x1;
  679. blit->h = dirty->unit_y2 - dirty->unit_y1;
  680. }
  681. dirty->num_hits++;
  682. /* Destination bounding box */
  683. sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
  684. sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
  685. sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
  686. sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
  687. }
  688. /**
  689. * vmw_stdu_surface_fifo_commit - Callback to fill in and submit a surface
  690. * copy command.
  691. *
  692. * @dirty: The closure structure.
  693. *
  694. * Fills in the missing fields in a surface copy command, and encodes a screen
  695. * target update command.
  696. */
  697. static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty)
  698. {
  699. struct vmw_stdu_dirty *sdirty =
  700. container_of(dirty, struct vmw_stdu_dirty, base);
  701. struct vmw_screen_target_display_unit *stdu =
  702. container_of(dirty->unit, typeof(*stdu), base);
  703. struct vmw_stdu_surface_copy *cmd = dirty->cmd;
  704. struct vmw_stdu_update *update;
  705. size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits;
  706. size_t commit_size;
  707. if (!dirty->num_hits) {
  708. vmw_fifo_commit(dirty->dev_priv, 0);
  709. return;
  710. }
  711. if (sdirty->sid != stdu->display_srf->res.id) {
  712. struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
  713. cmd->header.id = SVGA_3D_CMD_SURFACE_COPY;
  714. cmd->header.size = sizeof(cmd->body) + blit_size;
  715. cmd->body.src.sid = sdirty->sid;
  716. cmd->body.dest.sid = stdu->display_srf->res.id;
  717. update = (struct vmw_stdu_update *) &blit[dirty->num_hits];
  718. commit_size = sizeof(*cmd) + blit_size + sizeof(*update);
  719. } else {
  720. update = dirty->cmd;
  721. commit_size = sizeof(*update);
  722. }
  723. vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
  724. sdirty->right, sdirty->top, sdirty->bottom);
  725. vmw_fifo_commit(dirty->dev_priv, commit_size);
  726. sdirty->left = sdirty->top = S32_MAX;
  727. sdirty->right = sdirty->bottom = S32_MIN;
  728. }
  729. /**
  730. * vmw_kms_stdu_surface_dirty - Dirty part of a surface backed framebuffer
  731. *
  732. * @dev_priv: Pointer to the device private structure.
  733. * @framebuffer: Pointer to the surface-buffer backed framebuffer.
  734. * @clips: Array of clip rects. Either @clips or @vclips must be NULL.
  735. * @vclips: Alternate array of clip rects. Either @clips or @vclips must
  736. * be NULL.
  737. * @srf: Pointer to surface to blit from. If NULL, the surface attached
  738. * to @framebuffer will be used.
  739. * @dest_x: X coordinate offset to align @srf with framebuffer coordinates.
  740. * @dest_y: Y coordinate offset to align @srf with framebuffer coordinates.
  741. * @num_clips: Number of clip rects in @clips.
  742. * @inc: Increment to use when looping over @clips.
  743. * @out_fence: If non-NULL, will return a ref-counted pointer to a
  744. * struct vmw_fence_obj. The returned fence pointer may be NULL in which
  745. * case the device has already synchronized.
  746. * @crtc: If crtc is passed, perform surface dirty on that crtc only.
  747. *
  748. * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
  749. * interrupted.
  750. */
  751. int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
  752. struct vmw_framebuffer *framebuffer,
  753. struct drm_clip_rect *clips,
  754. struct drm_vmw_rect *vclips,
  755. struct vmw_resource *srf,
  756. s32 dest_x,
  757. s32 dest_y,
  758. unsigned num_clips, int inc,
  759. struct vmw_fence_obj **out_fence,
  760. struct drm_crtc *crtc)
  761. {
  762. struct vmw_framebuffer_surface *vfbs =
  763. container_of(framebuffer, typeof(*vfbs), base);
  764. struct vmw_stdu_dirty sdirty;
  765. struct vmw_validation_ctx ctx;
  766. int ret;
  767. if (!srf)
  768. srf = &vfbs->surface->res;
  769. ret = vmw_kms_helper_resource_prepare(srf, true, &ctx);
  770. if (ret)
  771. return ret;
  772. if (vfbs->is_dmabuf_proxy) {
  773. ret = vmw_kms_update_proxy(srf, clips, num_clips, inc);
  774. if (ret)
  775. goto out_finish;
  776. }
  777. sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit;
  778. sdirty.base.clip = vmw_kms_stdu_surface_clip;
  779. sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) +
  780. sizeof(SVGA3dCopyBox) * num_clips +
  781. sizeof(struct vmw_stdu_update);
  782. sdirty.base.crtc = crtc;
  783. sdirty.sid = srf->id;
  784. sdirty.left = sdirty.top = S32_MAX;
  785. sdirty.right = sdirty.bottom = S32_MIN;
  786. ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
  787. dest_x, dest_y, num_clips, inc,
  788. &sdirty.base);
  789. out_finish:
  790. vmw_kms_helper_resource_finish(&ctx, out_fence);
  791. return ret;
  792. }
  793. /*
  794. * Screen Target CRTC dispatch table
  795. */
  796. static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
  797. .gamma_set = vmw_du_crtc_gamma_set,
  798. .destroy = vmw_stdu_crtc_destroy,
  799. .reset = vmw_du_crtc_reset,
  800. .atomic_duplicate_state = vmw_du_crtc_duplicate_state,
  801. .atomic_destroy_state = vmw_du_crtc_destroy_state,
  802. .set_config = vmw_kms_set_config,
  803. .page_flip = vmw_stdu_crtc_page_flip,
  804. };
  805. /******************************************************************************
  806. * Screen Target Display Unit Encoder Functions
  807. *****************************************************************************/
  808. /**
  809. * vmw_stdu_encoder_destroy - cleans up the STDU
  810. *
  811. * @encoder: used the get the containing STDU
  812. *
  813. * vmwgfx cleans up crtc/encoder/connector all at the same time so technically
  814. * this can be a no-op. Nevertheless, it doesn't hurt of have this in case
  815. * the common KMS code changes and somehow vmw_stdu_crtc_destroy() doesn't
  816. * get called.
  817. */
  818. static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder)
  819. {
  820. vmw_stdu_destroy(vmw_encoder_to_stdu(encoder));
  821. }
  822. static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = {
  823. .destroy = vmw_stdu_encoder_destroy,
  824. };
  825. /******************************************************************************
  826. * Screen Target Display Unit Connector Functions
  827. *****************************************************************************/
  828. /**
  829. * vmw_stdu_connector_destroy - cleans up the STDU
  830. *
  831. * @connector: used to get the containing STDU
  832. *
  833. * vmwgfx cleans up crtc/encoder/connector all at the same time so technically
  834. * this can be a no-op. Nevertheless, it doesn't hurt of have this in case
  835. * the common KMS code changes and somehow vmw_stdu_crtc_destroy() doesn't
  836. * get called.
  837. */
  838. static void vmw_stdu_connector_destroy(struct drm_connector *connector)
  839. {
  840. vmw_stdu_destroy(vmw_connector_to_stdu(connector));
  841. }
  842. static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
  843. .dpms = vmw_du_connector_dpms,
  844. .detect = vmw_du_connector_detect,
  845. .fill_modes = vmw_du_connector_fill_modes,
  846. .set_property = vmw_du_connector_set_property,
  847. .destroy = vmw_stdu_connector_destroy,
  848. .reset = vmw_du_connector_reset,
  849. .atomic_duplicate_state = vmw_du_connector_duplicate_state,
  850. .atomic_destroy_state = vmw_du_connector_destroy_state,
  851. .atomic_set_property = vmw_du_connector_atomic_set_property,
  852. .atomic_get_property = vmw_du_connector_atomic_get_property,
  853. };
  854. static const struct
  855. drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = {
  856. .best_encoder = drm_atomic_helper_best_encoder,
  857. };
  858. /******************************************************************************
  859. * Screen Target Display Plane Functions
  860. *****************************************************************************/
  861. /**
  862. * vmw_stdu_primary_plane_cleanup_fb - Unpins the display surface
  863. *
  864. * @plane: display plane
  865. * @old_state: Contains the FB to clean up
  866. *
  867. * Unpins the display surface
  868. *
  869. * Returns 0 on success
  870. */
  871. static void
  872. vmw_stdu_primary_plane_cleanup_fb(struct drm_plane *plane,
  873. struct drm_plane_state *old_state)
  874. {
  875. struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
  876. if (vps->surf)
  877. WARN_ON(!vps->pinned);
  878. vmw_du_plane_cleanup_fb(plane, old_state);
  879. vps->content_fb_type = SAME_AS_DISPLAY;
  880. vps->cpp = 0;
  881. }
  882. /**
  883. * vmw_stdu_primary_plane_prepare_fb - Readies the display surface
  884. *
  885. * @plane: display plane
  886. * @new_state: info on the new plane state, including the FB
  887. *
  888. * This function allocates a new display surface if the content is
  889. * backed by a DMA. The display surface is pinned here, and it'll
  890. * be unpinned in .cleanup_fb()
  891. *
  892. * Returns 0 on success
  893. */
  894. static int
  895. vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane,
  896. struct drm_plane_state *new_state)
  897. {
  898. struct vmw_private *dev_priv = vmw_priv(plane->dev);
  899. struct drm_framebuffer *new_fb = new_state->fb;
  900. struct vmw_framebuffer *vfb;
  901. struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
  902. enum stdu_content_type new_content_type;
  903. struct vmw_framebuffer_surface *new_vfbs;
  904. struct drm_crtc *crtc = new_state->crtc;
  905. uint32_t hdisplay = new_state->crtc_w, vdisplay = new_state->crtc_h;
  906. int ret;
  907. /* No FB to prepare */
  908. if (!new_fb) {
  909. if (vps->surf) {
  910. WARN_ON(vps->pinned != 0);
  911. vmw_surface_unreference(&vps->surf);
  912. }
  913. return 0;
  914. }
  915. vfb = vmw_framebuffer_to_vfb(new_fb);
  916. new_vfbs = (vfb->dmabuf) ? NULL : vmw_framebuffer_to_vfbs(new_fb);
  917. if (new_vfbs && new_vfbs->surface->base_size.width == hdisplay &&
  918. new_vfbs->surface->base_size.height == vdisplay)
  919. new_content_type = SAME_AS_DISPLAY;
  920. else if (vfb->dmabuf)
  921. new_content_type = SEPARATE_DMA;
  922. else
  923. new_content_type = SEPARATE_SURFACE;
  924. if (new_content_type != SAME_AS_DISPLAY) {
  925. struct vmw_surface content_srf;
  926. struct drm_vmw_size display_base_size = {0};
  927. display_base_size.width = hdisplay;
  928. display_base_size.height = vdisplay;
  929. display_base_size.depth = 1;
  930. /*
  931. * If content buffer is a DMA buf, then we have to construct
  932. * surface info
  933. */
  934. if (new_content_type == SEPARATE_DMA) {
  935. switch (new_fb->format->cpp[0]*8) {
  936. case 32:
  937. content_srf.format = SVGA3D_X8R8G8B8;
  938. break;
  939. case 16:
  940. content_srf.format = SVGA3D_R5G6B5;
  941. break;
  942. case 8:
  943. content_srf.format = SVGA3D_P8;
  944. break;
  945. default:
  946. DRM_ERROR("Invalid format\n");
  947. return -EINVAL;
  948. }
  949. content_srf.flags = 0;
  950. content_srf.mip_levels[0] = 1;
  951. content_srf.multisample_count = 0;
  952. } else {
  953. content_srf = *new_vfbs->surface;
  954. }
  955. if (vps->surf) {
  956. struct drm_vmw_size cur_base_size = vps->surf->base_size;
  957. if (cur_base_size.width != display_base_size.width ||
  958. cur_base_size.height != display_base_size.height ||
  959. vps->surf->format != content_srf.format) {
  960. WARN_ON(vps->pinned != 0);
  961. vmw_surface_unreference(&vps->surf);
  962. }
  963. }
  964. if (!vps->surf) {
  965. ret = vmw_surface_gb_priv_define
  966. (crtc->dev,
  967. /* Kernel visible only */
  968. 0,
  969. content_srf.flags,
  970. content_srf.format,
  971. true, /* a scanout buffer */
  972. content_srf.mip_levels[0],
  973. content_srf.multisample_count,
  974. 0,
  975. display_base_size,
  976. &vps->surf);
  977. if (ret != 0) {
  978. DRM_ERROR("Couldn't allocate STDU surface.\n");
  979. return ret;
  980. }
  981. }
  982. } else {
  983. /*
  984. * prepare_fb and clean_fb should only take care of pinning
  985. * and unpinning. References are tracked by state objects.
  986. * The only time we add a reference in prepare_fb is if the
  987. * state object doesn't have a reference to begin with
  988. */
  989. if (vps->surf) {
  990. WARN_ON(vps->pinned != 0);
  991. vmw_surface_unreference(&vps->surf);
  992. }
  993. vps->surf = vmw_surface_reference(new_vfbs->surface);
  994. }
  995. if (vps->surf) {
  996. /* Pin new surface before flipping */
  997. ret = vmw_resource_pin(&vps->surf->res, false);
  998. if (ret)
  999. goto out_srf_unref;
  1000. vps->pinned++;
  1001. }
  1002. vps->content_fb_type = new_content_type;
  1003. /*
  1004. * This should only happen if the DMA buf is too large to create a
  1005. * proxy surface for.
  1006. * If we are a 2D VM with a DMA buffer then we have to use CPU blit
  1007. * so cache these mappings
  1008. */
  1009. if (vps->content_fb_type == SEPARATE_DMA &&
  1010. !(dev_priv->capabilities & SVGA_CAP_3D))
  1011. vps->cpp = new_fb->pitches[0] / new_fb->width;
  1012. return 0;
  1013. out_srf_unref:
  1014. vmw_surface_unreference(&vps->surf);
  1015. return ret;
  1016. }
  1017. /**
  1018. * vmw_stdu_primary_plane_atomic_update - formally switches STDU to new plane
  1019. *
  1020. * @plane: display plane
  1021. * @old_state: Only used to get crtc info
  1022. *
  1023. * Formally update stdu->display_srf to the new plane, and bind the new
  1024. * plane STDU. This function is called during the commit phase when
  1025. * all the preparation have been done and all the configurations have
  1026. * been checked.
  1027. */
  1028. static void
  1029. vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane,
  1030. struct drm_plane_state *old_state)
  1031. {
  1032. struct vmw_plane_state *vps = vmw_plane_state_to_vps(plane->state);
  1033. struct drm_crtc *crtc = plane->state->crtc;
  1034. struct vmw_screen_target_display_unit *stdu;
  1035. struct drm_pending_vblank_event *event;
  1036. struct vmw_private *dev_priv;
  1037. int ret;
  1038. /*
  1039. * We cannot really fail this function, so if we do, then output an
  1040. * error and maintain consistent atomic state.
  1041. */
  1042. if (crtc && plane->state->fb) {
  1043. struct vmw_framebuffer *vfb =
  1044. vmw_framebuffer_to_vfb(plane->state->fb);
  1045. struct drm_vmw_rect vclips;
  1046. stdu = vmw_crtc_to_stdu(crtc);
  1047. dev_priv = vmw_priv(crtc->dev);
  1048. stdu->display_srf = vps->surf;
  1049. stdu->content_fb_type = vps->content_fb_type;
  1050. stdu->cpp = vps->cpp;
  1051. vclips.x = crtc->x;
  1052. vclips.y = crtc->y;
  1053. vclips.w = crtc->mode.hdisplay;
  1054. vclips.h = crtc->mode.vdisplay;
  1055. ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res);
  1056. if (ret)
  1057. DRM_ERROR("Failed to bind surface to STDU.\n");
  1058. if (vfb->dmabuf)
  1059. ret = vmw_kms_stdu_dma(dev_priv, NULL, vfb, NULL, NULL,
  1060. &vclips, 1, 1, true, false,
  1061. crtc);
  1062. else
  1063. ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL,
  1064. &vclips, NULL, 0, 0,
  1065. 1, 1, NULL, crtc);
  1066. if (ret)
  1067. DRM_ERROR("Failed to update STDU.\n");
  1068. crtc->primary->fb = plane->state->fb;
  1069. } else {
  1070. crtc = old_state->crtc;
  1071. stdu = vmw_crtc_to_stdu(crtc);
  1072. dev_priv = vmw_priv(crtc->dev);
  1073. /*
  1074. * When disabling a plane, CRTC and FB should always be NULL
  1075. * together, otherwise it's an error.
  1076. * Here primary plane is being disable so blank the screen
  1077. * target display unit, if not already done.
  1078. */
  1079. if (!stdu->defined)
  1080. return;
  1081. ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
  1082. if (ret)
  1083. DRM_ERROR("Failed to blank STDU\n");
  1084. ret = vmw_stdu_update_st(dev_priv, stdu);
  1085. if (ret)
  1086. DRM_ERROR("Failed to update STDU.\n");
  1087. return;
  1088. }
  1089. event = crtc->state->event;
  1090. /*
  1091. * In case of failure and other cases, vblank event will be sent in
  1092. * vmw_du_crtc_atomic_flush.
  1093. */
  1094. if (event && (ret == 0)) {
  1095. struct vmw_fence_obj *fence = NULL;
  1096. struct drm_file *file_priv = event->base.file_priv;
  1097. vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
  1098. /*
  1099. * If fence is NULL, then already sync.
  1100. */
  1101. if (fence) {
  1102. ret = vmw_event_fence_action_queue(
  1103. file_priv, fence, &event->base,
  1104. &event->event.vbl.tv_sec,
  1105. &event->event.vbl.tv_usec,
  1106. true);
  1107. if (ret)
  1108. DRM_ERROR("Failed to queue event on fence.\n");
  1109. else
  1110. crtc->state->event = NULL;
  1111. vmw_fence_obj_unreference(&fence);
  1112. }
  1113. } else {
  1114. (void) vmw_fifo_flush(dev_priv, false);
  1115. }
  1116. }
  1117. static const struct drm_plane_funcs vmw_stdu_plane_funcs = {
  1118. .update_plane = drm_atomic_helper_update_plane,
  1119. .disable_plane = drm_atomic_helper_disable_plane,
  1120. .destroy = vmw_du_primary_plane_destroy,
  1121. .reset = vmw_du_plane_reset,
  1122. .atomic_duplicate_state = vmw_du_plane_duplicate_state,
  1123. .atomic_destroy_state = vmw_du_plane_destroy_state,
  1124. };
  1125. static const struct drm_plane_funcs vmw_stdu_cursor_funcs = {
  1126. .update_plane = drm_atomic_helper_update_plane,
  1127. .disable_plane = drm_atomic_helper_disable_plane,
  1128. .destroy = vmw_du_cursor_plane_destroy,
  1129. .reset = vmw_du_plane_reset,
  1130. .atomic_duplicate_state = vmw_du_plane_duplicate_state,
  1131. .atomic_destroy_state = vmw_du_plane_destroy_state,
  1132. };
  1133. /*
  1134. * Atomic Helpers
  1135. */
  1136. static const struct
  1137. drm_plane_helper_funcs vmw_stdu_cursor_plane_helper_funcs = {
  1138. .atomic_check = vmw_du_cursor_plane_atomic_check,
  1139. .atomic_update = vmw_du_cursor_plane_atomic_update,
  1140. .prepare_fb = vmw_du_cursor_plane_prepare_fb,
  1141. .cleanup_fb = vmw_du_plane_cleanup_fb,
  1142. };
  1143. static const struct
  1144. drm_plane_helper_funcs vmw_stdu_primary_plane_helper_funcs = {
  1145. .atomic_check = vmw_du_primary_plane_atomic_check,
  1146. .atomic_update = vmw_stdu_primary_plane_atomic_update,
  1147. .prepare_fb = vmw_stdu_primary_plane_prepare_fb,
  1148. .cleanup_fb = vmw_stdu_primary_plane_cleanup_fb,
  1149. };
  1150. static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = {
  1151. .prepare = vmw_stdu_crtc_helper_prepare,
  1152. .mode_set_nofb = vmw_stdu_crtc_mode_set_nofb,
  1153. .atomic_check = vmw_du_crtc_atomic_check,
  1154. .atomic_begin = vmw_du_crtc_atomic_begin,
  1155. .atomic_flush = vmw_du_crtc_atomic_flush,
  1156. .atomic_enable = vmw_stdu_crtc_atomic_enable,
  1157. .atomic_disable = vmw_stdu_crtc_atomic_disable,
  1158. };
  1159. /**
  1160. * vmw_stdu_init - Sets up a Screen Target Display Unit
  1161. *
  1162. * @dev_priv: VMW DRM device
  1163. * @unit: unit number range from 0 to VMWGFX_NUM_DISPLAY_UNITS
  1164. *
  1165. * This function is called once per CRTC, and allocates one Screen Target
  1166. * display unit to represent that CRTC. Since the SVGA device does not separate
  1167. * out encoder and connector, they are represented as part of the STDU as well.
  1168. */
  1169. static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
  1170. {
  1171. struct vmw_screen_target_display_unit *stdu;
  1172. struct drm_device *dev = dev_priv->dev;
  1173. struct drm_connector *connector;
  1174. struct drm_encoder *encoder;
  1175. struct drm_plane *primary, *cursor;
  1176. struct drm_crtc *crtc;
  1177. int ret;
  1178. stdu = kzalloc(sizeof(*stdu), GFP_KERNEL);
  1179. if (!stdu)
  1180. return -ENOMEM;
  1181. stdu->base.unit = unit;
  1182. crtc = &stdu->base.crtc;
  1183. encoder = &stdu->base.encoder;
  1184. connector = &stdu->base.connector;
  1185. primary = &stdu->base.primary;
  1186. cursor = &stdu->base.cursor;
  1187. stdu->base.pref_active = (unit == 0);
  1188. stdu->base.pref_width = dev_priv->initial_width;
  1189. stdu->base.pref_height = dev_priv->initial_height;
  1190. /*
  1191. * Remove this after enabling atomic because property values can
  1192. * only exist in a state object
  1193. */
  1194. stdu->base.is_implicit = false;
  1195. /* Initialize primary plane */
  1196. vmw_du_plane_reset(primary);
  1197. ret = drm_universal_plane_init(dev, primary,
  1198. 0, &vmw_stdu_plane_funcs,
  1199. vmw_primary_plane_formats,
  1200. ARRAY_SIZE(vmw_primary_plane_formats),
  1201. NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
  1202. if (ret) {
  1203. DRM_ERROR("Failed to initialize primary plane");
  1204. goto err_free;
  1205. }
  1206. drm_plane_helper_add(primary, &vmw_stdu_primary_plane_helper_funcs);
  1207. /* Initialize cursor plane */
  1208. vmw_du_plane_reset(cursor);
  1209. ret = drm_universal_plane_init(dev, cursor,
  1210. 0, &vmw_stdu_cursor_funcs,
  1211. vmw_cursor_plane_formats,
  1212. ARRAY_SIZE(vmw_cursor_plane_formats),
  1213. NULL, DRM_PLANE_TYPE_CURSOR, NULL);
  1214. if (ret) {
  1215. DRM_ERROR("Failed to initialize cursor plane");
  1216. drm_plane_cleanup(&stdu->base.primary);
  1217. goto err_free;
  1218. }
  1219. drm_plane_helper_add(cursor, &vmw_stdu_cursor_plane_helper_funcs);
  1220. vmw_du_connector_reset(connector);
  1221. ret = drm_connector_init(dev, connector, &vmw_stdu_connector_funcs,
  1222. DRM_MODE_CONNECTOR_VIRTUAL);
  1223. if (ret) {
  1224. DRM_ERROR("Failed to initialize connector\n");
  1225. goto err_free;
  1226. }
  1227. drm_connector_helper_add(connector, &vmw_stdu_connector_helper_funcs);
  1228. connector->status = vmw_du_connector_detect(connector, false);
  1229. vmw_connector_state_to_vcs(connector->state)->is_implicit = false;
  1230. ret = drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs,
  1231. DRM_MODE_ENCODER_VIRTUAL, NULL);
  1232. if (ret) {
  1233. DRM_ERROR("Failed to initialize encoder\n");
  1234. goto err_free_connector;
  1235. }
  1236. (void) drm_mode_connector_attach_encoder(connector, encoder);
  1237. encoder->possible_crtcs = (1 << unit);
  1238. encoder->possible_clones = 0;
  1239. ret = drm_connector_register(connector);
  1240. if (ret) {
  1241. DRM_ERROR("Failed to register connector\n");
  1242. goto err_free_encoder;
  1243. }
  1244. vmw_du_crtc_reset(crtc);
  1245. ret = drm_crtc_init_with_planes(dev, crtc, &stdu->base.primary,
  1246. &stdu->base.cursor,
  1247. &vmw_stdu_crtc_funcs, NULL);
  1248. if (ret) {
  1249. DRM_ERROR("Failed to initialize CRTC\n");
  1250. goto err_free_unregister;
  1251. }
  1252. drm_crtc_helper_add(crtc, &vmw_stdu_crtc_helper_funcs);
  1253. drm_mode_crtc_set_gamma_size(crtc, 256);
  1254. drm_object_attach_property(&connector->base,
  1255. dev_priv->hotplug_mode_update_property, 1);
  1256. drm_object_attach_property(&connector->base,
  1257. dev->mode_config.suggested_x_property, 0);
  1258. drm_object_attach_property(&connector->base,
  1259. dev->mode_config.suggested_y_property, 0);
  1260. if (dev_priv->implicit_placement_property)
  1261. drm_object_attach_property
  1262. (&connector->base,
  1263. dev_priv->implicit_placement_property,
  1264. stdu->base.is_implicit);
  1265. return 0;
  1266. err_free_unregister:
  1267. drm_connector_unregister(connector);
  1268. err_free_encoder:
  1269. drm_encoder_cleanup(encoder);
  1270. err_free_connector:
  1271. drm_connector_cleanup(connector);
  1272. err_free:
  1273. kfree(stdu);
  1274. return ret;
  1275. }
  1276. /**
  1277. * vmw_stdu_destroy - Cleans up a vmw_screen_target_display_unit
  1278. *
  1279. * @stdu: Screen Target Display Unit to be destroyed
  1280. *
  1281. * Clean up after vmw_stdu_init
  1282. */
  1283. static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu)
  1284. {
  1285. vmw_du_cleanup(&stdu->base);
  1286. kfree(stdu);
  1287. }
  1288. /******************************************************************************
  1289. * Screen Target Display KMS Functions
  1290. *
  1291. * These functions are called by the common KMS code in vmwgfx_kms.c
  1292. *****************************************************************************/
  1293. /**
  1294. * vmw_kms_stdu_init_display - Initializes a Screen Target based display
  1295. *
  1296. * @dev_priv: VMW DRM device
  1297. *
  1298. * This function initialize a Screen Target based display device. It checks
  1299. * the capability bits to make sure the underlying hardware can support
  1300. * screen targets, and then creates the maximum number of CRTCs, a.k.a Display
  1301. * Units, as supported by the display hardware.
  1302. *
  1303. * RETURNS:
  1304. * 0 on success, error code otherwise
  1305. */
  1306. int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
  1307. {
  1308. struct drm_device *dev = dev_priv->dev;
  1309. int i, ret;
  1310. /* Do nothing if Screen Target support is turned off */
  1311. if (!VMWGFX_ENABLE_SCREEN_TARGET_OTABLE)
  1312. return -ENOSYS;
  1313. if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
  1314. return -ENOSYS;
  1315. ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
  1316. if (unlikely(ret != 0))
  1317. return ret;
  1318. dev_priv->active_display_unit = vmw_du_screen_target;
  1319. if (dev_priv->capabilities & SVGA_CAP_3D) {
  1320. /*
  1321. * For 3D VMs, display (scanout) buffer size is the smaller of
  1322. * max texture and max STDU
  1323. */
  1324. uint32_t max_width, max_height;
  1325. max_width = min(dev_priv->texture_max_width,
  1326. dev_priv->stdu_max_width);
  1327. max_height = min(dev_priv->texture_max_height,
  1328. dev_priv->stdu_max_height);
  1329. dev->mode_config.max_width = max_width;
  1330. dev->mode_config.max_height = max_height;
  1331. } else {
  1332. /*
  1333. * Given various display aspect ratios, there's no way to
  1334. * estimate these using prim_bb_mem. So just set these to
  1335. * something arbitrarily large and we will reject any layout
  1336. * that doesn't fit prim_bb_mem later
  1337. */
  1338. dev->mode_config.max_width = 8192;
  1339. dev->mode_config.max_height = 8192;
  1340. }
  1341. vmw_kms_create_implicit_placement_property(dev_priv, false);
  1342. for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
  1343. ret = vmw_stdu_init(dev_priv, i);
  1344. if (unlikely(ret != 0)) {
  1345. DRM_ERROR("Failed to initialize STDU %d", i);
  1346. return ret;
  1347. }
  1348. }
  1349. DRM_INFO("Screen Target Display device initialized\n");
  1350. return 0;
  1351. }