vc4_regs.h 34 KB

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  1. /*
  2. * Copyright © 2014-2015 Broadcom
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #ifndef VC4_REGS_H
  9. #define VC4_REGS_H
  10. #include <linux/bitops.h>
  11. #define VC4_MASK(high, low) ((u32)GENMASK(high, low))
  12. /* Using the GNU statement expression extension */
  13. #define VC4_SET_FIELD(value, field) \
  14. ({ \
  15. uint32_t fieldval = (value) << field##_SHIFT; \
  16. WARN_ON((fieldval & ~field##_MASK) != 0); \
  17. fieldval & field##_MASK; \
  18. })
  19. #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \
  20. field##_SHIFT)
  21. #define V3D_IDENT0 0x00000
  22. # define V3D_EXPECTED_IDENT0 \
  23. ((2 << 24) | \
  24. ('V' << 0) | \
  25. ('3' << 8) | \
  26. ('D' << 16))
  27. #define V3D_IDENT1 0x00004
  28. /* Multiples of 1kb */
  29. # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
  30. # define V3D_IDENT1_VPM_SIZE_SHIFT 28
  31. # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
  32. # define V3D_IDENT1_NSEM_SHIFT 16
  33. # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
  34. # define V3D_IDENT1_TUPS_SHIFT 12
  35. # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
  36. # define V3D_IDENT1_QUPS_SHIFT 8
  37. # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
  38. # define V3D_IDENT1_NSLC_SHIFT 4
  39. # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
  40. # define V3D_IDENT1_REV_SHIFT 0
  41. #define V3D_IDENT2 0x00008
  42. #define V3D_SCRATCH 0x00010
  43. #define V3D_L2CACTL 0x00020
  44. # define V3D_L2CACTL_L2CCLR BIT(2)
  45. # define V3D_L2CACTL_L2CDIS BIT(1)
  46. # define V3D_L2CACTL_L2CENA BIT(0)
  47. #define V3D_SLCACTL 0x00024
  48. # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
  49. # define V3D_SLCACTL_T1CC_SHIFT 24
  50. # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
  51. # define V3D_SLCACTL_T0CC_SHIFT 16
  52. # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
  53. # define V3D_SLCACTL_UCC_SHIFT 8
  54. # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
  55. # define V3D_SLCACTL_ICC_SHIFT 0
  56. #define V3D_INTCTL 0x00030
  57. #define V3D_INTENA 0x00034
  58. #define V3D_INTDIS 0x00038
  59. # define V3D_INT_SPILLUSE BIT(3)
  60. # define V3D_INT_OUTOMEM BIT(2)
  61. # define V3D_INT_FLDONE BIT(1)
  62. # define V3D_INT_FRDONE BIT(0)
  63. #define V3D_CT0CS 0x00100
  64. #define V3D_CT1CS 0x00104
  65. #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
  66. # define V3D_CTRSTA BIT(15)
  67. # define V3D_CTSEMA BIT(12)
  68. # define V3D_CTRTSD BIT(8)
  69. # define V3D_CTRUN BIT(5)
  70. # define V3D_CTSUBS BIT(4)
  71. # define V3D_CTERR BIT(3)
  72. # define V3D_CTMODE BIT(0)
  73. #define V3D_CT0EA 0x00108
  74. #define V3D_CT1EA 0x0010c
  75. #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
  76. #define V3D_CT0CA 0x00110
  77. #define V3D_CT1CA 0x00114
  78. #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
  79. #define V3D_CT00RA0 0x00118
  80. #define V3D_CT01RA0 0x0011c
  81. #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
  82. #define V3D_CT0LC 0x00120
  83. #define V3D_CT1LC 0x00124
  84. #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
  85. #define V3D_CT0PC 0x00128
  86. #define V3D_CT1PC 0x0012c
  87. #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
  88. #define V3D_PCS 0x00130
  89. # define V3D_BMOOM BIT(8)
  90. # define V3D_RMBUSY BIT(3)
  91. # define V3D_RMACTIVE BIT(2)
  92. # define V3D_BMBUSY BIT(1)
  93. # define V3D_BMACTIVE BIT(0)
  94. #define V3D_BFC 0x00134
  95. #define V3D_RFC 0x00138
  96. #define V3D_BPCA 0x00300
  97. #define V3D_BPCS 0x00304
  98. #define V3D_BPOA 0x00308
  99. #define V3D_BPOS 0x0030c
  100. #define V3D_BXCF 0x00310
  101. #define V3D_SQRSV0 0x00410
  102. #define V3D_SQRSV1 0x00414
  103. #define V3D_SQCNTL 0x00418
  104. #define V3D_SRQPC 0x00430
  105. #define V3D_SRQUA 0x00434
  106. #define V3D_SRQUL 0x00438
  107. #define V3D_SRQCS 0x0043c
  108. #define V3D_VPACNTL 0x00500
  109. #define V3D_VPMBASE 0x00504
  110. #define V3D_PCTRC 0x00670
  111. #define V3D_PCTRE 0x00674
  112. # define V3D_PCTRE_EN BIT(31)
  113. #define V3D_PCTR(x) (0x00680 + ((x) * 8))
  114. #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
  115. #define V3D_DBGE 0x00f00
  116. #define V3D_FDBGO 0x00f04
  117. #define V3D_FDBGB 0x00f08
  118. #define V3D_FDBGR 0x00f0c
  119. #define V3D_FDBGS 0x00f10
  120. #define V3D_ERRSTAT 0x00f20
  121. #define PV_CONTROL 0x00
  122. # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
  123. # define PV_CONTROL_FORMAT_SHIFT 21
  124. # define PV_CONTROL_FORMAT_24 0
  125. # define PV_CONTROL_FORMAT_DSIV_16 1
  126. # define PV_CONTROL_FORMAT_DSIC_16 2
  127. # define PV_CONTROL_FORMAT_DSIV_18 3
  128. # define PV_CONTROL_FORMAT_DSIV_24 4
  129. # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
  130. # define PV_CONTROL_FIFO_LEVEL_SHIFT 15
  131. # define PV_CONTROL_CLR_AT_START BIT(14)
  132. # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
  133. # define PV_CONTROL_WAIT_HSTART BIT(12)
  134. # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
  135. # define PV_CONTROL_PIXEL_REP_SHIFT 4
  136. # define PV_CONTROL_CLK_SELECT_DSI 0
  137. # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
  138. # define PV_CONTROL_CLK_SELECT_VEC 2
  139. # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
  140. # define PV_CONTROL_CLK_SELECT_SHIFT 2
  141. # define PV_CONTROL_FIFO_CLR BIT(1)
  142. # define PV_CONTROL_EN BIT(0)
  143. #define PV_V_CONTROL 0x04
  144. # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
  145. # define PV_VCONTROL_ODD_DELAY_SHIFT 6
  146. # define PV_VCONTROL_ODD_FIRST BIT(5)
  147. # define PV_VCONTROL_INTERLACE BIT(4)
  148. # define PV_VCONTROL_DSI BIT(3)
  149. # define PV_VCONTROL_COMMAND BIT(2)
  150. # define PV_VCONTROL_CONTINUOUS BIT(1)
  151. # define PV_VCONTROL_VIDEN BIT(0)
  152. #define PV_VSYNCD_EVEN 0x08
  153. #define PV_HORZA 0x0c
  154. # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
  155. # define PV_HORZA_HBP_SHIFT 16
  156. # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
  157. # define PV_HORZA_HSYNC_SHIFT 0
  158. #define PV_HORZB 0x10
  159. # define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
  160. # define PV_HORZB_HFP_SHIFT 16
  161. # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
  162. # define PV_HORZB_HACTIVE_SHIFT 0
  163. #define PV_VERTA 0x14
  164. # define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
  165. # define PV_VERTA_VBP_SHIFT 16
  166. # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
  167. # define PV_VERTA_VSYNC_SHIFT 0
  168. #define PV_VERTB 0x18
  169. # define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
  170. # define PV_VERTB_VFP_SHIFT 16
  171. # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
  172. # define PV_VERTB_VACTIVE_SHIFT 0
  173. #define PV_VERTA_EVEN 0x1c
  174. #define PV_VERTB_EVEN 0x20
  175. #define PV_INTEN 0x24
  176. #define PV_INTSTAT 0x28
  177. # define PV_INT_VID_IDLE BIT(9)
  178. # define PV_INT_VFP_END BIT(8)
  179. # define PV_INT_VFP_START BIT(7)
  180. # define PV_INT_VACT_START BIT(6)
  181. # define PV_INT_VBP_START BIT(5)
  182. # define PV_INT_VSYNC_START BIT(4)
  183. # define PV_INT_HFP_START BIT(3)
  184. # define PV_INT_HACT_START BIT(2)
  185. # define PV_INT_HBP_START BIT(1)
  186. # define PV_INT_HSYNC_START BIT(0)
  187. #define PV_STAT 0x2c
  188. #define PV_HACT_ACT 0x30
  189. #define SCALER_DISPCTRL 0x00000000
  190. /* Global register for clock gating the HVS */
  191. # define SCALER_DISPCTRL_ENABLE BIT(31)
  192. # define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
  193. # define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
  194. # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
  195. # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
  196. /* Enables Display 0 short line and underrun contribution to
  197. * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
  198. * always enabled.
  199. */
  200. # define SCALER_DISPCTRL_DSP0EISLUR BIT(13)
  201. # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12)
  202. # define SCALER_DISPCTRL_DSP2EIEOF BIT(11)
  203. # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10)
  204. # define SCALER_DISPCTRL_DSP1EIEOF BIT(9)
  205. /* Enables Display 0 end-of-line-N contribution to
  206. * SCALER_DISPSTAT_IRQDISP0
  207. */
  208. # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8)
  209. /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
  210. # define SCALER_DISPCTRL_DSP0EIEOF BIT(7)
  211. # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
  212. # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
  213. # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
  214. # define SCALER_DISPCTRL_DISP2EIRQ BIT(3)
  215. # define SCALER_DISPCTRL_DISP1EIRQ BIT(2)
  216. /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
  217. * bits and short frames..
  218. */
  219. # define SCALER_DISPCTRL_DISP0EIRQ BIT(1)
  220. /* Enables interrupt generation on scaler profiler interrupt. */
  221. # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
  222. #define SCALER_DISPSTAT 0x00000004
  223. # define SCALER_DISPSTAT_COBLOW2 BIT(29)
  224. # define SCALER_DISPSTAT_EOLN2 BIT(28)
  225. # define SCALER_DISPSTAT_ESFRAME2 BIT(27)
  226. # define SCALER_DISPSTAT_ESLINE2 BIT(26)
  227. # define SCALER_DISPSTAT_EUFLOW2 BIT(25)
  228. # define SCALER_DISPSTAT_EOF2 BIT(24)
  229. # define SCALER_DISPSTAT_COBLOW1 BIT(21)
  230. # define SCALER_DISPSTAT_EOLN1 BIT(20)
  231. # define SCALER_DISPSTAT_ESFRAME1 BIT(19)
  232. # define SCALER_DISPSTAT_ESLINE1 BIT(18)
  233. # define SCALER_DISPSTAT_EUFLOW1 BIT(17)
  234. # define SCALER_DISPSTAT_EOF1 BIT(16)
  235. # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
  236. # define SCALER_DISPSTAT_RESP_SHIFT 14
  237. # define SCALER_DISPSTAT_RESP_OKAY 0
  238. # define SCALER_DISPSTAT_RESP_EXOKAY 1
  239. # define SCALER_DISPSTAT_RESP_SLVERR 2
  240. # define SCALER_DISPSTAT_RESP_DECERR 3
  241. # define SCALER_DISPSTAT_COBLOW0 BIT(13)
  242. /* Set when the DISPEOLN line is done compositing. */
  243. # define SCALER_DISPSTAT_EOLN0 BIT(12)
  244. /* Set when VSTART is seen but there are still pixels in the current
  245. * output line.
  246. */
  247. # define SCALER_DISPSTAT_ESFRAME0 BIT(11)
  248. /* Set when HSTART is seen but there are still pixels in the current
  249. * output line.
  250. */
  251. # define SCALER_DISPSTAT_ESLINE0 BIT(10)
  252. /* Set when the the downstream tries to read from the display FIFO
  253. * while it's empty.
  254. */
  255. # define SCALER_DISPSTAT_EUFLOW0 BIT(9)
  256. /* Set when the display mode changes from RUN to EOF */
  257. # define SCALER_DISPSTAT_EOF0 BIT(8)
  258. /* Set on AXI invalid DMA ID error. */
  259. # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
  260. /* Set on AXI slave read decode error */
  261. # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
  262. /* Set on AXI slave write decode error */
  263. # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
  264. /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or
  265. * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
  266. */
  267. # define SCALER_DISPSTAT_IRQDMA BIT(4)
  268. # define SCALER_DISPSTAT_IRQDISP2 BIT(3)
  269. # define SCALER_DISPSTAT_IRQDISP1 BIT(2)
  270. /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
  271. * corresponding interrupt bit is enabled in DISPCTRL.
  272. */
  273. # define SCALER_DISPSTAT_IRQDISP0 BIT(1)
  274. /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */
  275. # define SCALER_DISPSTAT_IRQSCL BIT(0)
  276. #define SCALER_DISPID 0x00000008
  277. #define SCALER_DISPECTRL 0x0000000c
  278. #define SCALER_DISPPROF 0x00000010
  279. #define SCALER_DISPDITHER 0x00000014
  280. #define SCALER_DISPEOLN 0x00000018
  281. #define SCALER_DISPLIST0 0x00000020
  282. #define SCALER_DISPLIST1 0x00000024
  283. #define SCALER_DISPLIST2 0x00000028
  284. #define SCALER_DISPLSTAT 0x0000002c
  285. #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
  286. (x) * (SCALER_DISPLIST1 - \
  287. SCALER_DISPLIST0))
  288. #define SCALER_DISPLACT0 0x00000030
  289. #define SCALER_DISPLACT1 0x00000034
  290. #define SCALER_DISPLACT2 0x00000038
  291. #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
  292. (x) * (SCALER_DISPLACT1 - \
  293. SCALER_DISPLACT0))
  294. #define SCALER_DISPCTRL0 0x00000040
  295. # define SCALER_DISPCTRLX_ENABLE BIT(31)
  296. # define SCALER_DISPCTRLX_RESET BIT(30)
  297. # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
  298. # define SCALER_DISPCTRLX_WIDTH_SHIFT 12
  299. # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
  300. # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
  301. #define SCALER_DISPBKGND0 0x00000044
  302. # define SCALER_DISPBKGND_AUTOHS BIT(31)
  303. # define SCALER_DISPBKGND_INTERLACE BIT(30)
  304. # define SCALER_DISPBKGND_GAMMA BIT(29)
  305. # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
  306. # define SCALER_DISPBKGND_TESTMODE_SHIFT 25
  307. /* Enables filling the scaler line with the RGB value in the low 24
  308. * bits before compositing. Costs cycles, so should be skipped if
  309. * opaque display planes will cover everything.
  310. */
  311. # define SCALER_DISPBKGND_FILL BIT(24)
  312. #define SCALER_DISPSTAT0 0x00000048
  313. # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
  314. # define SCALER_DISPSTATX_MODE_SHIFT 30
  315. # define SCALER_DISPSTATX_MODE_DISABLED 0
  316. # define SCALER_DISPSTATX_MODE_INIT 1
  317. # define SCALER_DISPSTATX_MODE_RUN 2
  318. # define SCALER_DISPSTATX_MODE_EOF 3
  319. # define SCALER_DISPSTATX_FULL BIT(29)
  320. # define SCALER_DISPSTATX_EMPTY BIT(28)
  321. # define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12)
  322. # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12
  323. # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
  324. # define SCALER_DISPSTATX_LINE_SHIFT 0
  325. #define SCALER_DISPBASE0 0x0000004c
  326. /* Last pixel in the COB (display FIFO memory) allocated to this HVS
  327. * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
  328. * next COB base).
  329. */
  330. # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
  331. # define SCALER_DISPBASEX_TOP_SHIFT 16
  332. /* First pixel in the COB (display FIFO memory) allocated to this HVS
  333. * channel. Must be 4-pixel aligned.
  334. */
  335. # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
  336. # define SCALER_DISPBASEX_BASE_SHIFT 0
  337. #define SCALER_DISPCTRL1 0x00000050
  338. #define SCALER_DISPBKGND1 0x00000054
  339. #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
  340. (x) * (SCALER_DISPBKGND1 - \
  341. SCALER_DISPBKGND0))
  342. #define SCALER_DISPSTAT1 0x00000058
  343. #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
  344. (x) * (SCALER_DISPSTAT1 - \
  345. SCALER_DISPSTAT0))
  346. #define SCALER_DISPBASE1 0x0000005c
  347. #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
  348. (x) * (SCALER_DISPBASE1 - \
  349. SCALER_DISPBASE0))
  350. #define SCALER_DISPCTRL2 0x00000060
  351. #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
  352. (x) * (SCALER_DISPCTRL1 - \
  353. SCALER_DISPCTRL0))
  354. #define SCALER_DISPBKGND2 0x00000064
  355. #define SCALER_DISPSTAT2 0x00000068
  356. #define SCALER_DISPBASE2 0x0000006c
  357. #define SCALER_DISPALPHA2 0x00000070
  358. #define SCALER_GAMADDR 0x00000078
  359. # define SCALER_GAMADDR_AUTOINC BIT(31)
  360. /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
  361. * enabled.
  362. */
  363. # define SCALER_GAMADDR_SRAMENB BIT(30)
  364. #define SCALER_GAMDATA 0x000000e0
  365. #define SCALER_DLIST_START 0x00002000
  366. #define SCALER_DLIST_SIZE 0x00004000
  367. #define VC4_HDMI_CORE_REV 0x000
  368. #define VC4_HDMI_SW_RESET_CONTROL 0x004
  369. # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
  370. # define VC4_HDMI_SW_RESET_HDMI BIT(0)
  371. #define VC4_HDMI_HOTPLUG_INT 0x008
  372. #define VC4_HDMI_HOTPLUG 0x00c
  373. # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
  374. /* 3 bits per field, where each field maps from that corresponding MAI
  375. * bus channel to the given HDMI channel.
  376. */
  377. #define VC4_HDMI_MAI_CHANNEL_MAP 0x090
  378. #define VC4_HDMI_MAI_CONFIG 0x094
  379. # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
  380. # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
  381. # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
  382. # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
  383. /* Last received format word on the MAI bus. */
  384. #define VC4_HDMI_MAI_FORMAT 0x098
  385. #define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c
  386. # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
  387. # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
  388. # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
  389. # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
  390. # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
  391. # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10
  392. /* If set, then multichannel, otherwise 2 channel. */
  393. # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
  394. /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */
  395. # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
  396. # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
  397. # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
  398. #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0
  399. # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
  400. #define VC4_HDMI_RAM_PACKET_STATUS 0x0a4
  401. #define VC4_HDMI_CRP_CFG 0x0a8
  402. /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead
  403. * of pixel clock.
  404. */
  405. # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
  406. /* When set, no CRP packets will be sent. */
  407. # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
  408. /* If set, generates CTS values based on N, audio clock, and video
  409. * clock. N must be divisible by 128.
  410. */
  411. # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
  412. # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
  413. # define VC4_HDMI_CRP_CFG_N_SHIFT 0
  414. /* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */
  415. #define VC4_HDMI_CTS_0 0x0ac
  416. #define VC4_HDMI_CTS_1 0x0b0
  417. /* 20-bit fields containing number of clocks to send CTS0/1 before
  418. * switching to the other one.
  419. */
  420. #define VC4_HDMI_CTS_PERIOD_0 0x0b4
  421. #define VC4_HDMI_CTS_PERIOD_1 0x0b8
  422. #define VC4_HDMI_HORZA 0x0c4
  423. # define VC4_HDMI_HORZA_VPOS BIT(14)
  424. # define VC4_HDMI_HORZA_HPOS BIT(13)
  425. /* Horizontal active pixels (hdisplay). */
  426. # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
  427. # define VC4_HDMI_HORZA_HAP_SHIFT 0
  428. #define VC4_HDMI_HORZB 0x0c8
  429. /* Horizontal pack porch (htotal - hsync_end). */
  430. # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
  431. # define VC4_HDMI_HORZB_HBP_SHIFT 20
  432. /* Horizontal sync pulse (hsync_end - hsync_start). */
  433. # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
  434. # define VC4_HDMI_HORZB_HSP_SHIFT 10
  435. /* Horizontal front porch (hsync_start - hdisplay). */
  436. # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
  437. # define VC4_HDMI_HORZB_HFP_SHIFT 0
  438. #define VC4_HDMI_FIFO_CTL 0x05c
  439. # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
  440. # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
  441. # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
  442. # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
  443. # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
  444. # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
  445. # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
  446. # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
  447. # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
  448. # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
  449. # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
  450. #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0
  451. # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
  452. # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
  453. # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
  454. # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
  455. # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
  456. #define VC4_HDMI_VERTA0 0x0cc
  457. #define VC4_HDMI_VERTA1 0x0d4
  458. /* Vertical sync pulse (vsync_end - vsync_start). */
  459. # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
  460. # define VC4_HDMI_VERTA_VSP_SHIFT 20
  461. /* Vertical front porch (vsync_start - vdisplay). */
  462. # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
  463. # define VC4_HDMI_VERTA_VFP_SHIFT 13
  464. /* Vertical active lines (vdisplay). */
  465. # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
  466. # define VC4_HDMI_VERTA_VAL_SHIFT 0
  467. #define VC4_HDMI_VERTB0 0x0d0
  468. #define VC4_HDMI_VERTB1 0x0d8
  469. /* Vertical sync pulse offset (for interlaced) */
  470. # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
  471. # define VC4_HDMI_VERTB_VSPO_SHIFT 9
  472. /* Vertical pack porch (vtotal - vsync_end). */
  473. # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
  474. # define VC4_HDMI_VERTB_VBP_SHIFT 0
  475. #define VC4_HDMI_CEC_CNTRL_1 0x0e8
  476. /* Set when the transmission has ended. */
  477. # define VC4_HDMI_CEC_TX_EOM BIT(31)
  478. /* If set, transmission was acked on the 1st or 2nd attempt (only one
  479. * retry is attempted). If in continuous mode, this means TX needs to
  480. * be filled if !TX_EOM.
  481. */
  482. # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
  483. # define VC4_HDMI_CEC_RX_EOM BIT(29)
  484. # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
  485. /* Number of bytes received for the message. */
  486. # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
  487. # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
  488. /* Sets continuous receive mode. Generates interrupt after each 8
  489. * bytes to signal that RX_DATA should be consumed, and at RX_EOM.
  490. *
  491. * If disabled, maximum 16 bytes will be received (including header),
  492. * and interrupt at RX_EOM. Later bytes will be acked but not put
  493. * into the RX_DATA.
  494. */
  495. # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
  496. # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
  497. /* Set this after a CEC interrupt. */
  498. # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
  499. /* Starts a TX. Will wait for appropriate idel time before CEC
  500. * activity. Must be cleared in between transmits.
  501. */
  502. # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
  503. # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
  504. # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
  505. /* Device's CEC address */
  506. # define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
  507. # define VC4_HDMI_CEC_ADDR_SHIFT 12
  508. /* Divides off of HSM clock to generate CEC bit clock. */
  509. /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
  510. # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
  511. # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
  512. /* Set these fields to how many bit clock cycles get to that many
  513. * microseconds.
  514. */
  515. #define VC4_HDMI_CEC_CNTRL_2 0x0ec
  516. # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
  517. # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
  518. # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
  519. # define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
  520. # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
  521. # define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
  522. # define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
  523. # define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
  524. # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
  525. # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
  526. #define VC4_HDMI_CEC_CNTRL_3 0x0f0
  527. # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
  528. # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
  529. # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
  530. # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
  531. # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
  532. # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
  533. # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
  534. # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
  535. #define VC4_HDMI_CEC_CNTRL_4 0x0f4
  536. # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
  537. # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
  538. # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
  539. # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
  540. # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
  541. # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
  542. # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
  543. # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
  544. #define VC4_HDMI_CEC_CNTRL_5 0x0f8
  545. # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
  546. # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
  547. # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
  548. # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
  549. # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
  550. # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
  551. # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
  552. # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
  553. # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
  554. # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
  555. # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
  556. /* Transmit data, first byte is low byte of the 32-bit reg. MSB of
  557. * each byte transmitted first.
  558. */
  559. #define VC4_HDMI_CEC_TX_DATA_1 0x0fc
  560. #define VC4_HDMI_CEC_TX_DATA_2 0x100
  561. #define VC4_HDMI_CEC_TX_DATA_3 0x104
  562. #define VC4_HDMI_CEC_TX_DATA_4 0x108
  563. #define VC4_HDMI_CEC_RX_DATA_1 0x10c
  564. #define VC4_HDMI_CEC_RX_DATA_2 0x110
  565. #define VC4_HDMI_CEC_RX_DATA_3 0x114
  566. #define VC4_HDMI_CEC_RX_DATA_4 0x118
  567. #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
  568. #define VC4_HDMI_TX_PHY_CTL0 0x2c4
  569. # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
  570. /* Interrupt status bits */
  571. #define VC4_HDMI_CPU_STATUS 0x340
  572. #define VC4_HDMI_CPU_SET 0x344
  573. #define VC4_HDMI_CPU_CLEAR 0x348
  574. # define VC4_HDMI_CPU_CEC BIT(6)
  575. # define VC4_HDMI_CPU_HOTPLUG BIT(0)
  576. #define VC4_HDMI_CPU_MASK_STATUS 0x34c
  577. #define VC4_HDMI_CPU_MASK_SET 0x350
  578. #define VC4_HDMI_CPU_MASK_CLEAR 0x354
  579. #define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4))
  580. #define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24))
  581. #define VC4_HDMI_PACKET_STRIDE 0x24
  582. #define VC4_HD_M_CTL 0x00c
  583. /* Debug: Current receive value on the CEC pad. */
  584. # define VC4_HD_CECRXD BIT(9)
  585. /* Debug: Override CEC output to 0. */
  586. # define VC4_HD_CECOVR BIT(8)
  587. # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
  588. # define VC4_HD_M_RAM_STANDBY (3 << 4)
  589. # define VC4_HD_M_SW_RST BIT(2)
  590. # define VC4_HD_M_ENABLE BIT(0)
  591. #define VC4_HD_MAI_CTL 0x014
  592. /* Set when audio stream is received at a slower rate than the
  593. * sampling period, so MAI fifo goes empty. Write 1 to clear.
  594. */
  595. # define VC4_HD_MAI_CTL_DLATE BIT(15)
  596. # define VC4_HD_MAI_CTL_BUSY BIT(14)
  597. # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
  598. # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
  599. # define VC4_HD_MAI_CTL_FULL BIT(11)
  600. # define VC4_HD_MAI_CTL_EMPTY BIT(10)
  601. # define VC4_HD_MAI_CTL_FLUSH BIT(9)
  602. /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
  603. * through.
  604. */
  605. # define VC4_HD_MAI_CTL_PAREN BIT(8)
  606. # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)
  607. # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4
  608. # define VC4_HD_MAI_CTL_ENABLE BIT(3)
  609. /* Underflow error status bit, write 1 to clear. */
  610. # define VC4_HD_MAI_CTL_ERRORE BIT(2)
  611. /* Overflow error status bit, write 1 to clear. */
  612. # define VC4_HD_MAI_CTL_ERRORF BIT(1)
  613. /* Single-shot reset bit. Read value is undefined. */
  614. # define VC4_HD_MAI_CTL_RESET BIT(0)
  615. #define VC4_HD_MAI_THR 0x018
  616. # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
  617. # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
  618. # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
  619. # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
  620. # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
  621. # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
  622. # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
  623. # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
  624. /* Format header to be placed on the MAI data. Unused. */
  625. #define VC4_HD_MAI_FMT 0x01c
  626. /* Register for DMAing in audio data to be transported over the MAI
  627. * bus to the Falcon core.
  628. */
  629. #define VC4_HD_MAI_DATA 0x020
  630. /* Divider from HDMI HSM clock to MAI serial clock. Sampling period
  631. * converges to N / (M + 1) cycles.
  632. */
  633. #define VC4_HD_MAI_SMP 0x02c
  634. # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
  635. # define VC4_HD_MAI_SMP_N_SHIFT 8
  636. # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
  637. # define VC4_HD_MAI_SMP_M_SHIFT 0
  638. #define VC4_HD_VID_CTL 0x038
  639. # define VC4_HD_VID_CTL_ENABLE BIT(31)
  640. # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
  641. # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
  642. # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
  643. # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
  644. #define VC4_HD_CSC_CTL 0x040
  645. # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
  646. # define VC4_HD_CSC_CTL_ORDER_SHIFT 5
  647. # define VC4_HD_CSC_CTL_ORDER_RGB 0
  648. # define VC4_HD_CSC_CTL_ORDER_BGR 1
  649. # define VC4_HD_CSC_CTL_ORDER_BRG 2
  650. # define VC4_HD_CSC_CTL_ORDER_GRB 3
  651. # define VC4_HD_CSC_CTL_ORDER_GBR 4
  652. # define VC4_HD_CSC_CTL_ORDER_RBG 5
  653. # define VC4_HD_CSC_CTL_PADMSB BIT(4)
  654. # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
  655. # define VC4_HD_CSC_CTL_MODE_SHIFT 2
  656. # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
  657. # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
  658. # define VC4_HD_CSC_CTL_MODE_CUSTOM 3
  659. # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
  660. # define VC4_HD_CSC_CTL_ENABLE BIT(0)
  661. #define VC4_HD_CSC_12_11 0x044
  662. #define VC4_HD_CSC_14_13 0x048
  663. #define VC4_HD_CSC_22_21 0x04c
  664. #define VC4_HD_CSC_24_23 0x050
  665. #define VC4_HD_CSC_32_31 0x054
  666. #define VC4_HD_CSC_34_33 0x058
  667. #define VC4_HD_FRAME_COUNT 0x068
  668. /* HVS display list information. */
  669. #define HVS_BOOTLOADER_DLIST_END 32
  670. enum hvs_pixel_format {
  671. /* 8bpp */
  672. HVS_PIXEL_FORMAT_RGB332 = 0,
  673. /* 16bpp */
  674. HVS_PIXEL_FORMAT_RGBA4444 = 1,
  675. HVS_PIXEL_FORMAT_RGB555 = 2,
  676. HVS_PIXEL_FORMAT_RGBA5551 = 3,
  677. HVS_PIXEL_FORMAT_RGB565 = 4,
  678. /* 24bpp */
  679. HVS_PIXEL_FORMAT_RGB888 = 5,
  680. HVS_PIXEL_FORMAT_RGBA6666 = 6,
  681. /* 32bpp */
  682. HVS_PIXEL_FORMAT_RGBA8888 = 7,
  683. HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
  684. HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
  685. HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
  686. HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
  687. };
  688. /* Note: the LSB is the rightmost character shown. Only valid for
  689. * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
  690. */
  691. #define HVS_PIXEL_ORDER_RGBA 0
  692. #define HVS_PIXEL_ORDER_BGRA 1
  693. #define HVS_PIXEL_ORDER_ARGB 2
  694. #define HVS_PIXEL_ORDER_ABGR 3
  695. #define HVS_PIXEL_ORDER_XBRG 0
  696. #define HVS_PIXEL_ORDER_XRBG 1
  697. #define HVS_PIXEL_ORDER_XRGB 2
  698. #define HVS_PIXEL_ORDER_XBGR 3
  699. #define HVS_PIXEL_ORDER_XYCBCR 0
  700. #define HVS_PIXEL_ORDER_XYCRCB 1
  701. #define HVS_PIXEL_ORDER_YXCBCR 2
  702. #define HVS_PIXEL_ORDER_YXCRCB 3
  703. #define SCALER_CTL0_END BIT(31)
  704. #define SCALER_CTL0_VALID BIT(30)
  705. #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
  706. #define SCALER_CTL0_SIZE_SHIFT 24
  707. #define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
  708. #define SCALER_CTL0_TILING_SHIFT 20
  709. #define SCALER_CTL0_TILING_LINEAR 0
  710. #define SCALER_CTL0_TILING_64B 1
  711. #define SCALER_CTL0_TILING_128B 2
  712. #define SCALER_CTL0_TILING_256B_OR_T 3
  713. #define SCALER_CTL0_HFLIP BIT(16)
  714. #define SCALER_CTL0_VFLIP BIT(15)
  715. #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
  716. #define SCALER_CTL0_ORDER_SHIFT 13
  717. #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
  718. #define SCALER_CTL0_SCL1_SHIFT 8
  719. #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
  720. #define SCALER_CTL0_SCL0_SHIFT 5
  721. #define SCALER_CTL0_SCL_H_PPF_V_PPF 0
  722. #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
  723. #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
  724. #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
  725. #define SCALER_CTL0_SCL_H_PPF_V_NONE 4
  726. #define SCALER_CTL0_SCL_H_NONE_V_PPF 5
  727. #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
  728. #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
  729. /* Set to indicate no scaling. */
  730. #define SCALER_CTL0_UNITY BIT(4)
  731. #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
  732. #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
  733. #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
  734. #define SCALER_POS0_FIXED_ALPHA_SHIFT 24
  735. #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
  736. #define SCALER_POS0_START_Y_SHIFT 12
  737. #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
  738. #define SCALER_POS0_START_X_SHIFT 0
  739. #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
  740. #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
  741. #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
  742. #define SCALER_POS1_SCL_WIDTH_SHIFT 0
  743. #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
  744. #define SCALER_POS2_ALPHA_MODE_SHIFT 30
  745. #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
  746. #define SCALER_POS2_ALPHA_MODE_FIXED 1
  747. #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
  748. #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
  749. #define SCALER_POS2_ALPHA_PREMULT BIT(29)
  750. #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
  751. #define SCALER_POS2_HEIGHT_SHIFT 16
  752. #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
  753. #define SCALER_POS2_WIDTH_SHIFT 0
  754. /* Color Space Conversion words. Some values are S2.8 signed
  755. * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
  756. * 0x2: 2, 0x3: -1}
  757. */
  758. /* bottom 8 bits of S2.8 contribution of Cr to Blue */
  759. #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
  760. #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
  761. /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
  762. #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
  763. #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
  764. /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
  765. #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
  766. #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
  767. /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
  768. #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
  769. #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
  770. #define SCALER_CSC0_ITR_R_601_5 0x00f00000
  771. #define SCALER_CSC0_ITR_R_709_3 0x00f00000
  772. #define SCALER_CSC0_JPEG_JFIF 0x00000000
  773. /* S2.8 contribution of Cb to Green */
  774. #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
  775. #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
  776. /* S2.8 contribution of Cr to Green */
  777. #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
  778. #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
  779. /* S2.8 contribution of Y to all of RGB */
  780. #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
  781. #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
  782. /* top 2 bits of S2.8 contribution of Cr to Blue */
  783. #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
  784. #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
  785. #define SCALER_CSC1_ITR_R_601_5 0xe73304a8
  786. #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
  787. #define SCALER_CSC1_JPEG_JFIF 0xea34a400
  788. /* S2.8 contribution of Cb to Red */
  789. #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
  790. #define SCALER_CSC2_COEF_CB_RED_SHIFT 20
  791. /* S2.8 contribution of Cr to Red */
  792. #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
  793. #define SCALER_CSC2_COEF_CR_RED_SHIFT 10
  794. /* S2.8 contribution of Cb to Blue */
  795. #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
  796. #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
  797. #define SCALER_CSC2_ITR_R_601_5 0x00066204
  798. #define SCALER_CSC2_ITR_R_709_3 0x00072a1c
  799. #define SCALER_CSC2_JPEG_JFIF 0x000599c5
  800. #define SCALER_TPZ0_VERT_RECALC BIT(31)
  801. #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
  802. #define SCALER_TPZ0_SCALE_SHIFT 8
  803. #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
  804. #define SCALER_TPZ0_IPHASE_SHIFT 0
  805. #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
  806. #define SCALER_TPZ1_RECIP_SHIFT 0
  807. /* Skips interpolating coefficients to 64 phases, so just 8 are used.
  808. * Required for nearest neighbor.
  809. */
  810. #define SCALER_PPF_NOINTERP BIT(31)
  811. /* Replaes the highest valued coefficient with one that makes all 4
  812. * sum to unity.
  813. */
  814. #define SCALER_PPF_AGC BIT(30)
  815. #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
  816. #define SCALER_PPF_SCALE_SHIFT 8
  817. #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
  818. #define SCALER_PPF_IPHASE_SHIFT 0
  819. #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
  820. #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
  821. #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
  822. /* PITCH0/1/2 fields for raster. */
  823. #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
  824. #define SCALER_SRC_PITCH_SHIFT 0
  825. /* PITCH0 fields for T-tiled. */
  826. #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
  827. #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
  828. #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
  829. #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
  830. /* Y offset within a tile. */
  831. #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
  832. #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
  833. #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
  834. #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
  835. #endif /* VC4_REGS_H */