nouveau_ttm.c 9.4 KB

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  1. /*
  2. * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
  3. * All Rights Reserved.
  4. * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sub license,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. */
  26. #include "nouveau_drv.h"
  27. #include "nouveau_gem.h"
  28. #include "nouveau_mem.h"
  29. #include "nouveau_ttm.h"
  30. #include <drm/drm_legacy.h>
  31. #include <core/tegra.h>
  32. static int
  33. nouveau_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
  34. {
  35. return 0;
  36. }
  37. static int
  38. nouveau_manager_fini(struct ttm_mem_type_manager *man)
  39. {
  40. return 0;
  41. }
  42. static void
  43. nouveau_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *reg)
  44. {
  45. nouveau_mem_del(reg);
  46. }
  47. static void
  48. nouveau_manager_debug(struct ttm_mem_type_manager *man,
  49. struct drm_printer *printer)
  50. {
  51. }
  52. static int
  53. nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
  54. struct ttm_buffer_object *bo,
  55. const struct ttm_place *place,
  56. struct ttm_mem_reg *reg)
  57. {
  58. struct nouveau_bo *nvbo = nouveau_bo(bo);
  59. struct nouveau_drm *drm = nvbo->cli->drm;
  60. struct nouveau_mem *mem;
  61. int ret;
  62. if (drm->client.device.info.ram_size == 0)
  63. return -ENOMEM;
  64. ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
  65. mem = nouveau_mem(reg);
  66. if (ret)
  67. return ret;
  68. ret = nouveau_mem_vram(reg, nvbo->contig, nvbo->page);
  69. if (ret) {
  70. nouveau_mem_del(reg);
  71. if (ret == -ENOSPC) {
  72. reg->mm_node = NULL;
  73. return 0;
  74. }
  75. return ret;
  76. }
  77. return 0;
  78. }
  79. const struct ttm_mem_type_manager_func nouveau_vram_manager = {
  80. .init = nouveau_manager_init,
  81. .takedown = nouveau_manager_fini,
  82. .get_node = nouveau_vram_manager_new,
  83. .put_node = nouveau_manager_del,
  84. .debug = nouveau_manager_debug,
  85. };
  86. static int
  87. nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
  88. struct ttm_buffer_object *bo,
  89. const struct ttm_place *place,
  90. struct ttm_mem_reg *reg)
  91. {
  92. struct nouveau_bo *nvbo = nouveau_bo(bo);
  93. struct nouveau_drm *drm = nvbo->cli->drm;
  94. struct nouveau_mem *mem;
  95. int ret;
  96. ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
  97. mem = nouveau_mem(reg);
  98. if (ret)
  99. return ret;
  100. reg->start = 0;
  101. return 0;
  102. }
  103. const struct ttm_mem_type_manager_func nouveau_gart_manager = {
  104. .init = nouveau_manager_init,
  105. .takedown = nouveau_manager_fini,
  106. .get_node = nouveau_gart_manager_new,
  107. .put_node = nouveau_manager_del,
  108. .debug = nouveau_manager_debug
  109. };
  110. static int
  111. nv04_gart_manager_new(struct ttm_mem_type_manager *man,
  112. struct ttm_buffer_object *bo,
  113. const struct ttm_place *place,
  114. struct ttm_mem_reg *reg)
  115. {
  116. struct nouveau_bo *nvbo = nouveau_bo(bo);
  117. struct nouveau_drm *drm = nvbo->cli->drm;
  118. struct nouveau_mem *mem;
  119. int ret;
  120. ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
  121. mem = nouveau_mem(reg);
  122. if (ret)
  123. return ret;
  124. ret = nvif_vmm_get(&mem->cli->vmm.vmm, PTES, false, 12, 0,
  125. reg->num_pages << PAGE_SHIFT, &mem->vma[0]);
  126. if (ret) {
  127. nouveau_mem_del(reg);
  128. if (ret == -ENOSPC) {
  129. reg->mm_node = NULL;
  130. return 0;
  131. }
  132. return ret;
  133. }
  134. reg->start = mem->vma[0].addr >> PAGE_SHIFT;
  135. return 0;
  136. }
  137. const struct ttm_mem_type_manager_func nv04_gart_manager = {
  138. .init = nouveau_manager_init,
  139. .takedown = nouveau_manager_fini,
  140. .get_node = nv04_gart_manager_new,
  141. .put_node = nouveau_manager_del,
  142. .debug = nouveau_manager_debug
  143. };
  144. int
  145. nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
  146. {
  147. struct drm_file *file_priv = filp->private_data;
  148. struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
  149. if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
  150. return drm_legacy_mmap(filp, vma);
  151. return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
  152. }
  153. static int
  154. nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
  155. {
  156. return ttm_mem_global_init(ref->object);
  157. }
  158. static void
  159. nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
  160. {
  161. ttm_mem_global_release(ref->object);
  162. }
  163. int
  164. nouveau_ttm_global_init(struct nouveau_drm *drm)
  165. {
  166. struct drm_global_reference *global_ref;
  167. int ret;
  168. global_ref = &drm->ttm.mem_global_ref;
  169. global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  170. global_ref->size = sizeof(struct ttm_mem_global);
  171. global_ref->init = &nouveau_ttm_mem_global_init;
  172. global_ref->release = &nouveau_ttm_mem_global_release;
  173. ret = drm_global_item_ref(global_ref);
  174. if (unlikely(ret != 0)) {
  175. DRM_ERROR("Failed setting up TTM memory accounting\n");
  176. drm->ttm.mem_global_ref.release = NULL;
  177. return ret;
  178. }
  179. drm->ttm.bo_global_ref.mem_glob = global_ref->object;
  180. global_ref = &drm->ttm.bo_global_ref.ref;
  181. global_ref->global_type = DRM_GLOBAL_TTM_BO;
  182. global_ref->size = sizeof(struct ttm_bo_global);
  183. global_ref->init = &ttm_bo_global_init;
  184. global_ref->release = &ttm_bo_global_release;
  185. ret = drm_global_item_ref(global_ref);
  186. if (unlikely(ret != 0)) {
  187. DRM_ERROR("Failed setting up TTM BO subsystem\n");
  188. drm_global_item_unref(&drm->ttm.mem_global_ref);
  189. drm->ttm.mem_global_ref.release = NULL;
  190. return ret;
  191. }
  192. return 0;
  193. }
  194. void
  195. nouveau_ttm_global_release(struct nouveau_drm *drm)
  196. {
  197. if (drm->ttm.mem_global_ref.release == NULL)
  198. return;
  199. drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
  200. drm_global_item_unref(&drm->ttm.mem_global_ref);
  201. drm->ttm.mem_global_ref.release = NULL;
  202. }
  203. static int
  204. nouveau_ttm_init_host(struct nouveau_drm *drm, u8 kind)
  205. {
  206. struct nvif_mmu *mmu = &drm->client.mmu;
  207. int typei;
  208. typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE |
  209. kind | NVIF_MEM_COHERENT);
  210. if (typei < 0)
  211. return -ENOSYS;
  212. drm->ttm.type_host[!!kind] = typei;
  213. typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE | kind);
  214. if (typei < 0)
  215. return -ENOSYS;
  216. drm->ttm.type_ncoh[!!kind] = typei;
  217. return 0;
  218. }
  219. int
  220. nouveau_ttm_init(struct nouveau_drm *drm)
  221. {
  222. struct nvkm_device *device = nvxx_device(&drm->client.device);
  223. struct nvkm_pci *pci = device->pci;
  224. struct nvif_mmu *mmu = &drm->client.mmu;
  225. struct drm_device *dev = drm->dev;
  226. int typei, ret;
  227. ret = nouveau_ttm_init_host(drm, 0);
  228. if (ret)
  229. return ret;
  230. if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
  231. drm->client.device.info.chipset != 0x50) {
  232. ret = nouveau_ttm_init_host(drm, NVIF_MEM_KIND);
  233. if (ret)
  234. return ret;
  235. }
  236. if (drm->client.device.info.platform != NV_DEVICE_INFO_V0_SOC &&
  237. drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  238. typei = nvif_mmu_type(mmu, NVIF_MEM_VRAM | NVIF_MEM_MAPPABLE |
  239. NVIF_MEM_KIND |
  240. NVIF_MEM_COMP |
  241. NVIF_MEM_DISP);
  242. if (typei < 0)
  243. return -ENOSYS;
  244. drm->ttm.type_vram = typei;
  245. } else {
  246. drm->ttm.type_vram = -1;
  247. }
  248. if (pci && pci->agp.bridge) {
  249. drm->agp.bridge = pci->agp.bridge;
  250. drm->agp.base = pci->agp.base;
  251. drm->agp.size = pci->agp.size;
  252. drm->agp.cma = pci->agp.cma;
  253. }
  254. ret = nouveau_ttm_global_init(drm);
  255. if (ret)
  256. return ret;
  257. ret = ttm_bo_device_init(&drm->ttm.bdev,
  258. drm->ttm.bo_global_ref.ref.object,
  259. &nouveau_bo_driver,
  260. dev->anon_inode->i_mapping,
  261. DRM_FILE_PAGE_OFFSET,
  262. drm->client.mmu.dmabits <= 32 ? true : false);
  263. if (ret) {
  264. NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
  265. return ret;
  266. }
  267. /* VRAM init */
  268. drm->gem.vram_available = drm->client.device.info.ram_user;
  269. arch_io_reserve_memtype_wc(device->func->resource_addr(device, 1),
  270. device->func->resource_size(device, 1));
  271. ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
  272. drm->gem.vram_available >> PAGE_SHIFT);
  273. if (ret) {
  274. NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
  275. return ret;
  276. }
  277. drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1),
  278. device->func->resource_size(device, 1));
  279. /* GART init */
  280. if (!drm->agp.bridge) {
  281. drm->gem.gart_available = drm->client.vmm.vmm.limit;
  282. } else {
  283. drm->gem.gart_available = drm->agp.size;
  284. }
  285. ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
  286. drm->gem.gart_available >> PAGE_SHIFT);
  287. if (ret) {
  288. NV_ERROR(drm, "GART mm init failed, %d\n", ret);
  289. return ret;
  290. }
  291. NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
  292. NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
  293. return 0;
  294. }
  295. void
  296. nouveau_ttm_fini(struct nouveau_drm *drm)
  297. {
  298. struct nvkm_device *device = nvxx_device(&drm->client.device);
  299. ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
  300. ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
  301. ttm_bo_device_release(&drm->ttm.bdev);
  302. nouveau_ttm_global_release(drm);
  303. arch_phys_wc_del(drm->ttm.mtrr);
  304. drm->ttm.mtrr = 0;
  305. arch_io_free_memtype_wc(device->func->resource_addr(device, 1),
  306. device->func->resource_size(device, 1));
  307. }