nouveau_drm.c 30 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <linux/console.h>
  25. #include <linux/delay.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/vga_switcheroo.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <core/gpuobj.h>
  33. #include <core/option.h>
  34. #include <core/pci.h>
  35. #include <core/tegra.h>
  36. #include <nvif/driver.h>
  37. #include <nvif/class.h>
  38. #include <nvif/cl0002.h>
  39. #include <nvif/cla06f.h>
  40. #include <nvif/if0004.h>
  41. #include "nouveau_drv.h"
  42. #include "nouveau_dma.h"
  43. #include "nouveau_ttm.h"
  44. #include "nouveau_gem.h"
  45. #include "nouveau_vga.h"
  46. #include "nouveau_led.h"
  47. #include "nouveau_hwmon.h"
  48. #include "nouveau_acpi.h"
  49. #include "nouveau_bios.h"
  50. #include "nouveau_ioctl.h"
  51. #include "nouveau_abi16.h"
  52. #include "nouveau_fbcon.h"
  53. #include "nouveau_fence.h"
  54. #include "nouveau_debugfs.h"
  55. #include "nouveau_usif.h"
  56. #include "nouveau_connector.h"
  57. #include "nouveau_platform.h"
  58. MODULE_PARM_DESC(config, "option string to pass to driver core");
  59. static char *nouveau_config;
  60. module_param_named(config, nouveau_config, charp, 0400);
  61. MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  62. static char *nouveau_debug;
  63. module_param_named(debug, nouveau_debug, charp, 0400);
  64. MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  65. static int nouveau_noaccel = 0;
  66. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  67. MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
  68. "0 = disabled, 1 = enabled, 2 = headless)");
  69. int nouveau_modeset = -1;
  70. module_param_named(modeset, nouveau_modeset, int, 0400);
  71. MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
  72. static int nouveau_runtime_pm = -1;
  73. module_param_named(runpm, nouveau_runtime_pm, int, 0400);
  74. static struct drm_driver driver_stub;
  75. static struct drm_driver driver_pci;
  76. static struct drm_driver driver_platform;
  77. static u64
  78. nouveau_pci_name(struct pci_dev *pdev)
  79. {
  80. u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
  81. name |= pdev->bus->number << 16;
  82. name |= PCI_SLOT(pdev->devfn) << 8;
  83. return name | PCI_FUNC(pdev->devfn);
  84. }
  85. static u64
  86. nouveau_platform_name(struct platform_device *platformdev)
  87. {
  88. return platformdev->id;
  89. }
  90. static u64
  91. nouveau_name(struct drm_device *dev)
  92. {
  93. if (dev->pdev)
  94. return nouveau_pci_name(dev->pdev);
  95. else
  96. return nouveau_platform_name(to_platform_device(dev->dev));
  97. }
  98. static inline bool
  99. nouveau_cli_work_ready(struct dma_fence *fence, bool wait)
  100. {
  101. if (!dma_fence_is_signaled(fence)) {
  102. if (!wait)
  103. return false;
  104. WARN_ON(dma_fence_wait_timeout(fence, false, 2 * HZ) <= 0);
  105. }
  106. dma_fence_put(fence);
  107. return true;
  108. }
  109. static void
  110. nouveau_cli_work_flush(struct nouveau_cli *cli, bool wait)
  111. {
  112. struct nouveau_cli_work *work, *wtmp;
  113. mutex_lock(&cli->lock);
  114. list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
  115. if (!work->fence || nouveau_cli_work_ready(work->fence, wait)) {
  116. list_del(&work->head);
  117. work->func(work);
  118. }
  119. }
  120. mutex_unlock(&cli->lock);
  121. }
  122. static void
  123. nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
  124. {
  125. struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
  126. schedule_work(&work->cli->work);
  127. }
  128. void
  129. nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
  130. struct nouveau_cli_work *work)
  131. {
  132. work->fence = dma_fence_get(fence);
  133. work->cli = cli;
  134. mutex_lock(&cli->lock);
  135. list_add_tail(&work->head, &cli->worker);
  136. if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
  137. nouveau_cli_work_fence(fence, &work->cb);
  138. mutex_unlock(&cli->lock);
  139. }
  140. static void
  141. nouveau_cli_work(struct work_struct *w)
  142. {
  143. struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
  144. nouveau_cli_work_flush(cli, false);
  145. }
  146. static void
  147. nouveau_cli_fini(struct nouveau_cli *cli)
  148. {
  149. nouveau_cli_work_flush(cli, true);
  150. usif_client_fini(cli);
  151. nouveau_vmm_fini(&cli->vmm);
  152. nvif_mmu_fini(&cli->mmu);
  153. nvif_device_fini(&cli->device);
  154. mutex_lock(&cli->drm->master.lock);
  155. nvif_client_fini(&cli->base);
  156. mutex_unlock(&cli->drm->master.lock);
  157. }
  158. static int
  159. nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
  160. struct nouveau_cli *cli)
  161. {
  162. static const struct nvif_mclass
  163. mems[] = {
  164. { NVIF_CLASS_MEM_GF100, -1 },
  165. { NVIF_CLASS_MEM_NV50 , -1 },
  166. { NVIF_CLASS_MEM_NV04 , -1 },
  167. {}
  168. };
  169. static const struct nvif_mclass
  170. mmus[] = {
  171. { NVIF_CLASS_MMU_GF100, -1 },
  172. { NVIF_CLASS_MMU_NV50 , -1 },
  173. { NVIF_CLASS_MMU_NV04 , -1 },
  174. {}
  175. };
  176. static const struct nvif_mclass
  177. vmms[] = {
  178. { NVIF_CLASS_VMM_GP100, -1 },
  179. { NVIF_CLASS_VMM_GM200, -1 },
  180. { NVIF_CLASS_VMM_GF100, -1 },
  181. { NVIF_CLASS_VMM_NV50 , -1 },
  182. { NVIF_CLASS_VMM_NV04 , -1 },
  183. {}
  184. };
  185. u64 device = nouveau_name(drm->dev);
  186. int ret;
  187. snprintf(cli->name, sizeof(cli->name), "%s", sname);
  188. cli->drm = drm;
  189. mutex_init(&cli->mutex);
  190. usif_client_init(cli);
  191. INIT_WORK(&cli->work, nouveau_cli_work);
  192. INIT_LIST_HEAD(&cli->worker);
  193. mutex_init(&cli->lock);
  194. if (cli == &drm->master) {
  195. ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
  196. cli->name, device, &cli->base);
  197. } else {
  198. mutex_lock(&drm->master.lock);
  199. ret = nvif_client_init(&drm->master.base, cli->name, device,
  200. &cli->base);
  201. mutex_unlock(&drm->master.lock);
  202. }
  203. if (ret) {
  204. NV_ERROR(drm, "Client allocation failed: %d\n", ret);
  205. goto done;
  206. }
  207. ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
  208. &(struct nv_device_v0) {
  209. .device = ~0,
  210. }, sizeof(struct nv_device_v0),
  211. &cli->device);
  212. if (ret) {
  213. NV_ERROR(drm, "Device allocation failed: %d\n", ret);
  214. goto done;
  215. }
  216. ret = nvif_mclass(&cli->device.object, mmus);
  217. if (ret < 0) {
  218. NV_ERROR(drm, "No supported MMU class\n");
  219. goto done;
  220. }
  221. ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
  222. if (ret) {
  223. NV_ERROR(drm, "MMU allocation failed: %d\n", ret);
  224. goto done;
  225. }
  226. ret = nvif_mclass(&cli->mmu.object, vmms);
  227. if (ret < 0) {
  228. NV_ERROR(drm, "No supported VMM class\n");
  229. goto done;
  230. }
  231. ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
  232. if (ret) {
  233. NV_ERROR(drm, "VMM allocation failed: %d\n", ret);
  234. goto done;
  235. }
  236. ret = nvif_mclass(&cli->mmu.object, mems);
  237. if (ret < 0) {
  238. NV_ERROR(drm, "No supported MEM class\n");
  239. goto done;
  240. }
  241. cli->mem = &mems[ret];
  242. return 0;
  243. done:
  244. if (ret)
  245. nouveau_cli_fini(cli);
  246. return ret;
  247. }
  248. static void
  249. nouveau_accel_fini(struct nouveau_drm *drm)
  250. {
  251. nouveau_channel_idle(drm->channel);
  252. nvif_object_fini(&drm->ntfy);
  253. nvkm_gpuobj_del(&drm->notify);
  254. nvif_notify_fini(&drm->flip);
  255. nvif_object_fini(&drm->nvsw);
  256. nouveau_channel_del(&drm->channel);
  257. nouveau_channel_idle(drm->cechan);
  258. nvif_object_fini(&drm->ttm.copy);
  259. nouveau_channel_del(&drm->cechan);
  260. if (drm->fence)
  261. nouveau_fence(drm)->dtor(drm);
  262. }
  263. static void
  264. nouveau_accel_init(struct nouveau_drm *drm)
  265. {
  266. struct nvif_device *device = &drm->client.device;
  267. struct nvif_sclass *sclass;
  268. u32 arg0, arg1;
  269. int ret, i, n;
  270. if (nouveau_noaccel)
  271. return;
  272. /* initialise synchronisation routines */
  273. /*XXX: this is crap, but the fence/channel stuff is a little
  274. * backwards in some places. this will be fixed.
  275. */
  276. ret = n = nvif_object_sclass_get(&device->object, &sclass);
  277. if (ret < 0)
  278. return;
  279. for (ret = -ENOSYS, i = 0; i < n; i++) {
  280. switch (sclass[i].oclass) {
  281. case NV03_CHANNEL_DMA:
  282. ret = nv04_fence_create(drm);
  283. break;
  284. case NV10_CHANNEL_DMA:
  285. ret = nv10_fence_create(drm);
  286. break;
  287. case NV17_CHANNEL_DMA:
  288. case NV40_CHANNEL_DMA:
  289. ret = nv17_fence_create(drm);
  290. break;
  291. case NV50_CHANNEL_GPFIFO:
  292. ret = nv50_fence_create(drm);
  293. break;
  294. case G82_CHANNEL_GPFIFO:
  295. ret = nv84_fence_create(drm);
  296. break;
  297. case FERMI_CHANNEL_GPFIFO:
  298. case KEPLER_CHANNEL_GPFIFO_A:
  299. case KEPLER_CHANNEL_GPFIFO_B:
  300. case MAXWELL_CHANNEL_GPFIFO_A:
  301. case PASCAL_CHANNEL_GPFIFO_A:
  302. ret = nvc0_fence_create(drm);
  303. break;
  304. default:
  305. break;
  306. }
  307. }
  308. nvif_object_sclass_put(&sclass);
  309. if (ret) {
  310. NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
  311. nouveau_accel_fini(drm);
  312. return;
  313. }
  314. if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
  315. ret = nouveau_channel_new(drm, &drm->client.device,
  316. NVA06F_V0_ENGINE_CE0 |
  317. NVA06F_V0_ENGINE_CE1,
  318. 0, &drm->cechan);
  319. if (ret)
  320. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  321. arg0 = NVA06F_V0_ENGINE_GR;
  322. arg1 = 1;
  323. } else
  324. if (device->info.chipset >= 0xa3 &&
  325. device->info.chipset != 0xaa &&
  326. device->info.chipset != 0xac) {
  327. ret = nouveau_channel_new(drm, &drm->client.device,
  328. NvDmaFB, NvDmaTT, &drm->cechan);
  329. if (ret)
  330. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  331. arg0 = NvDmaFB;
  332. arg1 = NvDmaTT;
  333. } else {
  334. arg0 = NvDmaFB;
  335. arg1 = NvDmaTT;
  336. }
  337. ret = nouveau_channel_new(drm, &drm->client.device,
  338. arg0, arg1, &drm->channel);
  339. if (ret) {
  340. NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
  341. nouveau_accel_fini(drm);
  342. return;
  343. }
  344. ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
  345. nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
  346. if (ret == 0) {
  347. ret = RING_SPACE(drm->channel, 2);
  348. if (ret == 0) {
  349. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  350. BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
  351. OUT_RING (drm->channel, NVDRM_NVSW);
  352. } else
  353. if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
  354. BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
  355. OUT_RING (drm->channel, 0x001f0000);
  356. }
  357. }
  358. ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete,
  359. false, NV04_NVSW_NTFY_UEVENT,
  360. NULL, 0, 0, &drm->flip);
  361. if (ret == 0)
  362. ret = nvif_notify_get(&drm->flip);
  363. if (ret) {
  364. nouveau_accel_fini(drm);
  365. return;
  366. }
  367. }
  368. if (ret) {
  369. NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
  370. nouveau_accel_fini(drm);
  371. return;
  372. }
  373. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  374. ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0,
  375. false, NULL, &drm->notify);
  376. if (ret) {
  377. NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
  378. nouveau_accel_fini(drm);
  379. return;
  380. }
  381. ret = nvif_object_init(&drm->channel->user, NvNotify0,
  382. NV_DMA_IN_MEMORY,
  383. &(struct nv_dma_v0) {
  384. .target = NV_DMA_V0_TARGET_VRAM,
  385. .access = NV_DMA_V0_ACCESS_RDWR,
  386. .start = drm->notify->addr,
  387. .limit = drm->notify->addr + 31
  388. }, sizeof(struct nv_dma_v0),
  389. &drm->ntfy);
  390. if (ret) {
  391. nouveau_accel_fini(drm);
  392. return;
  393. }
  394. }
  395. nouveau_bo_move_init(drm);
  396. }
  397. static int nouveau_drm_probe(struct pci_dev *pdev,
  398. const struct pci_device_id *pent)
  399. {
  400. struct nvkm_device *device;
  401. struct apertures_struct *aper;
  402. bool boot = false;
  403. int ret;
  404. if (vga_switcheroo_client_probe_defer(pdev))
  405. return -EPROBE_DEFER;
  406. /* We need to check that the chipset is supported before booting
  407. * fbdev off the hardware, as there's no way to put it back.
  408. */
  409. ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device);
  410. if (ret)
  411. return ret;
  412. nvkm_device_del(&device);
  413. /* Remove conflicting drivers (vesafb, efifb etc). */
  414. aper = alloc_apertures(3);
  415. if (!aper)
  416. return -ENOMEM;
  417. aper->ranges[0].base = pci_resource_start(pdev, 1);
  418. aper->ranges[0].size = pci_resource_len(pdev, 1);
  419. aper->count = 1;
  420. if (pci_resource_len(pdev, 2)) {
  421. aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
  422. aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
  423. aper->count++;
  424. }
  425. if (pci_resource_len(pdev, 3)) {
  426. aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
  427. aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
  428. aper->count++;
  429. }
  430. #ifdef CONFIG_X86
  431. boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  432. #endif
  433. if (nouveau_modeset != 2)
  434. drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
  435. kfree(aper);
  436. ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
  437. true, true, ~0ULL, &device);
  438. if (ret)
  439. return ret;
  440. pci_set_master(pdev);
  441. ret = drm_get_pci_dev(pdev, pent, &driver_pci);
  442. if (ret) {
  443. nvkm_device_del(&device);
  444. return ret;
  445. }
  446. return 0;
  447. }
  448. static int
  449. nouveau_drm_load(struct drm_device *dev, unsigned long flags)
  450. {
  451. struct nouveau_drm *drm;
  452. int ret;
  453. if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
  454. return -ENOMEM;
  455. dev->dev_private = drm;
  456. drm->dev = dev;
  457. ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
  458. if (ret)
  459. return ret;
  460. ret = nouveau_cli_init(drm, "DRM", &drm->client);
  461. if (ret)
  462. return ret;
  463. dev->irq_enabled = true;
  464. nvxx_client(&drm->client.base)->debug =
  465. nvkm_dbgopt(nouveau_debug, "DRM");
  466. INIT_LIST_HEAD(&drm->clients);
  467. spin_lock_init(&drm->tile.lock);
  468. /* workaround an odd issue on nvc1 by disabling the device's
  469. * nosnoop capability. hopefully won't cause issues until a
  470. * better fix is found - assuming there is one...
  471. */
  472. if (drm->client.device.info.chipset == 0xc1)
  473. nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
  474. nouveau_vga_init(drm);
  475. ret = nouveau_ttm_init(drm);
  476. if (ret)
  477. goto fail_ttm;
  478. ret = nouveau_bios_init(dev);
  479. if (ret)
  480. goto fail_bios;
  481. ret = nouveau_display_create(dev);
  482. if (ret)
  483. goto fail_dispctor;
  484. if (dev->mode_config.num_crtc) {
  485. ret = nouveau_display_init(dev);
  486. if (ret)
  487. goto fail_dispinit;
  488. }
  489. nouveau_debugfs_init(drm);
  490. nouveau_hwmon_init(dev);
  491. nouveau_accel_init(drm);
  492. nouveau_fbcon_init(dev);
  493. nouveau_led_init(dev);
  494. if (nouveau_pmops_runtime()) {
  495. pm_runtime_use_autosuspend(dev->dev);
  496. pm_runtime_set_autosuspend_delay(dev->dev, 5000);
  497. pm_runtime_set_active(dev->dev);
  498. pm_runtime_allow(dev->dev);
  499. pm_runtime_mark_last_busy(dev->dev);
  500. pm_runtime_put(dev->dev);
  501. } else {
  502. /* enable polling for external displays */
  503. drm_kms_helper_poll_enable(dev);
  504. }
  505. return 0;
  506. fail_dispinit:
  507. nouveau_display_destroy(dev);
  508. fail_dispctor:
  509. nouveau_bios_takedown(dev);
  510. fail_bios:
  511. nouveau_ttm_fini(drm);
  512. fail_ttm:
  513. nouveau_vga_fini(drm);
  514. nouveau_cli_fini(&drm->client);
  515. nouveau_cli_fini(&drm->master);
  516. kfree(drm);
  517. return ret;
  518. }
  519. static void
  520. nouveau_drm_unload(struct drm_device *dev)
  521. {
  522. struct nouveau_drm *drm = nouveau_drm(dev);
  523. if (nouveau_pmops_runtime()) {
  524. pm_runtime_get_sync(dev->dev);
  525. pm_runtime_forbid(dev->dev);
  526. }
  527. nouveau_led_fini(dev);
  528. nouveau_fbcon_fini(dev);
  529. nouveau_accel_fini(drm);
  530. nouveau_hwmon_fini(dev);
  531. nouveau_debugfs_fini(drm);
  532. if (dev->mode_config.num_crtc)
  533. nouveau_display_fini(dev, false);
  534. nouveau_display_destroy(dev);
  535. nouveau_bios_takedown(dev);
  536. nouveau_ttm_fini(drm);
  537. nouveau_vga_fini(drm);
  538. nouveau_cli_fini(&drm->client);
  539. nouveau_cli_fini(&drm->master);
  540. kfree(drm);
  541. }
  542. void
  543. nouveau_drm_device_remove(struct drm_device *dev)
  544. {
  545. struct nouveau_drm *drm = nouveau_drm(dev);
  546. struct nvkm_client *client;
  547. struct nvkm_device *device;
  548. dev->irq_enabled = false;
  549. client = nvxx_client(&drm->client.base);
  550. device = nvkm_device_find(client->device);
  551. drm_put_dev(dev);
  552. nvkm_device_del(&device);
  553. }
  554. static void
  555. nouveau_drm_remove(struct pci_dev *pdev)
  556. {
  557. struct drm_device *dev = pci_get_drvdata(pdev);
  558. nouveau_drm_device_remove(dev);
  559. }
  560. static int
  561. nouveau_do_suspend(struct drm_device *dev, bool runtime)
  562. {
  563. struct nouveau_drm *drm = nouveau_drm(dev);
  564. int ret;
  565. nouveau_led_suspend(dev);
  566. if (dev->mode_config.num_crtc) {
  567. NV_DEBUG(drm, "suspending console...\n");
  568. nouveau_fbcon_set_suspend(dev, 1);
  569. NV_DEBUG(drm, "suspending display...\n");
  570. ret = nouveau_display_suspend(dev, runtime);
  571. if (ret)
  572. return ret;
  573. }
  574. NV_DEBUG(drm, "evicting buffers...\n");
  575. ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
  576. NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
  577. if (drm->cechan) {
  578. ret = nouveau_channel_idle(drm->cechan);
  579. if (ret)
  580. goto fail_display;
  581. }
  582. if (drm->channel) {
  583. ret = nouveau_channel_idle(drm->channel);
  584. if (ret)
  585. goto fail_display;
  586. }
  587. NV_DEBUG(drm, "suspending fence...\n");
  588. if (drm->fence && nouveau_fence(drm)->suspend) {
  589. if (!nouveau_fence(drm)->suspend(drm)) {
  590. ret = -ENOMEM;
  591. goto fail_display;
  592. }
  593. }
  594. NV_DEBUG(drm, "suspending object tree...\n");
  595. ret = nvif_client_suspend(&drm->master.base);
  596. if (ret)
  597. goto fail_client;
  598. return 0;
  599. fail_client:
  600. if (drm->fence && nouveau_fence(drm)->resume)
  601. nouveau_fence(drm)->resume(drm);
  602. fail_display:
  603. if (dev->mode_config.num_crtc) {
  604. NV_DEBUG(drm, "resuming display...\n");
  605. nouveau_display_resume(dev, runtime);
  606. }
  607. return ret;
  608. }
  609. static int
  610. nouveau_do_resume(struct drm_device *dev, bool runtime)
  611. {
  612. struct nouveau_drm *drm = nouveau_drm(dev);
  613. NV_DEBUG(drm, "resuming object tree...\n");
  614. nvif_client_resume(&drm->master.base);
  615. NV_DEBUG(drm, "resuming fence...\n");
  616. if (drm->fence && nouveau_fence(drm)->resume)
  617. nouveau_fence(drm)->resume(drm);
  618. nouveau_run_vbios_init(dev);
  619. if (dev->mode_config.num_crtc) {
  620. NV_DEBUG(drm, "resuming display...\n");
  621. nouveau_display_resume(dev, runtime);
  622. NV_DEBUG(drm, "resuming console...\n");
  623. nouveau_fbcon_set_suspend(dev, 0);
  624. }
  625. nouveau_led_resume(dev);
  626. return 0;
  627. }
  628. int
  629. nouveau_pmops_suspend(struct device *dev)
  630. {
  631. struct pci_dev *pdev = to_pci_dev(dev);
  632. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  633. int ret;
  634. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  635. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  636. return 0;
  637. ret = nouveau_do_suspend(drm_dev, false);
  638. if (ret)
  639. return ret;
  640. pci_save_state(pdev);
  641. pci_disable_device(pdev);
  642. pci_set_power_state(pdev, PCI_D3hot);
  643. udelay(200);
  644. return 0;
  645. }
  646. int
  647. nouveau_pmops_resume(struct device *dev)
  648. {
  649. struct pci_dev *pdev = to_pci_dev(dev);
  650. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  651. int ret;
  652. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  653. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  654. return 0;
  655. pci_set_power_state(pdev, PCI_D0);
  656. pci_restore_state(pdev);
  657. ret = pci_enable_device(pdev);
  658. if (ret)
  659. return ret;
  660. pci_set_master(pdev);
  661. ret = nouveau_do_resume(drm_dev, false);
  662. /* Monitors may have been connected / disconnected during suspend */
  663. schedule_work(&nouveau_drm(drm_dev)->hpd_work);
  664. return ret;
  665. }
  666. static int
  667. nouveau_pmops_freeze(struct device *dev)
  668. {
  669. struct pci_dev *pdev = to_pci_dev(dev);
  670. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  671. return nouveau_do_suspend(drm_dev, false);
  672. }
  673. static int
  674. nouveau_pmops_thaw(struct device *dev)
  675. {
  676. struct pci_dev *pdev = to_pci_dev(dev);
  677. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  678. return nouveau_do_resume(drm_dev, false);
  679. }
  680. bool
  681. nouveau_pmops_runtime(void)
  682. {
  683. if (nouveau_runtime_pm == -1)
  684. return nouveau_is_optimus() || nouveau_is_v1_dsm();
  685. return nouveau_runtime_pm == 1;
  686. }
  687. static int
  688. nouveau_pmops_runtime_suspend(struct device *dev)
  689. {
  690. struct pci_dev *pdev = to_pci_dev(dev);
  691. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  692. int ret;
  693. if (!nouveau_pmops_runtime()) {
  694. pm_runtime_forbid(dev);
  695. return -EBUSY;
  696. }
  697. drm_kms_helper_poll_disable(drm_dev);
  698. nouveau_switcheroo_optimus_dsm();
  699. ret = nouveau_do_suspend(drm_dev, true);
  700. pci_save_state(pdev);
  701. pci_disable_device(pdev);
  702. pci_ignore_hotplug(pdev);
  703. pci_set_power_state(pdev, PCI_D3cold);
  704. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  705. return ret;
  706. }
  707. static int
  708. nouveau_pmops_runtime_resume(struct device *dev)
  709. {
  710. struct pci_dev *pdev = to_pci_dev(dev);
  711. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  712. struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
  713. int ret;
  714. if (!nouveau_pmops_runtime()) {
  715. pm_runtime_forbid(dev);
  716. return -EBUSY;
  717. }
  718. pci_set_power_state(pdev, PCI_D0);
  719. pci_restore_state(pdev);
  720. ret = pci_enable_device(pdev);
  721. if (ret)
  722. return ret;
  723. pci_set_master(pdev);
  724. ret = nouveau_do_resume(drm_dev, true);
  725. /* do magic */
  726. nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
  727. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  728. /* Monitors may have been connected / disconnected during suspend */
  729. schedule_work(&nouveau_drm(drm_dev)->hpd_work);
  730. return ret;
  731. }
  732. static int
  733. nouveau_pmops_runtime_idle(struct device *dev)
  734. {
  735. struct pci_dev *pdev = to_pci_dev(dev);
  736. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  737. struct nouveau_drm *drm = nouveau_drm(drm_dev);
  738. struct drm_crtc *crtc;
  739. if (!nouveau_pmops_runtime()) {
  740. pm_runtime_forbid(dev);
  741. return -EBUSY;
  742. }
  743. list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
  744. if (crtc->enabled) {
  745. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  746. return -EBUSY;
  747. }
  748. }
  749. pm_runtime_mark_last_busy(dev);
  750. pm_runtime_autosuspend(dev);
  751. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  752. return 1;
  753. }
  754. static int
  755. nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
  756. {
  757. struct nouveau_drm *drm = nouveau_drm(dev);
  758. struct nouveau_cli *cli;
  759. char name[32], tmpname[TASK_COMM_LEN];
  760. int ret;
  761. /* need to bring up power immediately if opening device */
  762. ret = pm_runtime_get_sync(dev->dev);
  763. if (ret < 0 && ret != -EACCES)
  764. return ret;
  765. get_task_comm(tmpname, current);
  766. snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
  767. if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL)))
  768. return ret;
  769. ret = nouveau_cli_init(drm, name, cli);
  770. if (ret)
  771. goto done;
  772. cli->base.super = false;
  773. fpriv->driver_priv = cli;
  774. mutex_lock(&drm->client.mutex);
  775. list_add(&cli->head, &drm->clients);
  776. mutex_unlock(&drm->client.mutex);
  777. done:
  778. if (ret && cli) {
  779. nouveau_cli_fini(cli);
  780. kfree(cli);
  781. }
  782. pm_runtime_mark_last_busy(dev->dev);
  783. pm_runtime_put_autosuspend(dev->dev);
  784. return ret;
  785. }
  786. static void
  787. nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
  788. {
  789. struct nouveau_cli *cli = nouveau_cli(fpriv);
  790. struct nouveau_drm *drm = nouveau_drm(dev);
  791. pm_runtime_get_sync(dev->dev);
  792. mutex_lock(&cli->mutex);
  793. if (cli->abi16)
  794. nouveau_abi16_fini(cli->abi16);
  795. mutex_unlock(&cli->mutex);
  796. mutex_lock(&drm->client.mutex);
  797. list_del(&cli->head);
  798. mutex_unlock(&drm->client.mutex);
  799. nouveau_cli_fini(cli);
  800. kfree(cli);
  801. pm_runtime_mark_last_busy(dev->dev);
  802. pm_runtime_put_autosuspend(dev->dev);
  803. }
  804. static const struct drm_ioctl_desc
  805. nouveau_ioctls[] = {
  806. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
  807. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  808. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
  809. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
  810. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
  811. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
  812. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
  813. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
  814. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
  815. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
  816. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
  817. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
  818. };
  819. long
  820. nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  821. {
  822. struct drm_file *filp = file->private_data;
  823. struct drm_device *dev = filp->minor->dev;
  824. long ret;
  825. ret = pm_runtime_get_sync(dev->dev);
  826. if (ret < 0 && ret != -EACCES)
  827. return ret;
  828. switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
  829. case DRM_NOUVEAU_NVIF:
  830. ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
  831. break;
  832. default:
  833. ret = drm_ioctl(file, cmd, arg);
  834. break;
  835. }
  836. pm_runtime_mark_last_busy(dev->dev);
  837. pm_runtime_put_autosuspend(dev->dev);
  838. return ret;
  839. }
  840. static const struct file_operations
  841. nouveau_driver_fops = {
  842. .owner = THIS_MODULE,
  843. .open = drm_open,
  844. .release = drm_release,
  845. .unlocked_ioctl = nouveau_drm_ioctl,
  846. .mmap = nouveau_ttm_mmap,
  847. .poll = drm_poll,
  848. .read = drm_read,
  849. #if defined(CONFIG_COMPAT)
  850. .compat_ioctl = nouveau_compat_ioctl,
  851. #endif
  852. .llseek = noop_llseek,
  853. };
  854. static struct drm_driver
  855. driver_stub = {
  856. .driver_features =
  857. DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
  858. DRIVER_KMS_LEGACY_CONTEXT,
  859. .load = nouveau_drm_load,
  860. .unload = nouveau_drm_unload,
  861. .open = nouveau_drm_open,
  862. .postclose = nouveau_drm_postclose,
  863. .lastclose = nouveau_vga_lastclose,
  864. #if defined(CONFIG_DEBUG_FS)
  865. .debugfs_init = nouveau_drm_debugfs_init,
  866. #endif
  867. .enable_vblank = nouveau_display_vblank_enable,
  868. .disable_vblank = nouveau_display_vblank_disable,
  869. .get_scanout_position = nouveau_display_scanoutpos,
  870. .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
  871. .ioctls = nouveau_ioctls,
  872. .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
  873. .fops = &nouveau_driver_fops,
  874. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  875. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  876. .gem_prime_export = drm_gem_prime_export,
  877. .gem_prime_import = drm_gem_prime_import,
  878. .gem_prime_pin = nouveau_gem_prime_pin,
  879. .gem_prime_res_obj = nouveau_gem_prime_res_obj,
  880. .gem_prime_unpin = nouveau_gem_prime_unpin,
  881. .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
  882. .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
  883. .gem_prime_vmap = nouveau_gem_prime_vmap,
  884. .gem_prime_vunmap = nouveau_gem_prime_vunmap,
  885. .gem_free_object_unlocked = nouveau_gem_object_del,
  886. .gem_open_object = nouveau_gem_object_open,
  887. .gem_close_object = nouveau_gem_object_close,
  888. .dumb_create = nouveau_display_dumb_create,
  889. .dumb_map_offset = nouveau_display_dumb_map_offset,
  890. .name = DRIVER_NAME,
  891. .desc = DRIVER_DESC,
  892. #ifdef GIT_REVISION
  893. .date = GIT_REVISION,
  894. #else
  895. .date = DRIVER_DATE,
  896. #endif
  897. .major = DRIVER_MAJOR,
  898. .minor = DRIVER_MINOR,
  899. .patchlevel = DRIVER_PATCHLEVEL,
  900. };
  901. static struct pci_device_id
  902. nouveau_drm_pci_table[] = {
  903. {
  904. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  905. .class = PCI_BASE_CLASS_DISPLAY << 16,
  906. .class_mask = 0xff << 16,
  907. },
  908. {
  909. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  910. .class = PCI_BASE_CLASS_DISPLAY << 16,
  911. .class_mask = 0xff << 16,
  912. },
  913. {}
  914. };
  915. static void nouveau_display_options(void)
  916. {
  917. DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
  918. DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
  919. DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
  920. DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
  921. DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
  922. DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
  923. DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
  924. DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
  925. DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
  926. DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
  927. DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
  928. DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
  929. }
  930. static const struct dev_pm_ops nouveau_pm_ops = {
  931. .suspend = nouveau_pmops_suspend,
  932. .resume = nouveau_pmops_resume,
  933. .freeze = nouveau_pmops_freeze,
  934. .thaw = nouveau_pmops_thaw,
  935. .poweroff = nouveau_pmops_freeze,
  936. .restore = nouveau_pmops_resume,
  937. .runtime_suspend = nouveau_pmops_runtime_suspend,
  938. .runtime_resume = nouveau_pmops_runtime_resume,
  939. .runtime_idle = nouveau_pmops_runtime_idle,
  940. };
  941. static struct pci_driver
  942. nouveau_drm_pci_driver = {
  943. .name = "nouveau",
  944. .id_table = nouveau_drm_pci_table,
  945. .probe = nouveau_drm_probe,
  946. .remove = nouveau_drm_remove,
  947. .driver.pm = &nouveau_pm_ops,
  948. };
  949. struct drm_device *
  950. nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
  951. struct platform_device *pdev,
  952. struct nvkm_device **pdevice)
  953. {
  954. struct drm_device *drm;
  955. int err;
  956. err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
  957. true, true, ~0ULL, pdevice);
  958. if (err)
  959. goto err_free;
  960. drm = drm_dev_alloc(&driver_platform, &pdev->dev);
  961. if (IS_ERR(drm)) {
  962. err = PTR_ERR(drm);
  963. goto err_free;
  964. }
  965. platform_set_drvdata(pdev, drm);
  966. return drm;
  967. err_free:
  968. nvkm_device_del(pdevice);
  969. return ERR_PTR(err);
  970. }
  971. static int __init
  972. nouveau_drm_init(void)
  973. {
  974. driver_pci = driver_stub;
  975. driver_platform = driver_stub;
  976. nouveau_display_options();
  977. if (nouveau_modeset == -1) {
  978. if (vgacon_text_force())
  979. nouveau_modeset = 0;
  980. }
  981. if (!nouveau_modeset)
  982. return 0;
  983. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  984. platform_driver_register(&nouveau_platform_driver);
  985. #endif
  986. nouveau_register_dsm_handler();
  987. nouveau_backlight_ctor();
  988. #ifdef CONFIG_PCI
  989. return pci_register_driver(&nouveau_drm_pci_driver);
  990. #else
  991. return 0;
  992. #endif
  993. }
  994. static void __exit
  995. nouveau_drm_exit(void)
  996. {
  997. if (!nouveau_modeset)
  998. return;
  999. #ifdef CONFIG_PCI
  1000. pci_unregister_driver(&nouveau_drm_pci_driver);
  1001. #endif
  1002. nouveau_backlight_dtor();
  1003. nouveau_unregister_dsm_handler();
  1004. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  1005. platform_driver_unregister(&nouveau_platform_driver);
  1006. #endif
  1007. }
  1008. module_init(nouveau_drm_init);
  1009. module_exit(nouveau_drm_exit);
  1010. MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
  1011. MODULE_AUTHOR(DRIVER_AUTHOR);
  1012. MODULE_DESCRIPTION(DRIVER_DESC);
  1013. MODULE_LICENSE("GPL and additional rights");