i915_gem_timeline.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154
  1. /*
  2. * Copyright © 2016 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #include "i915_drv.h"
  25. #include "i915_syncmap.h"
  26. static void __intel_timeline_init(struct intel_timeline *tl,
  27. struct i915_gem_timeline *parent,
  28. u64 context,
  29. struct lock_class_key *lockclass,
  30. const char *lockname)
  31. {
  32. tl->fence_context = context;
  33. tl->common = parent;
  34. spin_lock_init(&tl->lock);
  35. lockdep_set_class_and_name(&tl->lock, lockclass, lockname);
  36. init_request_active(&tl->last_request, NULL);
  37. INIT_LIST_HEAD(&tl->requests);
  38. i915_syncmap_init(&tl->sync);
  39. }
  40. static void __intel_timeline_fini(struct intel_timeline *tl)
  41. {
  42. GEM_BUG_ON(!list_empty(&tl->requests));
  43. i915_syncmap_free(&tl->sync);
  44. }
  45. static int __i915_gem_timeline_init(struct drm_i915_private *i915,
  46. struct i915_gem_timeline *timeline,
  47. const char *name,
  48. struct lock_class_key *lockclass,
  49. const char *lockname)
  50. {
  51. unsigned int i;
  52. u64 fences;
  53. lockdep_assert_held(&i915->drm.struct_mutex);
  54. /*
  55. * Ideally we want a set of engines on a single leaf as we expect
  56. * to mostly be tracking synchronisation between engines. It is not
  57. * a huge issue if this is not the case, but we may want to mitigate
  58. * any page crossing penalties if they become an issue.
  59. */
  60. BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
  61. timeline->i915 = i915;
  62. timeline->name = kstrdup(name ?: "[kernel]", GFP_KERNEL);
  63. if (!timeline->name)
  64. return -ENOMEM;
  65. list_add(&timeline->link, &i915->gt.timelines);
  66. /* Called during early_init before we know how many engines there are */
  67. fences = dma_fence_context_alloc(ARRAY_SIZE(timeline->engine));
  68. for (i = 0; i < ARRAY_SIZE(timeline->engine); i++)
  69. __intel_timeline_init(&timeline->engine[i],
  70. timeline, fences++,
  71. lockclass, lockname);
  72. return 0;
  73. }
  74. int i915_gem_timeline_init(struct drm_i915_private *i915,
  75. struct i915_gem_timeline *timeline,
  76. const char *name)
  77. {
  78. static struct lock_class_key class;
  79. return __i915_gem_timeline_init(i915, timeline, name,
  80. &class, "&timeline->lock");
  81. }
  82. int i915_gem_timeline_init__global(struct drm_i915_private *i915)
  83. {
  84. static struct lock_class_key class;
  85. return __i915_gem_timeline_init(i915,
  86. &i915->gt.global_timeline,
  87. "[execution]",
  88. &class, "&global_timeline->lock");
  89. }
  90. /**
  91. * i915_gem_timelines_park - called when the driver idles
  92. * @i915: the drm_i915_private device
  93. *
  94. * When the driver is completely idle, we know that all of our sync points
  95. * have been signaled and our tracking is then entirely redundant. Any request
  96. * to wait upon an older sync point will be completed instantly as we know
  97. * the fence is signaled and therefore we will not even look them up in the
  98. * sync point map.
  99. */
  100. void i915_gem_timelines_park(struct drm_i915_private *i915)
  101. {
  102. struct i915_gem_timeline *timeline;
  103. int i;
  104. lockdep_assert_held(&i915->drm.struct_mutex);
  105. list_for_each_entry(timeline, &i915->gt.timelines, link) {
  106. for (i = 0; i < ARRAY_SIZE(timeline->engine); i++) {
  107. struct intel_timeline *tl = &timeline->engine[i];
  108. /*
  109. * All known fences are completed so we can scrap
  110. * the current sync point tracking and start afresh,
  111. * any attempt to wait upon a previous sync point
  112. * will be skipped as the fence was signaled.
  113. */
  114. i915_syncmap_free(&tl->sync);
  115. }
  116. }
  117. }
  118. void i915_gem_timeline_fini(struct i915_gem_timeline *timeline)
  119. {
  120. int i;
  121. lockdep_assert_held(&timeline->i915->drm.struct_mutex);
  122. for (i = 0; i < ARRAY_SIZE(timeline->engine); i++)
  123. __intel_timeline_fini(&timeline->engine[i]);
  124. list_del(&timeline->link);
  125. kfree(timeline->name);
  126. }
  127. #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  128. #include "selftests/mock_timeline.c"
  129. #include "selftests/i915_gem_timeline.c"
  130. #endif