gpio-pca953x.c 25 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/acpi.h>
  14. #include <linux/gpio.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/i2c.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/platform_data/pca953x.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/slab.h>
  24. #include <asm/unaligned.h>
  25. #define PCA953X_INPUT 0
  26. #define PCA953X_OUTPUT 1
  27. #define PCA953X_INVERT 2
  28. #define PCA953X_DIRECTION 3
  29. #define REG_ADDR_AI 0x80
  30. #define PCA957X_IN 0
  31. #define PCA957X_INVRT 1
  32. #define PCA957X_BKEN 2
  33. #define PCA957X_PUPD 3
  34. #define PCA957X_CFG 4
  35. #define PCA957X_OUT 5
  36. #define PCA957X_MSK 6
  37. #define PCA957X_INTS 7
  38. #define PCAL953X_IN_LATCH 34
  39. #define PCAL953X_INT_MASK 37
  40. #define PCAL953X_INT_STAT 38
  41. #define PCA_GPIO_MASK 0x00FF
  42. #define PCA_INT 0x0100
  43. #define PCA_PCAL 0x0200
  44. #define PCA953X_TYPE 0x1000
  45. #define PCA957X_TYPE 0x2000
  46. #define PCA_TYPE_MASK 0xF000
  47. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  48. static const struct i2c_device_id pca953x_id[] = {
  49. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9536", 4 | PCA953X_TYPE, },
  53. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  54. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  55. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  56. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  57. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  58. { "pca9556", 8 | PCA953X_TYPE, },
  59. { "pca9557", 8 | PCA953X_TYPE, },
  60. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  61. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  62. { "pca9698", 40 | PCA953X_TYPE, },
  63. { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  64. { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  65. { "max7310", 8 | PCA953X_TYPE, },
  66. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  67. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  68. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  69. { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
  70. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  71. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  72. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  73. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  74. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  75. { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
  76. { "xra1202", 8 | PCA953X_TYPE },
  77. { }
  78. };
  79. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  80. static const struct acpi_device_id pca953x_acpi_ids[] = {
  81. { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  82. { }
  83. };
  84. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  85. #define MAX_BANK 5
  86. #define BANK_SZ 8
  87. #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
  88. struct pca953x_reg_config {
  89. int direction;
  90. int output;
  91. int input;
  92. };
  93. static const struct pca953x_reg_config pca953x_regs = {
  94. .direction = PCA953X_DIRECTION,
  95. .output = PCA953X_OUTPUT,
  96. .input = PCA953X_INPUT,
  97. };
  98. static const struct pca953x_reg_config pca957x_regs = {
  99. .direction = PCA957X_CFG,
  100. .output = PCA957X_OUT,
  101. .input = PCA957X_IN,
  102. };
  103. struct pca953x_chip {
  104. unsigned gpio_start;
  105. u8 reg_output[MAX_BANK];
  106. u8 reg_direction[MAX_BANK];
  107. struct mutex i2c_lock;
  108. #ifdef CONFIG_GPIO_PCA953X_IRQ
  109. struct mutex irq_lock;
  110. u8 irq_mask[MAX_BANK];
  111. u8 irq_stat[MAX_BANK];
  112. u8 irq_trig_raise[MAX_BANK];
  113. u8 irq_trig_fall[MAX_BANK];
  114. #endif
  115. struct i2c_client *client;
  116. struct gpio_chip gpio_chip;
  117. const char *const *names;
  118. unsigned long driver_data;
  119. struct regulator *regulator;
  120. const struct pca953x_reg_config *regs;
  121. int (*write_regs)(struct pca953x_chip *, int, u8 *);
  122. int (*read_regs)(struct pca953x_chip *, int, u8 *);
  123. };
  124. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  125. int off)
  126. {
  127. int ret;
  128. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  129. int offset = off / BANK_SZ;
  130. ret = i2c_smbus_read_byte_data(chip->client,
  131. (reg << bank_shift) + offset);
  132. *val = ret;
  133. if (ret < 0) {
  134. dev_err(&chip->client->dev, "failed reading register\n");
  135. return ret;
  136. }
  137. return 0;
  138. }
  139. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  140. int off)
  141. {
  142. int ret;
  143. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  144. int offset = off / BANK_SZ;
  145. ret = i2c_smbus_write_byte_data(chip->client,
  146. (reg << bank_shift) + offset, val);
  147. if (ret < 0) {
  148. dev_err(&chip->client->dev, "failed writing register\n");
  149. return ret;
  150. }
  151. return 0;
  152. }
  153. static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
  154. {
  155. return i2c_smbus_write_byte_data(chip->client, reg, *val);
  156. }
  157. static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  158. {
  159. u16 word = get_unaligned((u16 *)val);
  160. return i2c_smbus_write_word_data(chip->client, reg << 1, word);
  161. }
  162. static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  163. {
  164. int ret;
  165. ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]);
  166. if (ret < 0)
  167. return ret;
  168. return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]);
  169. }
  170. static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
  171. {
  172. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  173. return i2c_smbus_write_i2c_block_data(chip->client,
  174. (reg << bank_shift) | REG_ADDR_AI,
  175. NBANK(chip), val);
  176. }
  177. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  178. {
  179. int ret = 0;
  180. ret = chip->write_regs(chip, reg, val);
  181. if (ret < 0) {
  182. dev_err(&chip->client->dev, "failed writing register\n");
  183. return ret;
  184. }
  185. return 0;
  186. }
  187. static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
  188. {
  189. int ret;
  190. ret = i2c_smbus_read_byte_data(chip->client, reg);
  191. *val = ret;
  192. return ret;
  193. }
  194. static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  195. {
  196. int ret;
  197. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  198. put_unaligned(ret, (u16 *)val);
  199. return ret;
  200. }
  201. static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
  202. {
  203. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  204. return i2c_smbus_read_i2c_block_data(chip->client,
  205. (reg << bank_shift) | REG_ADDR_AI,
  206. NBANK(chip), val);
  207. }
  208. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  209. {
  210. int ret;
  211. ret = chip->read_regs(chip, reg, val);
  212. if (ret < 0) {
  213. dev_err(&chip->client->dev, "failed reading register\n");
  214. return ret;
  215. }
  216. return 0;
  217. }
  218. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  219. {
  220. struct pca953x_chip *chip = gpiochip_get_data(gc);
  221. u8 reg_val;
  222. int ret;
  223. mutex_lock(&chip->i2c_lock);
  224. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  225. ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
  226. if (ret)
  227. goto exit;
  228. chip->reg_direction[off / BANK_SZ] = reg_val;
  229. exit:
  230. mutex_unlock(&chip->i2c_lock);
  231. return ret;
  232. }
  233. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  234. unsigned off, int val)
  235. {
  236. struct pca953x_chip *chip = gpiochip_get_data(gc);
  237. u8 reg_val;
  238. int ret;
  239. mutex_lock(&chip->i2c_lock);
  240. /* set output level */
  241. if (val)
  242. reg_val = chip->reg_output[off / BANK_SZ]
  243. | (1u << (off % BANK_SZ));
  244. else
  245. reg_val = chip->reg_output[off / BANK_SZ]
  246. & ~(1u << (off % BANK_SZ));
  247. ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
  248. if (ret)
  249. goto exit;
  250. chip->reg_output[off / BANK_SZ] = reg_val;
  251. /* then direction */
  252. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  253. ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
  254. if (ret)
  255. goto exit;
  256. chip->reg_direction[off / BANK_SZ] = reg_val;
  257. exit:
  258. mutex_unlock(&chip->i2c_lock);
  259. return ret;
  260. }
  261. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  262. {
  263. struct pca953x_chip *chip = gpiochip_get_data(gc);
  264. u32 reg_val;
  265. int ret;
  266. mutex_lock(&chip->i2c_lock);
  267. ret = pca953x_read_single(chip, chip->regs->input, &reg_val, off);
  268. mutex_unlock(&chip->i2c_lock);
  269. if (ret < 0) {
  270. /* NOTE: diagnostic already emitted; that's all we should
  271. * do unless gpio_*_value_cansleep() calls become different
  272. * from their nonsleeping siblings (and report faults).
  273. */
  274. return 0;
  275. }
  276. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  277. }
  278. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  279. {
  280. struct pca953x_chip *chip = gpiochip_get_data(gc);
  281. u8 reg_val;
  282. int ret;
  283. mutex_lock(&chip->i2c_lock);
  284. if (val)
  285. reg_val = chip->reg_output[off / BANK_SZ]
  286. | (1u << (off % BANK_SZ));
  287. else
  288. reg_val = chip->reg_output[off / BANK_SZ]
  289. & ~(1u << (off % BANK_SZ));
  290. ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
  291. if (ret)
  292. goto exit;
  293. chip->reg_output[off / BANK_SZ] = reg_val;
  294. exit:
  295. mutex_unlock(&chip->i2c_lock);
  296. }
  297. static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
  298. {
  299. struct pca953x_chip *chip = gpiochip_get_data(gc);
  300. u32 reg_val;
  301. int ret;
  302. mutex_lock(&chip->i2c_lock);
  303. ret = pca953x_read_single(chip, chip->regs->direction, &reg_val, off);
  304. mutex_unlock(&chip->i2c_lock);
  305. if (ret < 0)
  306. return ret;
  307. return !!(reg_val & (1u << (off % BANK_SZ)));
  308. }
  309. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  310. unsigned long *mask, unsigned long *bits)
  311. {
  312. struct pca953x_chip *chip = gpiochip_get_data(gc);
  313. unsigned int bank_mask, bank_val;
  314. int bank_shift, bank;
  315. u8 reg_val[MAX_BANK];
  316. int ret;
  317. bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  318. mutex_lock(&chip->i2c_lock);
  319. memcpy(reg_val, chip->reg_output, NBANK(chip));
  320. for (bank = 0; bank < NBANK(chip); bank++) {
  321. bank_mask = mask[bank / sizeof(*mask)] >>
  322. ((bank % sizeof(*mask)) * 8);
  323. if (bank_mask) {
  324. bank_val = bits[bank / sizeof(*bits)] >>
  325. ((bank % sizeof(*bits)) * 8);
  326. bank_val &= bank_mask;
  327. reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
  328. }
  329. }
  330. ret = i2c_smbus_write_i2c_block_data(chip->client,
  331. chip->regs->output << bank_shift,
  332. NBANK(chip), reg_val);
  333. if (ret)
  334. goto exit;
  335. memcpy(chip->reg_output, reg_val, NBANK(chip));
  336. exit:
  337. mutex_unlock(&chip->i2c_lock);
  338. }
  339. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  340. {
  341. struct gpio_chip *gc;
  342. gc = &chip->gpio_chip;
  343. gc->direction_input = pca953x_gpio_direction_input;
  344. gc->direction_output = pca953x_gpio_direction_output;
  345. gc->get = pca953x_gpio_get_value;
  346. gc->set = pca953x_gpio_set_value;
  347. gc->get_direction = pca953x_gpio_get_direction;
  348. gc->set_multiple = pca953x_gpio_set_multiple;
  349. gc->can_sleep = true;
  350. gc->base = chip->gpio_start;
  351. gc->ngpio = gpios;
  352. gc->label = chip->client->name;
  353. gc->parent = &chip->client->dev;
  354. gc->owner = THIS_MODULE;
  355. gc->names = chip->names;
  356. }
  357. #ifdef CONFIG_GPIO_PCA953X_IRQ
  358. static void pca953x_irq_mask(struct irq_data *d)
  359. {
  360. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  361. struct pca953x_chip *chip = gpiochip_get_data(gc);
  362. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  363. }
  364. static void pca953x_irq_unmask(struct irq_data *d)
  365. {
  366. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  367. struct pca953x_chip *chip = gpiochip_get_data(gc);
  368. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  369. }
  370. static void pca953x_irq_bus_lock(struct irq_data *d)
  371. {
  372. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  373. struct pca953x_chip *chip = gpiochip_get_data(gc);
  374. mutex_lock(&chip->irq_lock);
  375. }
  376. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  377. {
  378. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  379. struct pca953x_chip *chip = gpiochip_get_data(gc);
  380. u8 new_irqs;
  381. int level, i;
  382. u8 invert_irq_mask[MAX_BANK];
  383. if (chip->driver_data & PCA_PCAL) {
  384. /* Enable latch on interrupt-enabled inputs */
  385. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  386. for (i = 0; i < NBANK(chip); i++)
  387. invert_irq_mask[i] = ~chip->irq_mask[i];
  388. /* Unmask enabled interrupts */
  389. pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
  390. }
  391. /* Look for any newly setup interrupt */
  392. for (i = 0; i < NBANK(chip); i++) {
  393. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  394. new_irqs &= ~chip->reg_direction[i];
  395. while (new_irqs) {
  396. level = __ffs(new_irqs);
  397. pca953x_gpio_direction_input(&chip->gpio_chip,
  398. level + (BANK_SZ * i));
  399. new_irqs &= ~(1 << level);
  400. }
  401. }
  402. mutex_unlock(&chip->irq_lock);
  403. }
  404. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  405. {
  406. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  407. struct pca953x_chip *chip = gpiochip_get_data(gc);
  408. int bank_nb = d->hwirq / BANK_SZ;
  409. u8 mask = 1 << (d->hwirq % BANK_SZ);
  410. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  411. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  412. d->irq, type);
  413. return -EINVAL;
  414. }
  415. if (type & IRQ_TYPE_EDGE_FALLING)
  416. chip->irq_trig_fall[bank_nb] |= mask;
  417. else
  418. chip->irq_trig_fall[bank_nb] &= ~mask;
  419. if (type & IRQ_TYPE_EDGE_RISING)
  420. chip->irq_trig_raise[bank_nb] |= mask;
  421. else
  422. chip->irq_trig_raise[bank_nb] &= ~mask;
  423. return 0;
  424. }
  425. static struct irq_chip pca953x_irq_chip = {
  426. .name = "pca953x",
  427. .irq_mask = pca953x_irq_mask,
  428. .irq_unmask = pca953x_irq_unmask,
  429. .irq_bus_lock = pca953x_irq_bus_lock,
  430. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  431. .irq_set_type = pca953x_irq_set_type,
  432. };
  433. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  434. {
  435. u8 cur_stat[MAX_BANK];
  436. u8 old_stat[MAX_BANK];
  437. bool pending_seen = false;
  438. bool trigger_seen = false;
  439. u8 trigger[MAX_BANK];
  440. int ret, i;
  441. if (chip->driver_data & PCA_PCAL) {
  442. /* Read the current interrupt status from the device */
  443. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  444. if (ret)
  445. return false;
  446. /* Check latched inputs and clear interrupt status */
  447. ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
  448. if (ret)
  449. return false;
  450. for (i = 0; i < NBANK(chip); i++) {
  451. /* Apply filter for rising/falling edge selection */
  452. pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
  453. (cur_stat[i] & chip->irq_trig_raise[i]);
  454. pending[i] &= trigger[i];
  455. if (pending[i])
  456. pending_seen = true;
  457. }
  458. return pending_seen;
  459. }
  460. ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
  461. if (ret)
  462. return false;
  463. /* Remove output pins from the equation */
  464. for (i = 0; i < NBANK(chip); i++)
  465. cur_stat[i] &= chip->reg_direction[i];
  466. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  467. for (i = 0; i < NBANK(chip); i++) {
  468. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  469. if (trigger[i])
  470. trigger_seen = true;
  471. }
  472. if (!trigger_seen)
  473. return false;
  474. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  475. for (i = 0; i < NBANK(chip); i++) {
  476. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  477. (cur_stat[i] & chip->irq_trig_raise[i]);
  478. pending[i] &= trigger[i];
  479. if (pending[i])
  480. pending_seen = true;
  481. }
  482. return pending_seen;
  483. }
  484. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  485. {
  486. struct pca953x_chip *chip = devid;
  487. u8 pending[MAX_BANK];
  488. u8 level;
  489. unsigned nhandled = 0;
  490. int i;
  491. if (!pca953x_irq_pending(chip, pending))
  492. return IRQ_NONE;
  493. for (i = 0; i < NBANK(chip); i++) {
  494. while (pending[i]) {
  495. level = __ffs(pending[i]);
  496. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
  497. level + (BANK_SZ * i)));
  498. pending[i] &= ~(1 << level);
  499. nhandled++;
  500. }
  501. }
  502. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  503. }
  504. static int pca953x_irq_setup(struct pca953x_chip *chip,
  505. int irq_base)
  506. {
  507. struct i2c_client *client = chip->client;
  508. int ret, i;
  509. if (client->irq && irq_base != -1
  510. && (chip->driver_data & PCA_INT)) {
  511. ret = pca953x_read_regs(chip,
  512. chip->regs->input, chip->irq_stat);
  513. if (ret)
  514. return ret;
  515. /*
  516. * There is no way to know which GPIO line generated the
  517. * interrupt. We have to rely on the previous read for
  518. * this purpose.
  519. */
  520. for (i = 0; i < NBANK(chip); i++)
  521. chip->irq_stat[i] &= chip->reg_direction[i];
  522. mutex_init(&chip->irq_lock);
  523. ret = devm_request_threaded_irq(&client->dev,
  524. client->irq,
  525. NULL,
  526. pca953x_irq_handler,
  527. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  528. IRQF_SHARED,
  529. dev_name(&client->dev), chip);
  530. if (ret) {
  531. dev_err(&client->dev, "failed to request irq %d\n",
  532. client->irq);
  533. return ret;
  534. }
  535. ret = gpiochip_irqchip_add_nested(&chip->gpio_chip,
  536. &pca953x_irq_chip,
  537. irq_base,
  538. handle_simple_irq,
  539. IRQ_TYPE_NONE);
  540. if (ret) {
  541. dev_err(&client->dev,
  542. "could not connect irqchip to gpiochip\n");
  543. return ret;
  544. }
  545. gpiochip_set_nested_irqchip(&chip->gpio_chip,
  546. &pca953x_irq_chip,
  547. client->irq);
  548. }
  549. return 0;
  550. }
  551. #else /* CONFIG_GPIO_PCA953X_IRQ */
  552. static int pca953x_irq_setup(struct pca953x_chip *chip,
  553. int irq_base)
  554. {
  555. struct i2c_client *client = chip->client;
  556. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  557. dev_warn(&client->dev, "interrupt support not compiled in\n");
  558. return 0;
  559. }
  560. #endif
  561. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  562. {
  563. int ret;
  564. u8 val[MAX_BANK];
  565. chip->regs = &pca953x_regs;
  566. ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
  567. if (ret)
  568. goto out;
  569. ret = pca953x_read_regs(chip, chip->regs->direction,
  570. chip->reg_direction);
  571. if (ret)
  572. goto out;
  573. /* set platform specific polarity inversion */
  574. if (invert)
  575. memset(val, 0xFF, NBANK(chip));
  576. else
  577. memset(val, 0, NBANK(chip));
  578. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  579. out:
  580. return ret;
  581. }
  582. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  583. {
  584. int ret;
  585. u8 val[MAX_BANK];
  586. chip->regs = &pca957x_regs;
  587. ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
  588. if (ret)
  589. goto out;
  590. ret = pca953x_read_regs(chip, chip->regs->direction,
  591. chip->reg_direction);
  592. if (ret)
  593. goto out;
  594. /* set platform specific polarity inversion */
  595. if (invert)
  596. memset(val, 0xFF, NBANK(chip));
  597. else
  598. memset(val, 0, NBANK(chip));
  599. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  600. if (ret)
  601. goto out;
  602. /* To enable register 6, 7 to control pull up and pull down */
  603. memset(val, 0x02, NBANK(chip));
  604. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  605. if (ret)
  606. goto out;
  607. return 0;
  608. out:
  609. return ret;
  610. }
  611. static const struct of_device_id pca953x_dt_ids[];
  612. static int pca953x_probe(struct i2c_client *client,
  613. const struct i2c_device_id *i2c_id)
  614. {
  615. struct pca953x_platform_data *pdata;
  616. struct pca953x_chip *chip;
  617. int irq_base = 0;
  618. int ret;
  619. u32 invert = 0;
  620. struct regulator *reg;
  621. chip = devm_kzalloc(&client->dev,
  622. sizeof(struct pca953x_chip), GFP_KERNEL);
  623. if (chip == NULL)
  624. return -ENOMEM;
  625. pdata = dev_get_platdata(&client->dev);
  626. if (pdata) {
  627. irq_base = pdata->irq_base;
  628. chip->gpio_start = pdata->gpio_base;
  629. invert = pdata->invert;
  630. chip->names = pdata->names;
  631. } else {
  632. struct gpio_desc *reset_gpio;
  633. chip->gpio_start = -1;
  634. irq_base = 0;
  635. /*
  636. * See if we need to de-assert a reset pin.
  637. *
  638. * There is no known ACPI-enabled platforms that are
  639. * using "reset" GPIO. Otherwise any of those platform
  640. * must use _DSD method with corresponding property.
  641. */
  642. reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
  643. GPIOD_OUT_LOW);
  644. if (IS_ERR(reset_gpio))
  645. return PTR_ERR(reset_gpio);
  646. }
  647. chip->client = client;
  648. reg = devm_regulator_get(&client->dev, "vcc");
  649. if (IS_ERR(reg)) {
  650. ret = PTR_ERR(reg);
  651. if (ret != -EPROBE_DEFER)
  652. dev_err(&client->dev, "reg get err: %d\n", ret);
  653. return ret;
  654. }
  655. ret = regulator_enable(reg);
  656. if (ret) {
  657. dev_err(&client->dev, "reg en err: %d\n", ret);
  658. return ret;
  659. }
  660. chip->regulator = reg;
  661. if (i2c_id) {
  662. chip->driver_data = i2c_id->driver_data;
  663. } else {
  664. const struct acpi_device_id *acpi_id;
  665. const struct of_device_id *match;
  666. match = of_match_device(pca953x_dt_ids, &client->dev);
  667. if (match) {
  668. chip->driver_data = (int)(uintptr_t)match->data;
  669. } else {
  670. acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  671. if (!acpi_id) {
  672. ret = -ENODEV;
  673. goto err_exit;
  674. }
  675. chip->driver_data = acpi_id->driver_data;
  676. }
  677. }
  678. mutex_init(&chip->i2c_lock);
  679. /*
  680. * In case we have an i2c-mux controlled by a GPIO provided by an
  681. * expander using the same driver higher on the device tree, read the
  682. * i2c adapter nesting depth and use the retrieved value as lockdep
  683. * subclass for chip->i2c_lock.
  684. *
  685. * REVISIT: This solution is not complete. It protects us from lockdep
  686. * false positives when the expander controlling the i2c-mux is on
  687. * a different level on the device tree, but not when it's on the same
  688. * level on a different branch (in which case the subclass number
  689. * would be the same).
  690. *
  691. * TODO: Once a correct solution is developed, a similar fix should be
  692. * applied to all other i2c-controlled GPIO expanders (and potentially
  693. * regmap-i2c).
  694. */
  695. lockdep_set_subclass(&chip->i2c_lock,
  696. i2c_adapter_depth(client->adapter));
  697. /* initialize cached registers from their original values.
  698. * we can't share this chip with another i2c master.
  699. */
  700. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  701. if (chip->gpio_chip.ngpio <= 8) {
  702. chip->write_regs = pca953x_write_regs_8;
  703. chip->read_regs = pca953x_read_regs_8;
  704. } else if (chip->gpio_chip.ngpio >= 24) {
  705. chip->write_regs = pca953x_write_regs_24;
  706. chip->read_regs = pca953x_read_regs_24;
  707. } else {
  708. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  709. chip->write_regs = pca953x_write_regs_16;
  710. else
  711. chip->write_regs = pca957x_write_regs_16;
  712. chip->read_regs = pca953x_read_regs_16;
  713. }
  714. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  715. ret = device_pca953x_init(chip, invert);
  716. else
  717. ret = device_pca957x_init(chip, invert);
  718. if (ret)
  719. goto err_exit;
  720. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  721. if (ret)
  722. goto err_exit;
  723. ret = pca953x_irq_setup(chip, irq_base);
  724. if (ret)
  725. goto err_exit;
  726. if (pdata && pdata->setup) {
  727. ret = pdata->setup(client, chip->gpio_chip.base,
  728. chip->gpio_chip.ngpio, pdata->context);
  729. if (ret < 0)
  730. dev_warn(&client->dev, "setup failed, %d\n", ret);
  731. }
  732. i2c_set_clientdata(client, chip);
  733. return 0;
  734. err_exit:
  735. regulator_disable(chip->regulator);
  736. return ret;
  737. }
  738. static int pca953x_remove(struct i2c_client *client)
  739. {
  740. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  741. struct pca953x_chip *chip = i2c_get_clientdata(client);
  742. int ret;
  743. if (pdata && pdata->teardown) {
  744. ret = pdata->teardown(client, chip->gpio_chip.base,
  745. chip->gpio_chip.ngpio, pdata->context);
  746. if (ret < 0)
  747. dev_err(&client->dev, "%s failed, %d\n",
  748. "teardown", ret);
  749. } else {
  750. ret = 0;
  751. }
  752. regulator_disable(chip->regulator);
  753. return ret;
  754. }
  755. /* convenience to stop overlong match-table lines */
  756. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  757. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  758. static const struct of_device_id pca953x_dt_ids[] = {
  759. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  760. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  761. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  762. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  763. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  764. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  765. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  766. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  767. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  768. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  769. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  770. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  771. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  772. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  773. { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_INT), },
  774. { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_INT), },
  775. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  776. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  777. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  778. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  779. { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
  780. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  781. { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
  782. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  783. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  784. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  785. { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
  786. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  787. { }
  788. };
  789. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  790. static struct i2c_driver pca953x_driver = {
  791. .driver = {
  792. .name = "pca953x",
  793. .of_match_table = pca953x_dt_ids,
  794. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  795. },
  796. .probe = pca953x_probe,
  797. .remove = pca953x_remove,
  798. .id_table = pca953x_id,
  799. };
  800. static int __init pca953x_init(void)
  801. {
  802. return i2c_add_driver(&pca953x_driver);
  803. }
  804. /* register after i2c postcore initcall and before
  805. * subsys initcalls that may rely on these GPIOs
  806. */
  807. subsys_initcall(pca953x_init);
  808. static void __exit pca953x_exit(void)
  809. {
  810. i2c_del_driver(&pca953x_driver);
  811. }
  812. module_exit(pca953x_exit);
  813. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  814. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  815. MODULE_LICENSE("GPL");