fsi-master-hub.c 9.6 KB

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  1. /*
  2. * FSI hub master driver
  3. *
  4. * Copyright (C) IBM Corporation 2016
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/fsi.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/slab.h>
  20. #include "fsi-master.h"
  21. /* Control Registers */
  22. #define FSI_MMODE 0x0 /* R/W: mode */
  23. #define FSI_MDLYR 0x4 /* R/W: delay */
  24. #define FSI_MCRSP 0x8 /* R/W: clock rate */
  25. #define FSI_MENP0 0x10 /* R/W: enable */
  26. #define FSI_MLEVP0 0x18 /* R: plug detect */
  27. #define FSI_MSENP0 0x18 /* S: Set enable */
  28. #define FSI_MCENP0 0x20 /* C: Clear enable */
  29. #define FSI_MAEB 0x70 /* R: Error address */
  30. #define FSI_MVER 0x74 /* R: master version/type */
  31. #define FSI_MRESP0 0xd0 /* W: Port reset */
  32. #define FSI_MESRB0 0x1d0 /* R: Master error status */
  33. #define FSI_MRESB0 0x1d0 /* W: Reset bridge */
  34. #define FSI_MECTRL 0x2e0 /* W: Error control */
  35. /* MMODE: Mode control */
  36. #define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */
  37. #define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */
  38. #define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */
  39. #define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */
  40. /* MSB=1, LSB=0 is 0.8 ms */
  41. /* MSB=0, LSB=1 is 0.9 ms */
  42. #define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */
  43. #define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */
  44. #define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */
  45. #define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */
  46. /* MRESB: Reset brindge */
  47. #define FSI_MRESB_RST_GEN 0x80000000 /* General reset */
  48. #define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */
  49. /* MRESB: Reset port */
  50. #define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */
  51. #define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */
  52. #define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */
  53. #define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */
  54. #define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */
  55. /* MECTRL: Error control */
  56. #define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */
  57. /* master 0 in error */
  58. #define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */
  59. #define FSI_ENGID_HUB_MASTER 0x1c
  60. #define FSI_HUB_LINK_OFFSET 0x80000
  61. #define FSI_HUB_LINK_SIZE 0x80000
  62. #define FSI_HUB_MASTER_MAX_LINKS 8
  63. #define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */
  64. /*
  65. * FSI hub master support
  66. *
  67. * A hub master increases the number of potential target devices that the
  68. * primary FSI master can access. For each link a primary master supports,
  69. * each of those links can in turn be chained to a hub master with multiple
  70. * links of its own.
  71. *
  72. * The hub is controlled by a set of control registers exposed as a regular fsi
  73. * device (the hub->upstream device), and provides access to the downstream FSI
  74. * bus as through an address range on the slave itself (->addr and ->size).
  75. *
  76. * [This differs from "cascaded" masters, which expose the entire downstream
  77. * bus entirely through the fsi device address range, and so have a smaller
  78. * accessible address space.]
  79. */
  80. struct fsi_master_hub {
  81. struct fsi_master master;
  82. struct fsi_device *upstream;
  83. uint32_t addr, size; /* slave-relative addr of */
  84. /* master address space */
  85. };
  86. #define to_fsi_master_hub(m) container_of(m, struct fsi_master_hub, master)
  87. static int hub_master_read(struct fsi_master *master, int link,
  88. uint8_t id, uint32_t addr, void *val, size_t size)
  89. {
  90. struct fsi_master_hub *hub = to_fsi_master_hub(master);
  91. if (id != 0)
  92. return -EINVAL;
  93. addr += hub->addr + (link * FSI_HUB_LINK_SIZE);
  94. return fsi_slave_read(hub->upstream->slave, addr, val, size);
  95. }
  96. static int hub_master_write(struct fsi_master *master, int link,
  97. uint8_t id, uint32_t addr, const void *val, size_t size)
  98. {
  99. struct fsi_master_hub *hub = to_fsi_master_hub(master);
  100. if (id != 0)
  101. return -EINVAL;
  102. addr += hub->addr + (link * FSI_HUB_LINK_SIZE);
  103. return fsi_slave_write(hub->upstream->slave, addr, val, size);
  104. }
  105. static int hub_master_break(struct fsi_master *master, int link)
  106. {
  107. uint32_t addr, cmd;
  108. addr = 0x4;
  109. cmd = cpu_to_be32(0xc0de0000);
  110. return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd));
  111. }
  112. static int hub_master_link_enable(struct fsi_master *master, int link)
  113. {
  114. struct fsi_master_hub *hub = to_fsi_master_hub(master);
  115. int idx, bit;
  116. __be32 reg;
  117. int rc;
  118. idx = link / 32;
  119. bit = link % 32;
  120. reg = cpu_to_be32(0x80000000 >> bit);
  121. rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), &reg, 4);
  122. mdelay(FSI_LINK_ENABLE_SETUP_TIME);
  123. fsi_device_read(hub->upstream, FSI_MENP0 + (4 * idx), &reg, 4);
  124. return rc;
  125. }
  126. static void hub_master_release(struct device *dev)
  127. {
  128. struct fsi_master_hub *hub = to_fsi_master_hub(dev_to_fsi_master(dev));
  129. kfree(hub);
  130. }
  131. /* mmode encoders */
  132. static inline u32 fsi_mmode_crs0(u32 x)
  133. {
  134. return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
  135. }
  136. static inline u32 fsi_mmode_crs1(u32 x)
  137. {
  138. return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
  139. }
  140. static int hub_master_init(struct fsi_master_hub *hub)
  141. {
  142. struct fsi_device *dev = hub->upstream;
  143. __be32 reg;
  144. int rc;
  145. reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
  146. | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
  147. rc = fsi_device_write(dev, FSI_MRESP0, &reg, sizeof(reg));
  148. if (rc)
  149. return rc;
  150. /* Initialize the MFSI (hub master) engine */
  151. reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
  152. | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
  153. rc = fsi_device_write(dev, FSI_MRESP0, &reg, sizeof(reg));
  154. if (rc)
  155. return rc;
  156. reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);
  157. rc = fsi_device_write(dev, FSI_MECTRL, &reg, sizeof(reg));
  158. if (rc)
  159. return rc;
  160. reg = cpu_to_be32(FSI_MMODE_EIP | FSI_MMODE_ECRC | FSI_MMODE_EPC
  161. | fsi_mmode_crs0(1) | fsi_mmode_crs1(1)
  162. | FSI_MMODE_P8_TO_LSB);
  163. rc = fsi_device_write(dev, FSI_MMODE, &reg, sizeof(reg));
  164. if (rc)
  165. return rc;
  166. reg = cpu_to_be32(0xffff0000);
  167. rc = fsi_device_write(dev, FSI_MDLYR, &reg, sizeof(reg));
  168. if (rc)
  169. return rc;
  170. reg = ~0;
  171. rc = fsi_device_write(dev, FSI_MSENP0, &reg, sizeof(reg));
  172. if (rc)
  173. return rc;
  174. /* Leave enabled long enough for master logic to set up */
  175. mdelay(FSI_LINK_ENABLE_SETUP_TIME);
  176. rc = fsi_device_write(dev, FSI_MCENP0, &reg, sizeof(reg));
  177. if (rc)
  178. return rc;
  179. rc = fsi_device_read(dev, FSI_MAEB, &reg, sizeof(reg));
  180. if (rc)
  181. return rc;
  182. reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);
  183. rc = fsi_device_write(dev, FSI_MRESP0, &reg, sizeof(reg));
  184. if (rc)
  185. return rc;
  186. rc = fsi_device_read(dev, FSI_MLEVP0, &reg, sizeof(reg));
  187. if (rc)
  188. return rc;
  189. /* Reset the master bridge */
  190. reg = cpu_to_be32(FSI_MRESB_RST_GEN);
  191. rc = fsi_device_write(dev, FSI_MRESB0, &reg, sizeof(reg));
  192. if (rc)
  193. return rc;
  194. reg = cpu_to_be32(FSI_MRESB_RST_ERR);
  195. return fsi_device_write(dev, FSI_MRESB0, &reg, sizeof(reg));
  196. }
  197. static int hub_master_probe(struct device *dev)
  198. {
  199. struct fsi_device *fsi_dev = to_fsi_dev(dev);
  200. struct fsi_master_hub *hub;
  201. uint32_t reg, links;
  202. __be32 __reg;
  203. int rc;
  204. rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg));
  205. if (rc)
  206. return rc;
  207. reg = be32_to_cpu(__reg);
  208. links = (reg >> 8) & 0xff;
  209. dev_dbg(dev, "hub version %08x (%d links)\n", reg, links);
  210. rc = fsi_slave_claim_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET,
  211. FSI_HUB_LINK_SIZE * links);
  212. if (rc) {
  213. dev_err(dev, "can't claim slave address range for links");
  214. return rc;
  215. }
  216. hub = kzalloc(sizeof(*hub), GFP_KERNEL);
  217. if (!hub) {
  218. rc = -ENOMEM;
  219. goto err_release;
  220. }
  221. hub->addr = FSI_HUB_LINK_OFFSET;
  222. hub->size = FSI_HUB_LINK_SIZE * links;
  223. hub->upstream = fsi_dev;
  224. hub->master.dev.parent = dev;
  225. hub->master.dev.release = hub_master_release;
  226. hub->master.dev.of_node = of_node_get(dev_of_node(dev));
  227. hub->master.n_links = links;
  228. hub->master.read = hub_master_read;
  229. hub->master.write = hub_master_write;
  230. hub->master.send_break = hub_master_break;
  231. hub->master.link_enable = hub_master_link_enable;
  232. dev_set_drvdata(dev, hub);
  233. hub_master_init(hub);
  234. rc = fsi_master_register(&hub->master);
  235. if (rc)
  236. goto err_release;
  237. /* At this point, fsi_master_register performs the device_initialize(),
  238. * and holds the sole reference on master.dev. This means the device
  239. * will be freed (via ->release) during any subsequent call to
  240. * fsi_master_unregister. We add our own reference to it here, so we
  241. * can perform cleanup (in _remove()) without it being freed before
  242. * we're ready.
  243. */
  244. get_device(&hub->master.dev);
  245. return 0;
  246. err_release:
  247. fsi_slave_release_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET,
  248. FSI_HUB_LINK_SIZE * links);
  249. return rc;
  250. }
  251. static int hub_master_remove(struct device *dev)
  252. {
  253. struct fsi_master_hub *hub = dev_get_drvdata(dev);
  254. fsi_master_unregister(&hub->master);
  255. fsi_slave_release_range(hub->upstream->slave, hub->addr, hub->size);
  256. of_node_put(hub->master.dev.of_node);
  257. /*
  258. * master.dev will likely be ->release()ed after this, which free()s
  259. * the hub
  260. */
  261. put_device(&hub->master.dev);
  262. return 0;
  263. }
  264. static struct fsi_device_id hub_master_ids[] = {
  265. {
  266. .engine_type = FSI_ENGID_HUB_MASTER,
  267. .version = FSI_VERSION_ANY,
  268. },
  269. { 0 }
  270. };
  271. static struct fsi_driver hub_master_driver = {
  272. .id_table = hub_master_ids,
  273. .drv = {
  274. .name = "fsi-master-hub",
  275. .bus = &fsi_bus_type,
  276. .probe = hub_master_probe,
  277. .remove = hub_master_remove,
  278. }
  279. };
  280. module_fsi_driver(hub_master_driver);
  281. MODULE_LICENSE("GPL");