fsi-master-gpio.c 16 KB

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  1. /*
  2. * A FSI master controller, using a simple GPIO bit-banging interface
  3. */
  4. #include <linux/crc4.h>
  5. #include <linux/delay.h>
  6. #include <linux/device.h>
  7. #include <linux/fsi.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/spinlock.h>
  15. #include "fsi-master.h"
  16. #define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
  17. #define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
  18. #define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
  19. #define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
  20. #define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
  21. #define FSI_INIT_CLOCKS 5000 /* Clock out any old data */
  22. #define FSI_GPIO_STD_DELAY 10 /* Standard GPIO delay in nS */
  23. /* todo: adjust down as low as */
  24. /* possible or eliminate */
  25. #define FSI_GPIO_CMD_DPOLL 0x2
  26. #define FSI_GPIO_CMD_TERM 0x3f
  27. #define FSI_GPIO_CMD_ABS_AR 0x4
  28. #define FSI_GPIO_DPOLL_CLOCKS 100 /* < 21 will cause slave to hang */
  29. /* Bus errors */
  30. #define FSI_GPIO_ERR_BUSY 1 /* Slave stuck in busy state */
  31. #define FSI_GPIO_RESP_ERRA 2 /* Any (misc) Error */
  32. #define FSI_GPIO_RESP_ERRC 3 /* Slave reports master CRC error */
  33. #define FSI_GPIO_MTOE 4 /* Master time out error */
  34. #define FSI_GPIO_CRC_INVAL 5 /* Master reports slave CRC error */
  35. /* Normal slave responses */
  36. #define FSI_GPIO_RESP_BUSY 1
  37. #define FSI_GPIO_RESP_ACK 0
  38. #define FSI_GPIO_RESP_ACKD 4
  39. #define FSI_GPIO_MAX_BUSY 100
  40. #define FSI_GPIO_MTOE_COUNT 1000
  41. #define FSI_GPIO_DRAIN_BITS 20
  42. #define FSI_GPIO_CRC_SIZE 4
  43. #define FSI_GPIO_MSG_ID_SIZE 2
  44. #define FSI_GPIO_MSG_RESPID_SIZE 2
  45. #define FSI_GPIO_PRIME_SLAVE_CLOCKS 100
  46. struct fsi_master_gpio {
  47. struct fsi_master master;
  48. struct device *dev;
  49. spinlock_t cmd_lock; /* Lock for commands */
  50. struct gpio_desc *gpio_clk;
  51. struct gpio_desc *gpio_data;
  52. struct gpio_desc *gpio_trans; /* Voltage translator */
  53. struct gpio_desc *gpio_enable; /* FSI enable */
  54. struct gpio_desc *gpio_mux; /* Mux control */
  55. bool external_mode;
  56. };
  57. #define CREATE_TRACE_POINTS
  58. #include <trace/events/fsi_master_gpio.h>
  59. #define to_fsi_master_gpio(m) container_of(m, struct fsi_master_gpio, master)
  60. struct fsi_gpio_msg {
  61. uint64_t msg;
  62. uint8_t bits;
  63. };
  64. static void clock_toggle(struct fsi_master_gpio *master, int count)
  65. {
  66. int i;
  67. for (i = 0; i < count; i++) {
  68. ndelay(FSI_GPIO_STD_DLY);
  69. gpiod_set_value(master->gpio_clk, 0);
  70. ndelay(FSI_GPIO_STD_DLY);
  71. gpiod_set_value(master->gpio_clk, 1);
  72. }
  73. }
  74. static int sda_in(struct fsi_master_gpio *master)
  75. {
  76. int in;
  77. ndelay(FSI_GPIO_STD_DLY);
  78. in = gpiod_get_value(master->gpio_data);
  79. return in ? 1 : 0;
  80. }
  81. static void sda_out(struct fsi_master_gpio *master, int value)
  82. {
  83. gpiod_set_value(master->gpio_data, value);
  84. }
  85. static void set_sda_input(struct fsi_master_gpio *master)
  86. {
  87. gpiod_direction_input(master->gpio_data);
  88. gpiod_set_value(master->gpio_trans, 0);
  89. }
  90. static void set_sda_output(struct fsi_master_gpio *master, int value)
  91. {
  92. gpiod_set_value(master->gpio_trans, 1);
  93. gpiod_direction_output(master->gpio_data, value);
  94. }
  95. static void clock_zeros(struct fsi_master_gpio *master, int count)
  96. {
  97. set_sda_output(master, 1);
  98. clock_toggle(master, count);
  99. }
  100. static void serial_in(struct fsi_master_gpio *master, struct fsi_gpio_msg *msg,
  101. uint8_t num_bits)
  102. {
  103. uint8_t bit, in_bit;
  104. set_sda_input(master);
  105. for (bit = 0; bit < num_bits; bit++) {
  106. clock_toggle(master, 1);
  107. in_bit = sda_in(master);
  108. msg->msg <<= 1;
  109. msg->msg |= ~in_bit & 0x1; /* Data is active low */
  110. }
  111. msg->bits += num_bits;
  112. trace_fsi_master_gpio_in(master, num_bits, msg->msg);
  113. }
  114. static void serial_out(struct fsi_master_gpio *master,
  115. const struct fsi_gpio_msg *cmd)
  116. {
  117. uint8_t bit;
  118. uint64_t msg = ~cmd->msg; /* Data is active low */
  119. uint64_t sda_mask = 0x1ULL << (cmd->bits - 1);
  120. uint64_t last_bit = ~0;
  121. int next_bit;
  122. trace_fsi_master_gpio_out(master, cmd->bits, cmd->msg);
  123. if (!cmd->bits) {
  124. dev_warn(master->dev, "trying to output 0 bits\n");
  125. return;
  126. }
  127. set_sda_output(master, 0);
  128. /* Send the start bit */
  129. sda_out(master, 0);
  130. clock_toggle(master, 1);
  131. /* Send the message */
  132. for (bit = 0; bit < cmd->bits; bit++) {
  133. next_bit = (msg & sda_mask) >> (cmd->bits - 1);
  134. if (last_bit ^ next_bit) {
  135. sda_out(master, next_bit);
  136. last_bit = next_bit;
  137. }
  138. clock_toggle(master, 1);
  139. msg <<= 1;
  140. }
  141. }
  142. static void msg_push_bits(struct fsi_gpio_msg *msg, uint64_t data, int bits)
  143. {
  144. msg->msg <<= bits;
  145. msg->msg |= data & ((1ull << bits) - 1);
  146. msg->bits += bits;
  147. }
  148. static void msg_push_crc(struct fsi_gpio_msg *msg)
  149. {
  150. uint8_t crc;
  151. int top;
  152. top = msg->bits & 0x3;
  153. /* start bit, and any non-aligned top bits */
  154. crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
  155. /* aligned bits */
  156. crc = crc4(crc, msg->msg, msg->bits - top);
  157. msg_push_bits(msg, crc, 4);
  158. }
  159. /*
  160. * Encode an Absolute Address command
  161. */
  162. static void build_abs_ar_command(struct fsi_gpio_msg *cmd,
  163. uint8_t id, uint32_t addr, size_t size, const void *data)
  164. {
  165. bool write = !!data;
  166. uint8_t ds;
  167. int i;
  168. cmd->bits = 0;
  169. cmd->msg = 0;
  170. msg_push_bits(cmd, id, 2);
  171. msg_push_bits(cmd, FSI_GPIO_CMD_ABS_AR, 3);
  172. msg_push_bits(cmd, write ? 0 : 1, 1);
  173. /*
  174. * The read/write size is encoded in the lower bits of the address
  175. * (as it must be naturally-aligned), and the following ds bit.
  176. *
  177. * size addr:1 addr:0 ds
  178. * 1 x x 0
  179. * 2 x 0 1
  180. * 4 0 1 1
  181. *
  182. */
  183. ds = size > 1 ? 1 : 0;
  184. addr &= ~(size - 1);
  185. if (size == 4)
  186. addr |= 1;
  187. msg_push_bits(cmd, addr & ((1 << 21) - 1), 21);
  188. msg_push_bits(cmd, ds, 1);
  189. for (i = 0; write && i < size; i++)
  190. msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
  191. msg_push_crc(cmd);
  192. }
  193. static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
  194. {
  195. cmd->bits = 0;
  196. cmd->msg = 0;
  197. msg_push_bits(cmd, slave_id, 2);
  198. msg_push_bits(cmd, FSI_GPIO_CMD_DPOLL, 3);
  199. msg_push_crc(cmd);
  200. }
  201. static void echo_delay(struct fsi_master_gpio *master)
  202. {
  203. set_sda_output(master, 1);
  204. clock_toggle(master, FSI_ECHO_DELAY_CLOCKS);
  205. }
  206. static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
  207. {
  208. cmd->bits = 0;
  209. cmd->msg = 0;
  210. msg_push_bits(cmd, slave_id, 2);
  211. msg_push_bits(cmd, FSI_GPIO_CMD_TERM, 6);
  212. msg_push_crc(cmd);
  213. }
  214. /*
  215. * Store information on master errors so handler can detect and clean
  216. * up the bus
  217. */
  218. static void fsi_master_gpio_error(struct fsi_master_gpio *master, int error)
  219. {
  220. }
  221. static int read_one_response(struct fsi_master_gpio *master,
  222. uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp)
  223. {
  224. struct fsi_gpio_msg msg;
  225. uint8_t id, tag;
  226. uint32_t crc;
  227. int i;
  228. /* wait for the start bit */
  229. for (i = 0; i < FSI_GPIO_MTOE_COUNT; i++) {
  230. msg.bits = 0;
  231. msg.msg = 0;
  232. serial_in(master, &msg, 1);
  233. if (msg.msg)
  234. break;
  235. }
  236. if (i == FSI_GPIO_MTOE_COUNT) {
  237. dev_dbg(master->dev,
  238. "Master time out waiting for response\n");
  239. fsi_master_gpio_error(master, FSI_GPIO_MTOE);
  240. return -EIO;
  241. }
  242. msg.bits = 0;
  243. msg.msg = 0;
  244. /* Read slave ID & response tag */
  245. serial_in(master, &msg, 4);
  246. id = (msg.msg >> FSI_GPIO_MSG_RESPID_SIZE) & 0x3;
  247. tag = msg.msg & 0x3;
  248. /* If we have an ACK and we're expecting data, clock the data in too */
  249. if (tag == FSI_GPIO_RESP_ACK && data_size)
  250. serial_in(master, &msg, data_size * 8);
  251. /* read CRC */
  252. serial_in(master, &msg, FSI_GPIO_CRC_SIZE);
  253. /* we have a whole message now; check CRC */
  254. crc = crc4(0, 1, 1);
  255. crc = crc4(crc, msg.msg, msg.bits);
  256. if (crc) {
  257. dev_dbg(master->dev, "ERR response CRC\n");
  258. fsi_master_gpio_error(master, FSI_GPIO_CRC_INVAL);
  259. return -EIO;
  260. }
  261. if (msgp)
  262. *msgp = msg;
  263. if (tagp)
  264. *tagp = tag;
  265. return 0;
  266. }
  267. static int issue_term(struct fsi_master_gpio *master, uint8_t slave)
  268. {
  269. struct fsi_gpio_msg cmd;
  270. uint8_t tag;
  271. int rc;
  272. build_term_command(&cmd, slave);
  273. serial_out(master, &cmd);
  274. echo_delay(master);
  275. rc = read_one_response(master, 0, NULL, &tag);
  276. if (rc < 0) {
  277. dev_err(master->dev,
  278. "TERM failed; lost communication with slave\n");
  279. return -EIO;
  280. } else if (tag != FSI_GPIO_RESP_ACK) {
  281. dev_err(master->dev, "TERM failed; response %d\n", tag);
  282. return -EIO;
  283. }
  284. return 0;
  285. }
  286. static int poll_for_response(struct fsi_master_gpio *master,
  287. uint8_t slave, uint8_t size, void *data)
  288. {
  289. struct fsi_gpio_msg response, cmd;
  290. int busy_count = 0, rc, i;
  291. uint8_t tag;
  292. uint8_t *data_byte = data;
  293. retry:
  294. rc = read_one_response(master, size, &response, &tag);
  295. if (rc)
  296. return rc;
  297. switch (tag) {
  298. case FSI_GPIO_RESP_ACK:
  299. if (size && data) {
  300. uint64_t val = response.msg;
  301. /* clear crc & mask */
  302. val >>= 4;
  303. val &= (1ull << (size * 8)) - 1;
  304. for (i = 0; i < size; i++) {
  305. data_byte[size-i-1] = val;
  306. val >>= 8;
  307. }
  308. }
  309. break;
  310. case FSI_GPIO_RESP_BUSY:
  311. /*
  312. * Its necessary to clock slave before issuing
  313. * d-poll, not indicated in the hardware protocol
  314. * spec. < 20 clocks causes slave to hang, 21 ok.
  315. */
  316. clock_zeros(master, FSI_GPIO_DPOLL_CLOCKS);
  317. if (busy_count++ < FSI_GPIO_MAX_BUSY) {
  318. build_dpoll_command(&cmd, slave);
  319. serial_out(master, &cmd);
  320. echo_delay(master);
  321. goto retry;
  322. }
  323. dev_warn(master->dev,
  324. "ERR slave is stuck in busy state, issuing TERM\n");
  325. issue_term(master, slave);
  326. rc = -EIO;
  327. break;
  328. case FSI_GPIO_RESP_ERRA:
  329. case FSI_GPIO_RESP_ERRC:
  330. dev_dbg(master->dev, "ERR%c received: 0x%x\n",
  331. tag == FSI_GPIO_RESP_ERRA ? 'A' : 'C',
  332. (int)response.msg);
  333. fsi_master_gpio_error(master, response.msg);
  334. rc = -EIO;
  335. break;
  336. }
  337. /* Clock the slave enough to be ready for next operation */
  338. clock_zeros(master, FSI_GPIO_PRIME_SLAVE_CLOCKS);
  339. return rc;
  340. }
  341. static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave,
  342. struct fsi_gpio_msg *cmd, size_t resp_len, void *resp)
  343. {
  344. unsigned long flags;
  345. int rc;
  346. spin_lock_irqsave(&master->cmd_lock, flags);
  347. if (master->external_mode) {
  348. spin_unlock_irqrestore(&master->cmd_lock, flags);
  349. return -EBUSY;
  350. }
  351. serial_out(master, cmd);
  352. echo_delay(master);
  353. rc = poll_for_response(master, slave, resp_len, resp);
  354. spin_unlock_irqrestore(&master->cmd_lock, flags);
  355. return rc;
  356. }
  357. static int fsi_master_gpio_read(struct fsi_master *_master, int link,
  358. uint8_t id, uint32_t addr, void *val, size_t size)
  359. {
  360. struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
  361. struct fsi_gpio_msg cmd;
  362. if (link != 0)
  363. return -ENODEV;
  364. build_abs_ar_command(&cmd, id, addr, size, NULL);
  365. return fsi_master_gpio_xfer(master, id, &cmd, size, val);
  366. }
  367. static int fsi_master_gpio_write(struct fsi_master *_master, int link,
  368. uint8_t id, uint32_t addr, const void *val, size_t size)
  369. {
  370. struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
  371. struct fsi_gpio_msg cmd;
  372. if (link != 0)
  373. return -ENODEV;
  374. build_abs_ar_command(&cmd, id, addr, size, val);
  375. return fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
  376. }
  377. static int fsi_master_gpio_term(struct fsi_master *_master,
  378. int link, uint8_t id)
  379. {
  380. struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
  381. struct fsi_gpio_msg cmd;
  382. if (link != 0)
  383. return -ENODEV;
  384. build_term_command(&cmd, id);
  385. return fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
  386. }
  387. static int fsi_master_gpio_break(struct fsi_master *_master, int link)
  388. {
  389. struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
  390. unsigned long flags;
  391. if (link != 0)
  392. return -ENODEV;
  393. trace_fsi_master_gpio_break(master);
  394. spin_lock_irqsave(&master->cmd_lock, flags);
  395. if (master->external_mode) {
  396. spin_unlock_irqrestore(&master->cmd_lock, flags);
  397. return -EBUSY;
  398. }
  399. set_sda_output(master, 1);
  400. sda_out(master, 1);
  401. clock_toggle(master, FSI_PRE_BREAK_CLOCKS);
  402. sda_out(master, 0);
  403. clock_toggle(master, FSI_BREAK_CLOCKS);
  404. echo_delay(master);
  405. sda_out(master, 1);
  406. clock_toggle(master, FSI_POST_BREAK_CLOCKS);
  407. spin_unlock_irqrestore(&master->cmd_lock, flags);
  408. /* Wait for logic reset to take effect */
  409. udelay(200);
  410. return 0;
  411. }
  412. static void fsi_master_gpio_init(struct fsi_master_gpio *master)
  413. {
  414. gpiod_direction_output(master->gpio_mux, 1);
  415. gpiod_direction_output(master->gpio_trans, 1);
  416. gpiod_direction_output(master->gpio_enable, 1);
  417. gpiod_direction_output(master->gpio_clk, 1);
  418. gpiod_direction_output(master->gpio_data, 1);
  419. /* todo: evaluate if clocks can be reduced */
  420. clock_zeros(master, FSI_INIT_CLOCKS);
  421. }
  422. static void fsi_master_gpio_init_external(struct fsi_master_gpio *master)
  423. {
  424. gpiod_direction_output(master->gpio_mux, 0);
  425. gpiod_direction_output(master->gpio_trans, 0);
  426. gpiod_direction_output(master->gpio_enable, 1);
  427. gpiod_direction_input(master->gpio_clk);
  428. gpiod_direction_input(master->gpio_data);
  429. }
  430. static int fsi_master_gpio_link_enable(struct fsi_master *_master, int link)
  431. {
  432. struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
  433. unsigned long flags;
  434. int rc = -EBUSY;
  435. if (link != 0)
  436. return -ENODEV;
  437. spin_lock_irqsave(&master->cmd_lock, flags);
  438. if (!master->external_mode) {
  439. gpiod_set_value(master->gpio_enable, 1);
  440. rc = 0;
  441. }
  442. spin_unlock_irqrestore(&master->cmd_lock, flags);
  443. return rc;
  444. }
  445. static ssize_t external_mode_show(struct device *dev,
  446. struct device_attribute *attr, char *buf)
  447. {
  448. struct fsi_master_gpio *master = dev_get_drvdata(dev);
  449. return snprintf(buf, PAGE_SIZE - 1, "%u\n",
  450. master->external_mode ? 1 : 0);
  451. }
  452. static ssize_t external_mode_store(struct device *dev,
  453. struct device_attribute *attr, const char *buf, size_t count)
  454. {
  455. struct fsi_master_gpio *master = dev_get_drvdata(dev);
  456. unsigned long flags, val;
  457. bool external_mode;
  458. int err;
  459. err = kstrtoul(buf, 0, &val);
  460. if (err)
  461. return err;
  462. external_mode = !!val;
  463. spin_lock_irqsave(&master->cmd_lock, flags);
  464. if (external_mode == master->external_mode) {
  465. spin_unlock_irqrestore(&master->cmd_lock, flags);
  466. return count;
  467. }
  468. master->external_mode = external_mode;
  469. if (master->external_mode)
  470. fsi_master_gpio_init_external(master);
  471. else
  472. fsi_master_gpio_init(master);
  473. spin_unlock_irqrestore(&master->cmd_lock, flags);
  474. fsi_master_rescan(&master->master);
  475. return count;
  476. }
  477. static DEVICE_ATTR(external_mode, 0664,
  478. external_mode_show, external_mode_store);
  479. static int fsi_master_gpio_probe(struct platform_device *pdev)
  480. {
  481. struct fsi_master_gpio *master;
  482. struct gpio_desc *gpio;
  483. int rc;
  484. master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
  485. if (!master)
  486. return -ENOMEM;
  487. master->dev = &pdev->dev;
  488. master->master.dev.parent = master->dev;
  489. master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
  490. gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
  491. if (IS_ERR(gpio)) {
  492. dev_err(&pdev->dev, "failed to get clock gpio\n");
  493. return PTR_ERR(gpio);
  494. }
  495. master->gpio_clk = gpio;
  496. gpio = devm_gpiod_get(&pdev->dev, "data", 0);
  497. if (IS_ERR(gpio)) {
  498. dev_err(&pdev->dev, "failed to get data gpio\n");
  499. return PTR_ERR(gpio);
  500. }
  501. master->gpio_data = gpio;
  502. /* Optional GPIOs */
  503. gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
  504. if (IS_ERR(gpio)) {
  505. dev_err(&pdev->dev, "failed to get trans gpio\n");
  506. return PTR_ERR(gpio);
  507. }
  508. master->gpio_trans = gpio;
  509. gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
  510. if (IS_ERR(gpio)) {
  511. dev_err(&pdev->dev, "failed to get enable gpio\n");
  512. return PTR_ERR(gpio);
  513. }
  514. master->gpio_enable = gpio;
  515. gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
  516. if (IS_ERR(gpio)) {
  517. dev_err(&pdev->dev, "failed to get mux gpio\n");
  518. return PTR_ERR(gpio);
  519. }
  520. master->gpio_mux = gpio;
  521. master->master.n_links = 1;
  522. master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
  523. master->master.read = fsi_master_gpio_read;
  524. master->master.write = fsi_master_gpio_write;
  525. master->master.term = fsi_master_gpio_term;
  526. master->master.send_break = fsi_master_gpio_break;
  527. master->master.link_enable = fsi_master_gpio_link_enable;
  528. platform_set_drvdata(pdev, master);
  529. spin_lock_init(&master->cmd_lock);
  530. fsi_master_gpio_init(master);
  531. rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
  532. if (rc)
  533. return rc;
  534. return fsi_master_register(&master->master);
  535. }
  536. static int fsi_master_gpio_remove(struct platform_device *pdev)
  537. {
  538. struct fsi_master_gpio *master = platform_get_drvdata(pdev);
  539. devm_gpiod_put(&pdev->dev, master->gpio_clk);
  540. devm_gpiod_put(&pdev->dev, master->gpio_data);
  541. if (master->gpio_trans)
  542. devm_gpiod_put(&pdev->dev, master->gpio_trans);
  543. if (master->gpio_enable)
  544. devm_gpiod_put(&pdev->dev, master->gpio_enable);
  545. if (master->gpio_mux)
  546. devm_gpiod_put(&pdev->dev, master->gpio_mux);
  547. fsi_master_unregister(&master->master);
  548. of_node_put(master->master.dev.of_node);
  549. return 0;
  550. }
  551. static const struct of_device_id fsi_master_gpio_match[] = {
  552. { .compatible = "fsi-master-gpio" },
  553. { },
  554. };
  555. static struct platform_driver fsi_master_gpio_driver = {
  556. .driver = {
  557. .name = "fsi-master-gpio",
  558. .of_match_table = fsi_master_gpio_match,
  559. },
  560. .probe = fsi_master_gpio_probe,
  561. .remove = fsi_master_gpio_remove,
  562. };
  563. module_platform_driver(fsi_master_gpio_driver);
  564. MODULE_LICENSE("GPL");