pl330.c 68 KB

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  1. /*
  2. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  6. * Jaswinder Singh <jassi.brar@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/io.h>
  15. #include <linux/init.h>
  16. #include <linux/slab.h>
  17. #include <linux/module.h>
  18. #include <linux/string.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/dmaengine.h>
  23. #include <linux/amba/bus.h>
  24. #include <linux/scatterlist.h>
  25. #include <linux/of.h>
  26. #include <linux/of_dma.h>
  27. #include <linux/err.h>
  28. #include <linux/pm_runtime.h>
  29. #include "dmaengine.h"
  30. #define PL330_MAX_CHAN 8
  31. #define PL330_MAX_IRQS 32
  32. #define PL330_MAX_PERI 32
  33. #define PL330_MAX_BURST 16
  34. #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
  35. enum pl330_cachectrl {
  36. CCTRL0, /* Noncacheable and nonbufferable */
  37. CCTRL1, /* Bufferable only */
  38. CCTRL2, /* Cacheable, but do not allocate */
  39. CCTRL3, /* Cacheable and bufferable, but do not allocate */
  40. INVALID1, /* AWCACHE = 0x1000 */
  41. INVALID2,
  42. CCTRL6, /* Cacheable write-through, allocate on writes only */
  43. CCTRL7, /* Cacheable write-back, allocate on writes only */
  44. };
  45. enum pl330_byteswap {
  46. SWAP_NO,
  47. SWAP_2,
  48. SWAP_4,
  49. SWAP_8,
  50. SWAP_16,
  51. };
  52. /* Register and Bit field Definitions */
  53. #define DS 0x0
  54. #define DS_ST_STOP 0x0
  55. #define DS_ST_EXEC 0x1
  56. #define DS_ST_CMISS 0x2
  57. #define DS_ST_UPDTPC 0x3
  58. #define DS_ST_WFE 0x4
  59. #define DS_ST_ATBRR 0x5
  60. #define DS_ST_QBUSY 0x6
  61. #define DS_ST_WFP 0x7
  62. #define DS_ST_KILL 0x8
  63. #define DS_ST_CMPLT 0x9
  64. #define DS_ST_FLTCMP 0xe
  65. #define DS_ST_FAULT 0xf
  66. #define DPC 0x4
  67. #define INTEN 0x20
  68. #define ES 0x24
  69. #define INTSTATUS 0x28
  70. #define INTCLR 0x2c
  71. #define FSM 0x30
  72. #define FSC 0x34
  73. #define FTM 0x38
  74. #define _FTC 0x40
  75. #define FTC(n) (_FTC + (n)*0x4)
  76. #define _CS 0x100
  77. #define CS(n) (_CS + (n)*0x8)
  78. #define CS_CNS (1 << 21)
  79. #define _CPC 0x104
  80. #define CPC(n) (_CPC + (n)*0x8)
  81. #define _SA 0x400
  82. #define SA(n) (_SA + (n)*0x20)
  83. #define _DA 0x404
  84. #define DA(n) (_DA + (n)*0x20)
  85. #define _CC 0x408
  86. #define CC(n) (_CC + (n)*0x20)
  87. #define CC_SRCINC (1 << 0)
  88. #define CC_DSTINC (1 << 14)
  89. #define CC_SRCPRI (1 << 8)
  90. #define CC_DSTPRI (1 << 22)
  91. #define CC_SRCNS (1 << 9)
  92. #define CC_DSTNS (1 << 23)
  93. #define CC_SRCIA (1 << 10)
  94. #define CC_DSTIA (1 << 24)
  95. #define CC_SRCBRSTLEN_SHFT 4
  96. #define CC_DSTBRSTLEN_SHFT 18
  97. #define CC_SRCBRSTSIZE_SHFT 1
  98. #define CC_DSTBRSTSIZE_SHFT 15
  99. #define CC_SRCCCTRL_SHFT 11
  100. #define CC_SRCCCTRL_MASK 0x7
  101. #define CC_DSTCCTRL_SHFT 25
  102. #define CC_DRCCCTRL_MASK 0x7
  103. #define CC_SWAP_SHFT 28
  104. #define _LC0 0x40c
  105. #define LC0(n) (_LC0 + (n)*0x20)
  106. #define _LC1 0x410
  107. #define LC1(n) (_LC1 + (n)*0x20)
  108. #define DBGSTATUS 0xd00
  109. #define DBG_BUSY (1 << 0)
  110. #define DBGCMD 0xd04
  111. #define DBGINST0 0xd08
  112. #define DBGINST1 0xd0c
  113. #define CR0 0xe00
  114. #define CR1 0xe04
  115. #define CR2 0xe08
  116. #define CR3 0xe0c
  117. #define CR4 0xe10
  118. #define CRD 0xe14
  119. #define PERIPH_ID 0xfe0
  120. #define PERIPH_REV_SHIFT 20
  121. #define PERIPH_REV_MASK 0xf
  122. #define PERIPH_REV_R0P0 0
  123. #define PERIPH_REV_R1P0 1
  124. #define PERIPH_REV_R1P1 2
  125. #define CR0_PERIPH_REQ_SET (1 << 0)
  126. #define CR0_BOOT_EN_SET (1 << 1)
  127. #define CR0_BOOT_MAN_NS (1 << 2)
  128. #define CR0_NUM_CHANS_SHIFT 4
  129. #define CR0_NUM_CHANS_MASK 0x7
  130. #define CR0_NUM_PERIPH_SHIFT 12
  131. #define CR0_NUM_PERIPH_MASK 0x1f
  132. #define CR0_NUM_EVENTS_SHIFT 17
  133. #define CR0_NUM_EVENTS_MASK 0x1f
  134. #define CR1_ICACHE_LEN_SHIFT 0
  135. #define CR1_ICACHE_LEN_MASK 0x7
  136. #define CR1_NUM_ICACHELINES_SHIFT 4
  137. #define CR1_NUM_ICACHELINES_MASK 0xf
  138. #define CRD_DATA_WIDTH_SHIFT 0
  139. #define CRD_DATA_WIDTH_MASK 0x7
  140. #define CRD_WR_CAP_SHIFT 4
  141. #define CRD_WR_CAP_MASK 0x7
  142. #define CRD_WR_Q_DEP_SHIFT 8
  143. #define CRD_WR_Q_DEP_MASK 0xf
  144. #define CRD_RD_CAP_SHIFT 12
  145. #define CRD_RD_CAP_MASK 0x7
  146. #define CRD_RD_Q_DEP_SHIFT 16
  147. #define CRD_RD_Q_DEP_MASK 0xf
  148. #define CRD_DATA_BUFF_SHIFT 20
  149. #define CRD_DATA_BUFF_MASK 0x3ff
  150. #define PART 0x330
  151. #define DESIGNER 0x41
  152. #define REVISION 0x0
  153. #define INTEG_CFG 0x0
  154. #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
  155. #define PL330_STATE_STOPPED (1 << 0)
  156. #define PL330_STATE_EXECUTING (1 << 1)
  157. #define PL330_STATE_WFE (1 << 2)
  158. #define PL330_STATE_FAULTING (1 << 3)
  159. #define PL330_STATE_COMPLETING (1 << 4)
  160. #define PL330_STATE_WFP (1 << 5)
  161. #define PL330_STATE_KILLING (1 << 6)
  162. #define PL330_STATE_FAULT_COMPLETING (1 << 7)
  163. #define PL330_STATE_CACHEMISS (1 << 8)
  164. #define PL330_STATE_UPDTPC (1 << 9)
  165. #define PL330_STATE_ATBARRIER (1 << 10)
  166. #define PL330_STATE_QUEUEBUSY (1 << 11)
  167. #define PL330_STATE_INVALID (1 << 15)
  168. #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
  169. | PL330_STATE_WFE | PL330_STATE_FAULTING)
  170. #define CMD_DMAADDH 0x54
  171. #define CMD_DMAEND 0x00
  172. #define CMD_DMAFLUSHP 0x35
  173. #define CMD_DMAGO 0xa0
  174. #define CMD_DMALD 0x04
  175. #define CMD_DMALDP 0x25
  176. #define CMD_DMALP 0x20
  177. #define CMD_DMALPEND 0x28
  178. #define CMD_DMAKILL 0x01
  179. #define CMD_DMAMOV 0xbc
  180. #define CMD_DMANOP 0x18
  181. #define CMD_DMARMB 0x12
  182. #define CMD_DMASEV 0x34
  183. #define CMD_DMAST 0x08
  184. #define CMD_DMASTP 0x29
  185. #define CMD_DMASTZ 0x0c
  186. #define CMD_DMAWFE 0x36
  187. #define CMD_DMAWFP 0x30
  188. #define CMD_DMAWMB 0x13
  189. #define SZ_DMAADDH 3
  190. #define SZ_DMAEND 1
  191. #define SZ_DMAFLUSHP 2
  192. #define SZ_DMALD 1
  193. #define SZ_DMALDP 2
  194. #define SZ_DMALP 2
  195. #define SZ_DMALPEND 2
  196. #define SZ_DMAKILL 1
  197. #define SZ_DMAMOV 6
  198. #define SZ_DMANOP 1
  199. #define SZ_DMARMB 1
  200. #define SZ_DMASEV 2
  201. #define SZ_DMAST 1
  202. #define SZ_DMASTP 2
  203. #define SZ_DMASTZ 1
  204. #define SZ_DMAWFE 2
  205. #define SZ_DMAWFP 2
  206. #define SZ_DMAWMB 1
  207. #define SZ_DMAGO 6
  208. #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
  209. #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
  210. #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
  211. #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
  212. /*
  213. * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
  214. * at 1byte/burst for P<->M and M<->M respectively.
  215. * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
  216. * should be enough for P<->M and M<->M respectively.
  217. */
  218. #define MCODE_BUFF_PER_REQ 256
  219. /* Use this _only_ to wait on transient states */
  220. #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
  221. #ifdef PL330_DEBUG_MCGEN
  222. static unsigned cmd_line;
  223. #define PL330_DBGCMD_DUMP(off, x...) do { \
  224. printk("%x:", cmd_line); \
  225. printk(x); \
  226. cmd_line += off; \
  227. } while (0)
  228. #define PL330_DBGMC_START(addr) (cmd_line = addr)
  229. #else
  230. #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
  231. #define PL330_DBGMC_START(addr) do {} while (0)
  232. #endif
  233. /* The number of default descriptors */
  234. #define NR_DEFAULT_DESC 16
  235. /* Delay for runtime PM autosuspend, ms */
  236. #define PL330_AUTOSUSPEND_DELAY 20
  237. /* Populated by the PL330 core driver for DMA API driver's info */
  238. struct pl330_config {
  239. u32 periph_id;
  240. #define DMAC_MODE_NS (1 << 0)
  241. unsigned int mode;
  242. unsigned int data_bus_width:10; /* In number of bits */
  243. unsigned int data_buf_dep:11;
  244. unsigned int num_chan:4;
  245. unsigned int num_peri:6;
  246. u32 peri_ns;
  247. unsigned int num_events:6;
  248. u32 irq_ns;
  249. };
  250. /**
  251. * Request Configuration.
  252. * The PL330 core does not modify this and uses the last
  253. * working configuration if the request doesn't provide any.
  254. *
  255. * The Client may want to provide this info only for the
  256. * first request and a request with new settings.
  257. */
  258. struct pl330_reqcfg {
  259. /* Address Incrementing */
  260. unsigned dst_inc:1;
  261. unsigned src_inc:1;
  262. /*
  263. * For now, the SRC & DST protection levels
  264. * and burst size/length are assumed same.
  265. */
  266. bool nonsecure;
  267. bool privileged;
  268. bool insnaccess;
  269. unsigned brst_len:5;
  270. unsigned brst_size:3; /* in power of 2 */
  271. enum pl330_cachectrl dcctl;
  272. enum pl330_cachectrl scctl;
  273. enum pl330_byteswap swap;
  274. struct pl330_config *pcfg;
  275. };
  276. /*
  277. * One cycle of DMAC operation.
  278. * There may be more than one xfer in a request.
  279. */
  280. struct pl330_xfer {
  281. u32 src_addr;
  282. u32 dst_addr;
  283. /* Size to xfer */
  284. u32 bytes;
  285. };
  286. /* The xfer callbacks are made with one of these arguments. */
  287. enum pl330_op_err {
  288. /* The all xfers in the request were success. */
  289. PL330_ERR_NONE,
  290. /* If req aborted due to global error. */
  291. PL330_ERR_ABORT,
  292. /* If req failed due to problem with Channel. */
  293. PL330_ERR_FAIL,
  294. };
  295. enum dmamov_dst {
  296. SAR = 0,
  297. CCR,
  298. DAR,
  299. };
  300. enum pl330_dst {
  301. SRC = 0,
  302. DST,
  303. };
  304. enum pl330_cond {
  305. SINGLE,
  306. BURST,
  307. ALWAYS,
  308. };
  309. struct dma_pl330_desc;
  310. struct _pl330_req {
  311. u32 mc_bus;
  312. void *mc_cpu;
  313. struct dma_pl330_desc *desc;
  314. };
  315. /* ToBeDone for tasklet */
  316. struct _pl330_tbd {
  317. bool reset_dmac;
  318. bool reset_mngr;
  319. u8 reset_chan;
  320. };
  321. /* A DMAC Thread */
  322. struct pl330_thread {
  323. u8 id;
  324. int ev;
  325. /* If the channel is not yet acquired by any client */
  326. bool free;
  327. /* Parent DMAC */
  328. struct pl330_dmac *dmac;
  329. /* Only two at a time */
  330. struct _pl330_req req[2];
  331. /* Index of the last enqueued request */
  332. unsigned lstenq;
  333. /* Index of the last submitted request or -1 if the DMA is stopped */
  334. int req_running;
  335. };
  336. enum pl330_dmac_state {
  337. UNINIT,
  338. INIT,
  339. DYING,
  340. };
  341. enum desc_status {
  342. /* In the DMAC pool */
  343. FREE,
  344. /*
  345. * Allocated to some channel during prep_xxx
  346. * Also may be sitting on the work_list.
  347. */
  348. PREP,
  349. /*
  350. * Sitting on the work_list and already submitted
  351. * to the PL330 core. Not more than two descriptors
  352. * of a channel can be BUSY at any time.
  353. */
  354. BUSY,
  355. /*
  356. * Sitting on the channel work_list but xfer done
  357. * by PL330 core
  358. */
  359. DONE,
  360. };
  361. struct dma_pl330_chan {
  362. /* Schedule desc completion */
  363. struct tasklet_struct task;
  364. /* DMA-Engine Channel */
  365. struct dma_chan chan;
  366. /* List of submitted descriptors */
  367. struct list_head submitted_list;
  368. /* List of issued descriptors */
  369. struct list_head work_list;
  370. /* List of completed descriptors */
  371. struct list_head completed_list;
  372. /* Pointer to the DMAC that manages this channel,
  373. * NULL if the channel is available to be acquired.
  374. * As the parent, this DMAC also provides descriptors
  375. * to the channel.
  376. */
  377. struct pl330_dmac *dmac;
  378. /* To protect channel manipulation */
  379. spinlock_t lock;
  380. /*
  381. * Hardware channel thread of PL330 DMAC. NULL if the channel is
  382. * available.
  383. */
  384. struct pl330_thread *thread;
  385. /* For D-to-M and M-to-D channels */
  386. int burst_sz; /* the peripheral fifo width */
  387. int burst_len; /* the number of burst */
  388. phys_addr_t fifo_addr;
  389. /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
  390. dma_addr_t fifo_dma;
  391. enum dma_data_direction dir;
  392. /* for cyclic capability */
  393. bool cyclic;
  394. /* for runtime pm tracking */
  395. bool active;
  396. };
  397. struct pl330_dmac {
  398. /* DMA-Engine Device */
  399. struct dma_device ddma;
  400. /* Holds info about sg limitations */
  401. struct device_dma_parameters dma_parms;
  402. /* Pool of descriptors available for the DMAC's channels */
  403. struct list_head desc_pool;
  404. /* To protect desc_pool manipulation */
  405. spinlock_t pool_lock;
  406. /* Size of MicroCode buffers for each channel. */
  407. unsigned mcbufsz;
  408. /* ioremap'ed address of PL330 registers. */
  409. void __iomem *base;
  410. /* Populated by the PL330 core driver during pl330_add */
  411. struct pl330_config pcfg;
  412. spinlock_t lock;
  413. /* Maximum possible events/irqs */
  414. int events[32];
  415. /* BUS address of MicroCode buffer */
  416. dma_addr_t mcode_bus;
  417. /* CPU address of MicroCode buffer */
  418. void *mcode_cpu;
  419. /* List of all Channel threads */
  420. struct pl330_thread *channels;
  421. /* Pointer to the MANAGER thread */
  422. struct pl330_thread *manager;
  423. /* To handle bad news in interrupt */
  424. struct tasklet_struct tasks;
  425. struct _pl330_tbd dmac_tbd;
  426. /* State of DMAC operation */
  427. enum pl330_dmac_state state;
  428. /* Holds list of reqs with due callbacks */
  429. struct list_head req_done;
  430. /* Peripheral channels connected to this DMAC */
  431. unsigned int num_peripherals;
  432. struct dma_pl330_chan *peripherals; /* keep at end */
  433. int quirks;
  434. };
  435. static struct pl330_of_quirks {
  436. char *quirk;
  437. int id;
  438. } of_quirks[] = {
  439. {
  440. .quirk = "arm,pl330-broken-no-flushp",
  441. .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
  442. }
  443. };
  444. struct dma_pl330_desc {
  445. /* To attach to a queue as child */
  446. struct list_head node;
  447. /* Descriptor for the DMA Engine API */
  448. struct dma_async_tx_descriptor txd;
  449. /* Xfer for PL330 core */
  450. struct pl330_xfer px;
  451. struct pl330_reqcfg rqcfg;
  452. enum desc_status status;
  453. int bytes_requested;
  454. bool last;
  455. /* The channel which currently holds this desc */
  456. struct dma_pl330_chan *pchan;
  457. enum dma_transfer_direction rqtype;
  458. /* Index of peripheral for the xfer. */
  459. unsigned peri:5;
  460. /* Hook to attach to DMAC's list of reqs with due callback */
  461. struct list_head rqd;
  462. };
  463. struct _xfer_spec {
  464. u32 ccr;
  465. struct dma_pl330_desc *desc;
  466. };
  467. static inline bool _queue_full(struct pl330_thread *thrd)
  468. {
  469. return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
  470. }
  471. static inline bool is_manager(struct pl330_thread *thrd)
  472. {
  473. return thrd->dmac->manager == thrd;
  474. }
  475. /* If manager of the thread is in Non-Secure mode */
  476. static inline bool _manager_ns(struct pl330_thread *thrd)
  477. {
  478. return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
  479. }
  480. static inline u32 get_revision(u32 periph_id)
  481. {
  482. return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
  483. }
  484. static inline u32 _emit_END(unsigned dry_run, u8 buf[])
  485. {
  486. if (dry_run)
  487. return SZ_DMAEND;
  488. buf[0] = CMD_DMAEND;
  489. PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
  490. return SZ_DMAEND;
  491. }
  492. static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
  493. {
  494. if (dry_run)
  495. return SZ_DMAFLUSHP;
  496. buf[0] = CMD_DMAFLUSHP;
  497. peri &= 0x1f;
  498. peri <<= 3;
  499. buf[1] = peri;
  500. PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
  501. return SZ_DMAFLUSHP;
  502. }
  503. static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
  504. {
  505. if (dry_run)
  506. return SZ_DMALD;
  507. buf[0] = CMD_DMALD;
  508. if (cond == SINGLE)
  509. buf[0] |= (0 << 1) | (1 << 0);
  510. else if (cond == BURST)
  511. buf[0] |= (1 << 1) | (1 << 0);
  512. PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
  513. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
  514. return SZ_DMALD;
  515. }
  516. static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
  517. enum pl330_cond cond, u8 peri)
  518. {
  519. if (dry_run)
  520. return SZ_DMALDP;
  521. buf[0] = CMD_DMALDP;
  522. if (cond == BURST)
  523. buf[0] |= (1 << 1);
  524. peri &= 0x1f;
  525. peri <<= 3;
  526. buf[1] = peri;
  527. PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
  528. cond == SINGLE ? 'S' : 'B', peri >> 3);
  529. return SZ_DMALDP;
  530. }
  531. static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
  532. unsigned loop, u8 cnt)
  533. {
  534. if (dry_run)
  535. return SZ_DMALP;
  536. buf[0] = CMD_DMALP;
  537. if (loop)
  538. buf[0] |= (1 << 1);
  539. cnt--; /* DMAC increments by 1 internally */
  540. buf[1] = cnt;
  541. PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
  542. return SZ_DMALP;
  543. }
  544. struct _arg_LPEND {
  545. enum pl330_cond cond;
  546. bool forever;
  547. unsigned loop;
  548. u8 bjump;
  549. };
  550. static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
  551. const struct _arg_LPEND *arg)
  552. {
  553. enum pl330_cond cond = arg->cond;
  554. bool forever = arg->forever;
  555. unsigned loop = arg->loop;
  556. u8 bjump = arg->bjump;
  557. if (dry_run)
  558. return SZ_DMALPEND;
  559. buf[0] = CMD_DMALPEND;
  560. if (loop)
  561. buf[0] |= (1 << 2);
  562. if (!forever)
  563. buf[0] |= (1 << 4);
  564. if (cond == SINGLE)
  565. buf[0] |= (0 << 1) | (1 << 0);
  566. else if (cond == BURST)
  567. buf[0] |= (1 << 1) | (1 << 0);
  568. buf[1] = bjump;
  569. PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
  570. forever ? "FE" : "END",
  571. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
  572. loop ? '1' : '0',
  573. bjump);
  574. return SZ_DMALPEND;
  575. }
  576. static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
  577. {
  578. if (dry_run)
  579. return SZ_DMAKILL;
  580. buf[0] = CMD_DMAKILL;
  581. return SZ_DMAKILL;
  582. }
  583. static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
  584. enum dmamov_dst dst, u32 val)
  585. {
  586. if (dry_run)
  587. return SZ_DMAMOV;
  588. buf[0] = CMD_DMAMOV;
  589. buf[1] = dst;
  590. buf[2] = val;
  591. buf[3] = val >> 8;
  592. buf[4] = val >> 16;
  593. buf[5] = val >> 24;
  594. PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
  595. dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
  596. return SZ_DMAMOV;
  597. }
  598. static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
  599. {
  600. if (dry_run)
  601. return SZ_DMARMB;
  602. buf[0] = CMD_DMARMB;
  603. PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
  604. return SZ_DMARMB;
  605. }
  606. static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
  607. {
  608. if (dry_run)
  609. return SZ_DMASEV;
  610. buf[0] = CMD_DMASEV;
  611. ev &= 0x1f;
  612. ev <<= 3;
  613. buf[1] = ev;
  614. PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
  615. return SZ_DMASEV;
  616. }
  617. static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
  618. {
  619. if (dry_run)
  620. return SZ_DMAST;
  621. buf[0] = CMD_DMAST;
  622. if (cond == SINGLE)
  623. buf[0] |= (0 << 1) | (1 << 0);
  624. else if (cond == BURST)
  625. buf[0] |= (1 << 1) | (1 << 0);
  626. PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
  627. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
  628. return SZ_DMAST;
  629. }
  630. static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
  631. enum pl330_cond cond, u8 peri)
  632. {
  633. if (dry_run)
  634. return SZ_DMASTP;
  635. buf[0] = CMD_DMASTP;
  636. if (cond == BURST)
  637. buf[0] |= (1 << 1);
  638. peri &= 0x1f;
  639. peri <<= 3;
  640. buf[1] = peri;
  641. PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
  642. cond == SINGLE ? 'S' : 'B', peri >> 3);
  643. return SZ_DMASTP;
  644. }
  645. static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
  646. enum pl330_cond cond, u8 peri)
  647. {
  648. if (dry_run)
  649. return SZ_DMAWFP;
  650. buf[0] = CMD_DMAWFP;
  651. if (cond == SINGLE)
  652. buf[0] |= (0 << 1) | (0 << 0);
  653. else if (cond == BURST)
  654. buf[0] |= (1 << 1) | (0 << 0);
  655. else
  656. buf[0] |= (0 << 1) | (1 << 0);
  657. peri &= 0x1f;
  658. peri <<= 3;
  659. buf[1] = peri;
  660. PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
  661. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
  662. return SZ_DMAWFP;
  663. }
  664. static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
  665. {
  666. if (dry_run)
  667. return SZ_DMAWMB;
  668. buf[0] = CMD_DMAWMB;
  669. PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
  670. return SZ_DMAWMB;
  671. }
  672. struct _arg_GO {
  673. u8 chan;
  674. u32 addr;
  675. unsigned ns;
  676. };
  677. static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
  678. const struct _arg_GO *arg)
  679. {
  680. u8 chan = arg->chan;
  681. u32 addr = arg->addr;
  682. unsigned ns = arg->ns;
  683. if (dry_run)
  684. return SZ_DMAGO;
  685. buf[0] = CMD_DMAGO;
  686. buf[0] |= (ns << 1);
  687. buf[1] = chan & 0x7;
  688. buf[2] = addr;
  689. buf[3] = addr >> 8;
  690. buf[4] = addr >> 16;
  691. buf[5] = addr >> 24;
  692. return SZ_DMAGO;
  693. }
  694. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  695. /* Returns Time-Out */
  696. static bool _until_dmac_idle(struct pl330_thread *thrd)
  697. {
  698. void __iomem *regs = thrd->dmac->base;
  699. unsigned long loops = msecs_to_loops(5);
  700. do {
  701. /* Until Manager is Idle */
  702. if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
  703. break;
  704. cpu_relax();
  705. } while (--loops);
  706. if (!loops)
  707. return true;
  708. return false;
  709. }
  710. static inline void _execute_DBGINSN(struct pl330_thread *thrd,
  711. u8 insn[], bool as_manager)
  712. {
  713. void __iomem *regs = thrd->dmac->base;
  714. u32 val;
  715. val = (insn[0] << 16) | (insn[1] << 24);
  716. if (!as_manager) {
  717. val |= (1 << 0);
  718. val |= (thrd->id << 8); /* Channel Number */
  719. }
  720. writel(val, regs + DBGINST0);
  721. val = le32_to_cpu(*((__le32 *)&insn[2]));
  722. writel(val, regs + DBGINST1);
  723. /* If timed out due to halted state-machine */
  724. if (_until_dmac_idle(thrd)) {
  725. dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
  726. return;
  727. }
  728. /* Get going */
  729. writel(0, regs + DBGCMD);
  730. }
  731. static inline u32 _state(struct pl330_thread *thrd)
  732. {
  733. void __iomem *regs = thrd->dmac->base;
  734. u32 val;
  735. if (is_manager(thrd))
  736. val = readl(regs + DS) & 0xf;
  737. else
  738. val = readl(regs + CS(thrd->id)) & 0xf;
  739. switch (val) {
  740. case DS_ST_STOP:
  741. return PL330_STATE_STOPPED;
  742. case DS_ST_EXEC:
  743. return PL330_STATE_EXECUTING;
  744. case DS_ST_CMISS:
  745. return PL330_STATE_CACHEMISS;
  746. case DS_ST_UPDTPC:
  747. return PL330_STATE_UPDTPC;
  748. case DS_ST_WFE:
  749. return PL330_STATE_WFE;
  750. case DS_ST_FAULT:
  751. return PL330_STATE_FAULTING;
  752. case DS_ST_ATBRR:
  753. if (is_manager(thrd))
  754. return PL330_STATE_INVALID;
  755. else
  756. return PL330_STATE_ATBARRIER;
  757. case DS_ST_QBUSY:
  758. if (is_manager(thrd))
  759. return PL330_STATE_INVALID;
  760. else
  761. return PL330_STATE_QUEUEBUSY;
  762. case DS_ST_WFP:
  763. if (is_manager(thrd))
  764. return PL330_STATE_INVALID;
  765. else
  766. return PL330_STATE_WFP;
  767. case DS_ST_KILL:
  768. if (is_manager(thrd))
  769. return PL330_STATE_INVALID;
  770. else
  771. return PL330_STATE_KILLING;
  772. case DS_ST_CMPLT:
  773. if (is_manager(thrd))
  774. return PL330_STATE_INVALID;
  775. else
  776. return PL330_STATE_COMPLETING;
  777. case DS_ST_FLTCMP:
  778. if (is_manager(thrd))
  779. return PL330_STATE_INVALID;
  780. else
  781. return PL330_STATE_FAULT_COMPLETING;
  782. default:
  783. return PL330_STATE_INVALID;
  784. }
  785. }
  786. static void _stop(struct pl330_thread *thrd)
  787. {
  788. void __iomem *regs = thrd->dmac->base;
  789. u8 insn[6] = {0, 0, 0, 0, 0, 0};
  790. if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
  791. UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
  792. /* Return if nothing needs to be done */
  793. if (_state(thrd) == PL330_STATE_COMPLETING
  794. || _state(thrd) == PL330_STATE_KILLING
  795. || _state(thrd) == PL330_STATE_STOPPED)
  796. return;
  797. _emit_KILL(0, insn);
  798. /* Stop generating interrupts for SEV */
  799. writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
  800. _execute_DBGINSN(thrd, insn, is_manager(thrd));
  801. }
  802. /* Start doing req 'idx' of thread 'thrd' */
  803. static bool _trigger(struct pl330_thread *thrd)
  804. {
  805. void __iomem *regs = thrd->dmac->base;
  806. struct _pl330_req *req;
  807. struct dma_pl330_desc *desc;
  808. struct _arg_GO go;
  809. unsigned ns;
  810. u8 insn[6] = {0, 0, 0, 0, 0, 0};
  811. int idx;
  812. /* Return if already ACTIVE */
  813. if (_state(thrd) != PL330_STATE_STOPPED)
  814. return true;
  815. idx = 1 - thrd->lstenq;
  816. if (thrd->req[idx].desc != NULL) {
  817. req = &thrd->req[idx];
  818. } else {
  819. idx = thrd->lstenq;
  820. if (thrd->req[idx].desc != NULL)
  821. req = &thrd->req[idx];
  822. else
  823. req = NULL;
  824. }
  825. /* Return if no request */
  826. if (!req)
  827. return true;
  828. /* Return if req is running */
  829. if (idx == thrd->req_running)
  830. return true;
  831. desc = req->desc;
  832. ns = desc->rqcfg.nonsecure ? 1 : 0;
  833. /* See 'Abort Sources' point-4 at Page 2-25 */
  834. if (_manager_ns(thrd) && !ns)
  835. dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
  836. __func__, __LINE__);
  837. go.chan = thrd->id;
  838. go.addr = req->mc_bus;
  839. go.ns = ns;
  840. _emit_GO(0, insn, &go);
  841. /* Set to generate interrupts for SEV */
  842. writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
  843. /* Only manager can execute GO */
  844. _execute_DBGINSN(thrd, insn, true);
  845. thrd->req_running = idx;
  846. return true;
  847. }
  848. static bool _start(struct pl330_thread *thrd)
  849. {
  850. switch (_state(thrd)) {
  851. case PL330_STATE_FAULT_COMPLETING:
  852. UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
  853. if (_state(thrd) == PL330_STATE_KILLING)
  854. UNTIL(thrd, PL330_STATE_STOPPED)
  855. case PL330_STATE_FAULTING:
  856. _stop(thrd);
  857. case PL330_STATE_KILLING:
  858. case PL330_STATE_COMPLETING:
  859. UNTIL(thrd, PL330_STATE_STOPPED)
  860. case PL330_STATE_STOPPED:
  861. return _trigger(thrd);
  862. case PL330_STATE_WFP:
  863. case PL330_STATE_QUEUEBUSY:
  864. case PL330_STATE_ATBARRIER:
  865. case PL330_STATE_UPDTPC:
  866. case PL330_STATE_CACHEMISS:
  867. case PL330_STATE_EXECUTING:
  868. return true;
  869. case PL330_STATE_WFE: /* For RESUME, nothing yet */
  870. default:
  871. return false;
  872. }
  873. }
  874. static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
  875. const struct _xfer_spec *pxs, int cyc)
  876. {
  877. int off = 0;
  878. struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
  879. /* check lock-up free version */
  880. if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
  881. while (cyc--) {
  882. off += _emit_LD(dry_run, &buf[off], ALWAYS);
  883. off += _emit_ST(dry_run, &buf[off], ALWAYS);
  884. }
  885. } else {
  886. while (cyc--) {
  887. off += _emit_LD(dry_run, &buf[off], ALWAYS);
  888. off += _emit_RMB(dry_run, &buf[off]);
  889. off += _emit_ST(dry_run, &buf[off], ALWAYS);
  890. off += _emit_WMB(dry_run, &buf[off]);
  891. }
  892. }
  893. return off;
  894. }
  895. static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
  896. u8 buf[], const struct _xfer_spec *pxs,
  897. int cyc)
  898. {
  899. int off = 0;
  900. enum pl330_cond cond;
  901. if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
  902. cond = BURST;
  903. else
  904. cond = SINGLE;
  905. while (cyc--) {
  906. off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
  907. off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
  908. off += _emit_ST(dry_run, &buf[off], ALWAYS);
  909. if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
  910. off += _emit_FLUSHP(dry_run, &buf[off],
  911. pxs->desc->peri);
  912. }
  913. return off;
  914. }
  915. static inline int _ldst_memtodev(struct pl330_dmac *pl330,
  916. unsigned dry_run, u8 buf[],
  917. const struct _xfer_spec *pxs, int cyc)
  918. {
  919. int off = 0;
  920. enum pl330_cond cond;
  921. if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
  922. cond = BURST;
  923. else
  924. cond = SINGLE;
  925. while (cyc--) {
  926. off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
  927. off += _emit_LD(dry_run, &buf[off], ALWAYS);
  928. off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
  929. if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
  930. off += _emit_FLUSHP(dry_run, &buf[off],
  931. pxs->desc->peri);
  932. }
  933. return off;
  934. }
  935. static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
  936. const struct _xfer_spec *pxs, int cyc)
  937. {
  938. int off = 0;
  939. switch (pxs->desc->rqtype) {
  940. case DMA_MEM_TO_DEV:
  941. off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
  942. break;
  943. case DMA_DEV_TO_MEM:
  944. off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
  945. break;
  946. case DMA_MEM_TO_MEM:
  947. off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
  948. break;
  949. default:
  950. off += 0x40000000; /* Scare off the Client */
  951. break;
  952. }
  953. return off;
  954. }
  955. /* Returns bytes consumed and updates bursts */
  956. static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
  957. unsigned long *bursts, const struct _xfer_spec *pxs)
  958. {
  959. int cyc, cycmax, szlp, szlpend, szbrst, off;
  960. unsigned lcnt0, lcnt1, ljmp0, ljmp1;
  961. struct _arg_LPEND lpend;
  962. if (*bursts == 1)
  963. return _bursts(pl330, dry_run, buf, pxs, 1);
  964. /* Max iterations possible in DMALP is 256 */
  965. if (*bursts >= 256*256) {
  966. lcnt1 = 256;
  967. lcnt0 = 256;
  968. cyc = *bursts / lcnt1 / lcnt0;
  969. } else if (*bursts > 256) {
  970. lcnt1 = 256;
  971. lcnt0 = *bursts / lcnt1;
  972. cyc = 1;
  973. } else {
  974. lcnt1 = *bursts;
  975. lcnt0 = 0;
  976. cyc = 1;
  977. }
  978. szlp = _emit_LP(1, buf, 0, 0);
  979. szbrst = _bursts(pl330, 1, buf, pxs, 1);
  980. lpend.cond = ALWAYS;
  981. lpend.forever = false;
  982. lpend.loop = 0;
  983. lpend.bjump = 0;
  984. szlpend = _emit_LPEND(1, buf, &lpend);
  985. if (lcnt0) {
  986. szlp *= 2;
  987. szlpend *= 2;
  988. }
  989. /*
  990. * Max bursts that we can unroll due to limit on the
  991. * size of backward jump that can be encoded in DMALPEND
  992. * which is 8-bits and hence 255
  993. */
  994. cycmax = (255 - (szlp + szlpend)) / szbrst;
  995. cyc = (cycmax < cyc) ? cycmax : cyc;
  996. off = 0;
  997. if (lcnt0) {
  998. off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
  999. ljmp0 = off;
  1000. }
  1001. off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
  1002. ljmp1 = off;
  1003. off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
  1004. lpend.cond = ALWAYS;
  1005. lpend.forever = false;
  1006. lpend.loop = 1;
  1007. lpend.bjump = off - ljmp1;
  1008. off += _emit_LPEND(dry_run, &buf[off], &lpend);
  1009. if (lcnt0) {
  1010. lpend.cond = ALWAYS;
  1011. lpend.forever = false;
  1012. lpend.loop = 0;
  1013. lpend.bjump = off - ljmp0;
  1014. off += _emit_LPEND(dry_run, &buf[off], &lpend);
  1015. }
  1016. *bursts = lcnt1 * cyc;
  1017. if (lcnt0)
  1018. *bursts *= lcnt0;
  1019. return off;
  1020. }
  1021. static inline int _setup_loops(struct pl330_dmac *pl330,
  1022. unsigned dry_run, u8 buf[],
  1023. const struct _xfer_spec *pxs)
  1024. {
  1025. struct pl330_xfer *x = &pxs->desc->px;
  1026. u32 ccr = pxs->ccr;
  1027. unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
  1028. int off = 0;
  1029. while (bursts) {
  1030. c = bursts;
  1031. off += _loop(pl330, dry_run, &buf[off], &c, pxs);
  1032. bursts -= c;
  1033. }
  1034. return off;
  1035. }
  1036. static inline int _setup_xfer(struct pl330_dmac *pl330,
  1037. unsigned dry_run, u8 buf[],
  1038. const struct _xfer_spec *pxs)
  1039. {
  1040. struct pl330_xfer *x = &pxs->desc->px;
  1041. int off = 0;
  1042. /* DMAMOV SAR, x->src_addr */
  1043. off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
  1044. /* DMAMOV DAR, x->dst_addr */
  1045. off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
  1046. /* Setup Loop(s) */
  1047. off += _setup_loops(pl330, dry_run, &buf[off], pxs);
  1048. return off;
  1049. }
  1050. /*
  1051. * A req is a sequence of one or more xfer units.
  1052. * Returns the number of bytes taken to setup the MC for the req.
  1053. */
  1054. static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
  1055. struct pl330_thread *thrd, unsigned index,
  1056. struct _xfer_spec *pxs)
  1057. {
  1058. struct _pl330_req *req = &thrd->req[index];
  1059. struct pl330_xfer *x;
  1060. u8 *buf = req->mc_cpu;
  1061. int off = 0;
  1062. PL330_DBGMC_START(req->mc_bus);
  1063. /* DMAMOV CCR, ccr */
  1064. off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
  1065. x = &pxs->desc->px;
  1066. /* Error if xfer length is not aligned at burst size */
  1067. if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
  1068. return -EINVAL;
  1069. off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
  1070. /* DMASEV peripheral/event */
  1071. off += _emit_SEV(dry_run, &buf[off], thrd->ev);
  1072. /* DMAEND */
  1073. off += _emit_END(dry_run, &buf[off]);
  1074. return off;
  1075. }
  1076. static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
  1077. {
  1078. u32 ccr = 0;
  1079. if (rqc->src_inc)
  1080. ccr |= CC_SRCINC;
  1081. if (rqc->dst_inc)
  1082. ccr |= CC_DSTINC;
  1083. /* We set same protection levels for Src and DST for now */
  1084. if (rqc->privileged)
  1085. ccr |= CC_SRCPRI | CC_DSTPRI;
  1086. if (rqc->nonsecure)
  1087. ccr |= CC_SRCNS | CC_DSTNS;
  1088. if (rqc->insnaccess)
  1089. ccr |= CC_SRCIA | CC_DSTIA;
  1090. ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
  1091. ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
  1092. ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
  1093. ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
  1094. ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
  1095. ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
  1096. ccr |= (rqc->swap << CC_SWAP_SHFT);
  1097. return ccr;
  1098. }
  1099. /*
  1100. * Submit a list of xfers after which the client wants notification.
  1101. * Client is not notified after each xfer unit, just once after all
  1102. * xfer units are done or some error occurs.
  1103. */
  1104. static int pl330_submit_req(struct pl330_thread *thrd,
  1105. struct dma_pl330_desc *desc)
  1106. {
  1107. struct pl330_dmac *pl330 = thrd->dmac;
  1108. struct _xfer_spec xs;
  1109. unsigned long flags;
  1110. unsigned idx;
  1111. u32 ccr;
  1112. int ret = 0;
  1113. if (pl330->state == DYING
  1114. || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
  1115. dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
  1116. __func__, __LINE__);
  1117. return -EAGAIN;
  1118. }
  1119. /* If request for non-existing peripheral */
  1120. if (desc->rqtype != DMA_MEM_TO_MEM &&
  1121. desc->peri >= pl330->pcfg.num_peri) {
  1122. dev_info(thrd->dmac->ddma.dev,
  1123. "%s:%d Invalid peripheral(%u)!\n",
  1124. __func__, __LINE__, desc->peri);
  1125. return -EINVAL;
  1126. }
  1127. spin_lock_irqsave(&pl330->lock, flags);
  1128. if (_queue_full(thrd)) {
  1129. ret = -EAGAIN;
  1130. goto xfer_exit;
  1131. }
  1132. /* Prefer Secure Channel */
  1133. if (!_manager_ns(thrd))
  1134. desc->rqcfg.nonsecure = 0;
  1135. else
  1136. desc->rqcfg.nonsecure = 1;
  1137. ccr = _prepare_ccr(&desc->rqcfg);
  1138. idx = thrd->req[0].desc == NULL ? 0 : 1;
  1139. xs.ccr = ccr;
  1140. xs.desc = desc;
  1141. /* First dry run to check if req is acceptable */
  1142. ret = _setup_req(pl330, 1, thrd, idx, &xs);
  1143. if (ret < 0)
  1144. goto xfer_exit;
  1145. if (ret > pl330->mcbufsz / 2) {
  1146. dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
  1147. __func__, __LINE__, ret, pl330->mcbufsz / 2);
  1148. ret = -ENOMEM;
  1149. goto xfer_exit;
  1150. }
  1151. /* Hook the request */
  1152. thrd->lstenq = idx;
  1153. thrd->req[idx].desc = desc;
  1154. _setup_req(pl330, 0, thrd, idx, &xs);
  1155. ret = 0;
  1156. xfer_exit:
  1157. spin_unlock_irqrestore(&pl330->lock, flags);
  1158. return ret;
  1159. }
  1160. static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
  1161. {
  1162. struct dma_pl330_chan *pch;
  1163. unsigned long flags;
  1164. if (!desc)
  1165. return;
  1166. pch = desc->pchan;
  1167. /* If desc aborted */
  1168. if (!pch)
  1169. return;
  1170. spin_lock_irqsave(&pch->lock, flags);
  1171. desc->status = DONE;
  1172. spin_unlock_irqrestore(&pch->lock, flags);
  1173. tasklet_schedule(&pch->task);
  1174. }
  1175. static void pl330_dotask(unsigned long data)
  1176. {
  1177. struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
  1178. unsigned long flags;
  1179. int i;
  1180. spin_lock_irqsave(&pl330->lock, flags);
  1181. /* The DMAC itself gone nuts */
  1182. if (pl330->dmac_tbd.reset_dmac) {
  1183. pl330->state = DYING;
  1184. /* Reset the manager too */
  1185. pl330->dmac_tbd.reset_mngr = true;
  1186. /* Clear the reset flag */
  1187. pl330->dmac_tbd.reset_dmac = false;
  1188. }
  1189. if (pl330->dmac_tbd.reset_mngr) {
  1190. _stop(pl330->manager);
  1191. /* Reset all channels */
  1192. pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
  1193. /* Clear the reset flag */
  1194. pl330->dmac_tbd.reset_mngr = false;
  1195. }
  1196. for (i = 0; i < pl330->pcfg.num_chan; i++) {
  1197. if (pl330->dmac_tbd.reset_chan & (1 << i)) {
  1198. struct pl330_thread *thrd = &pl330->channels[i];
  1199. void __iomem *regs = pl330->base;
  1200. enum pl330_op_err err;
  1201. _stop(thrd);
  1202. if (readl(regs + FSC) & (1 << thrd->id))
  1203. err = PL330_ERR_FAIL;
  1204. else
  1205. err = PL330_ERR_ABORT;
  1206. spin_unlock_irqrestore(&pl330->lock, flags);
  1207. dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
  1208. dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
  1209. spin_lock_irqsave(&pl330->lock, flags);
  1210. thrd->req[0].desc = NULL;
  1211. thrd->req[1].desc = NULL;
  1212. thrd->req_running = -1;
  1213. /* Clear the reset flag */
  1214. pl330->dmac_tbd.reset_chan &= ~(1 << i);
  1215. }
  1216. }
  1217. spin_unlock_irqrestore(&pl330->lock, flags);
  1218. return;
  1219. }
  1220. /* Returns 1 if state was updated, 0 otherwise */
  1221. static int pl330_update(struct pl330_dmac *pl330)
  1222. {
  1223. struct dma_pl330_desc *descdone;
  1224. unsigned long flags;
  1225. void __iomem *regs;
  1226. u32 val;
  1227. int id, ev, ret = 0;
  1228. regs = pl330->base;
  1229. spin_lock_irqsave(&pl330->lock, flags);
  1230. val = readl(regs + FSM) & 0x1;
  1231. if (val)
  1232. pl330->dmac_tbd.reset_mngr = true;
  1233. else
  1234. pl330->dmac_tbd.reset_mngr = false;
  1235. val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
  1236. pl330->dmac_tbd.reset_chan |= val;
  1237. if (val) {
  1238. int i = 0;
  1239. while (i < pl330->pcfg.num_chan) {
  1240. if (val & (1 << i)) {
  1241. dev_info(pl330->ddma.dev,
  1242. "Reset Channel-%d\t CS-%x FTC-%x\n",
  1243. i, readl(regs + CS(i)),
  1244. readl(regs + FTC(i)));
  1245. _stop(&pl330->channels[i]);
  1246. }
  1247. i++;
  1248. }
  1249. }
  1250. /* Check which event happened i.e, thread notified */
  1251. val = readl(regs + ES);
  1252. if (pl330->pcfg.num_events < 32
  1253. && val & ~((1 << pl330->pcfg.num_events) - 1)) {
  1254. pl330->dmac_tbd.reset_dmac = true;
  1255. dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
  1256. __LINE__);
  1257. ret = 1;
  1258. goto updt_exit;
  1259. }
  1260. for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
  1261. if (val & (1 << ev)) { /* Event occurred */
  1262. struct pl330_thread *thrd;
  1263. u32 inten = readl(regs + INTEN);
  1264. int active;
  1265. /* Clear the event */
  1266. if (inten & (1 << ev))
  1267. writel(1 << ev, regs + INTCLR);
  1268. ret = 1;
  1269. id = pl330->events[ev];
  1270. thrd = &pl330->channels[id];
  1271. active = thrd->req_running;
  1272. if (active == -1) /* Aborted */
  1273. continue;
  1274. /* Detach the req */
  1275. descdone = thrd->req[active].desc;
  1276. thrd->req[active].desc = NULL;
  1277. thrd->req_running = -1;
  1278. /* Get going again ASAP */
  1279. _start(thrd);
  1280. /* For now, just make a list of callbacks to be done */
  1281. list_add_tail(&descdone->rqd, &pl330->req_done);
  1282. }
  1283. }
  1284. /* Now that we are in no hurry, do the callbacks */
  1285. while (!list_empty(&pl330->req_done)) {
  1286. descdone = list_first_entry(&pl330->req_done,
  1287. struct dma_pl330_desc, rqd);
  1288. list_del(&descdone->rqd);
  1289. spin_unlock_irqrestore(&pl330->lock, flags);
  1290. dma_pl330_rqcb(descdone, PL330_ERR_NONE);
  1291. spin_lock_irqsave(&pl330->lock, flags);
  1292. }
  1293. updt_exit:
  1294. spin_unlock_irqrestore(&pl330->lock, flags);
  1295. if (pl330->dmac_tbd.reset_dmac
  1296. || pl330->dmac_tbd.reset_mngr
  1297. || pl330->dmac_tbd.reset_chan) {
  1298. ret = 1;
  1299. tasklet_schedule(&pl330->tasks);
  1300. }
  1301. return ret;
  1302. }
  1303. /* Reserve an event */
  1304. static inline int _alloc_event(struct pl330_thread *thrd)
  1305. {
  1306. struct pl330_dmac *pl330 = thrd->dmac;
  1307. int ev;
  1308. for (ev = 0; ev < pl330->pcfg.num_events; ev++)
  1309. if (pl330->events[ev] == -1) {
  1310. pl330->events[ev] = thrd->id;
  1311. return ev;
  1312. }
  1313. return -1;
  1314. }
  1315. static bool _chan_ns(const struct pl330_dmac *pl330, int i)
  1316. {
  1317. return pl330->pcfg.irq_ns & (1 << i);
  1318. }
  1319. /* Upon success, returns IdentityToken for the
  1320. * allocated channel, NULL otherwise.
  1321. */
  1322. static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
  1323. {
  1324. struct pl330_thread *thrd = NULL;
  1325. int chans, i;
  1326. if (pl330->state == DYING)
  1327. return NULL;
  1328. chans = pl330->pcfg.num_chan;
  1329. for (i = 0; i < chans; i++) {
  1330. thrd = &pl330->channels[i];
  1331. if ((thrd->free) && (!_manager_ns(thrd) ||
  1332. _chan_ns(pl330, i))) {
  1333. thrd->ev = _alloc_event(thrd);
  1334. if (thrd->ev >= 0) {
  1335. thrd->free = false;
  1336. thrd->lstenq = 1;
  1337. thrd->req[0].desc = NULL;
  1338. thrd->req[1].desc = NULL;
  1339. thrd->req_running = -1;
  1340. break;
  1341. }
  1342. }
  1343. thrd = NULL;
  1344. }
  1345. return thrd;
  1346. }
  1347. /* Release an event */
  1348. static inline void _free_event(struct pl330_thread *thrd, int ev)
  1349. {
  1350. struct pl330_dmac *pl330 = thrd->dmac;
  1351. /* If the event is valid and was held by the thread */
  1352. if (ev >= 0 && ev < pl330->pcfg.num_events
  1353. && pl330->events[ev] == thrd->id)
  1354. pl330->events[ev] = -1;
  1355. }
  1356. static void pl330_release_channel(struct pl330_thread *thrd)
  1357. {
  1358. struct pl330_dmac *pl330;
  1359. if (!thrd || thrd->free)
  1360. return;
  1361. _stop(thrd);
  1362. dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
  1363. dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
  1364. pl330 = thrd->dmac;
  1365. _free_event(thrd, thrd->ev);
  1366. thrd->free = true;
  1367. }
  1368. /* Initialize the structure for PL330 configuration, that can be used
  1369. * by the client driver the make best use of the DMAC
  1370. */
  1371. static void read_dmac_config(struct pl330_dmac *pl330)
  1372. {
  1373. void __iomem *regs = pl330->base;
  1374. u32 val;
  1375. val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
  1376. val &= CRD_DATA_WIDTH_MASK;
  1377. pl330->pcfg.data_bus_width = 8 * (1 << val);
  1378. val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
  1379. val &= CRD_DATA_BUFF_MASK;
  1380. pl330->pcfg.data_buf_dep = val + 1;
  1381. val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
  1382. val &= CR0_NUM_CHANS_MASK;
  1383. val += 1;
  1384. pl330->pcfg.num_chan = val;
  1385. val = readl(regs + CR0);
  1386. if (val & CR0_PERIPH_REQ_SET) {
  1387. val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
  1388. val += 1;
  1389. pl330->pcfg.num_peri = val;
  1390. pl330->pcfg.peri_ns = readl(regs + CR4);
  1391. } else {
  1392. pl330->pcfg.num_peri = 0;
  1393. }
  1394. val = readl(regs + CR0);
  1395. if (val & CR0_BOOT_MAN_NS)
  1396. pl330->pcfg.mode |= DMAC_MODE_NS;
  1397. else
  1398. pl330->pcfg.mode &= ~DMAC_MODE_NS;
  1399. val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
  1400. val &= CR0_NUM_EVENTS_MASK;
  1401. val += 1;
  1402. pl330->pcfg.num_events = val;
  1403. pl330->pcfg.irq_ns = readl(regs + CR3);
  1404. }
  1405. static inline void _reset_thread(struct pl330_thread *thrd)
  1406. {
  1407. struct pl330_dmac *pl330 = thrd->dmac;
  1408. thrd->req[0].mc_cpu = pl330->mcode_cpu
  1409. + (thrd->id * pl330->mcbufsz);
  1410. thrd->req[0].mc_bus = pl330->mcode_bus
  1411. + (thrd->id * pl330->mcbufsz);
  1412. thrd->req[0].desc = NULL;
  1413. thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
  1414. + pl330->mcbufsz / 2;
  1415. thrd->req[1].mc_bus = thrd->req[0].mc_bus
  1416. + pl330->mcbufsz / 2;
  1417. thrd->req[1].desc = NULL;
  1418. thrd->req_running = -1;
  1419. }
  1420. static int dmac_alloc_threads(struct pl330_dmac *pl330)
  1421. {
  1422. int chans = pl330->pcfg.num_chan;
  1423. struct pl330_thread *thrd;
  1424. int i;
  1425. /* Allocate 1 Manager and 'chans' Channel threads */
  1426. pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
  1427. GFP_KERNEL);
  1428. if (!pl330->channels)
  1429. return -ENOMEM;
  1430. /* Init Channel threads */
  1431. for (i = 0; i < chans; i++) {
  1432. thrd = &pl330->channels[i];
  1433. thrd->id = i;
  1434. thrd->dmac = pl330;
  1435. _reset_thread(thrd);
  1436. thrd->free = true;
  1437. }
  1438. /* MANAGER is indexed at the end */
  1439. thrd = &pl330->channels[chans];
  1440. thrd->id = chans;
  1441. thrd->dmac = pl330;
  1442. thrd->free = false;
  1443. pl330->manager = thrd;
  1444. return 0;
  1445. }
  1446. static int dmac_alloc_resources(struct pl330_dmac *pl330)
  1447. {
  1448. int chans = pl330->pcfg.num_chan;
  1449. int ret;
  1450. /*
  1451. * Alloc MicroCode buffer for 'chans' Channel threads.
  1452. * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
  1453. */
  1454. pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
  1455. chans * pl330->mcbufsz,
  1456. &pl330->mcode_bus, GFP_KERNEL,
  1457. DMA_ATTR_PRIVILEGED);
  1458. if (!pl330->mcode_cpu) {
  1459. dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
  1460. __func__, __LINE__);
  1461. return -ENOMEM;
  1462. }
  1463. ret = dmac_alloc_threads(pl330);
  1464. if (ret) {
  1465. dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
  1466. __func__, __LINE__);
  1467. dma_free_coherent(pl330->ddma.dev,
  1468. chans * pl330->mcbufsz,
  1469. pl330->mcode_cpu, pl330->mcode_bus);
  1470. return ret;
  1471. }
  1472. return 0;
  1473. }
  1474. static int pl330_add(struct pl330_dmac *pl330)
  1475. {
  1476. int i, ret;
  1477. /* Check if we can handle this DMAC */
  1478. if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
  1479. dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
  1480. pl330->pcfg.periph_id);
  1481. return -EINVAL;
  1482. }
  1483. /* Read the configuration of the DMAC */
  1484. read_dmac_config(pl330);
  1485. if (pl330->pcfg.num_events == 0) {
  1486. dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
  1487. __func__, __LINE__);
  1488. return -EINVAL;
  1489. }
  1490. spin_lock_init(&pl330->lock);
  1491. INIT_LIST_HEAD(&pl330->req_done);
  1492. /* Use default MC buffer size if not provided */
  1493. if (!pl330->mcbufsz)
  1494. pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
  1495. /* Mark all events as free */
  1496. for (i = 0; i < pl330->pcfg.num_events; i++)
  1497. pl330->events[i] = -1;
  1498. /* Allocate resources needed by the DMAC */
  1499. ret = dmac_alloc_resources(pl330);
  1500. if (ret) {
  1501. dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
  1502. return ret;
  1503. }
  1504. tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
  1505. pl330->state = INIT;
  1506. return 0;
  1507. }
  1508. static int dmac_free_threads(struct pl330_dmac *pl330)
  1509. {
  1510. struct pl330_thread *thrd;
  1511. int i;
  1512. /* Release Channel threads */
  1513. for (i = 0; i < pl330->pcfg.num_chan; i++) {
  1514. thrd = &pl330->channels[i];
  1515. pl330_release_channel(thrd);
  1516. }
  1517. /* Free memory */
  1518. kfree(pl330->channels);
  1519. return 0;
  1520. }
  1521. static void pl330_del(struct pl330_dmac *pl330)
  1522. {
  1523. pl330->state = UNINIT;
  1524. tasklet_kill(&pl330->tasks);
  1525. /* Free DMAC resources */
  1526. dmac_free_threads(pl330);
  1527. dma_free_coherent(pl330->ddma.dev,
  1528. pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
  1529. pl330->mcode_bus);
  1530. }
  1531. /* forward declaration */
  1532. static struct amba_driver pl330_driver;
  1533. static inline struct dma_pl330_chan *
  1534. to_pchan(struct dma_chan *ch)
  1535. {
  1536. if (!ch)
  1537. return NULL;
  1538. return container_of(ch, struct dma_pl330_chan, chan);
  1539. }
  1540. static inline struct dma_pl330_desc *
  1541. to_desc(struct dma_async_tx_descriptor *tx)
  1542. {
  1543. return container_of(tx, struct dma_pl330_desc, txd);
  1544. }
  1545. static inline void fill_queue(struct dma_pl330_chan *pch)
  1546. {
  1547. struct dma_pl330_desc *desc;
  1548. int ret;
  1549. list_for_each_entry(desc, &pch->work_list, node) {
  1550. /* If already submitted */
  1551. if (desc->status == BUSY)
  1552. continue;
  1553. ret = pl330_submit_req(pch->thread, desc);
  1554. if (!ret) {
  1555. desc->status = BUSY;
  1556. } else if (ret == -EAGAIN) {
  1557. /* QFull or DMAC Dying */
  1558. break;
  1559. } else {
  1560. /* Unacceptable request */
  1561. desc->status = DONE;
  1562. dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
  1563. __func__, __LINE__, desc->txd.cookie);
  1564. tasklet_schedule(&pch->task);
  1565. }
  1566. }
  1567. }
  1568. static void pl330_tasklet(unsigned long data)
  1569. {
  1570. struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
  1571. struct dma_pl330_desc *desc, *_dt;
  1572. unsigned long flags;
  1573. bool power_down = false;
  1574. spin_lock_irqsave(&pch->lock, flags);
  1575. /* Pick up ripe tomatoes */
  1576. list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
  1577. if (desc->status == DONE) {
  1578. if (!pch->cyclic)
  1579. dma_cookie_complete(&desc->txd);
  1580. list_move_tail(&desc->node, &pch->completed_list);
  1581. }
  1582. /* Try to submit a req imm. next to the last completed cookie */
  1583. fill_queue(pch);
  1584. if (list_empty(&pch->work_list)) {
  1585. spin_lock(&pch->thread->dmac->lock);
  1586. _stop(pch->thread);
  1587. spin_unlock(&pch->thread->dmac->lock);
  1588. power_down = true;
  1589. pch->active = false;
  1590. } else {
  1591. /* Make sure the PL330 Channel thread is active */
  1592. spin_lock(&pch->thread->dmac->lock);
  1593. _start(pch->thread);
  1594. spin_unlock(&pch->thread->dmac->lock);
  1595. }
  1596. while (!list_empty(&pch->completed_list)) {
  1597. struct dmaengine_desc_callback cb;
  1598. desc = list_first_entry(&pch->completed_list,
  1599. struct dma_pl330_desc, node);
  1600. dmaengine_desc_get_callback(&desc->txd, &cb);
  1601. if (pch->cyclic) {
  1602. desc->status = PREP;
  1603. list_move_tail(&desc->node, &pch->work_list);
  1604. if (power_down) {
  1605. pch->active = true;
  1606. spin_lock(&pch->thread->dmac->lock);
  1607. _start(pch->thread);
  1608. spin_unlock(&pch->thread->dmac->lock);
  1609. power_down = false;
  1610. }
  1611. } else {
  1612. desc->status = FREE;
  1613. list_move_tail(&desc->node, &pch->dmac->desc_pool);
  1614. }
  1615. dma_descriptor_unmap(&desc->txd);
  1616. if (dmaengine_desc_callback_valid(&cb)) {
  1617. spin_unlock_irqrestore(&pch->lock, flags);
  1618. dmaengine_desc_callback_invoke(&cb, NULL);
  1619. spin_lock_irqsave(&pch->lock, flags);
  1620. }
  1621. }
  1622. spin_unlock_irqrestore(&pch->lock, flags);
  1623. /* If work list empty, power down */
  1624. if (power_down) {
  1625. pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
  1626. pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
  1627. }
  1628. }
  1629. static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
  1630. struct of_dma *ofdma)
  1631. {
  1632. int count = dma_spec->args_count;
  1633. struct pl330_dmac *pl330 = ofdma->of_dma_data;
  1634. unsigned int chan_id;
  1635. if (!pl330)
  1636. return NULL;
  1637. if (count != 1)
  1638. return NULL;
  1639. chan_id = dma_spec->args[0];
  1640. if (chan_id >= pl330->num_peripherals)
  1641. return NULL;
  1642. return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
  1643. }
  1644. static int pl330_alloc_chan_resources(struct dma_chan *chan)
  1645. {
  1646. struct dma_pl330_chan *pch = to_pchan(chan);
  1647. struct pl330_dmac *pl330 = pch->dmac;
  1648. unsigned long flags;
  1649. spin_lock_irqsave(&pl330->lock, flags);
  1650. dma_cookie_init(chan);
  1651. pch->cyclic = false;
  1652. pch->thread = pl330_request_channel(pl330);
  1653. if (!pch->thread) {
  1654. spin_unlock_irqrestore(&pl330->lock, flags);
  1655. return -ENOMEM;
  1656. }
  1657. tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
  1658. spin_unlock_irqrestore(&pl330->lock, flags);
  1659. return 1;
  1660. }
  1661. /*
  1662. * We need the data direction between the DMAC (the dma-mapping "device") and
  1663. * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
  1664. */
  1665. static enum dma_data_direction
  1666. pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
  1667. {
  1668. switch (dir) {
  1669. case DMA_MEM_TO_DEV:
  1670. return DMA_FROM_DEVICE;
  1671. case DMA_DEV_TO_MEM:
  1672. return DMA_TO_DEVICE;
  1673. case DMA_DEV_TO_DEV:
  1674. return DMA_BIDIRECTIONAL;
  1675. default:
  1676. return DMA_NONE;
  1677. }
  1678. }
  1679. static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
  1680. {
  1681. if (pch->dir != DMA_NONE)
  1682. dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
  1683. 1 << pch->burst_sz, pch->dir, 0);
  1684. pch->dir = DMA_NONE;
  1685. }
  1686. static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
  1687. enum dma_transfer_direction dir)
  1688. {
  1689. struct device *dev = pch->chan.device->dev;
  1690. enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
  1691. /* Already mapped for this config? */
  1692. if (pch->dir == dma_dir)
  1693. return true;
  1694. pl330_unprep_slave_fifo(pch);
  1695. pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
  1696. 1 << pch->burst_sz, dma_dir, 0);
  1697. if (dma_mapping_error(dev, pch->fifo_dma))
  1698. return false;
  1699. pch->dir = dma_dir;
  1700. return true;
  1701. }
  1702. static int pl330_config(struct dma_chan *chan,
  1703. struct dma_slave_config *slave_config)
  1704. {
  1705. struct dma_pl330_chan *pch = to_pchan(chan);
  1706. pl330_unprep_slave_fifo(pch);
  1707. if (slave_config->direction == DMA_MEM_TO_DEV) {
  1708. if (slave_config->dst_addr)
  1709. pch->fifo_addr = slave_config->dst_addr;
  1710. if (slave_config->dst_addr_width)
  1711. pch->burst_sz = __ffs(slave_config->dst_addr_width);
  1712. if (slave_config->dst_maxburst)
  1713. pch->burst_len = slave_config->dst_maxburst;
  1714. } else if (slave_config->direction == DMA_DEV_TO_MEM) {
  1715. if (slave_config->src_addr)
  1716. pch->fifo_addr = slave_config->src_addr;
  1717. if (slave_config->src_addr_width)
  1718. pch->burst_sz = __ffs(slave_config->src_addr_width);
  1719. if (slave_config->src_maxburst)
  1720. pch->burst_len = slave_config->src_maxburst;
  1721. }
  1722. return 0;
  1723. }
  1724. static int pl330_terminate_all(struct dma_chan *chan)
  1725. {
  1726. struct dma_pl330_chan *pch = to_pchan(chan);
  1727. struct dma_pl330_desc *desc;
  1728. unsigned long flags;
  1729. struct pl330_dmac *pl330 = pch->dmac;
  1730. LIST_HEAD(list);
  1731. bool power_down = false;
  1732. pm_runtime_get_sync(pl330->ddma.dev);
  1733. spin_lock_irqsave(&pch->lock, flags);
  1734. spin_lock(&pl330->lock);
  1735. _stop(pch->thread);
  1736. spin_unlock(&pl330->lock);
  1737. pch->thread->req[0].desc = NULL;
  1738. pch->thread->req[1].desc = NULL;
  1739. pch->thread->req_running = -1;
  1740. power_down = pch->active;
  1741. pch->active = false;
  1742. /* Mark all desc done */
  1743. list_for_each_entry(desc, &pch->submitted_list, node) {
  1744. desc->status = FREE;
  1745. dma_cookie_complete(&desc->txd);
  1746. }
  1747. list_for_each_entry(desc, &pch->work_list , node) {
  1748. desc->status = FREE;
  1749. dma_cookie_complete(&desc->txd);
  1750. }
  1751. list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
  1752. list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
  1753. list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
  1754. spin_unlock_irqrestore(&pch->lock, flags);
  1755. pm_runtime_mark_last_busy(pl330->ddma.dev);
  1756. if (power_down)
  1757. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1758. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1759. return 0;
  1760. }
  1761. /*
  1762. * We don't support DMA_RESUME command because of hardware
  1763. * limitations, so after pausing the channel we cannot restore
  1764. * it to active state. We have to terminate channel and setup
  1765. * DMA transfer again. This pause feature was implemented to
  1766. * allow safely read residue before channel termination.
  1767. */
  1768. static int pl330_pause(struct dma_chan *chan)
  1769. {
  1770. struct dma_pl330_chan *pch = to_pchan(chan);
  1771. struct pl330_dmac *pl330 = pch->dmac;
  1772. unsigned long flags;
  1773. pm_runtime_get_sync(pl330->ddma.dev);
  1774. spin_lock_irqsave(&pch->lock, flags);
  1775. spin_lock(&pl330->lock);
  1776. _stop(pch->thread);
  1777. spin_unlock(&pl330->lock);
  1778. spin_unlock_irqrestore(&pch->lock, flags);
  1779. pm_runtime_mark_last_busy(pl330->ddma.dev);
  1780. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1781. return 0;
  1782. }
  1783. static void pl330_free_chan_resources(struct dma_chan *chan)
  1784. {
  1785. struct dma_pl330_chan *pch = to_pchan(chan);
  1786. struct pl330_dmac *pl330 = pch->dmac;
  1787. unsigned long flags;
  1788. tasklet_kill(&pch->task);
  1789. pm_runtime_get_sync(pch->dmac->ddma.dev);
  1790. spin_lock_irqsave(&pl330->lock, flags);
  1791. pl330_release_channel(pch->thread);
  1792. pch->thread = NULL;
  1793. if (pch->cyclic)
  1794. list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
  1795. spin_unlock_irqrestore(&pl330->lock, flags);
  1796. pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
  1797. pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
  1798. pl330_unprep_slave_fifo(pch);
  1799. }
  1800. static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
  1801. struct dma_pl330_desc *desc)
  1802. {
  1803. struct pl330_thread *thrd = pch->thread;
  1804. struct pl330_dmac *pl330 = pch->dmac;
  1805. void __iomem *regs = thrd->dmac->base;
  1806. u32 val, addr;
  1807. pm_runtime_get_sync(pl330->ddma.dev);
  1808. val = addr = 0;
  1809. if (desc->rqcfg.src_inc) {
  1810. val = readl(regs + SA(thrd->id));
  1811. addr = desc->px.src_addr;
  1812. } else {
  1813. val = readl(regs + DA(thrd->id));
  1814. addr = desc->px.dst_addr;
  1815. }
  1816. pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
  1817. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1818. /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
  1819. if (!val)
  1820. return 0;
  1821. return val - addr;
  1822. }
  1823. static enum dma_status
  1824. pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
  1825. struct dma_tx_state *txstate)
  1826. {
  1827. enum dma_status ret;
  1828. unsigned long flags;
  1829. struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
  1830. struct dma_pl330_chan *pch = to_pchan(chan);
  1831. unsigned int transferred, residual = 0;
  1832. ret = dma_cookie_status(chan, cookie, txstate);
  1833. if (!txstate)
  1834. return ret;
  1835. if (ret == DMA_COMPLETE)
  1836. goto out;
  1837. spin_lock_irqsave(&pch->lock, flags);
  1838. spin_lock(&pch->thread->dmac->lock);
  1839. if (pch->thread->req_running != -1)
  1840. running = pch->thread->req[pch->thread->req_running].desc;
  1841. last_enq = pch->thread->req[pch->thread->lstenq].desc;
  1842. /* Check in pending list */
  1843. list_for_each_entry(desc, &pch->work_list, node) {
  1844. if (desc->status == DONE)
  1845. transferred = desc->bytes_requested;
  1846. else if (running && desc == running)
  1847. transferred =
  1848. pl330_get_current_xferred_count(pch, desc);
  1849. else if (desc->status == BUSY)
  1850. /*
  1851. * Busy but not running means either just enqueued,
  1852. * or finished and not yet marked done
  1853. */
  1854. if (desc == last_enq)
  1855. transferred = 0;
  1856. else
  1857. transferred = desc->bytes_requested;
  1858. else
  1859. transferred = 0;
  1860. residual += desc->bytes_requested - transferred;
  1861. if (desc->txd.cookie == cookie) {
  1862. switch (desc->status) {
  1863. case DONE:
  1864. ret = DMA_COMPLETE;
  1865. break;
  1866. case PREP:
  1867. case BUSY:
  1868. ret = DMA_IN_PROGRESS;
  1869. break;
  1870. default:
  1871. WARN_ON(1);
  1872. }
  1873. break;
  1874. }
  1875. if (desc->last)
  1876. residual = 0;
  1877. }
  1878. spin_unlock(&pch->thread->dmac->lock);
  1879. spin_unlock_irqrestore(&pch->lock, flags);
  1880. out:
  1881. dma_set_residue(txstate, residual);
  1882. return ret;
  1883. }
  1884. static void pl330_issue_pending(struct dma_chan *chan)
  1885. {
  1886. struct dma_pl330_chan *pch = to_pchan(chan);
  1887. unsigned long flags;
  1888. spin_lock_irqsave(&pch->lock, flags);
  1889. if (list_empty(&pch->work_list)) {
  1890. /*
  1891. * Warn on nothing pending. Empty submitted_list may
  1892. * break our pm_runtime usage counter as it is
  1893. * updated on work_list emptiness status.
  1894. */
  1895. WARN_ON(list_empty(&pch->submitted_list));
  1896. pch->active = true;
  1897. pm_runtime_get_sync(pch->dmac->ddma.dev);
  1898. }
  1899. list_splice_tail_init(&pch->submitted_list, &pch->work_list);
  1900. spin_unlock_irqrestore(&pch->lock, flags);
  1901. pl330_tasklet((unsigned long)pch);
  1902. }
  1903. /*
  1904. * We returned the last one of the circular list of descriptor(s)
  1905. * from prep_xxx, so the argument to submit corresponds to the last
  1906. * descriptor of the list.
  1907. */
  1908. static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
  1909. {
  1910. struct dma_pl330_desc *desc, *last = to_desc(tx);
  1911. struct dma_pl330_chan *pch = to_pchan(tx->chan);
  1912. dma_cookie_t cookie;
  1913. unsigned long flags;
  1914. spin_lock_irqsave(&pch->lock, flags);
  1915. /* Assign cookies to all nodes */
  1916. while (!list_empty(&last->node)) {
  1917. desc = list_entry(last->node.next, struct dma_pl330_desc, node);
  1918. if (pch->cyclic) {
  1919. desc->txd.callback = last->txd.callback;
  1920. desc->txd.callback_param = last->txd.callback_param;
  1921. }
  1922. desc->last = false;
  1923. dma_cookie_assign(&desc->txd);
  1924. list_move_tail(&desc->node, &pch->submitted_list);
  1925. }
  1926. last->last = true;
  1927. cookie = dma_cookie_assign(&last->txd);
  1928. list_add_tail(&last->node, &pch->submitted_list);
  1929. spin_unlock_irqrestore(&pch->lock, flags);
  1930. return cookie;
  1931. }
  1932. static inline void _init_desc(struct dma_pl330_desc *desc)
  1933. {
  1934. desc->rqcfg.swap = SWAP_NO;
  1935. desc->rqcfg.scctl = CCTRL0;
  1936. desc->rqcfg.dcctl = CCTRL0;
  1937. desc->txd.tx_submit = pl330_tx_submit;
  1938. INIT_LIST_HEAD(&desc->node);
  1939. }
  1940. /* Returns the number of descriptors added to the DMAC pool */
  1941. static int add_desc(struct list_head *pool, spinlock_t *lock,
  1942. gfp_t flg, int count)
  1943. {
  1944. struct dma_pl330_desc *desc;
  1945. unsigned long flags;
  1946. int i;
  1947. desc = kcalloc(count, sizeof(*desc), flg);
  1948. if (!desc)
  1949. return 0;
  1950. spin_lock_irqsave(lock, flags);
  1951. for (i = 0; i < count; i++) {
  1952. _init_desc(&desc[i]);
  1953. list_add_tail(&desc[i].node, pool);
  1954. }
  1955. spin_unlock_irqrestore(lock, flags);
  1956. return count;
  1957. }
  1958. static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
  1959. spinlock_t *lock)
  1960. {
  1961. struct dma_pl330_desc *desc = NULL;
  1962. unsigned long flags;
  1963. spin_lock_irqsave(lock, flags);
  1964. if (!list_empty(pool)) {
  1965. desc = list_entry(pool->next,
  1966. struct dma_pl330_desc, node);
  1967. list_del_init(&desc->node);
  1968. desc->status = PREP;
  1969. desc->txd.callback = NULL;
  1970. }
  1971. spin_unlock_irqrestore(lock, flags);
  1972. return desc;
  1973. }
  1974. static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
  1975. {
  1976. struct pl330_dmac *pl330 = pch->dmac;
  1977. u8 *peri_id = pch->chan.private;
  1978. struct dma_pl330_desc *desc;
  1979. /* Pluck one desc from the pool of DMAC */
  1980. desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
  1981. /* If the DMAC pool is empty, alloc new */
  1982. if (!desc) {
  1983. DEFINE_SPINLOCK(lock);
  1984. LIST_HEAD(pool);
  1985. if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
  1986. return NULL;
  1987. desc = pluck_desc(&pool, &lock);
  1988. WARN_ON(!desc || !list_empty(&pool));
  1989. }
  1990. /* Initialize the descriptor */
  1991. desc->pchan = pch;
  1992. desc->txd.cookie = 0;
  1993. async_tx_ack(&desc->txd);
  1994. desc->peri = peri_id ? pch->chan.chan_id : 0;
  1995. desc->rqcfg.pcfg = &pch->dmac->pcfg;
  1996. dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
  1997. return desc;
  1998. }
  1999. static inline void fill_px(struct pl330_xfer *px,
  2000. dma_addr_t dst, dma_addr_t src, size_t len)
  2001. {
  2002. px->bytes = len;
  2003. px->dst_addr = dst;
  2004. px->src_addr = src;
  2005. }
  2006. static struct dma_pl330_desc *
  2007. __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
  2008. dma_addr_t src, size_t len)
  2009. {
  2010. struct dma_pl330_desc *desc = pl330_get_desc(pch);
  2011. if (!desc) {
  2012. dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
  2013. __func__, __LINE__);
  2014. return NULL;
  2015. }
  2016. /*
  2017. * Ideally we should lookout for reqs bigger than
  2018. * those that can be programmed with 256 bytes of
  2019. * MC buffer, but considering a req size is seldom
  2020. * going to be word-unaligned and more than 200MB,
  2021. * we take it easy.
  2022. * Also, should the limit is reached we'd rather
  2023. * have the platform increase MC buffer size than
  2024. * complicating this API driver.
  2025. */
  2026. fill_px(&desc->px, dst, src, len);
  2027. return desc;
  2028. }
  2029. /* Call after fixing burst size */
  2030. static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
  2031. {
  2032. struct dma_pl330_chan *pch = desc->pchan;
  2033. struct pl330_dmac *pl330 = pch->dmac;
  2034. int burst_len;
  2035. burst_len = pl330->pcfg.data_bus_width / 8;
  2036. burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
  2037. burst_len >>= desc->rqcfg.brst_size;
  2038. /* src/dst_burst_len can't be more than 16 */
  2039. if (burst_len > 16)
  2040. burst_len = 16;
  2041. while (burst_len > 1) {
  2042. if (!(len % (burst_len << desc->rqcfg.brst_size)))
  2043. break;
  2044. burst_len--;
  2045. }
  2046. return burst_len;
  2047. }
  2048. static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
  2049. struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
  2050. size_t period_len, enum dma_transfer_direction direction,
  2051. unsigned long flags)
  2052. {
  2053. struct dma_pl330_desc *desc = NULL, *first = NULL;
  2054. struct dma_pl330_chan *pch = to_pchan(chan);
  2055. struct pl330_dmac *pl330 = pch->dmac;
  2056. unsigned int i;
  2057. dma_addr_t dst;
  2058. dma_addr_t src;
  2059. if (len % period_len != 0)
  2060. return NULL;
  2061. if (!is_slave_direction(direction)) {
  2062. dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
  2063. __func__, __LINE__);
  2064. return NULL;
  2065. }
  2066. if (!pl330_prep_slave_fifo(pch, direction))
  2067. return NULL;
  2068. for (i = 0; i < len / period_len; i++) {
  2069. desc = pl330_get_desc(pch);
  2070. if (!desc) {
  2071. dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
  2072. __func__, __LINE__);
  2073. if (!first)
  2074. return NULL;
  2075. spin_lock_irqsave(&pl330->pool_lock, flags);
  2076. while (!list_empty(&first->node)) {
  2077. desc = list_entry(first->node.next,
  2078. struct dma_pl330_desc, node);
  2079. list_move_tail(&desc->node, &pl330->desc_pool);
  2080. }
  2081. list_move_tail(&first->node, &pl330->desc_pool);
  2082. spin_unlock_irqrestore(&pl330->pool_lock, flags);
  2083. return NULL;
  2084. }
  2085. switch (direction) {
  2086. case DMA_MEM_TO_DEV:
  2087. desc->rqcfg.src_inc = 1;
  2088. desc->rqcfg.dst_inc = 0;
  2089. src = dma_addr;
  2090. dst = pch->fifo_dma;
  2091. break;
  2092. case DMA_DEV_TO_MEM:
  2093. desc->rqcfg.src_inc = 0;
  2094. desc->rqcfg.dst_inc = 1;
  2095. src = pch->fifo_dma;
  2096. dst = dma_addr;
  2097. break;
  2098. default:
  2099. break;
  2100. }
  2101. desc->rqtype = direction;
  2102. desc->rqcfg.brst_size = pch->burst_sz;
  2103. desc->rqcfg.brst_len = 1;
  2104. desc->bytes_requested = period_len;
  2105. fill_px(&desc->px, dst, src, period_len);
  2106. if (!first)
  2107. first = desc;
  2108. else
  2109. list_add_tail(&desc->node, &first->node);
  2110. dma_addr += period_len;
  2111. }
  2112. if (!desc)
  2113. return NULL;
  2114. pch->cyclic = true;
  2115. desc->txd.flags = flags;
  2116. return &desc->txd;
  2117. }
  2118. static struct dma_async_tx_descriptor *
  2119. pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
  2120. dma_addr_t src, size_t len, unsigned long flags)
  2121. {
  2122. struct dma_pl330_desc *desc;
  2123. struct dma_pl330_chan *pch = to_pchan(chan);
  2124. struct pl330_dmac *pl330;
  2125. int burst;
  2126. if (unlikely(!pch || !len))
  2127. return NULL;
  2128. pl330 = pch->dmac;
  2129. desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
  2130. if (!desc)
  2131. return NULL;
  2132. desc->rqcfg.src_inc = 1;
  2133. desc->rqcfg.dst_inc = 1;
  2134. desc->rqtype = DMA_MEM_TO_MEM;
  2135. /* Select max possible burst size */
  2136. burst = pl330->pcfg.data_bus_width / 8;
  2137. /*
  2138. * Make sure we use a burst size that aligns with all the memcpy
  2139. * parameters because our DMA programming algorithm doesn't cope with
  2140. * transfers which straddle an entry in the DMA device's MFIFO.
  2141. */
  2142. while ((src | dst | len) & (burst - 1))
  2143. burst /= 2;
  2144. desc->rqcfg.brst_size = 0;
  2145. while (burst != (1 << desc->rqcfg.brst_size))
  2146. desc->rqcfg.brst_size++;
  2147. /*
  2148. * If burst size is smaller than bus width then make sure we only
  2149. * transfer one at a time to avoid a burst stradling an MFIFO entry.
  2150. */
  2151. if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
  2152. desc->rqcfg.brst_len = 1;
  2153. desc->rqcfg.brst_len = get_burst_len(desc, len);
  2154. desc->bytes_requested = len;
  2155. desc->txd.flags = flags;
  2156. return &desc->txd;
  2157. }
  2158. static void __pl330_giveback_desc(struct pl330_dmac *pl330,
  2159. struct dma_pl330_desc *first)
  2160. {
  2161. unsigned long flags;
  2162. struct dma_pl330_desc *desc;
  2163. if (!first)
  2164. return;
  2165. spin_lock_irqsave(&pl330->pool_lock, flags);
  2166. while (!list_empty(&first->node)) {
  2167. desc = list_entry(first->node.next,
  2168. struct dma_pl330_desc, node);
  2169. list_move_tail(&desc->node, &pl330->desc_pool);
  2170. }
  2171. list_move_tail(&first->node, &pl330->desc_pool);
  2172. spin_unlock_irqrestore(&pl330->pool_lock, flags);
  2173. }
  2174. static struct dma_async_tx_descriptor *
  2175. pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  2176. unsigned int sg_len, enum dma_transfer_direction direction,
  2177. unsigned long flg, void *context)
  2178. {
  2179. struct dma_pl330_desc *first, *desc = NULL;
  2180. struct dma_pl330_chan *pch = to_pchan(chan);
  2181. struct scatterlist *sg;
  2182. int i;
  2183. if (unlikely(!pch || !sgl || !sg_len))
  2184. return NULL;
  2185. if (!pl330_prep_slave_fifo(pch, direction))
  2186. return NULL;
  2187. first = NULL;
  2188. for_each_sg(sgl, sg, sg_len, i) {
  2189. desc = pl330_get_desc(pch);
  2190. if (!desc) {
  2191. struct pl330_dmac *pl330 = pch->dmac;
  2192. dev_err(pch->dmac->ddma.dev,
  2193. "%s:%d Unable to fetch desc\n",
  2194. __func__, __LINE__);
  2195. __pl330_giveback_desc(pl330, first);
  2196. return NULL;
  2197. }
  2198. if (!first)
  2199. first = desc;
  2200. else
  2201. list_add_tail(&desc->node, &first->node);
  2202. if (direction == DMA_MEM_TO_DEV) {
  2203. desc->rqcfg.src_inc = 1;
  2204. desc->rqcfg.dst_inc = 0;
  2205. fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
  2206. sg_dma_len(sg));
  2207. } else {
  2208. desc->rqcfg.src_inc = 0;
  2209. desc->rqcfg.dst_inc = 1;
  2210. fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
  2211. sg_dma_len(sg));
  2212. }
  2213. desc->rqcfg.brst_size = pch->burst_sz;
  2214. desc->rqcfg.brst_len = 1;
  2215. desc->rqtype = direction;
  2216. desc->bytes_requested = sg_dma_len(sg);
  2217. }
  2218. /* Return the last desc in the chain */
  2219. desc->txd.flags = flg;
  2220. return &desc->txd;
  2221. }
  2222. static irqreturn_t pl330_irq_handler(int irq, void *data)
  2223. {
  2224. if (pl330_update(data))
  2225. return IRQ_HANDLED;
  2226. else
  2227. return IRQ_NONE;
  2228. }
  2229. #define PL330_DMA_BUSWIDTHS \
  2230. BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  2231. BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  2232. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  2233. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  2234. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
  2235. /*
  2236. * Runtime PM callbacks are provided by amba/bus.c driver.
  2237. *
  2238. * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
  2239. * bus driver will only disable/enable the clock in runtime PM callbacks.
  2240. */
  2241. static int __maybe_unused pl330_suspend(struct device *dev)
  2242. {
  2243. struct amba_device *pcdev = to_amba_device(dev);
  2244. pm_runtime_disable(dev);
  2245. if (!pm_runtime_status_suspended(dev)) {
  2246. /* amba did not disable the clock */
  2247. amba_pclk_disable(pcdev);
  2248. }
  2249. amba_pclk_unprepare(pcdev);
  2250. return 0;
  2251. }
  2252. static int __maybe_unused pl330_resume(struct device *dev)
  2253. {
  2254. struct amba_device *pcdev = to_amba_device(dev);
  2255. int ret;
  2256. ret = amba_pclk_prepare(pcdev);
  2257. if (ret)
  2258. return ret;
  2259. if (!pm_runtime_status_suspended(dev))
  2260. ret = amba_pclk_enable(pcdev);
  2261. pm_runtime_enable(dev);
  2262. return ret;
  2263. }
  2264. static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
  2265. static int
  2266. pl330_probe(struct amba_device *adev, const struct amba_id *id)
  2267. {
  2268. struct pl330_config *pcfg;
  2269. struct pl330_dmac *pl330;
  2270. struct dma_pl330_chan *pch, *_p;
  2271. struct dma_device *pd;
  2272. struct resource *res;
  2273. int i, ret, irq;
  2274. int num_chan;
  2275. struct device_node *np = adev->dev.of_node;
  2276. ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
  2277. if (ret)
  2278. return ret;
  2279. /* Allocate a new DMAC and its Channels */
  2280. pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
  2281. if (!pl330)
  2282. return -ENOMEM;
  2283. pd = &pl330->ddma;
  2284. pd->dev = &adev->dev;
  2285. pl330->mcbufsz = 0;
  2286. /* get quirk */
  2287. for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
  2288. if (of_property_read_bool(np, of_quirks[i].quirk))
  2289. pl330->quirks |= of_quirks[i].id;
  2290. res = &adev->res;
  2291. pl330->base = devm_ioremap_resource(&adev->dev, res);
  2292. if (IS_ERR(pl330->base))
  2293. return PTR_ERR(pl330->base);
  2294. amba_set_drvdata(adev, pl330);
  2295. for (i = 0; i < AMBA_NR_IRQS; i++) {
  2296. irq = adev->irq[i];
  2297. if (irq) {
  2298. ret = devm_request_irq(&adev->dev, irq,
  2299. pl330_irq_handler, 0,
  2300. dev_name(&adev->dev), pl330);
  2301. if (ret)
  2302. return ret;
  2303. } else {
  2304. break;
  2305. }
  2306. }
  2307. pcfg = &pl330->pcfg;
  2308. pcfg->periph_id = adev->periphid;
  2309. ret = pl330_add(pl330);
  2310. if (ret)
  2311. return ret;
  2312. INIT_LIST_HEAD(&pl330->desc_pool);
  2313. spin_lock_init(&pl330->pool_lock);
  2314. /* Create a descriptor pool of default size */
  2315. if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
  2316. GFP_KERNEL, NR_DEFAULT_DESC))
  2317. dev_warn(&adev->dev, "unable to allocate desc\n");
  2318. INIT_LIST_HEAD(&pd->channels);
  2319. /* Initialize channel parameters */
  2320. num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
  2321. pl330->num_peripherals = num_chan;
  2322. pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
  2323. if (!pl330->peripherals) {
  2324. ret = -ENOMEM;
  2325. goto probe_err2;
  2326. }
  2327. for (i = 0; i < num_chan; i++) {
  2328. pch = &pl330->peripherals[i];
  2329. pch->chan.private = adev->dev.of_node;
  2330. INIT_LIST_HEAD(&pch->submitted_list);
  2331. INIT_LIST_HEAD(&pch->work_list);
  2332. INIT_LIST_HEAD(&pch->completed_list);
  2333. spin_lock_init(&pch->lock);
  2334. pch->thread = NULL;
  2335. pch->chan.device = pd;
  2336. pch->dmac = pl330;
  2337. pch->dir = DMA_NONE;
  2338. /* Add the channel to the DMAC list */
  2339. list_add_tail(&pch->chan.device_node, &pd->channels);
  2340. }
  2341. dma_cap_set(DMA_MEMCPY, pd->cap_mask);
  2342. if (pcfg->num_peri) {
  2343. dma_cap_set(DMA_SLAVE, pd->cap_mask);
  2344. dma_cap_set(DMA_CYCLIC, pd->cap_mask);
  2345. dma_cap_set(DMA_PRIVATE, pd->cap_mask);
  2346. }
  2347. pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
  2348. pd->device_free_chan_resources = pl330_free_chan_resources;
  2349. pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
  2350. pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
  2351. pd->device_tx_status = pl330_tx_status;
  2352. pd->device_prep_slave_sg = pl330_prep_slave_sg;
  2353. pd->device_config = pl330_config;
  2354. pd->device_pause = pl330_pause;
  2355. pd->device_terminate_all = pl330_terminate_all;
  2356. pd->device_issue_pending = pl330_issue_pending;
  2357. pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
  2358. pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
  2359. pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  2360. pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
  2361. pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
  2362. 1 : PL330_MAX_BURST);
  2363. ret = dma_async_device_register(pd);
  2364. if (ret) {
  2365. dev_err(&adev->dev, "unable to register DMAC\n");
  2366. goto probe_err3;
  2367. }
  2368. if (adev->dev.of_node) {
  2369. ret = of_dma_controller_register(adev->dev.of_node,
  2370. of_dma_pl330_xlate, pl330);
  2371. if (ret) {
  2372. dev_err(&adev->dev,
  2373. "unable to register DMA to the generic DT DMA helpers\n");
  2374. }
  2375. }
  2376. adev->dev.dma_parms = &pl330->dma_parms;
  2377. /*
  2378. * This is the limit for transfers with a buswidth of 1, larger
  2379. * buswidths will have larger limits.
  2380. */
  2381. ret = dma_set_max_seg_size(&adev->dev, 1900800);
  2382. if (ret)
  2383. dev_err(&adev->dev, "unable to set the seg size\n");
  2384. dev_info(&adev->dev,
  2385. "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
  2386. dev_info(&adev->dev,
  2387. "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
  2388. pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
  2389. pcfg->num_peri, pcfg->num_events);
  2390. pm_runtime_irq_safe(&adev->dev);
  2391. pm_runtime_use_autosuspend(&adev->dev);
  2392. pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
  2393. pm_runtime_mark_last_busy(&adev->dev);
  2394. pm_runtime_put_autosuspend(&adev->dev);
  2395. return 0;
  2396. probe_err3:
  2397. /* Idle the DMAC */
  2398. list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
  2399. chan.device_node) {
  2400. /* Remove the channel */
  2401. list_del(&pch->chan.device_node);
  2402. /* Flush the channel */
  2403. if (pch->thread) {
  2404. pl330_terminate_all(&pch->chan);
  2405. pl330_free_chan_resources(&pch->chan);
  2406. }
  2407. }
  2408. probe_err2:
  2409. pl330_del(pl330);
  2410. return ret;
  2411. }
  2412. static int pl330_remove(struct amba_device *adev)
  2413. {
  2414. struct pl330_dmac *pl330 = amba_get_drvdata(adev);
  2415. struct dma_pl330_chan *pch, *_p;
  2416. int i, irq;
  2417. pm_runtime_get_noresume(pl330->ddma.dev);
  2418. if (adev->dev.of_node)
  2419. of_dma_controller_free(adev->dev.of_node);
  2420. for (i = 0; i < AMBA_NR_IRQS; i++) {
  2421. irq = adev->irq[i];
  2422. if (irq)
  2423. devm_free_irq(&adev->dev, irq, pl330);
  2424. }
  2425. dma_async_device_unregister(&pl330->ddma);
  2426. /* Idle the DMAC */
  2427. list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
  2428. chan.device_node) {
  2429. /* Remove the channel */
  2430. list_del(&pch->chan.device_node);
  2431. /* Flush the channel */
  2432. if (pch->thread) {
  2433. pl330_terminate_all(&pch->chan);
  2434. pl330_free_chan_resources(&pch->chan);
  2435. }
  2436. }
  2437. pl330_del(pl330);
  2438. return 0;
  2439. }
  2440. static const struct amba_id pl330_ids[] = {
  2441. {
  2442. .id = 0x00041330,
  2443. .mask = 0x000fffff,
  2444. },
  2445. { 0, 0 },
  2446. };
  2447. MODULE_DEVICE_TABLE(amba, pl330_ids);
  2448. static struct amba_driver pl330_driver = {
  2449. .drv = {
  2450. .owner = THIS_MODULE,
  2451. .name = "dma-pl330",
  2452. .pm = &pl330_pm,
  2453. },
  2454. .id_table = pl330_ids,
  2455. .probe = pl330_probe,
  2456. .remove = pl330_remove,
  2457. };
  2458. module_amba_driver(pl330_driver);
  2459. MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
  2460. MODULE_DESCRIPTION("API Driver for PL330 DMAC");
  2461. MODULE_LICENSE("GPL");