clk-uniphier-sys.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280
  1. /*
  2. * Copyright (C) 2016 Socionext Inc.
  3. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/stddef.h>
  16. #include "clk-uniphier.h"
  17. #define UNIPHIER_LD4_SYS_CLK_SD \
  18. UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
  19. UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
  20. #define UNIPHIER_PRO5_SYS_CLK_SD \
  21. UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
  22. UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
  23. #define UNIPHIER_LD20_SYS_CLK_SD \
  24. UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
  25. UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
  26. /* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
  27. #define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
  28. UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \
  29. UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
  30. #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
  31. UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \
  32. UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
  33. #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
  34. UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \
  35. UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0)
  36. #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
  37. UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
  38. #define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
  39. UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
  40. #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
  41. UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
  42. #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
  43. UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
  44. #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
  45. UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
  46. #define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \
  47. UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
  48. UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
  49. #define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \
  50. UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
  51. UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
  52. #define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
  53. UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
  54. UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
  55. #define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
  56. UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
  57. UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
  58. #define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
  59. UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
  60. UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
  61. #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \
  62. UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
  63. #define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \
  64. UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
  65. const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
  66. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
  67. UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
  68. UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
  69. UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
  70. UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
  71. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  72. UNIPHIER_LD4_SYS_CLK_NAND(2),
  73. UNIPHIER_LD4_SYS_CLK_SD,
  74. UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  75. UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
  76. { /* sentinel */ }
  77. };
  78. const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
  79. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
  80. UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
  81. UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
  82. UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
  83. UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
  84. UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
  85. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
  86. UNIPHIER_LD4_SYS_CLK_NAND(2),
  87. UNIPHIER_LD4_SYS_CLK_SD,
  88. UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  89. UNIPHIER_PRO4_SYS_CLK_ETHER(6),
  90. UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
  91. UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
  92. UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
  93. UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
  94. UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
  95. UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
  96. UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
  97. UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
  98. UNIPHIER_PRO4_SYS_CLK_AIO(40),
  99. { /* sentinel */ }
  100. };
  101. const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
  102. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
  103. UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
  104. UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
  105. UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
  106. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  107. UNIPHIER_LD4_SYS_CLK_NAND(2),
  108. UNIPHIER_LD4_SYS_CLK_SD,
  109. UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  110. UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
  111. { /* sentinel */ }
  112. };
  113. const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
  114. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
  115. UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
  116. UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
  117. UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
  118. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
  119. UNIPHIER_PRO5_SYS_CLK_NAND(2),
  120. UNIPHIER_PRO5_SYS_CLK_SD,
  121. UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
  122. UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
  123. UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
  124. UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
  125. UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
  126. UNIPHIER_PRO5_SYS_CLK_AIO(40),
  127. { /* sentinel */ }
  128. };
  129. const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
  130. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
  131. UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
  132. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
  133. UNIPHIER_PRO5_SYS_CLK_NAND(2),
  134. UNIPHIER_PRO5_SYS_CLK_SD,
  135. UNIPHIER_PRO4_SYS_CLK_ETHER(6),
  136. UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
  137. /* GIO is always clock-enabled: no function for 0x2104 bit6 */
  138. UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
  139. UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
  140. /* The document mentions 0x2104 bit 18, but not functional */
  141. UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
  142. UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
  143. UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
  144. UNIPHIER_PRO5_SYS_CLK_AIO(40),
  145. { /* sentinel */ }
  146. };
  147. const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
  148. UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */
  149. UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
  150. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
  151. UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
  152. UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
  153. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
  154. UNIPHIER_LD11_SYS_CLK_NAND(2),
  155. UNIPHIER_LD11_SYS_CLK_EMMC(4),
  156. /* Index 5 reserved for eMMC PHY */
  157. UNIPHIER_LD11_SYS_CLK_ETHER(6),
  158. UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
  159. UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
  160. UNIPHIER_LD11_SYS_CLK_AIO(40),
  161. UNIPHIER_LD11_SYS_CLK_EVEA(41),
  162. UNIPHIER_LD11_SYS_CLK_EXIV(42),
  163. /* CPU gears */
  164. UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
  165. UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
  166. UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
  167. /* Note: both gear1 and gear4 are spll/4. This is not a bug. */
  168. UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
  169. "cpll/2", "spll/4", "cpll/3", "spll/3",
  170. "spll/4", "spll/8", "cpll/4", "cpll/8"),
  171. UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
  172. "mpll/2", "spll/4", "mpll/3", "spll/3",
  173. "spll/4", "spll/8", "mpll/4", "mpll/8"),
  174. { /* sentinel */ }
  175. };
  176. const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
  177. UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */
  178. UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */
  179. UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
  180. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
  181. UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */
  182. UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
  183. UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
  184. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
  185. UNIPHIER_LD11_SYS_CLK_NAND(2),
  186. UNIPHIER_LD11_SYS_CLK_EMMC(4),
  187. /* Index 5 reserved for eMMC PHY */
  188. UNIPHIER_LD20_SYS_CLK_SD,
  189. UNIPHIER_LD11_SYS_CLK_ETHER(6),
  190. UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
  191. /* GIO is always clock-enabled: no function for 0x210c bit5 */
  192. /*
  193. * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
  194. * We do not use bit 15 here.
  195. */
  196. UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
  197. UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
  198. UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
  199. UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
  200. UNIPHIER_LD11_SYS_CLK_AIO(40),
  201. UNIPHIER_LD11_SYS_CLK_EVEA(41),
  202. UNIPHIER_LD11_SYS_CLK_EXIV(42),
  203. /* CPU gears */
  204. UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
  205. UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
  206. UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
  207. UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
  208. "cpll/2", "spll/2", "cpll/3", "spll/3",
  209. "spll/4", "spll/8", "cpll/4", "cpll/8"),
  210. UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
  211. "cpll/2", "spll/2", "cpll/3", "spll/3",
  212. "spll/4", "spll/8", "cpll/4", "cpll/8"),
  213. UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
  214. "s2pll/2", "spll/2", "s2pll/3", "spll/3",
  215. "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
  216. { /* sentinel */ }
  217. };
  218. const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
  219. UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */
  220. UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
  221. UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
  222. UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
  223. UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
  224. UNIPHIER_LD20_SYS_CLK_SD,
  225. UNIPHIER_LD11_SYS_CLK_NAND(2),
  226. UNIPHIER_LD11_SYS_CLK_EMMC(4),
  227. UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
  228. UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
  229. UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
  230. UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
  231. UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
  232. UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
  233. UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
  234. UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
  235. UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
  236. UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
  237. UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
  238. UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
  239. UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
  240. UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
  241. /* CPU gears */
  242. UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
  243. UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
  244. UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
  245. UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
  246. "cpll/2", "spll/2", "cpll/3", "spll/3",
  247. "spll/4", "spll/8", "cpll/4", "cpll/8"),
  248. UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
  249. "s2pll/2", "spll/2", "s2pll/3", "spll/3",
  250. "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
  251. { /* sentinel */ }
  252. };