clk.c 17 KB

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  1. /*
  2. * Copyright (c) 2014 MundoReader S.L.
  3. * Author: Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
  6. * Author: Xing Zheng <zhengxing@rock-chips.com>
  7. *
  8. * based on
  9. *
  10. * samsung/clk.c
  11. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  12. * Copyright (c) 2013 Linaro Ltd.
  13. * Author: Thomas Abraham <thomas.ab@samsung.com>
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. */
  25. #include <linux/slab.h>
  26. #include <linux/clk.h>
  27. #include <linux/clk-provider.h>
  28. #include <linux/mfd/syscon.h>
  29. #include <linux/regmap.h>
  30. #include <linux/reboot.h>
  31. #include <linux/rational.h>
  32. #include "clk.h"
  33. /**
  34. * Register a clock branch.
  35. * Most clock branches have a form like
  36. *
  37. * src1 --|--\
  38. * |M |--[GATE]-[DIV]-
  39. * src2 --|--/
  40. *
  41. * sometimes without one of those components.
  42. */
  43. static struct clk *rockchip_clk_register_branch(const char *name,
  44. const char *const *parent_names, u8 num_parents,
  45. void __iomem *base,
  46. int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
  47. u8 div_shift, u8 div_width, u8 div_flags,
  48. struct clk_div_table *div_table, int gate_offset,
  49. u8 gate_shift, u8 gate_flags, unsigned long flags,
  50. spinlock_t *lock)
  51. {
  52. struct clk *clk;
  53. struct clk_mux *mux = NULL;
  54. struct clk_gate *gate = NULL;
  55. struct clk_divider *div = NULL;
  56. const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
  57. *gate_ops = NULL;
  58. int ret;
  59. if (num_parents > 1) {
  60. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  61. if (!mux)
  62. return ERR_PTR(-ENOMEM);
  63. mux->reg = base + muxdiv_offset;
  64. mux->shift = mux_shift;
  65. mux->mask = BIT(mux_width) - 1;
  66. mux->flags = mux_flags;
  67. mux->lock = lock;
  68. mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
  69. : &clk_mux_ops;
  70. }
  71. if (gate_offset >= 0) {
  72. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  73. if (!gate) {
  74. ret = -ENOMEM;
  75. goto err_gate;
  76. }
  77. gate->flags = gate_flags;
  78. gate->reg = base + gate_offset;
  79. gate->bit_idx = gate_shift;
  80. gate->lock = lock;
  81. gate_ops = &clk_gate_ops;
  82. }
  83. if (div_width > 0) {
  84. div = kzalloc(sizeof(*div), GFP_KERNEL);
  85. if (!div) {
  86. ret = -ENOMEM;
  87. goto err_div;
  88. }
  89. div->flags = div_flags;
  90. div->reg = base + muxdiv_offset;
  91. div->shift = div_shift;
  92. div->width = div_width;
  93. div->lock = lock;
  94. div->table = div_table;
  95. div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
  96. ? &clk_divider_ro_ops
  97. : &clk_divider_ops;
  98. }
  99. clk = clk_register_composite(NULL, name, parent_names, num_parents,
  100. mux ? &mux->hw : NULL, mux_ops,
  101. div ? &div->hw : NULL, div_ops,
  102. gate ? &gate->hw : NULL, gate_ops,
  103. flags);
  104. if (IS_ERR(clk)) {
  105. ret = PTR_ERR(clk);
  106. goto err_composite;
  107. }
  108. return clk;
  109. err_composite:
  110. kfree(div);
  111. err_div:
  112. kfree(gate);
  113. err_gate:
  114. kfree(mux);
  115. return ERR_PTR(ret);
  116. }
  117. struct rockchip_clk_frac {
  118. struct notifier_block clk_nb;
  119. struct clk_fractional_divider div;
  120. struct clk_gate gate;
  121. struct clk_mux mux;
  122. const struct clk_ops *mux_ops;
  123. int mux_frac_idx;
  124. bool rate_change_remuxed;
  125. int rate_change_idx;
  126. };
  127. #define to_rockchip_clk_frac_nb(nb) \
  128. container_of(nb, struct rockchip_clk_frac, clk_nb)
  129. static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
  130. unsigned long event, void *data)
  131. {
  132. struct clk_notifier_data *ndata = data;
  133. struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
  134. struct clk_mux *frac_mux = &frac->mux;
  135. int ret = 0;
  136. pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
  137. __func__, event, ndata->old_rate, ndata->new_rate);
  138. if (event == PRE_RATE_CHANGE) {
  139. frac->rate_change_idx =
  140. frac->mux_ops->get_parent(&frac_mux->hw);
  141. if (frac->rate_change_idx != frac->mux_frac_idx) {
  142. frac->mux_ops->set_parent(&frac_mux->hw,
  143. frac->mux_frac_idx);
  144. frac->rate_change_remuxed = 1;
  145. }
  146. } else if (event == POST_RATE_CHANGE) {
  147. /*
  148. * The POST_RATE_CHANGE notifier runs directly after the
  149. * divider clock is set in clk_change_rate, so we'll have
  150. * remuxed back to the original parent before clk_change_rate
  151. * reaches the mux itself.
  152. */
  153. if (frac->rate_change_remuxed) {
  154. frac->mux_ops->set_parent(&frac_mux->hw,
  155. frac->rate_change_idx);
  156. frac->rate_change_remuxed = 0;
  157. }
  158. }
  159. return notifier_from_errno(ret);
  160. }
  161. /**
  162. * fractional divider must set that denominator is 20 times larger than
  163. * numerator to generate precise clock frequency.
  164. */
  165. static void rockchip_fractional_approximation(struct clk_hw *hw,
  166. unsigned long rate, unsigned long *parent_rate,
  167. unsigned long *m, unsigned long *n)
  168. {
  169. struct clk_fractional_divider *fd = to_clk_fd(hw);
  170. unsigned long p_rate, p_parent_rate;
  171. struct clk_hw *p_parent;
  172. unsigned long scale;
  173. p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
  174. if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
  175. p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
  176. p_parent_rate = clk_hw_get_rate(p_parent);
  177. *parent_rate = p_parent_rate;
  178. }
  179. /*
  180. * Get rate closer to *parent_rate to guarantee there is no overflow
  181. * for m and n. In the result it will be the nearest rate left shifted
  182. * by (scale - fd->nwidth) bits.
  183. */
  184. scale = fls_long(*parent_rate / rate - 1);
  185. if (scale > fd->nwidth)
  186. rate <<= scale - fd->nwidth;
  187. rational_best_approximation(rate, *parent_rate,
  188. GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
  189. m, n);
  190. }
  191. static struct clk *rockchip_clk_register_frac_branch(
  192. struct rockchip_clk_provider *ctx, const char *name,
  193. const char *const *parent_names, u8 num_parents,
  194. void __iomem *base, int muxdiv_offset, u8 div_flags,
  195. int gate_offset, u8 gate_shift, u8 gate_flags,
  196. unsigned long flags, struct rockchip_clk_branch *child,
  197. spinlock_t *lock)
  198. {
  199. struct rockchip_clk_frac *frac;
  200. struct clk *clk;
  201. struct clk_gate *gate = NULL;
  202. struct clk_fractional_divider *div = NULL;
  203. const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
  204. if (muxdiv_offset < 0)
  205. return ERR_PTR(-EINVAL);
  206. if (child && child->branch_type != branch_mux) {
  207. pr_err("%s: fractional child clock for %s can only be a mux\n",
  208. __func__, name);
  209. return ERR_PTR(-EINVAL);
  210. }
  211. frac = kzalloc(sizeof(*frac), GFP_KERNEL);
  212. if (!frac)
  213. return ERR_PTR(-ENOMEM);
  214. if (gate_offset >= 0) {
  215. gate = &frac->gate;
  216. gate->flags = gate_flags;
  217. gate->reg = base + gate_offset;
  218. gate->bit_idx = gate_shift;
  219. gate->lock = lock;
  220. gate_ops = &clk_gate_ops;
  221. }
  222. div = &frac->div;
  223. div->flags = div_flags;
  224. div->reg = base + muxdiv_offset;
  225. div->mshift = 16;
  226. div->mwidth = 16;
  227. div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
  228. div->nshift = 0;
  229. div->nwidth = 16;
  230. div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
  231. div->lock = lock;
  232. div->approximation = rockchip_fractional_approximation;
  233. div_ops = &clk_fractional_divider_ops;
  234. clk = clk_register_composite(NULL, name, parent_names, num_parents,
  235. NULL, NULL,
  236. &div->hw, div_ops,
  237. gate ? &gate->hw : NULL, gate_ops,
  238. flags | CLK_SET_RATE_UNGATE);
  239. if (IS_ERR(clk)) {
  240. kfree(frac);
  241. return clk;
  242. }
  243. if (child) {
  244. struct clk_mux *frac_mux = &frac->mux;
  245. struct clk_init_data init;
  246. struct clk *mux_clk;
  247. int i, ret;
  248. frac->mux_frac_idx = -1;
  249. for (i = 0; i < child->num_parents; i++) {
  250. if (!strcmp(name, child->parent_names[i])) {
  251. pr_debug("%s: found fractional parent in mux at pos %d\n",
  252. __func__, i);
  253. frac->mux_frac_idx = i;
  254. break;
  255. }
  256. }
  257. frac->mux_ops = &clk_mux_ops;
  258. frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
  259. frac_mux->reg = base + child->muxdiv_offset;
  260. frac_mux->shift = child->mux_shift;
  261. frac_mux->mask = BIT(child->mux_width) - 1;
  262. frac_mux->flags = child->mux_flags;
  263. frac_mux->lock = lock;
  264. frac_mux->hw.init = &init;
  265. init.name = child->name;
  266. init.flags = child->flags | CLK_SET_RATE_PARENT;
  267. init.ops = frac->mux_ops;
  268. init.parent_names = child->parent_names;
  269. init.num_parents = child->num_parents;
  270. mux_clk = clk_register(NULL, &frac_mux->hw);
  271. if (IS_ERR(mux_clk)) {
  272. kfree(frac);
  273. return clk;
  274. }
  275. rockchip_clk_add_lookup(ctx, mux_clk, child->id);
  276. /* notifier on the fraction divider to catch rate changes */
  277. if (frac->mux_frac_idx >= 0) {
  278. ret = clk_notifier_register(clk, &frac->clk_nb);
  279. if (ret)
  280. pr_err("%s: failed to register clock notifier for %s\n",
  281. __func__, name);
  282. } else {
  283. pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
  284. __func__, name, child->name);
  285. }
  286. }
  287. return clk;
  288. }
  289. static struct clk *rockchip_clk_register_factor_branch(const char *name,
  290. const char *const *parent_names, u8 num_parents,
  291. void __iomem *base, unsigned int mult, unsigned int div,
  292. int gate_offset, u8 gate_shift, u8 gate_flags,
  293. unsigned long flags, spinlock_t *lock)
  294. {
  295. struct clk *clk;
  296. struct clk_gate *gate = NULL;
  297. struct clk_fixed_factor *fix = NULL;
  298. /* without gate, register a simple factor clock */
  299. if (gate_offset == 0) {
  300. return clk_register_fixed_factor(NULL, name,
  301. parent_names[0], flags, mult,
  302. div);
  303. }
  304. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  305. if (!gate)
  306. return ERR_PTR(-ENOMEM);
  307. gate->flags = gate_flags;
  308. gate->reg = base + gate_offset;
  309. gate->bit_idx = gate_shift;
  310. gate->lock = lock;
  311. fix = kzalloc(sizeof(*fix), GFP_KERNEL);
  312. if (!fix) {
  313. kfree(gate);
  314. return ERR_PTR(-ENOMEM);
  315. }
  316. fix->mult = mult;
  317. fix->div = div;
  318. clk = clk_register_composite(NULL, name, parent_names, num_parents,
  319. NULL, NULL,
  320. &fix->hw, &clk_fixed_factor_ops,
  321. &gate->hw, &clk_gate_ops, flags);
  322. if (IS_ERR(clk)) {
  323. kfree(fix);
  324. kfree(gate);
  325. }
  326. return clk;
  327. }
  328. struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
  329. void __iomem *base, unsigned long nr_clks)
  330. {
  331. struct rockchip_clk_provider *ctx;
  332. struct clk **clk_table;
  333. int i;
  334. ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
  335. if (!ctx)
  336. return ERR_PTR(-ENOMEM);
  337. clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
  338. if (!clk_table)
  339. goto err_free;
  340. for (i = 0; i < nr_clks; ++i)
  341. clk_table[i] = ERR_PTR(-ENOENT);
  342. ctx->reg_base = base;
  343. ctx->clk_data.clks = clk_table;
  344. ctx->clk_data.clk_num = nr_clks;
  345. ctx->cru_node = np;
  346. spin_lock_init(&ctx->lock);
  347. ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
  348. "rockchip,grf");
  349. return ctx;
  350. err_free:
  351. kfree(ctx);
  352. return ERR_PTR(-ENOMEM);
  353. }
  354. void __init rockchip_clk_of_add_provider(struct device_node *np,
  355. struct rockchip_clk_provider *ctx)
  356. {
  357. if (of_clk_add_provider(np, of_clk_src_onecell_get,
  358. &ctx->clk_data))
  359. pr_err("%s: could not register clk provider\n", __func__);
  360. }
  361. void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
  362. struct clk *clk, unsigned int id)
  363. {
  364. if (ctx->clk_data.clks && id)
  365. ctx->clk_data.clks[id] = clk;
  366. }
  367. void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
  368. struct rockchip_pll_clock *list,
  369. unsigned int nr_pll, int grf_lock_offset)
  370. {
  371. struct clk *clk;
  372. int idx;
  373. for (idx = 0; idx < nr_pll; idx++, list++) {
  374. clk = rockchip_clk_register_pll(ctx, list->type, list->name,
  375. list->parent_names, list->num_parents,
  376. list->con_offset, grf_lock_offset,
  377. list->lock_shift, list->mode_offset,
  378. list->mode_shift, list->rate_table,
  379. list->flags, list->pll_flags);
  380. if (IS_ERR(clk)) {
  381. pr_err("%s: failed to register clock %s\n", __func__,
  382. list->name);
  383. continue;
  384. }
  385. rockchip_clk_add_lookup(ctx, clk, list->id);
  386. }
  387. }
  388. void __init rockchip_clk_register_branches(
  389. struct rockchip_clk_provider *ctx,
  390. struct rockchip_clk_branch *list,
  391. unsigned int nr_clk)
  392. {
  393. struct clk *clk = NULL;
  394. unsigned int idx;
  395. unsigned long flags;
  396. for (idx = 0; idx < nr_clk; idx++, list++) {
  397. flags = list->flags;
  398. /* catch simple muxes */
  399. switch (list->branch_type) {
  400. case branch_mux:
  401. clk = clk_register_mux(NULL, list->name,
  402. list->parent_names, list->num_parents,
  403. flags, ctx->reg_base + list->muxdiv_offset,
  404. list->mux_shift, list->mux_width,
  405. list->mux_flags, &ctx->lock);
  406. break;
  407. case branch_muxgrf:
  408. clk = rockchip_clk_register_muxgrf(list->name,
  409. list->parent_names, list->num_parents,
  410. flags, ctx->grf, list->muxdiv_offset,
  411. list->mux_shift, list->mux_width,
  412. list->mux_flags);
  413. break;
  414. case branch_divider:
  415. if (list->div_table)
  416. clk = clk_register_divider_table(NULL,
  417. list->name, list->parent_names[0],
  418. flags,
  419. ctx->reg_base + list->muxdiv_offset,
  420. list->div_shift, list->div_width,
  421. list->div_flags, list->div_table,
  422. &ctx->lock);
  423. else
  424. clk = clk_register_divider(NULL, list->name,
  425. list->parent_names[0], flags,
  426. ctx->reg_base + list->muxdiv_offset,
  427. list->div_shift, list->div_width,
  428. list->div_flags, &ctx->lock);
  429. break;
  430. case branch_fraction_divider:
  431. clk = rockchip_clk_register_frac_branch(ctx, list->name,
  432. list->parent_names, list->num_parents,
  433. ctx->reg_base, list->muxdiv_offset,
  434. list->div_flags,
  435. list->gate_offset, list->gate_shift,
  436. list->gate_flags, flags, list->child,
  437. &ctx->lock);
  438. break;
  439. case branch_gate:
  440. flags |= CLK_SET_RATE_PARENT;
  441. clk = clk_register_gate(NULL, list->name,
  442. list->parent_names[0], flags,
  443. ctx->reg_base + list->gate_offset,
  444. list->gate_shift, list->gate_flags, &ctx->lock);
  445. break;
  446. case branch_composite:
  447. clk = rockchip_clk_register_branch(list->name,
  448. list->parent_names, list->num_parents,
  449. ctx->reg_base, list->muxdiv_offset,
  450. list->mux_shift,
  451. list->mux_width, list->mux_flags,
  452. list->div_shift, list->div_width,
  453. list->div_flags, list->div_table,
  454. list->gate_offset, list->gate_shift,
  455. list->gate_flags, flags, &ctx->lock);
  456. break;
  457. case branch_mmc:
  458. clk = rockchip_clk_register_mmc(
  459. list->name,
  460. list->parent_names, list->num_parents,
  461. ctx->reg_base + list->muxdiv_offset,
  462. list->div_shift
  463. );
  464. break;
  465. case branch_inverter:
  466. clk = rockchip_clk_register_inverter(
  467. list->name, list->parent_names,
  468. list->num_parents,
  469. ctx->reg_base + list->muxdiv_offset,
  470. list->div_shift, list->div_flags, &ctx->lock);
  471. break;
  472. case branch_factor:
  473. clk = rockchip_clk_register_factor_branch(
  474. list->name, list->parent_names,
  475. list->num_parents, ctx->reg_base,
  476. list->div_shift, list->div_width,
  477. list->gate_offset, list->gate_shift,
  478. list->gate_flags, flags, &ctx->lock);
  479. break;
  480. case branch_ddrclk:
  481. clk = rockchip_clk_register_ddrclk(
  482. list->name, list->flags,
  483. list->parent_names, list->num_parents,
  484. list->muxdiv_offset, list->mux_shift,
  485. list->mux_width, list->div_shift,
  486. list->div_width, list->div_flags,
  487. ctx->reg_base, &ctx->lock);
  488. break;
  489. }
  490. /* none of the cases above matched */
  491. if (!clk) {
  492. pr_err("%s: unknown clock type %d\n",
  493. __func__, list->branch_type);
  494. continue;
  495. }
  496. if (IS_ERR(clk)) {
  497. pr_err("%s: failed to register clock %s: %ld\n",
  498. __func__, list->name, PTR_ERR(clk));
  499. continue;
  500. }
  501. rockchip_clk_add_lookup(ctx, clk, list->id);
  502. }
  503. }
  504. void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
  505. unsigned int lookup_id,
  506. const char *name, const char *const *parent_names,
  507. u8 num_parents,
  508. const struct rockchip_cpuclk_reg_data *reg_data,
  509. const struct rockchip_cpuclk_rate_table *rates,
  510. int nrates)
  511. {
  512. struct clk *clk;
  513. clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
  514. reg_data, rates, nrates,
  515. ctx->reg_base, &ctx->lock);
  516. if (IS_ERR(clk)) {
  517. pr_err("%s: failed to register clock %s: %ld\n",
  518. __func__, name, PTR_ERR(clk));
  519. return;
  520. }
  521. rockchip_clk_add_lookup(ctx, clk, lookup_id);
  522. }
  523. void __init rockchip_clk_protect_critical(const char *const clocks[],
  524. int nclocks)
  525. {
  526. int i;
  527. /* Protect the clocks that needs to stay on */
  528. for (i = 0; i < nclocks; i++) {
  529. struct clk *clk = __clk_lookup(clocks[i]);
  530. if (clk)
  531. clk_prepare_enable(clk);
  532. }
  533. }
  534. static void __iomem *rst_base;
  535. static unsigned int reg_restart;
  536. static void (*cb_restart)(void);
  537. static int rockchip_restart_notify(struct notifier_block *this,
  538. unsigned long mode, void *cmd)
  539. {
  540. if (cb_restart)
  541. cb_restart();
  542. writel(0xfdb9, rst_base + reg_restart);
  543. return NOTIFY_DONE;
  544. }
  545. static struct notifier_block rockchip_restart_handler = {
  546. .notifier_call = rockchip_restart_notify,
  547. .priority = 128,
  548. };
  549. void __init
  550. rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
  551. unsigned int reg,
  552. void (*cb)(void))
  553. {
  554. int ret;
  555. rst_base = ctx->reg_base;
  556. reg_restart = reg;
  557. cb_restart = cb;
  558. ret = register_restart_handler(&rockchip_restart_handler);
  559. if (ret)
  560. pr_err("%s: cannot register restart handler, %d\n",
  561. __func__, ret);
  562. }