fpga-mgr.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653
  1. /*
  2. * FPGA Manager Core
  3. *
  4. * Copyright (C) 2013-2015 Altera Corporation
  5. * Copyright (C) 2017 Intel Corporation
  6. *
  7. * With code from the mailing list:
  8. * Copyright (C) 2013 Xilinx, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms and conditions of the GNU General Public License,
  12. * version 2, as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #include <linux/firmware.h>
  23. #include <linux/fpga/fpga-mgr.h>
  24. #include <linux/idr.h>
  25. #include <linux/module.h>
  26. #include <linux/of.h>
  27. #include <linux/mutex.h>
  28. #include <linux/slab.h>
  29. #include <linux/scatterlist.h>
  30. #include <linux/highmem.h>
  31. static DEFINE_IDA(fpga_mgr_ida);
  32. static struct class *fpga_mgr_class;
  33. struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
  34. {
  35. struct fpga_image_info *info;
  36. get_device(dev);
  37. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  38. if (!info) {
  39. put_device(dev);
  40. return NULL;
  41. }
  42. info->dev = dev;
  43. return info;
  44. }
  45. EXPORT_SYMBOL_GPL(fpga_image_info_alloc);
  46. void fpga_image_info_free(struct fpga_image_info *info)
  47. {
  48. struct device *dev;
  49. if (!info)
  50. return;
  51. dev = info->dev;
  52. if (info->firmware_name)
  53. devm_kfree(dev, info->firmware_name);
  54. devm_kfree(dev, info);
  55. put_device(dev);
  56. }
  57. EXPORT_SYMBOL_GPL(fpga_image_info_free);
  58. /*
  59. * Call the low level driver's write_init function. This will do the
  60. * device-specific things to get the FPGA into the state where it is ready to
  61. * receive an FPGA image. The low level driver only gets to see the first
  62. * initial_header_size bytes in the buffer.
  63. */
  64. static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
  65. struct fpga_image_info *info,
  66. const char *buf, size_t count)
  67. {
  68. int ret;
  69. mgr->state = FPGA_MGR_STATE_WRITE_INIT;
  70. if (!mgr->mops->initial_header_size)
  71. ret = mgr->mops->write_init(mgr, info, NULL, 0);
  72. else
  73. ret = mgr->mops->write_init(
  74. mgr, info, buf, min(mgr->mops->initial_header_size, count));
  75. if (ret) {
  76. dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
  77. mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
  78. return ret;
  79. }
  80. return 0;
  81. }
  82. static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
  83. struct fpga_image_info *info,
  84. struct sg_table *sgt)
  85. {
  86. struct sg_mapping_iter miter;
  87. size_t len;
  88. char *buf;
  89. int ret;
  90. if (!mgr->mops->initial_header_size)
  91. return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
  92. /*
  93. * First try to use miter to map the first fragment to access the
  94. * header, this is the typical path.
  95. */
  96. sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
  97. if (sg_miter_next(&miter) &&
  98. miter.length >= mgr->mops->initial_header_size) {
  99. ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
  100. miter.length);
  101. sg_miter_stop(&miter);
  102. return ret;
  103. }
  104. sg_miter_stop(&miter);
  105. /* Otherwise copy the fragments into temporary memory. */
  106. buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
  107. if (!buf)
  108. return -ENOMEM;
  109. len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
  110. mgr->mops->initial_header_size);
  111. ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
  112. kfree(buf);
  113. return ret;
  114. }
  115. /*
  116. * After all the FPGA image has been written, do the device specific steps to
  117. * finish and set the FPGA into operating mode.
  118. */
  119. static int fpga_mgr_write_complete(struct fpga_manager *mgr,
  120. struct fpga_image_info *info)
  121. {
  122. int ret;
  123. mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
  124. ret = mgr->mops->write_complete(mgr, info);
  125. if (ret) {
  126. dev_err(&mgr->dev, "Error after writing image data to FPGA\n");
  127. mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
  128. return ret;
  129. }
  130. mgr->state = FPGA_MGR_STATE_OPERATING;
  131. return 0;
  132. }
  133. /**
  134. * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list
  135. * @mgr: fpga manager
  136. * @info: fpga image specific information
  137. * @sgt: scatterlist table
  138. *
  139. * Step the low level fpga manager through the device-specific steps of getting
  140. * an FPGA ready to be configured, writing the image to it, then doing whatever
  141. * post-configuration steps necessary. This code assumes the caller got the
  142. * mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is
  143. * not an error code.
  144. *
  145. * This is the preferred entry point for FPGA programming, it does not require
  146. * any contiguous kernel memory.
  147. *
  148. * Return: 0 on success, negative error code otherwise.
  149. */
  150. static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
  151. struct fpga_image_info *info,
  152. struct sg_table *sgt)
  153. {
  154. int ret;
  155. ret = fpga_mgr_write_init_sg(mgr, info, sgt);
  156. if (ret)
  157. return ret;
  158. /* Write the FPGA image to the FPGA. */
  159. mgr->state = FPGA_MGR_STATE_WRITE;
  160. if (mgr->mops->write_sg) {
  161. ret = mgr->mops->write_sg(mgr, sgt);
  162. } else {
  163. struct sg_mapping_iter miter;
  164. sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
  165. while (sg_miter_next(&miter)) {
  166. ret = mgr->mops->write(mgr, miter.addr, miter.length);
  167. if (ret)
  168. break;
  169. }
  170. sg_miter_stop(&miter);
  171. }
  172. if (ret) {
  173. dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
  174. mgr->state = FPGA_MGR_STATE_WRITE_ERR;
  175. return ret;
  176. }
  177. return fpga_mgr_write_complete(mgr, info);
  178. }
  179. static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
  180. struct fpga_image_info *info,
  181. const char *buf, size_t count)
  182. {
  183. int ret;
  184. ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
  185. if (ret)
  186. return ret;
  187. /*
  188. * Write the FPGA image to the FPGA.
  189. */
  190. mgr->state = FPGA_MGR_STATE_WRITE;
  191. ret = mgr->mops->write(mgr, buf, count);
  192. if (ret) {
  193. dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
  194. mgr->state = FPGA_MGR_STATE_WRITE_ERR;
  195. return ret;
  196. }
  197. return fpga_mgr_write_complete(mgr, info);
  198. }
  199. /**
  200. * fpga_mgr_buf_load - load fpga from image in buffer
  201. * @mgr: fpga manager
  202. * @flags: flags setting fpga confuration modes
  203. * @buf: buffer contain fpga image
  204. * @count: byte count of buf
  205. *
  206. * Step the low level fpga manager through the device-specific steps of getting
  207. * an FPGA ready to be configured, writing the image to it, then doing whatever
  208. * post-configuration steps necessary. This code assumes the caller got the
  209. * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
  210. *
  211. * Return: 0 on success, negative error code otherwise.
  212. */
  213. static int fpga_mgr_buf_load(struct fpga_manager *mgr,
  214. struct fpga_image_info *info,
  215. const char *buf, size_t count)
  216. {
  217. struct page **pages;
  218. struct sg_table sgt;
  219. const void *p;
  220. int nr_pages;
  221. int index;
  222. int rc;
  223. /*
  224. * This is just a fast path if the caller has already created a
  225. * contiguous kernel buffer and the driver doesn't require SG, non-SG
  226. * drivers will still work on the slow path.
  227. */
  228. if (mgr->mops->write)
  229. return fpga_mgr_buf_load_mapped(mgr, info, buf, count);
  230. /*
  231. * Convert the linear kernel pointer into a sg_table of pages for use
  232. * by the driver.
  233. */
  234. nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) -
  235. (unsigned long)buf / PAGE_SIZE;
  236. pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
  237. if (!pages)
  238. return -ENOMEM;
  239. p = buf - offset_in_page(buf);
  240. for (index = 0; index < nr_pages; index++) {
  241. if (is_vmalloc_addr(p))
  242. pages[index] = vmalloc_to_page(p);
  243. else
  244. pages[index] = kmap_to_page((void *)p);
  245. if (!pages[index]) {
  246. kfree(pages);
  247. return -EFAULT;
  248. }
  249. p += PAGE_SIZE;
  250. }
  251. /*
  252. * The temporary pages list is used to code share the merging algorithm
  253. * in sg_alloc_table_from_pages
  254. */
  255. rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf),
  256. count, GFP_KERNEL);
  257. kfree(pages);
  258. if (rc)
  259. return rc;
  260. rc = fpga_mgr_buf_load_sg(mgr, info, &sgt);
  261. sg_free_table(&sgt);
  262. return rc;
  263. }
  264. /**
  265. * fpga_mgr_firmware_load - request firmware and load to fpga
  266. * @mgr: fpga manager
  267. * @info: fpga image specific information
  268. * @image_name: name of image file on the firmware search path
  269. *
  270. * Request an FPGA image using the firmware class, then write out to the FPGA.
  271. * Update the state before each step to provide info on what step failed if
  272. * there is a failure. This code assumes the caller got the mgr pointer
  273. * from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error
  274. * code.
  275. *
  276. * Return: 0 on success, negative error code otherwise.
  277. */
  278. static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
  279. struct fpga_image_info *info,
  280. const char *image_name)
  281. {
  282. struct device *dev = &mgr->dev;
  283. const struct firmware *fw;
  284. int ret;
  285. dev_info(dev, "writing %s to %s\n", image_name, mgr->name);
  286. mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ;
  287. ret = request_firmware(&fw, image_name, dev);
  288. if (ret) {
  289. mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR;
  290. dev_err(dev, "Error requesting firmware %s\n", image_name);
  291. return ret;
  292. }
  293. ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
  294. release_firmware(fw);
  295. return ret;
  296. }
  297. int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
  298. {
  299. if (info->sgt)
  300. return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
  301. if (info->buf && info->count)
  302. return fpga_mgr_buf_load(mgr, info, info->buf, info->count);
  303. if (info->firmware_name)
  304. return fpga_mgr_firmware_load(mgr, info, info->firmware_name);
  305. return -EINVAL;
  306. }
  307. EXPORT_SYMBOL_GPL(fpga_mgr_load);
  308. static const char * const state_str[] = {
  309. [FPGA_MGR_STATE_UNKNOWN] = "unknown",
  310. [FPGA_MGR_STATE_POWER_OFF] = "power off",
  311. [FPGA_MGR_STATE_POWER_UP] = "power up",
  312. [FPGA_MGR_STATE_RESET] = "reset",
  313. /* requesting FPGA image from firmware */
  314. [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
  315. [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
  316. /* Preparing FPGA to receive image */
  317. [FPGA_MGR_STATE_WRITE_INIT] = "write init",
  318. [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
  319. /* Writing image to FPGA */
  320. [FPGA_MGR_STATE_WRITE] = "write",
  321. [FPGA_MGR_STATE_WRITE_ERR] = "write error",
  322. /* Finishing configuration after image has been written */
  323. [FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete",
  324. [FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error",
  325. /* FPGA reports to be in normal operating mode */
  326. [FPGA_MGR_STATE_OPERATING] = "operating",
  327. };
  328. static ssize_t name_show(struct device *dev,
  329. struct device_attribute *attr, char *buf)
  330. {
  331. struct fpga_manager *mgr = to_fpga_manager(dev);
  332. return sprintf(buf, "%s\n", mgr->name);
  333. }
  334. static ssize_t state_show(struct device *dev,
  335. struct device_attribute *attr, char *buf)
  336. {
  337. struct fpga_manager *mgr = to_fpga_manager(dev);
  338. return sprintf(buf, "%s\n", state_str[mgr->state]);
  339. }
  340. static DEVICE_ATTR_RO(name);
  341. static DEVICE_ATTR_RO(state);
  342. static struct attribute *fpga_mgr_attrs[] = {
  343. &dev_attr_name.attr,
  344. &dev_attr_state.attr,
  345. NULL,
  346. };
  347. ATTRIBUTE_GROUPS(fpga_mgr);
  348. static struct fpga_manager *__fpga_mgr_get(struct device *dev)
  349. {
  350. struct fpga_manager *mgr;
  351. mgr = to_fpga_manager(dev);
  352. if (!mgr)
  353. goto err_dev;
  354. if (!try_module_get(dev->parent->driver->owner))
  355. goto err_dev;
  356. return mgr;
  357. err_dev:
  358. put_device(dev);
  359. return ERR_PTR(-ENODEV);
  360. }
  361. static int fpga_mgr_dev_match(struct device *dev, const void *data)
  362. {
  363. return dev->parent == data;
  364. }
  365. /**
  366. * fpga_mgr_get - get a reference to a fpga mgr
  367. * @dev: parent device that fpga mgr was registered with
  368. *
  369. * Given a device, get a reference to a fpga mgr.
  370. *
  371. * Return: fpga manager struct or IS_ERR() condition containing error code.
  372. */
  373. struct fpga_manager *fpga_mgr_get(struct device *dev)
  374. {
  375. struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
  376. fpga_mgr_dev_match);
  377. if (!mgr_dev)
  378. return ERR_PTR(-ENODEV);
  379. return __fpga_mgr_get(mgr_dev);
  380. }
  381. EXPORT_SYMBOL_GPL(fpga_mgr_get);
  382. static int fpga_mgr_of_node_match(struct device *dev, const void *data)
  383. {
  384. return dev->of_node == data;
  385. }
  386. /**
  387. * of_fpga_mgr_get - get a reference to a fpga mgr
  388. * @node: device node
  389. *
  390. * Given a device node, get a reference to a fpga mgr.
  391. *
  392. * Return: fpga manager struct or IS_ERR() condition containing error code.
  393. */
  394. struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
  395. {
  396. struct device *dev;
  397. dev = class_find_device(fpga_mgr_class, NULL, node,
  398. fpga_mgr_of_node_match);
  399. if (!dev)
  400. return ERR_PTR(-ENODEV);
  401. return __fpga_mgr_get(dev);
  402. }
  403. EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
  404. /**
  405. * fpga_mgr_put - release a reference to a fpga manager
  406. * @mgr: fpga manager structure
  407. */
  408. void fpga_mgr_put(struct fpga_manager *mgr)
  409. {
  410. module_put(mgr->dev.parent->driver->owner);
  411. put_device(&mgr->dev);
  412. }
  413. EXPORT_SYMBOL_GPL(fpga_mgr_put);
  414. /**
  415. * fpga_mgr_lock - Lock FPGA manager for exclusive use
  416. * @mgr: fpga manager
  417. *
  418. * Given a pointer to FPGA Manager (from fpga_mgr_get() or
  419. * of_fpga_mgr_put()) attempt to get the mutex.
  420. *
  421. * Return: 0 for success or -EBUSY
  422. */
  423. int fpga_mgr_lock(struct fpga_manager *mgr)
  424. {
  425. if (!mutex_trylock(&mgr->ref_mutex)) {
  426. dev_err(&mgr->dev, "FPGA manager is in use.\n");
  427. return -EBUSY;
  428. }
  429. return 0;
  430. }
  431. EXPORT_SYMBOL_GPL(fpga_mgr_lock);
  432. /**
  433. * fpga_mgr_unlock - Unlock FPGA manager
  434. * @mgr: fpga manager
  435. */
  436. void fpga_mgr_unlock(struct fpga_manager *mgr)
  437. {
  438. mutex_unlock(&mgr->ref_mutex);
  439. }
  440. EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
  441. /**
  442. * fpga_mgr_register - register a low level fpga manager driver
  443. * @dev: fpga manager device from pdev
  444. * @name: fpga manager name
  445. * @mops: pointer to structure of fpga manager ops
  446. * @priv: fpga manager private data
  447. *
  448. * Return: 0 on success, negative error code otherwise.
  449. */
  450. int fpga_mgr_register(struct device *dev, const char *name,
  451. const struct fpga_manager_ops *mops,
  452. void *priv)
  453. {
  454. struct fpga_manager *mgr;
  455. int id, ret;
  456. if (!mops || !mops->write_complete || !mops->state ||
  457. !mops->write_init || (!mops->write && !mops->write_sg) ||
  458. (mops->write && mops->write_sg)) {
  459. dev_err(dev, "Attempt to register without fpga_manager_ops\n");
  460. return -EINVAL;
  461. }
  462. if (!name || !strlen(name)) {
  463. dev_err(dev, "Attempt to register with no name!\n");
  464. return -EINVAL;
  465. }
  466. mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  467. if (!mgr)
  468. return -ENOMEM;
  469. id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
  470. if (id < 0) {
  471. ret = id;
  472. goto error_kfree;
  473. }
  474. mutex_init(&mgr->ref_mutex);
  475. mgr->name = name;
  476. mgr->mops = mops;
  477. mgr->priv = priv;
  478. /*
  479. * Initialize framework state by requesting low level driver read state
  480. * from device. FPGA may be in reset mode or may have been programmed
  481. * by bootloader or EEPROM.
  482. */
  483. mgr->state = mgr->mops->state(mgr);
  484. device_initialize(&mgr->dev);
  485. mgr->dev.class = fpga_mgr_class;
  486. mgr->dev.groups = mops->groups;
  487. mgr->dev.parent = dev;
  488. mgr->dev.of_node = dev->of_node;
  489. mgr->dev.id = id;
  490. dev_set_drvdata(dev, mgr);
  491. ret = dev_set_name(&mgr->dev, "fpga%d", id);
  492. if (ret)
  493. goto error_device;
  494. ret = device_add(&mgr->dev);
  495. if (ret)
  496. goto error_device;
  497. dev_info(&mgr->dev, "%s registered\n", mgr->name);
  498. return 0;
  499. error_device:
  500. ida_simple_remove(&fpga_mgr_ida, id);
  501. error_kfree:
  502. kfree(mgr);
  503. return ret;
  504. }
  505. EXPORT_SYMBOL_GPL(fpga_mgr_register);
  506. /**
  507. * fpga_mgr_unregister - unregister a low level fpga manager driver
  508. * @dev: fpga manager device from pdev
  509. */
  510. void fpga_mgr_unregister(struct device *dev)
  511. {
  512. struct fpga_manager *mgr = dev_get_drvdata(dev);
  513. dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
  514. /*
  515. * If the low level driver provides a method for putting fpga into
  516. * a desired state upon unregister, do it.
  517. */
  518. if (mgr->mops->fpga_remove)
  519. mgr->mops->fpga_remove(mgr);
  520. device_unregister(&mgr->dev);
  521. }
  522. EXPORT_SYMBOL_GPL(fpga_mgr_unregister);
  523. static void fpga_mgr_dev_release(struct device *dev)
  524. {
  525. struct fpga_manager *mgr = to_fpga_manager(dev);
  526. ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
  527. kfree(mgr);
  528. }
  529. static int __init fpga_mgr_class_init(void)
  530. {
  531. pr_info("FPGA manager framework\n");
  532. fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager");
  533. if (IS_ERR(fpga_mgr_class))
  534. return PTR_ERR(fpga_mgr_class);
  535. fpga_mgr_class->dev_groups = fpga_mgr_groups;
  536. fpga_mgr_class->dev_release = fpga_mgr_dev_release;
  537. return 0;
  538. }
  539. static void __exit fpga_mgr_class_exit(void)
  540. {
  541. class_destroy(fpga_mgr_class);
  542. ida_destroy(&fpga_mgr_ida);
  543. }
  544. MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
  545. MODULE_DESCRIPTION("FPGA manager framework");
  546. MODULE_LICENSE("GPL v2");
  547. subsys_initcall(fpga_mgr_class_init);
  548. module_exit(fpga_mgr_class_exit);