intel-pt.c 54 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <stdio.h>
  16. #include <stdbool.h>
  17. #include <errno.h>
  18. #include <linux/kernel.h>
  19. #include <linux/types.h>
  20. #include "../perf.h"
  21. #include "session.h"
  22. #include "machine.h"
  23. #include "sort.h"
  24. #include "tool.h"
  25. #include "event.h"
  26. #include "evlist.h"
  27. #include "evsel.h"
  28. #include "map.h"
  29. #include "color.h"
  30. #include "util.h"
  31. #include "thread.h"
  32. #include "thread-stack.h"
  33. #include "symbol.h"
  34. #include "callchain.h"
  35. #include "dso.h"
  36. #include "debug.h"
  37. #include "auxtrace.h"
  38. #include "tsc.h"
  39. #include "intel-pt.h"
  40. #include "intel-pt-decoder/intel-pt-log.h"
  41. #include "intel-pt-decoder/intel-pt-decoder.h"
  42. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  43. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  44. #define MAX_TIMESTAMP (~0ULL)
  45. struct intel_pt {
  46. struct auxtrace auxtrace;
  47. struct auxtrace_queues queues;
  48. struct auxtrace_heap heap;
  49. u32 auxtrace_type;
  50. struct perf_session *session;
  51. struct machine *machine;
  52. struct perf_evsel *switch_evsel;
  53. struct thread *unknown_thread;
  54. bool timeless_decoding;
  55. bool sampling_mode;
  56. bool snapshot_mode;
  57. bool per_cpu_mmaps;
  58. bool have_tsc;
  59. bool data_queued;
  60. bool est_tsc;
  61. bool sync_switch;
  62. bool mispred_all;
  63. int have_sched_switch;
  64. u32 pmu_type;
  65. u64 kernel_start;
  66. u64 switch_ip;
  67. u64 ptss_ip;
  68. struct perf_tsc_conversion tc;
  69. bool cap_user_time_zero;
  70. struct itrace_synth_opts synth_opts;
  71. bool sample_instructions;
  72. u64 instructions_sample_type;
  73. u64 instructions_sample_period;
  74. u64 instructions_id;
  75. bool sample_branches;
  76. u32 branches_filter;
  77. u64 branches_sample_type;
  78. u64 branches_id;
  79. bool sample_transactions;
  80. u64 transactions_sample_type;
  81. u64 transactions_id;
  82. bool synth_needs_swap;
  83. u64 tsc_bit;
  84. u64 mtc_bit;
  85. u64 mtc_freq_bits;
  86. u32 tsc_ctc_ratio_n;
  87. u32 tsc_ctc_ratio_d;
  88. u64 cyc_bit;
  89. u64 noretcomp_bit;
  90. unsigned max_non_turbo_ratio;
  91. unsigned long num_events;
  92. };
  93. enum switch_state {
  94. INTEL_PT_SS_NOT_TRACING,
  95. INTEL_PT_SS_UNKNOWN,
  96. INTEL_PT_SS_TRACING,
  97. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  98. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  99. };
  100. struct intel_pt_queue {
  101. struct intel_pt *pt;
  102. unsigned int queue_nr;
  103. struct auxtrace_buffer *buffer;
  104. void *decoder;
  105. const struct intel_pt_state *state;
  106. struct ip_callchain *chain;
  107. struct branch_stack *last_branch;
  108. struct branch_stack *last_branch_rb;
  109. size_t last_branch_pos;
  110. union perf_event *event_buf;
  111. bool on_heap;
  112. bool stop;
  113. bool step_through_buffers;
  114. bool use_buffer_pid_tid;
  115. pid_t pid, tid;
  116. int cpu;
  117. int switch_state;
  118. pid_t next_tid;
  119. struct thread *thread;
  120. bool exclude_kernel;
  121. bool have_sample;
  122. u64 time;
  123. u64 timestamp;
  124. u32 flags;
  125. u16 insn_len;
  126. u64 last_insn_cnt;
  127. };
  128. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  129. unsigned char *buf, size_t len)
  130. {
  131. struct intel_pt_pkt packet;
  132. size_t pos = 0;
  133. int ret, pkt_len, i;
  134. char desc[INTEL_PT_PKT_DESC_MAX];
  135. const char *color = PERF_COLOR_BLUE;
  136. color_fprintf(stdout, color,
  137. ". ... Intel Processor Trace data: size %zu bytes\n",
  138. len);
  139. while (len) {
  140. ret = intel_pt_get_packet(buf, len, &packet);
  141. if (ret > 0)
  142. pkt_len = ret;
  143. else
  144. pkt_len = 1;
  145. printf(".");
  146. color_fprintf(stdout, color, " %08x: ", pos);
  147. for (i = 0; i < pkt_len; i++)
  148. color_fprintf(stdout, color, " %02x", buf[i]);
  149. for (; i < 16; i++)
  150. color_fprintf(stdout, color, " ");
  151. if (ret > 0) {
  152. ret = intel_pt_pkt_desc(&packet, desc,
  153. INTEL_PT_PKT_DESC_MAX);
  154. if (ret > 0)
  155. color_fprintf(stdout, color, " %s\n", desc);
  156. } else {
  157. color_fprintf(stdout, color, " Bad packet!\n");
  158. }
  159. pos += pkt_len;
  160. buf += pkt_len;
  161. len -= pkt_len;
  162. }
  163. }
  164. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  165. size_t len)
  166. {
  167. printf(".\n");
  168. intel_pt_dump(pt, buf, len);
  169. }
  170. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  171. struct auxtrace_buffer *b)
  172. {
  173. void *start;
  174. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  175. pt->have_tsc);
  176. if (!start)
  177. return -EINVAL;
  178. b->use_size = b->data + b->size - start;
  179. b->use_data = start;
  180. return 0;
  181. }
  182. static void intel_pt_use_buffer_pid_tid(struct intel_pt_queue *ptq,
  183. struct auxtrace_queue *queue,
  184. struct auxtrace_buffer *buffer)
  185. {
  186. if (queue->cpu == -1 && buffer->cpu != -1)
  187. ptq->cpu = buffer->cpu;
  188. ptq->pid = buffer->pid;
  189. ptq->tid = buffer->tid;
  190. intel_pt_log("queue %u cpu %d pid %d tid %d\n",
  191. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  192. thread__zput(ptq->thread);
  193. if (ptq->tid != -1) {
  194. if (ptq->pid != -1)
  195. ptq->thread = machine__findnew_thread(ptq->pt->machine,
  196. ptq->pid,
  197. ptq->tid);
  198. else
  199. ptq->thread = machine__find_thread(ptq->pt->machine, -1,
  200. ptq->tid);
  201. }
  202. }
  203. /* This function assumes data is processed sequentially only */
  204. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  205. {
  206. struct intel_pt_queue *ptq = data;
  207. struct auxtrace_buffer *buffer = ptq->buffer, *old_buffer = buffer;
  208. struct auxtrace_queue *queue;
  209. if (ptq->stop) {
  210. b->len = 0;
  211. return 0;
  212. }
  213. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  214. buffer = auxtrace_buffer__next(queue, buffer);
  215. if (!buffer) {
  216. if (old_buffer)
  217. auxtrace_buffer__drop_data(old_buffer);
  218. b->len = 0;
  219. return 0;
  220. }
  221. ptq->buffer = buffer;
  222. if (!buffer->data) {
  223. int fd = perf_data_file__fd(ptq->pt->session->file);
  224. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  225. if (!buffer->data)
  226. return -ENOMEM;
  227. }
  228. if (ptq->pt->snapshot_mode && !buffer->consecutive && old_buffer &&
  229. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  230. return -ENOMEM;
  231. if (old_buffer)
  232. auxtrace_buffer__drop_data(old_buffer);
  233. if (buffer->use_data) {
  234. b->len = buffer->use_size;
  235. b->buf = buffer->use_data;
  236. } else {
  237. b->len = buffer->size;
  238. b->buf = buffer->data;
  239. }
  240. b->ref_timestamp = buffer->reference;
  241. if (!old_buffer || ptq->pt->sampling_mode || (ptq->pt->snapshot_mode &&
  242. !buffer->consecutive)) {
  243. b->consecutive = false;
  244. b->trace_nr = buffer->buffer_nr + 1;
  245. } else {
  246. b->consecutive = true;
  247. }
  248. if (ptq->use_buffer_pid_tid && (ptq->pid != buffer->pid ||
  249. ptq->tid != buffer->tid))
  250. intel_pt_use_buffer_pid_tid(ptq, queue, buffer);
  251. if (ptq->step_through_buffers)
  252. ptq->stop = true;
  253. if (!b->len)
  254. return intel_pt_get_trace(b, data);
  255. return 0;
  256. }
  257. struct intel_pt_cache_entry {
  258. struct auxtrace_cache_entry entry;
  259. u64 insn_cnt;
  260. u64 byte_cnt;
  261. enum intel_pt_insn_op op;
  262. enum intel_pt_insn_branch branch;
  263. int length;
  264. int32_t rel;
  265. };
  266. static int intel_pt_config_div(const char *var, const char *value, void *data)
  267. {
  268. int *d = data;
  269. long val;
  270. if (!strcmp(var, "intel-pt.cache-divisor")) {
  271. val = strtol(value, NULL, 0);
  272. if (val > 0 && val <= INT_MAX)
  273. *d = val;
  274. }
  275. return 0;
  276. }
  277. static int intel_pt_cache_divisor(void)
  278. {
  279. static int d;
  280. if (d)
  281. return d;
  282. perf_config(intel_pt_config_div, &d);
  283. if (!d)
  284. d = 64;
  285. return d;
  286. }
  287. static unsigned int intel_pt_cache_size(struct dso *dso,
  288. struct machine *machine)
  289. {
  290. off_t size;
  291. size = dso__data_size(dso, machine);
  292. size /= intel_pt_cache_divisor();
  293. if (size < 1000)
  294. return 10;
  295. if (size > (1 << 21))
  296. return 21;
  297. return 32 - __builtin_clz(size);
  298. }
  299. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  300. struct machine *machine)
  301. {
  302. struct auxtrace_cache *c;
  303. unsigned int bits;
  304. if (dso->auxtrace_cache)
  305. return dso->auxtrace_cache;
  306. bits = intel_pt_cache_size(dso, machine);
  307. /* Ignoring cache creation failure */
  308. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  309. dso->auxtrace_cache = c;
  310. return c;
  311. }
  312. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  313. u64 offset, u64 insn_cnt, u64 byte_cnt,
  314. struct intel_pt_insn *intel_pt_insn)
  315. {
  316. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  317. struct intel_pt_cache_entry *e;
  318. int err;
  319. if (!c)
  320. return -ENOMEM;
  321. e = auxtrace_cache__alloc_entry(c);
  322. if (!e)
  323. return -ENOMEM;
  324. e->insn_cnt = insn_cnt;
  325. e->byte_cnt = byte_cnt;
  326. e->op = intel_pt_insn->op;
  327. e->branch = intel_pt_insn->branch;
  328. e->length = intel_pt_insn->length;
  329. e->rel = intel_pt_insn->rel;
  330. err = auxtrace_cache__add(c, offset, &e->entry);
  331. if (err)
  332. auxtrace_cache__free_entry(c, e);
  333. return err;
  334. }
  335. static struct intel_pt_cache_entry *
  336. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  337. {
  338. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  339. if (!c)
  340. return NULL;
  341. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  342. }
  343. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  344. uint64_t *insn_cnt_ptr, uint64_t *ip,
  345. uint64_t to_ip, uint64_t max_insn_cnt,
  346. void *data)
  347. {
  348. struct intel_pt_queue *ptq = data;
  349. struct machine *machine = ptq->pt->machine;
  350. struct thread *thread;
  351. struct addr_location al;
  352. unsigned char buf[1024];
  353. size_t bufsz;
  354. ssize_t len;
  355. int x86_64;
  356. u8 cpumode;
  357. u64 offset, start_offset, start_ip;
  358. u64 insn_cnt = 0;
  359. bool one_map = true;
  360. if (to_ip && *ip == to_ip)
  361. goto out_no_cache;
  362. bufsz = intel_pt_insn_max_size();
  363. if (*ip >= ptq->pt->kernel_start)
  364. cpumode = PERF_RECORD_MISC_KERNEL;
  365. else
  366. cpumode = PERF_RECORD_MISC_USER;
  367. thread = ptq->thread;
  368. if (!thread) {
  369. if (cpumode != PERF_RECORD_MISC_KERNEL)
  370. return -EINVAL;
  371. thread = ptq->pt->unknown_thread;
  372. }
  373. while (1) {
  374. thread__find_addr_map(thread, cpumode, MAP__FUNCTION, *ip, &al);
  375. if (!al.map || !al.map->dso)
  376. return -EINVAL;
  377. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  378. dso__data_status_seen(al.map->dso,
  379. DSO_DATA_STATUS_SEEN_ITRACE))
  380. return -ENOENT;
  381. offset = al.map->map_ip(al.map, *ip);
  382. if (!to_ip && one_map) {
  383. struct intel_pt_cache_entry *e;
  384. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  385. if (e &&
  386. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  387. *insn_cnt_ptr = e->insn_cnt;
  388. *ip += e->byte_cnt;
  389. intel_pt_insn->op = e->op;
  390. intel_pt_insn->branch = e->branch;
  391. intel_pt_insn->length = e->length;
  392. intel_pt_insn->rel = e->rel;
  393. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  394. return 0;
  395. }
  396. }
  397. start_offset = offset;
  398. start_ip = *ip;
  399. /* Load maps to ensure dso->is_64_bit has been updated */
  400. map__load(al.map, machine->symbol_filter);
  401. x86_64 = al.map->dso->is_64_bit;
  402. while (1) {
  403. len = dso__data_read_offset(al.map->dso, machine,
  404. offset, buf, bufsz);
  405. if (len <= 0)
  406. return -EINVAL;
  407. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  408. return -EINVAL;
  409. intel_pt_log_insn(intel_pt_insn, *ip);
  410. insn_cnt += 1;
  411. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  412. goto out;
  413. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  414. goto out_no_cache;
  415. *ip += intel_pt_insn->length;
  416. if (to_ip && *ip == to_ip)
  417. goto out_no_cache;
  418. if (*ip >= al.map->end)
  419. break;
  420. offset += intel_pt_insn->length;
  421. }
  422. one_map = false;
  423. }
  424. out:
  425. *insn_cnt_ptr = insn_cnt;
  426. if (!one_map)
  427. goto out_no_cache;
  428. /*
  429. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  430. * entries.
  431. */
  432. if (to_ip) {
  433. struct intel_pt_cache_entry *e;
  434. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  435. if (e)
  436. return 0;
  437. }
  438. /* Ignore cache errors */
  439. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  440. *ip - start_ip, intel_pt_insn);
  441. return 0;
  442. out_no_cache:
  443. *insn_cnt_ptr = insn_cnt;
  444. return 0;
  445. }
  446. static bool intel_pt_get_config(struct intel_pt *pt,
  447. struct perf_event_attr *attr, u64 *config)
  448. {
  449. if (attr->type == pt->pmu_type) {
  450. if (config)
  451. *config = attr->config;
  452. return true;
  453. }
  454. return false;
  455. }
  456. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  457. {
  458. struct perf_evsel *evsel;
  459. evlist__for_each(pt->session->evlist, evsel) {
  460. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  461. !evsel->attr.exclude_kernel)
  462. return false;
  463. }
  464. return true;
  465. }
  466. static bool intel_pt_return_compression(struct intel_pt *pt)
  467. {
  468. struct perf_evsel *evsel;
  469. u64 config;
  470. if (!pt->noretcomp_bit)
  471. return true;
  472. evlist__for_each(pt->session->evlist, evsel) {
  473. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  474. (config & pt->noretcomp_bit))
  475. return false;
  476. }
  477. return true;
  478. }
  479. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  480. {
  481. struct perf_evsel *evsel;
  482. unsigned int shift;
  483. u64 config;
  484. if (!pt->mtc_freq_bits)
  485. return 0;
  486. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  487. config >>= 1;
  488. evlist__for_each(pt->session->evlist, evsel) {
  489. if (intel_pt_get_config(pt, &evsel->attr, &config))
  490. return (config & pt->mtc_freq_bits) >> shift;
  491. }
  492. return 0;
  493. }
  494. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  495. {
  496. struct perf_evsel *evsel;
  497. bool timeless_decoding = true;
  498. u64 config;
  499. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  500. return true;
  501. evlist__for_each(pt->session->evlist, evsel) {
  502. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  503. return true;
  504. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  505. if (config & pt->tsc_bit)
  506. timeless_decoding = false;
  507. else
  508. return true;
  509. }
  510. }
  511. return timeless_decoding;
  512. }
  513. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  514. {
  515. struct perf_evsel *evsel;
  516. evlist__for_each(pt->session->evlist, evsel) {
  517. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  518. !evsel->attr.exclude_kernel)
  519. return true;
  520. }
  521. return false;
  522. }
  523. static bool intel_pt_have_tsc(struct intel_pt *pt)
  524. {
  525. struct perf_evsel *evsel;
  526. bool have_tsc = false;
  527. u64 config;
  528. if (!pt->tsc_bit)
  529. return false;
  530. evlist__for_each(pt->session->evlist, evsel) {
  531. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  532. if (config & pt->tsc_bit)
  533. have_tsc = true;
  534. else
  535. return false;
  536. }
  537. }
  538. return have_tsc;
  539. }
  540. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  541. {
  542. u64 quot, rem;
  543. quot = ns / pt->tc.time_mult;
  544. rem = ns % pt->tc.time_mult;
  545. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  546. pt->tc.time_mult;
  547. }
  548. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  549. unsigned int queue_nr)
  550. {
  551. struct intel_pt_params params = { .get_trace = 0, };
  552. struct intel_pt_queue *ptq;
  553. ptq = zalloc(sizeof(struct intel_pt_queue));
  554. if (!ptq)
  555. return NULL;
  556. if (pt->synth_opts.callchain) {
  557. size_t sz = sizeof(struct ip_callchain);
  558. sz += pt->synth_opts.callchain_sz * sizeof(u64);
  559. ptq->chain = zalloc(sz);
  560. if (!ptq->chain)
  561. goto out_free;
  562. }
  563. if (pt->synth_opts.last_branch) {
  564. size_t sz = sizeof(struct branch_stack);
  565. sz += pt->synth_opts.last_branch_sz *
  566. sizeof(struct branch_entry);
  567. ptq->last_branch = zalloc(sz);
  568. if (!ptq->last_branch)
  569. goto out_free;
  570. ptq->last_branch_rb = zalloc(sz);
  571. if (!ptq->last_branch_rb)
  572. goto out_free;
  573. }
  574. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  575. if (!ptq->event_buf)
  576. goto out_free;
  577. ptq->pt = pt;
  578. ptq->queue_nr = queue_nr;
  579. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  580. ptq->pid = -1;
  581. ptq->tid = -1;
  582. ptq->cpu = -1;
  583. ptq->next_tid = -1;
  584. params.get_trace = intel_pt_get_trace;
  585. params.walk_insn = intel_pt_walk_next_insn;
  586. params.data = ptq;
  587. params.return_compression = intel_pt_return_compression(pt);
  588. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  589. params.mtc_period = intel_pt_mtc_period(pt);
  590. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  591. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  592. if (pt->synth_opts.instructions) {
  593. if (pt->synth_opts.period) {
  594. switch (pt->synth_opts.period_type) {
  595. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  596. params.period_type =
  597. INTEL_PT_PERIOD_INSTRUCTIONS;
  598. params.period = pt->synth_opts.period;
  599. break;
  600. case PERF_ITRACE_PERIOD_TICKS:
  601. params.period_type = INTEL_PT_PERIOD_TICKS;
  602. params.period = pt->synth_opts.period;
  603. break;
  604. case PERF_ITRACE_PERIOD_NANOSECS:
  605. params.period_type = INTEL_PT_PERIOD_TICKS;
  606. params.period = intel_pt_ns_to_ticks(pt,
  607. pt->synth_opts.period);
  608. break;
  609. default:
  610. break;
  611. }
  612. }
  613. if (!params.period) {
  614. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  615. params.period = 1;
  616. }
  617. }
  618. ptq->decoder = intel_pt_decoder_new(&params);
  619. if (!ptq->decoder)
  620. goto out_free;
  621. return ptq;
  622. out_free:
  623. zfree(&ptq->event_buf);
  624. zfree(&ptq->last_branch);
  625. zfree(&ptq->last_branch_rb);
  626. zfree(&ptq->chain);
  627. free(ptq);
  628. return NULL;
  629. }
  630. static void intel_pt_free_queue(void *priv)
  631. {
  632. struct intel_pt_queue *ptq = priv;
  633. if (!ptq)
  634. return;
  635. thread__zput(ptq->thread);
  636. intel_pt_decoder_free(ptq->decoder);
  637. zfree(&ptq->event_buf);
  638. zfree(&ptq->last_branch);
  639. zfree(&ptq->last_branch_rb);
  640. zfree(&ptq->chain);
  641. free(ptq);
  642. }
  643. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  644. struct auxtrace_queue *queue)
  645. {
  646. struct intel_pt_queue *ptq = queue->priv;
  647. if (queue->tid == -1 || pt->have_sched_switch) {
  648. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  649. thread__zput(ptq->thread);
  650. }
  651. if (!ptq->thread && ptq->tid != -1)
  652. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  653. if (ptq->thread) {
  654. ptq->pid = ptq->thread->pid_;
  655. if (queue->cpu == -1)
  656. ptq->cpu = ptq->thread->cpu;
  657. }
  658. }
  659. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  660. {
  661. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  662. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  663. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  664. if (ptq->state->to_ip)
  665. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  666. PERF_IP_FLAG_ASYNC |
  667. PERF_IP_FLAG_INTERRUPT;
  668. else
  669. ptq->flags = PERF_IP_FLAG_BRANCH |
  670. PERF_IP_FLAG_TRACE_END;
  671. ptq->insn_len = 0;
  672. } else {
  673. if (ptq->state->from_ip)
  674. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  675. else
  676. ptq->flags = PERF_IP_FLAG_BRANCH |
  677. PERF_IP_FLAG_TRACE_BEGIN;
  678. if (ptq->state->flags & INTEL_PT_IN_TX)
  679. ptq->flags |= PERF_IP_FLAG_IN_TX;
  680. ptq->insn_len = ptq->state->insn_len;
  681. }
  682. }
  683. static int intel_pt_setup_queue(struct intel_pt *pt,
  684. struct auxtrace_queue *queue,
  685. unsigned int queue_nr)
  686. {
  687. struct intel_pt_queue *ptq = queue->priv;
  688. if (list_empty(&queue->head))
  689. return 0;
  690. if (!ptq) {
  691. ptq = intel_pt_alloc_queue(pt, queue_nr);
  692. if (!ptq)
  693. return -ENOMEM;
  694. queue->priv = ptq;
  695. if (queue->cpu != -1)
  696. ptq->cpu = queue->cpu;
  697. ptq->tid = queue->tid;
  698. if (pt->sampling_mode) {
  699. if (pt->timeless_decoding)
  700. ptq->step_through_buffers = true;
  701. if (pt->timeless_decoding || !pt->have_sched_switch)
  702. ptq->use_buffer_pid_tid = true;
  703. }
  704. }
  705. if (!ptq->on_heap &&
  706. (!pt->sync_switch ||
  707. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  708. const struct intel_pt_state *state;
  709. int ret;
  710. if (pt->timeless_decoding)
  711. return 0;
  712. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  713. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  714. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  715. while (1) {
  716. state = intel_pt_decode(ptq->decoder);
  717. if (state->err) {
  718. if (state->err == INTEL_PT_ERR_NODATA) {
  719. intel_pt_log("queue %u has no timestamp\n",
  720. queue_nr);
  721. return 0;
  722. }
  723. continue;
  724. }
  725. if (state->timestamp)
  726. break;
  727. }
  728. ptq->timestamp = state->timestamp;
  729. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  730. queue_nr, ptq->timestamp);
  731. ptq->state = state;
  732. ptq->have_sample = true;
  733. intel_pt_sample_flags(ptq);
  734. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  735. if (ret)
  736. return ret;
  737. ptq->on_heap = true;
  738. }
  739. return 0;
  740. }
  741. static int intel_pt_setup_queues(struct intel_pt *pt)
  742. {
  743. unsigned int i;
  744. int ret;
  745. for (i = 0; i < pt->queues.nr_queues; i++) {
  746. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  747. if (ret)
  748. return ret;
  749. }
  750. return 0;
  751. }
  752. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  753. {
  754. struct branch_stack *bs_src = ptq->last_branch_rb;
  755. struct branch_stack *bs_dst = ptq->last_branch;
  756. size_t nr = 0;
  757. bs_dst->nr = bs_src->nr;
  758. if (!bs_src->nr)
  759. return;
  760. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  761. memcpy(&bs_dst->entries[0],
  762. &bs_src->entries[ptq->last_branch_pos],
  763. sizeof(struct branch_entry) * nr);
  764. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  765. memcpy(&bs_dst->entries[nr],
  766. &bs_src->entries[0],
  767. sizeof(struct branch_entry) * ptq->last_branch_pos);
  768. }
  769. }
  770. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  771. {
  772. ptq->last_branch_pos = 0;
  773. ptq->last_branch_rb->nr = 0;
  774. }
  775. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  776. {
  777. const struct intel_pt_state *state = ptq->state;
  778. struct branch_stack *bs = ptq->last_branch_rb;
  779. struct branch_entry *be;
  780. if (!ptq->last_branch_pos)
  781. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  782. ptq->last_branch_pos -= 1;
  783. be = &bs->entries[ptq->last_branch_pos];
  784. be->from = state->from_ip;
  785. be->to = state->to_ip;
  786. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  787. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  788. /* No support for mispredict */
  789. be->flags.mispred = ptq->pt->mispred_all;
  790. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  791. bs->nr += 1;
  792. }
  793. static int intel_pt_inject_event(union perf_event *event,
  794. struct perf_sample *sample, u64 type,
  795. bool swapped)
  796. {
  797. event->header.size = perf_event__sample_event_size(sample, type, 0);
  798. return perf_event__synthesize_sample(event, type, 0, sample, swapped);
  799. }
  800. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  801. {
  802. int ret;
  803. struct intel_pt *pt = ptq->pt;
  804. union perf_event *event = ptq->event_buf;
  805. struct perf_sample sample = { .ip = 0, };
  806. struct dummy_branch_stack {
  807. u64 nr;
  808. struct branch_entry entries;
  809. } dummy_bs;
  810. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  811. return 0;
  812. if (pt->synth_opts.initial_skip &&
  813. pt->num_events++ < pt->synth_opts.initial_skip)
  814. return 0;
  815. event->sample.header.type = PERF_RECORD_SAMPLE;
  816. event->sample.header.misc = PERF_RECORD_MISC_USER;
  817. event->sample.header.size = sizeof(struct perf_event_header);
  818. if (!pt->timeless_decoding)
  819. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  820. sample.cpumode = PERF_RECORD_MISC_USER;
  821. sample.ip = ptq->state->from_ip;
  822. sample.pid = ptq->pid;
  823. sample.tid = ptq->tid;
  824. sample.addr = ptq->state->to_ip;
  825. sample.id = ptq->pt->branches_id;
  826. sample.stream_id = ptq->pt->branches_id;
  827. sample.period = 1;
  828. sample.cpu = ptq->cpu;
  829. sample.flags = ptq->flags;
  830. sample.insn_len = ptq->insn_len;
  831. /*
  832. * perf report cannot handle events without a branch stack when using
  833. * SORT_MODE__BRANCH so make a dummy one.
  834. */
  835. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  836. dummy_bs = (struct dummy_branch_stack){
  837. .nr = 1,
  838. .entries = {
  839. .from = sample.ip,
  840. .to = sample.addr,
  841. },
  842. };
  843. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  844. }
  845. if (pt->synth_opts.inject) {
  846. ret = intel_pt_inject_event(event, &sample,
  847. pt->branches_sample_type,
  848. pt->synth_needs_swap);
  849. if (ret)
  850. return ret;
  851. }
  852. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  853. if (ret)
  854. pr_err("Intel Processor Trace: failed to deliver branch event, error %d\n",
  855. ret);
  856. return ret;
  857. }
  858. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  859. {
  860. int ret;
  861. struct intel_pt *pt = ptq->pt;
  862. union perf_event *event = ptq->event_buf;
  863. struct perf_sample sample = { .ip = 0, };
  864. if (pt->synth_opts.initial_skip &&
  865. pt->num_events++ < pt->synth_opts.initial_skip)
  866. return 0;
  867. event->sample.header.type = PERF_RECORD_SAMPLE;
  868. event->sample.header.misc = PERF_RECORD_MISC_USER;
  869. event->sample.header.size = sizeof(struct perf_event_header);
  870. if (!pt->timeless_decoding)
  871. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  872. sample.cpumode = PERF_RECORD_MISC_USER;
  873. sample.ip = ptq->state->from_ip;
  874. sample.pid = ptq->pid;
  875. sample.tid = ptq->tid;
  876. sample.addr = ptq->state->to_ip;
  877. sample.id = ptq->pt->instructions_id;
  878. sample.stream_id = ptq->pt->instructions_id;
  879. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  880. sample.cpu = ptq->cpu;
  881. sample.flags = ptq->flags;
  882. sample.insn_len = ptq->insn_len;
  883. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  884. if (pt->synth_opts.callchain) {
  885. thread_stack__sample(ptq->thread, ptq->chain,
  886. pt->synth_opts.callchain_sz, sample.ip);
  887. sample.callchain = ptq->chain;
  888. }
  889. if (pt->synth_opts.last_branch) {
  890. intel_pt_copy_last_branch_rb(ptq);
  891. sample.branch_stack = ptq->last_branch;
  892. }
  893. if (pt->synth_opts.inject) {
  894. ret = intel_pt_inject_event(event, &sample,
  895. pt->instructions_sample_type,
  896. pt->synth_needs_swap);
  897. if (ret)
  898. return ret;
  899. }
  900. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  901. if (ret)
  902. pr_err("Intel Processor Trace: failed to deliver instruction event, error %d\n",
  903. ret);
  904. if (pt->synth_opts.last_branch)
  905. intel_pt_reset_last_branch_rb(ptq);
  906. return ret;
  907. }
  908. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  909. {
  910. int ret;
  911. struct intel_pt *pt = ptq->pt;
  912. union perf_event *event = ptq->event_buf;
  913. struct perf_sample sample = { .ip = 0, };
  914. if (pt->synth_opts.initial_skip &&
  915. pt->num_events++ < pt->synth_opts.initial_skip)
  916. return 0;
  917. event->sample.header.type = PERF_RECORD_SAMPLE;
  918. event->sample.header.misc = PERF_RECORD_MISC_USER;
  919. event->sample.header.size = sizeof(struct perf_event_header);
  920. if (!pt->timeless_decoding)
  921. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  922. sample.cpumode = PERF_RECORD_MISC_USER;
  923. sample.ip = ptq->state->from_ip;
  924. sample.pid = ptq->pid;
  925. sample.tid = ptq->tid;
  926. sample.addr = ptq->state->to_ip;
  927. sample.id = ptq->pt->transactions_id;
  928. sample.stream_id = ptq->pt->transactions_id;
  929. sample.period = 1;
  930. sample.cpu = ptq->cpu;
  931. sample.flags = ptq->flags;
  932. sample.insn_len = ptq->insn_len;
  933. if (pt->synth_opts.callchain) {
  934. thread_stack__sample(ptq->thread, ptq->chain,
  935. pt->synth_opts.callchain_sz, sample.ip);
  936. sample.callchain = ptq->chain;
  937. }
  938. if (pt->synth_opts.last_branch) {
  939. intel_pt_copy_last_branch_rb(ptq);
  940. sample.branch_stack = ptq->last_branch;
  941. }
  942. if (pt->synth_opts.inject) {
  943. ret = intel_pt_inject_event(event, &sample,
  944. pt->transactions_sample_type,
  945. pt->synth_needs_swap);
  946. if (ret)
  947. return ret;
  948. }
  949. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  950. if (ret)
  951. pr_err("Intel Processor Trace: failed to deliver transaction event, error %d\n",
  952. ret);
  953. if (pt->synth_opts.last_branch)
  954. intel_pt_reset_last_branch_rb(ptq);
  955. return ret;
  956. }
  957. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  958. pid_t pid, pid_t tid, u64 ip)
  959. {
  960. union perf_event event;
  961. char msg[MAX_AUXTRACE_ERROR_MSG];
  962. int err;
  963. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  964. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  965. code, cpu, pid, tid, ip, msg);
  966. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  967. if (err)
  968. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  969. err);
  970. return err;
  971. }
  972. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  973. {
  974. struct auxtrace_queue *queue;
  975. pid_t tid = ptq->next_tid;
  976. int err;
  977. if (tid == -1)
  978. return 0;
  979. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  980. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  981. queue = &pt->queues.queue_array[ptq->queue_nr];
  982. intel_pt_set_pid_tid_cpu(pt, queue);
  983. ptq->next_tid = -1;
  984. return err;
  985. }
  986. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  987. {
  988. struct intel_pt *pt = ptq->pt;
  989. return ip == pt->switch_ip &&
  990. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  991. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  992. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  993. }
  994. static int intel_pt_sample(struct intel_pt_queue *ptq)
  995. {
  996. const struct intel_pt_state *state = ptq->state;
  997. struct intel_pt *pt = ptq->pt;
  998. int err;
  999. if (!ptq->have_sample)
  1000. return 0;
  1001. ptq->have_sample = false;
  1002. if (pt->sample_instructions &&
  1003. (state->type & INTEL_PT_INSTRUCTION) &&
  1004. (!pt->synth_opts.initial_skip ||
  1005. pt->num_events++ >= pt->synth_opts.initial_skip)) {
  1006. err = intel_pt_synth_instruction_sample(ptq);
  1007. if (err)
  1008. return err;
  1009. }
  1010. if (pt->sample_transactions &&
  1011. (state->type & INTEL_PT_TRANSACTION) &&
  1012. (!pt->synth_opts.initial_skip ||
  1013. pt->num_events++ >= pt->synth_opts.initial_skip)) {
  1014. err = intel_pt_synth_transaction_sample(ptq);
  1015. if (err)
  1016. return err;
  1017. }
  1018. if (!(state->type & INTEL_PT_BRANCH))
  1019. return 0;
  1020. if (pt->synth_opts.callchain)
  1021. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1022. state->to_ip, ptq->insn_len,
  1023. state->trace_nr);
  1024. else
  1025. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1026. if (pt->sample_branches) {
  1027. err = intel_pt_synth_branch_sample(ptq);
  1028. if (err)
  1029. return err;
  1030. }
  1031. if (pt->synth_opts.last_branch)
  1032. intel_pt_update_last_branch_rb(ptq);
  1033. if (!pt->sync_switch)
  1034. return 0;
  1035. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1036. switch (ptq->switch_state) {
  1037. case INTEL_PT_SS_UNKNOWN:
  1038. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1039. err = intel_pt_next_tid(pt, ptq);
  1040. if (err)
  1041. return err;
  1042. ptq->switch_state = INTEL_PT_SS_TRACING;
  1043. break;
  1044. default:
  1045. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1046. return 1;
  1047. }
  1048. } else if (!state->to_ip) {
  1049. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1050. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1051. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1052. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1053. state->to_ip == pt->ptss_ip &&
  1054. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1055. ptq->switch_state = INTEL_PT_SS_TRACING;
  1056. }
  1057. return 0;
  1058. }
  1059. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1060. {
  1061. struct machine *machine = pt->machine;
  1062. struct map *map;
  1063. struct symbol *sym, *start;
  1064. u64 ip, switch_ip = 0;
  1065. const char *ptss;
  1066. if (ptss_ip)
  1067. *ptss_ip = 0;
  1068. map = machine__kernel_map(machine);
  1069. if (!map)
  1070. return 0;
  1071. if (map__load(map, machine->symbol_filter))
  1072. return 0;
  1073. start = dso__first_symbol(map->dso, MAP__FUNCTION);
  1074. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1075. if (sym->binding == STB_GLOBAL &&
  1076. !strcmp(sym->name, "__switch_to")) {
  1077. ip = map->unmap_ip(map, sym->start);
  1078. if (ip >= map->start && ip < map->end) {
  1079. switch_ip = ip;
  1080. break;
  1081. }
  1082. }
  1083. }
  1084. if (!switch_ip || !ptss_ip)
  1085. return 0;
  1086. if (pt->have_sched_switch == 1)
  1087. ptss = "perf_trace_sched_switch";
  1088. else
  1089. ptss = "__perf_event_task_sched_out";
  1090. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1091. if (!strcmp(sym->name, ptss)) {
  1092. ip = map->unmap_ip(map, sym->start);
  1093. if (ip >= map->start && ip < map->end) {
  1094. *ptss_ip = ip;
  1095. break;
  1096. }
  1097. }
  1098. }
  1099. return switch_ip;
  1100. }
  1101. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1102. {
  1103. const struct intel_pt_state *state = ptq->state;
  1104. struct intel_pt *pt = ptq->pt;
  1105. int err;
  1106. if (!pt->kernel_start) {
  1107. pt->kernel_start = machine__kernel_start(pt->machine);
  1108. if (pt->per_cpu_mmaps &&
  1109. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1110. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1111. !pt->sampling_mode) {
  1112. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1113. if (pt->switch_ip) {
  1114. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1115. pt->switch_ip, pt->ptss_ip);
  1116. pt->sync_switch = true;
  1117. }
  1118. }
  1119. }
  1120. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1121. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1122. while (1) {
  1123. err = intel_pt_sample(ptq);
  1124. if (err)
  1125. return err;
  1126. state = intel_pt_decode(ptq->decoder);
  1127. if (state->err) {
  1128. if (state->err == INTEL_PT_ERR_NODATA)
  1129. return 1;
  1130. if (pt->sync_switch &&
  1131. state->from_ip >= pt->kernel_start) {
  1132. pt->sync_switch = false;
  1133. intel_pt_next_tid(pt, ptq);
  1134. }
  1135. if (pt->synth_opts.errors) {
  1136. err = intel_pt_synth_error(pt, state->err,
  1137. ptq->cpu, ptq->pid,
  1138. ptq->tid,
  1139. state->from_ip);
  1140. if (err)
  1141. return err;
  1142. }
  1143. continue;
  1144. }
  1145. ptq->state = state;
  1146. ptq->have_sample = true;
  1147. intel_pt_sample_flags(ptq);
  1148. /* Use estimated TSC upon return to user space */
  1149. if (pt->est_tsc &&
  1150. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1151. state->to_ip && state->to_ip < pt->kernel_start) {
  1152. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1153. state->timestamp, state->est_timestamp);
  1154. ptq->timestamp = state->est_timestamp;
  1155. /* Use estimated TSC in unknown switch state */
  1156. } else if (pt->sync_switch &&
  1157. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1158. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1159. ptq->next_tid == -1) {
  1160. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1161. state->timestamp, state->est_timestamp);
  1162. ptq->timestamp = state->est_timestamp;
  1163. } else if (state->timestamp > ptq->timestamp) {
  1164. ptq->timestamp = state->timestamp;
  1165. }
  1166. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1167. *timestamp = ptq->timestamp;
  1168. return 0;
  1169. }
  1170. }
  1171. return 0;
  1172. }
  1173. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1174. {
  1175. if (pt->queues.new_data) {
  1176. pt->queues.new_data = false;
  1177. return intel_pt_setup_queues(pt);
  1178. }
  1179. return 0;
  1180. }
  1181. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1182. {
  1183. unsigned int queue_nr;
  1184. u64 ts;
  1185. int ret;
  1186. while (1) {
  1187. struct auxtrace_queue *queue;
  1188. struct intel_pt_queue *ptq;
  1189. if (!pt->heap.heap_cnt)
  1190. return 0;
  1191. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1192. return 0;
  1193. queue_nr = pt->heap.heap_array[0].queue_nr;
  1194. queue = &pt->queues.queue_array[queue_nr];
  1195. ptq = queue->priv;
  1196. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1197. queue_nr, pt->heap.heap_array[0].ordinal,
  1198. timestamp);
  1199. auxtrace_heap__pop(&pt->heap);
  1200. if (pt->heap.heap_cnt) {
  1201. ts = pt->heap.heap_array[0].ordinal + 1;
  1202. if (ts > timestamp)
  1203. ts = timestamp;
  1204. } else {
  1205. ts = timestamp;
  1206. }
  1207. intel_pt_set_pid_tid_cpu(pt, queue);
  1208. ret = intel_pt_run_decoder(ptq, &ts);
  1209. if (ret < 0) {
  1210. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1211. return ret;
  1212. }
  1213. if (!ret) {
  1214. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1215. if (ret < 0)
  1216. return ret;
  1217. } else {
  1218. ptq->on_heap = false;
  1219. }
  1220. }
  1221. return 0;
  1222. }
  1223. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1224. u64 time_)
  1225. {
  1226. struct auxtrace_queues *queues = &pt->queues;
  1227. unsigned int i;
  1228. u64 ts = 0;
  1229. for (i = 0; i < queues->nr_queues; i++) {
  1230. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1231. struct intel_pt_queue *ptq = queue->priv;
  1232. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1233. ptq->time = time_;
  1234. intel_pt_set_pid_tid_cpu(pt, queue);
  1235. intel_pt_run_decoder(ptq, &ts);
  1236. }
  1237. }
  1238. return 0;
  1239. }
  1240. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1241. {
  1242. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1243. sample->pid, sample->tid, 0);
  1244. }
  1245. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1246. {
  1247. unsigned i, j;
  1248. if (cpu < 0 || !pt->queues.nr_queues)
  1249. return NULL;
  1250. if ((unsigned)cpu >= pt->queues.nr_queues)
  1251. i = pt->queues.nr_queues - 1;
  1252. else
  1253. i = cpu;
  1254. if (pt->queues.queue_array[i].cpu == cpu)
  1255. return pt->queues.queue_array[i].priv;
  1256. for (j = 0; i > 0; j++) {
  1257. if (pt->queues.queue_array[--i].cpu == cpu)
  1258. return pt->queues.queue_array[i].priv;
  1259. }
  1260. for (; j < pt->queues.nr_queues; j++) {
  1261. if (pt->queues.queue_array[j].cpu == cpu)
  1262. return pt->queues.queue_array[j].priv;
  1263. }
  1264. return NULL;
  1265. }
  1266. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1267. u64 timestamp)
  1268. {
  1269. struct intel_pt_queue *ptq;
  1270. int err;
  1271. if (!pt->sync_switch)
  1272. return 1;
  1273. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1274. if (!ptq)
  1275. return 1;
  1276. switch (ptq->switch_state) {
  1277. case INTEL_PT_SS_NOT_TRACING:
  1278. ptq->next_tid = -1;
  1279. break;
  1280. case INTEL_PT_SS_UNKNOWN:
  1281. case INTEL_PT_SS_TRACING:
  1282. ptq->next_tid = tid;
  1283. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1284. return 0;
  1285. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1286. if (!ptq->on_heap) {
  1287. ptq->timestamp = perf_time_to_tsc(timestamp,
  1288. &pt->tc);
  1289. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1290. ptq->timestamp);
  1291. if (err)
  1292. return err;
  1293. ptq->on_heap = true;
  1294. }
  1295. ptq->switch_state = INTEL_PT_SS_TRACING;
  1296. break;
  1297. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1298. ptq->next_tid = tid;
  1299. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1300. break;
  1301. default:
  1302. break;
  1303. }
  1304. return 1;
  1305. }
  1306. static int intel_pt_process_switch(struct intel_pt *pt,
  1307. struct perf_sample *sample)
  1308. {
  1309. struct perf_evsel *evsel;
  1310. pid_t tid;
  1311. int cpu, ret;
  1312. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1313. if (evsel != pt->switch_evsel)
  1314. return 0;
  1315. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1316. cpu = sample->cpu;
  1317. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1318. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1319. &pt->tc));
  1320. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1321. if (ret <= 0)
  1322. return ret;
  1323. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1324. }
  1325. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1326. struct perf_sample *sample)
  1327. {
  1328. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1329. pid_t pid, tid;
  1330. int cpu, ret;
  1331. cpu = sample->cpu;
  1332. if (pt->have_sched_switch == 3) {
  1333. if (!out)
  1334. return 0;
  1335. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1336. pr_err("Expecting CPU-wide context switch event\n");
  1337. return -EINVAL;
  1338. }
  1339. pid = event->context_switch.next_prev_pid;
  1340. tid = event->context_switch.next_prev_tid;
  1341. } else {
  1342. if (out)
  1343. return 0;
  1344. pid = sample->pid;
  1345. tid = sample->tid;
  1346. }
  1347. if (tid == -1) {
  1348. pr_err("context_switch event has no tid\n");
  1349. return -EINVAL;
  1350. }
  1351. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1352. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1353. &pt->tc));
  1354. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1355. if (ret <= 0)
  1356. return ret;
  1357. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1358. }
  1359. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1360. union perf_event *event,
  1361. struct perf_sample *sample)
  1362. {
  1363. if (!pt->per_cpu_mmaps)
  1364. return 0;
  1365. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1366. sample->cpu, event->itrace_start.pid,
  1367. event->itrace_start.tid, sample->time,
  1368. perf_time_to_tsc(sample->time, &pt->tc));
  1369. return machine__set_current_tid(pt->machine, sample->cpu,
  1370. event->itrace_start.pid,
  1371. event->itrace_start.tid);
  1372. }
  1373. static int intel_pt_process_event(struct perf_session *session,
  1374. union perf_event *event,
  1375. struct perf_sample *sample,
  1376. struct perf_tool *tool)
  1377. {
  1378. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1379. auxtrace);
  1380. u64 timestamp;
  1381. int err = 0;
  1382. if (dump_trace)
  1383. return 0;
  1384. if (!tool->ordered_events) {
  1385. pr_err("Intel Processor Trace requires ordered events\n");
  1386. return -EINVAL;
  1387. }
  1388. if (sample->time && sample->time != (u64)-1)
  1389. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1390. else
  1391. timestamp = 0;
  1392. if (timestamp || pt->timeless_decoding) {
  1393. err = intel_pt_update_queues(pt);
  1394. if (err)
  1395. return err;
  1396. }
  1397. if (pt->timeless_decoding) {
  1398. if (event->header.type == PERF_RECORD_EXIT) {
  1399. err = intel_pt_process_timeless_queues(pt,
  1400. event->fork.tid,
  1401. sample->time);
  1402. }
  1403. } else if (timestamp) {
  1404. err = intel_pt_process_queues(pt, timestamp);
  1405. }
  1406. if (err)
  1407. return err;
  1408. if (event->header.type == PERF_RECORD_AUX &&
  1409. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1410. pt->synth_opts.errors) {
  1411. err = intel_pt_lost(pt, sample);
  1412. if (err)
  1413. return err;
  1414. }
  1415. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1416. err = intel_pt_process_switch(pt, sample);
  1417. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1418. err = intel_pt_process_itrace_start(pt, event, sample);
  1419. else if (event->header.type == PERF_RECORD_SWITCH ||
  1420. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1421. err = intel_pt_context_switch(pt, event, sample);
  1422. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1423. perf_event__name(event->header.type), event->header.type,
  1424. sample->cpu, sample->time, timestamp);
  1425. return err;
  1426. }
  1427. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1428. {
  1429. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1430. auxtrace);
  1431. int ret;
  1432. if (dump_trace)
  1433. return 0;
  1434. if (!tool->ordered_events)
  1435. return -EINVAL;
  1436. ret = intel_pt_update_queues(pt);
  1437. if (ret < 0)
  1438. return ret;
  1439. if (pt->timeless_decoding)
  1440. return intel_pt_process_timeless_queues(pt, -1,
  1441. MAX_TIMESTAMP - 1);
  1442. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1443. }
  1444. static void intel_pt_free_events(struct perf_session *session)
  1445. {
  1446. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1447. auxtrace);
  1448. struct auxtrace_queues *queues = &pt->queues;
  1449. unsigned int i;
  1450. for (i = 0; i < queues->nr_queues; i++) {
  1451. intel_pt_free_queue(queues->queue_array[i].priv);
  1452. queues->queue_array[i].priv = NULL;
  1453. }
  1454. intel_pt_log_disable();
  1455. auxtrace_queues__free(queues);
  1456. }
  1457. static void intel_pt_free(struct perf_session *session)
  1458. {
  1459. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1460. auxtrace);
  1461. auxtrace_heap__free(&pt->heap);
  1462. intel_pt_free_events(session);
  1463. session->auxtrace = NULL;
  1464. thread__put(pt->unknown_thread);
  1465. free(pt);
  1466. }
  1467. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1468. union perf_event *event,
  1469. struct perf_tool *tool __maybe_unused)
  1470. {
  1471. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1472. auxtrace);
  1473. if (pt->sampling_mode)
  1474. return 0;
  1475. if (!pt->data_queued) {
  1476. struct auxtrace_buffer *buffer;
  1477. off_t data_offset;
  1478. int fd = perf_data_file__fd(session->file);
  1479. int err;
  1480. if (perf_data_file__is_pipe(session->file)) {
  1481. data_offset = 0;
  1482. } else {
  1483. data_offset = lseek(fd, 0, SEEK_CUR);
  1484. if (data_offset == -1)
  1485. return -errno;
  1486. }
  1487. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1488. data_offset, &buffer);
  1489. if (err)
  1490. return err;
  1491. /* Dump here now we have copied a piped trace out of the pipe */
  1492. if (dump_trace) {
  1493. if (auxtrace_buffer__get_data(buffer, fd)) {
  1494. intel_pt_dump_event(pt, buffer->data,
  1495. buffer->size);
  1496. auxtrace_buffer__put_data(buffer);
  1497. }
  1498. }
  1499. }
  1500. return 0;
  1501. }
  1502. struct intel_pt_synth {
  1503. struct perf_tool dummy_tool;
  1504. struct perf_session *session;
  1505. };
  1506. static int intel_pt_event_synth(struct perf_tool *tool,
  1507. union perf_event *event,
  1508. struct perf_sample *sample __maybe_unused,
  1509. struct machine *machine __maybe_unused)
  1510. {
  1511. struct intel_pt_synth *intel_pt_synth =
  1512. container_of(tool, struct intel_pt_synth, dummy_tool);
  1513. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1514. NULL);
  1515. }
  1516. static int intel_pt_synth_event(struct perf_session *session,
  1517. struct perf_event_attr *attr, u64 id)
  1518. {
  1519. struct intel_pt_synth intel_pt_synth;
  1520. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1521. intel_pt_synth.session = session;
  1522. return perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1523. &id, intel_pt_event_synth);
  1524. }
  1525. static int intel_pt_synth_events(struct intel_pt *pt,
  1526. struct perf_session *session)
  1527. {
  1528. struct perf_evlist *evlist = session->evlist;
  1529. struct perf_evsel *evsel;
  1530. struct perf_event_attr attr;
  1531. bool found = false;
  1532. u64 id;
  1533. int err;
  1534. evlist__for_each(evlist, evsel) {
  1535. if (evsel->attr.type == pt->pmu_type && evsel->ids) {
  1536. found = true;
  1537. break;
  1538. }
  1539. }
  1540. if (!found) {
  1541. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1542. return 0;
  1543. }
  1544. memset(&attr, 0, sizeof(struct perf_event_attr));
  1545. attr.size = sizeof(struct perf_event_attr);
  1546. attr.type = PERF_TYPE_HARDWARE;
  1547. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1548. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1549. PERF_SAMPLE_PERIOD;
  1550. if (pt->timeless_decoding)
  1551. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1552. else
  1553. attr.sample_type |= PERF_SAMPLE_TIME;
  1554. if (!pt->per_cpu_mmaps)
  1555. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1556. attr.exclude_user = evsel->attr.exclude_user;
  1557. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1558. attr.exclude_hv = evsel->attr.exclude_hv;
  1559. attr.exclude_host = evsel->attr.exclude_host;
  1560. attr.exclude_guest = evsel->attr.exclude_guest;
  1561. attr.sample_id_all = evsel->attr.sample_id_all;
  1562. attr.read_format = evsel->attr.read_format;
  1563. id = evsel->id[0] + 1000000000;
  1564. if (!id)
  1565. id = 1;
  1566. if (pt->synth_opts.instructions) {
  1567. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1568. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1569. attr.sample_period =
  1570. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1571. else
  1572. attr.sample_period = pt->synth_opts.period;
  1573. pt->instructions_sample_period = attr.sample_period;
  1574. if (pt->synth_opts.callchain)
  1575. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1576. if (pt->synth_opts.last_branch)
  1577. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1578. pr_debug("Synthesizing 'instructions' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1579. id, (u64)attr.sample_type);
  1580. err = intel_pt_synth_event(session, &attr, id);
  1581. if (err) {
  1582. pr_err("%s: failed to synthesize 'instructions' event type\n",
  1583. __func__);
  1584. return err;
  1585. }
  1586. pt->sample_instructions = true;
  1587. pt->instructions_sample_type = attr.sample_type;
  1588. pt->instructions_id = id;
  1589. id += 1;
  1590. }
  1591. if (pt->synth_opts.transactions) {
  1592. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1593. attr.sample_period = 1;
  1594. if (pt->synth_opts.callchain)
  1595. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1596. if (pt->synth_opts.last_branch)
  1597. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1598. pr_debug("Synthesizing 'transactions' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1599. id, (u64)attr.sample_type);
  1600. err = intel_pt_synth_event(session, &attr, id);
  1601. if (err) {
  1602. pr_err("%s: failed to synthesize 'transactions' event type\n",
  1603. __func__);
  1604. return err;
  1605. }
  1606. pt->sample_transactions = true;
  1607. pt->transactions_id = id;
  1608. id += 1;
  1609. evlist__for_each(evlist, evsel) {
  1610. if (evsel->id && evsel->id[0] == pt->transactions_id) {
  1611. if (evsel->name)
  1612. zfree(&evsel->name);
  1613. evsel->name = strdup("transactions");
  1614. break;
  1615. }
  1616. }
  1617. }
  1618. if (pt->synth_opts.branches) {
  1619. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1620. attr.sample_period = 1;
  1621. attr.sample_type |= PERF_SAMPLE_ADDR;
  1622. attr.sample_type &= ~(u64)PERF_SAMPLE_CALLCHAIN;
  1623. attr.sample_type &= ~(u64)PERF_SAMPLE_BRANCH_STACK;
  1624. pr_debug("Synthesizing 'branches' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1625. id, (u64)attr.sample_type);
  1626. err = intel_pt_synth_event(session, &attr, id);
  1627. if (err) {
  1628. pr_err("%s: failed to synthesize 'branches' event type\n",
  1629. __func__);
  1630. return err;
  1631. }
  1632. pt->sample_branches = true;
  1633. pt->branches_sample_type = attr.sample_type;
  1634. pt->branches_id = id;
  1635. }
  1636. pt->synth_needs_swap = evsel->needs_swap;
  1637. return 0;
  1638. }
  1639. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1640. {
  1641. struct perf_evsel *evsel;
  1642. evlist__for_each_reverse(evlist, evsel) {
  1643. const char *name = perf_evsel__name(evsel);
  1644. if (!strcmp(name, "sched:sched_switch"))
  1645. return evsel;
  1646. }
  1647. return NULL;
  1648. }
  1649. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1650. {
  1651. struct perf_evsel *evsel;
  1652. evlist__for_each(evlist, evsel) {
  1653. if (evsel->attr.context_switch)
  1654. return true;
  1655. }
  1656. return false;
  1657. }
  1658. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1659. {
  1660. struct intel_pt *pt = data;
  1661. if (!strcmp(var, "intel-pt.mispred-all"))
  1662. pt->mispred_all = perf_config_bool(var, value);
  1663. return 0;
  1664. }
  1665. static const char * const intel_pt_info_fmts[] = {
  1666. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1667. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1668. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1669. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1670. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1671. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1672. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1673. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1674. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1675. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1676. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1677. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1678. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1679. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1680. };
  1681. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1682. {
  1683. int i;
  1684. if (!dump_trace)
  1685. return;
  1686. for (i = start; i <= finish; i++)
  1687. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1688. }
  1689. int intel_pt_process_auxtrace_info(union perf_event *event,
  1690. struct perf_session *session)
  1691. {
  1692. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1693. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1694. struct intel_pt *pt;
  1695. int err;
  1696. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1697. min_sz)
  1698. return -EINVAL;
  1699. pt = zalloc(sizeof(struct intel_pt));
  1700. if (!pt)
  1701. return -ENOMEM;
  1702. perf_config(intel_pt_perf_config, pt);
  1703. err = auxtrace_queues__init(&pt->queues);
  1704. if (err)
  1705. goto err_free;
  1706. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1707. pt->session = session;
  1708. pt->machine = &session->machines.host; /* No kvm support */
  1709. pt->auxtrace_type = auxtrace_info->type;
  1710. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  1711. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  1712. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  1713. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  1714. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  1715. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  1716. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  1717. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  1718. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  1719. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  1720. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  1721. INTEL_PT_PER_CPU_MMAPS);
  1722. if (auxtrace_info->header.size >= sizeof(struct auxtrace_info_event) +
  1723. (sizeof(u64) * INTEL_PT_CYC_BIT)) {
  1724. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  1725. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  1726. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  1727. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  1728. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  1729. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  1730. INTEL_PT_CYC_BIT);
  1731. }
  1732. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  1733. pt->have_tsc = intel_pt_have_tsc(pt);
  1734. pt->sampling_mode = false;
  1735. pt->est_tsc = !pt->timeless_decoding;
  1736. pt->unknown_thread = thread__new(999999999, 999999999);
  1737. if (!pt->unknown_thread) {
  1738. err = -ENOMEM;
  1739. goto err_free_queues;
  1740. }
  1741. /*
  1742. * Since this thread will not be kept in any rbtree not in a
  1743. * list, initialize its list node so that at thread__put() the
  1744. * current thread lifetime assuption is kept and we don't segfault
  1745. * at list_del_init().
  1746. */
  1747. INIT_LIST_HEAD(&pt->unknown_thread->node);
  1748. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  1749. if (err)
  1750. goto err_delete_thread;
  1751. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  1752. err = -ENOMEM;
  1753. goto err_delete_thread;
  1754. }
  1755. pt->auxtrace.process_event = intel_pt_process_event;
  1756. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  1757. pt->auxtrace.flush_events = intel_pt_flush;
  1758. pt->auxtrace.free_events = intel_pt_free_events;
  1759. pt->auxtrace.free = intel_pt_free;
  1760. session->auxtrace = &pt->auxtrace;
  1761. if (dump_trace)
  1762. return 0;
  1763. if (pt->have_sched_switch == 1) {
  1764. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  1765. if (!pt->switch_evsel) {
  1766. pr_err("%s: missing sched_switch event\n", __func__);
  1767. goto err_delete_thread;
  1768. }
  1769. } else if (pt->have_sched_switch == 2 &&
  1770. !intel_pt_find_switch(session->evlist)) {
  1771. pr_err("%s: missing context_switch attribute flag\n", __func__);
  1772. goto err_delete_thread;
  1773. }
  1774. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  1775. pt->synth_opts = *session->itrace_synth_opts;
  1776. } else {
  1777. itrace_synth_opts__set_default(&pt->synth_opts);
  1778. if (use_browser != -1) {
  1779. pt->synth_opts.branches = false;
  1780. pt->synth_opts.callchain = true;
  1781. }
  1782. }
  1783. if (pt->synth_opts.log)
  1784. intel_pt_log_enable();
  1785. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  1786. if (pt->tc.time_mult) {
  1787. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  1788. pt->max_non_turbo_ratio = (tsc_freq + 50000000) / 100000000;
  1789. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  1790. intel_pt_log("Maximum non-turbo ratio %u\n",
  1791. pt->max_non_turbo_ratio);
  1792. }
  1793. if (pt->synth_opts.calls)
  1794. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  1795. PERF_IP_FLAG_TRACE_END;
  1796. if (pt->synth_opts.returns)
  1797. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  1798. PERF_IP_FLAG_TRACE_BEGIN;
  1799. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  1800. symbol_conf.use_callchain = true;
  1801. if (callchain_register_param(&callchain_param) < 0) {
  1802. symbol_conf.use_callchain = false;
  1803. pt->synth_opts.callchain = false;
  1804. }
  1805. }
  1806. err = intel_pt_synth_events(pt, session);
  1807. if (err)
  1808. goto err_delete_thread;
  1809. err = auxtrace_queues__process_index(&pt->queues, session);
  1810. if (err)
  1811. goto err_delete_thread;
  1812. if (pt->queues.populated)
  1813. pt->data_queued = true;
  1814. if (pt->timeless_decoding)
  1815. pr_debug2("Intel PT decoding without timestamps\n");
  1816. return 0;
  1817. err_delete_thread:
  1818. thread__zput(pt->unknown_thread);
  1819. err_free_queues:
  1820. intel_pt_log_disable();
  1821. auxtrace_queues__free(&pt->queues);
  1822. session->auxtrace = NULL;
  1823. err_free:
  1824. free(pt);
  1825. return err;
  1826. }