gpio-pca953x.c 21 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/acpi.h>
  23. #define PCA953X_INPUT 0
  24. #define PCA953X_OUTPUT 1
  25. #define PCA953X_INVERT 2
  26. #define PCA953X_DIRECTION 3
  27. #define REG_ADDR_AI 0x80
  28. #define PCA957X_IN 0
  29. #define PCA957X_INVRT 1
  30. #define PCA957X_BKEN 2
  31. #define PCA957X_PUPD 3
  32. #define PCA957X_CFG 4
  33. #define PCA957X_OUT 5
  34. #define PCA957X_MSK 6
  35. #define PCA957X_INTS 7
  36. #define PCA_GPIO_MASK 0x00FF
  37. #define PCA_INT 0x0100
  38. #define PCA953X_TYPE 0x1000
  39. #define PCA957X_TYPE 0x2000
  40. #define PCA_TYPE_MASK 0xF000
  41. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  42. static const struct i2c_device_id pca953x_id[] = {
  43. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  44. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  45. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  46. { "pca9536", 4 | PCA953X_TYPE, },
  47. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9556", 8 | PCA953X_TYPE, },
  53. { "pca9557", 8 | PCA953X_TYPE, },
  54. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  55. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  56. { "pca9698", 40 | PCA953X_TYPE, },
  57. { "max7310", 8 | PCA953X_TYPE, },
  58. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  59. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  60. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  61. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  62. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  63. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  64. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  65. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  66. { "xra1202", 8 | PCA953X_TYPE },
  67. { }
  68. };
  69. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  70. static const struct acpi_device_id pca953x_acpi_ids[] = {
  71. { "INT3491", 16 | PCA953X_TYPE | PCA_INT, },
  72. { }
  73. };
  74. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  75. #define MAX_BANK 5
  76. #define BANK_SZ 8
  77. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  78. struct pca953x_chip {
  79. unsigned gpio_start;
  80. u8 reg_output[MAX_BANK];
  81. u8 reg_direction[MAX_BANK];
  82. struct mutex i2c_lock;
  83. #ifdef CONFIG_GPIO_PCA953X_IRQ
  84. struct mutex irq_lock;
  85. u8 irq_mask[MAX_BANK];
  86. u8 irq_stat[MAX_BANK];
  87. u8 irq_trig_raise[MAX_BANK];
  88. u8 irq_trig_fall[MAX_BANK];
  89. #endif
  90. struct i2c_client *client;
  91. struct gpio_chip gpio_chip;
  92. const char *const *names;
  93. int chip_type;
  94. unsigned long driver_data;
  95. };
  96. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  97. int off)
  98. {
  99. int ret;
  100. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  101. int offset = off / BANK_SZ;
  102. ret = i2c_smbus_read_byte_data(chip->client,
  103. (reg << bank_shift) + offset);
  104. *val = ret;
  105. if (ret < 0) {
  106. dev_err(&chip->client->dev, "failed reading register\n");
  107. return ret;
  108. }
  109. return 0;
  110. }
  111. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  112. int off)
  113. {
  114. int ret = 0;
  115. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  116. int offset = off / BANK_SZ;
  117. ret = i2c_smbus_write_byte_data(chip->client,
  118. (reg << bank_shift) + offset, val);
  119. if (ret < 0) {
  120. dev_err(&chip->client->dev, "failed writing register\n");
  121. return ret;
  122. }
  123. return 0;
  124. }
  125. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  126. {
  127. int ret = 0;
  128. if (chip->gpio_chip.ngpio <= 8)
  129. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  130. else if (chip->gpio_chip.ngpio >= 24) {
  131. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  132. ret = i2c_smbus_write_i2c_block_data(chip->client,
  133. (reg << bank_shift) | REG_ADDR_AI,
  134. NBANK(chip), val);
  135. } else {
  136. switch (chip->chip_type) {
  137. case PCA953X_TYPE:
  138. ret = i2c_smbus_write_word_data(chip->client,
  139. reg << 1, cpu_to_le16(get_unaligned((u16 *)val)));
  140. break;
  141. case PCA957X_TYPE:
  142. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  143. val[0]);
  144. if (ret < 0)
  145. break;
  146. ret = i2c_smbus_write_byte_data(chip->client,
  147. (reg << 1) + 1,
  148. val[1]);
  149. break;
  150. }
  151. }
  152. if (ret < 0) {
  153. dev_err(&chip->client->dev, "failed writing register\n");
  154. return ret;
  155. }
  156. return 0;
  157. }
  158. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  159. {
  160. int ret;
  161. if (chip->gpio_chip.ngpio <= 8) {
  162. ret = i2c_smbus_read_byte_data(chip->client, reg);
  163. *val = ret;
  164. } else if (chip->gpio_chip.ngpio >= 24) {
  165. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  166. ret = i2c_smbus_read_i2c_block_data(chip->client,
  167. (reg << bank_shift) | REG_ADDR_AI,
  168. NBANK(chip), val);
  169. } else {
  170. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  171. val[0] = (u16)ret & 0xFF;
  172. val[1] = (u16)ret >> 8;
  173. }
  174. if (ret < 0) {
  175. dev_err(&chip->client->dev, "failed reading register\n");
  176. return ret;
  177. }
  178. return 0;
  179. }
  180. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  181. {
  182. struct pca953x_chip *chip = gpiochip_get_data(gc);
  183. u8 reg_val;
  184. int ret, offset = 0;
  185. mutex_lock(&chip->i2c_lock);
  186. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  187. switch (chip->chip_type) {
  188. case PCA953X_TYPE:
  189. offset = PCA953X_DIRECTION;
  190. break;
  191. case PCA957X_TYPE:
  192. offset = PCA957X_CFG;
  193. break;
  194. }
  195. ret = pca953x_write_single(chip, offset, reg_val, off);
  196. if (ret)
  197. goto exit;
  198. chip->reg_direction[off / BANK_SZ] = reg_val;
  199. ret = 0;
  200. exit:
  201. mutex_unlock(&chip->i2c_lock);
  202. return ret;
  203. }
  204. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  205. unsigned off, int val)
  206. {
  207. struct pca953x_chip *chip = gpiochip_get_data(gc);
  208. u8 reg_val;
  209. int ret, offset = 0;
  210. mutex_lock(&chip->i2c_lock);
  211. /* set output level */
  212. if (val)
  213. reg_val = chip->reg_output[off / BANK_SZ]
  214. | (1u << (off % BANK_SZ));
  215. else
  216. reg_val = chip->reg_output[off / BANK_SZ]
  217. & ~(1u << (off % BANK_SZ));
  218. switch (chip->chip_type) {
  219. case PCA953X_TYPE:
  220. offset = PCA953X_OUTPUT;
  221. break;
  222. case PCA957X_TYPE:
  223. offset = PCA957X_OUT;
  224. break;
  225. }
  226. ret = pca953x_write_single(chip, offset, reg_val, off);
  227. if (ret)
  228. goto exit;
  229. chip->reg_output[off / BANK_SZ] = reg_val;
  230. /* then direction */
  231. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  232. switch (chip->chip_type) {
  233. case PCA953X_TYPE:
  234. offset = PCA953X_DIRECTION;
  235. break;
  236. case PCA957X_TYPE:
  237. offset = PCA957X_CFG;
  238. break;
  239. }
  240. ret = pca953x_write_single(chip, offset, reg_val, off);
  241. if (ret)
  242. goto exit;
  243. chip->reg_direction[off / BANK_SZ] = reg_val;
  244. ret = 0;
  245. exit:
  246. mutex_unlock(&chip->i2c_lock);
  247. return ret;
  248. }
  249. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  250. {
  251. struct pca953x_chip *chip = gpiochip_get_data(gc);
  252. u32 reg_val;
  253. int ret, offset = 0;
  254. mutex_lock(&chip->i2c_lock);
  255. switch (chip->chip_type) {
  256. case PCA953X_TYPE:
  257. offset = PCA953X_INPUT;
  258. break;
  259. case PCA957X_TYPE:
  260. offset = PCA957X_IN;
  261. break;
  262. }
  263. ret = pca953x_read_single(chip, offset, &reg_val, off);
  264. mutex_unlock(&chip->i2c_lock);
  265. if (ret < 0) {
  266. /* NOTE: diagnostic already emitted; that's all we should
  267. * do unless gpio_*_value_cansleep() calls become different
  268. * from their nonsleeping siblings (and report faults).
  269. */
  270. return 0;
  271. }
  272. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  273. }
  274. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  275. {
  276. struct pca953x_chip *chip = gpiochip_get_data(gc);
  277. u8 reg_val;
  278. int ret, offset = 0;
  279. mutex_lock(&chip->i2c_lock);
  280. if (val)
  281. reg_val = chip->reg_output[off / BANK_SZ]
  282. | (1u << (off % BANK_SZ));
  283. else
  284. reg_val = chip->reg_output[off / BANK_SZ]
  285. & ~(1u << (off % BANK_SZ));
  286. switch (chip->chip_type) {
  287. case PCA953X_TYPE:
  288. offset = PCA953X_OUTPUT;
  289. break;
  290. case PCA957X_TYPE:
  291. offset = PCA957X_OUT;
  292. break;
  293. }
  294. ret = pca953x_write_single(chip, offset, reg_val, off);
  295. if (ret)
  296. goto exit;
  297. chip->reg_output[off / BANK_SZ] = reg_val;
  298. exit:
  299. mutex_unlock(&chip->i2c_lock);
  300. }
  301. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  302. unsigned long *mask, unsigned long *bits)
  303. {
  304. struct pca953x_chip *chip = gpiochip_get_data(gc);
  305. u8 reg_val[MAX_BANK];
  306. int ret, offset = 0;
  307. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  308. int bank;
  309. switch (chip->chip_type) {
  310. case PCA953X_TYPE:
  311. offset = PCA953X_OUTPUT;
  312. break;
  313. case PCA957X_TYPE:
  314. offset = PCA957X_OUT;
  315. break;
  316. }
  317. memcpy(reg_val, chip->reg_output, NBANK(chip));
  318. mutex_lock(&chip->i2c_lock);
  319. for(bank=0; bank<NBANK(chip); bank++) {
  320. unsigned bankmask = mask[bank / sizeof(*mask)] >>
  321. ((bank % sizeof(*mask)) * 8);
  322. if(bankmask) {
  323. unsigned bankval = bits[bank / sizeof(*bits)] >>
  324. ((bank % sizeof(*bits)) * 8);
  325. reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
  326. }
  327. }
  328. ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
  329. if (ret)
  330. goto exit;
  331. memcpy(chip->reg_output, reg_val, NBANK(chip));
  332. exit:
  333. mutex_unlock(&chip->i2c_lock);
  334. }
  335. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  336. {
  337. struct gpio_chip *gc;
  338. gc = &chip->gpio_chip;
  339. gc->direction_input = pca953x_gpio_direction_input;
  340. gc->direction_output = pca953x_gpio_direction_output;
  341. gc->get = pca953x_gpio_get_value;
  342. gc->set = pca953x_gpio_set_value;
  343. gc->set_multiple = pca953x_gpio_set_multiple;
  344. gc->can_sleep = true;
  345. gc->base = chip->gpio_start;
  346. gc->ngpio = gpios;
  347. gc->label = chip->client->name;
  348. gc->parent = &chip->client->dev;
  349. gc->owner = THIS_MODULE;
  350. gc->names = chip->names;
  351. }
  352. #ifdef CONFIG_GPIO_PCA953X_IRQ
  353. static void pca953x_irq_mask(struct irq_data *d)
  354. {
  355. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  356. struct pca953x_chip *chip = gpiochip_get_data(gc);
  357. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  358. }
  359. static void pca953x_irq_unmask(struct irq_data *d)
  360. {
  361. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  362. struct pca953x_chip *chip = gpiochip_get_data(gc);
  363. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  364. }
  365. static void pca953x_irq_bus_lock(struct irq_data *d)
  366. {
  367. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  368. struct pca953x_chip *chip = gpiochip_get_data(gc);
  369. mutex_lock(&chip->irq_lock);
  370. }
  371. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  372. {
  373. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  374. struct pca953x_chip *chip = gpiochip_get_data(gc);
  375. u8 new_irqs;
  376. int level, i;
  377. /* Look for any newly setup interrupt */
  378. for (i = 0; i < NBANK(chip); i++) {
  379. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  380. new_irqs &= ~chip->reg_direction[i];
  381. while (new_irqs) {
  382. level = __ffs(new_irqs);
  383. pca953x_gpio_direction_input(&chip->gpio_chip,
  384. level + (BANK_SZ * i));
  385. new_irqs &= ~(1 << level);
  386. }
  387. }
  388. mutex_unlock(&chip->irq_lock);
  389. }
  390. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  391. {
  392. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  393. struct pca953x_chip *chip = gpiochip_get_data(gc);
  394. int bank_nb = d->hwirq / BANK_SZ;
  395. u8 mask = 1 << (d->hwirq % BANK_SZ);
  396. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  397. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  398. d->irq, type);
  399. return -EINVAL;
  400. }
  401. if (type & IRQ_TYPE_EDGE_FALLING)
  402. chip->irq_trig_fall[bank_nb] |= mask;
  403. else
  404. chip->irq_trig_fall[bank_nb] &= ~mask;
  405. if (type & IRQ_TYPE_EDGE_RISING)
  406. chip->irq_trig_raise[bank_nb] |= mask;
  407. else
  408. chip->irq_trig_raise[bank_nb] &= ~mask;
  409. return 0;
  410. }
  411. static struct irq_chip pca953x_irq_chip = {
  412. .name = "pca953x",
  413. .irq_mask = pca953x_irq_mask,
  414. .irq_unmask = pca953x_irq_unmask,
  415. .irq_bus_lock = pca953x_irq_bus_lock,
  416. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  417. .irq_set_type = pca953x_irq_set_type,
  418. };
  419. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  420. {
  421. u8 cur_stat[MAX_BANK];
  422. u8 old_stat[MAX_BANK];
  423. bool pending_seen = false;
  424. bool trigger_seen = false;
  425. u8 trigger[MAX_BANK];
  426. int ret, i, offset = 0;
  427. switch (chip->chip_type) {
  428. case PCA953X_TYPE:
  429. offset = PCA953X_INPUT;
  430. break;
  431. case PCA957X_TYPE:
  432. offset = PCA957X_IN;
  433. break;
  434. }
  435. ret = pca953x_read_regs(chip, offset, cur_stat);
  436. if (ret)
  437. return false;
  438. /* Remove output pins from the equation */
  439. for (i = 0; i < NBANK(chip); i++)
  440. cur_stat[i] &= chip->reg_direction[i];
  441. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  442. for (i = 0; i < NBANK(chip); i++) {
  443. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  444. if (trigger[i])
  445. trigger_seen = true;
  446. }
  447. if (!trigger_seen)
  448. return false;
  449. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  450. for (i = 0; i < NBANK(chip); i++) {
  451. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  452. (cur_stat[i] & chip->irq_trig_raise[i]);
  453. pending[i] &= trigger[i];
  454. if (pending[i])
  455. pending_seen = true;
  456. }
  457. return pending_seen;
  458. }
  459. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  460. {
  461. struct pca953x_chip *chip = devid;
  462. u8 pending[MAX_BANK];
  463. u8 level;
  464. unsigned nhandled = 0;
  465. int i;
  466. if (!pca953x_irq_pending(chip, pending))
  467. return IRQ_NONE;
  468. for (i = 0; i < NBANK(chip); i++) {
  469. while (pending[i]) {
  470. level = __ffs(pending[i]);
  471. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  472. level + (BANK_SZ * i)));
  473. pending[i] &= ~(1 << level);
  474. nhandled++;
  475. }
  476. }
  477. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  478. }
  479. static int pca953x_irq_setup(struct pca953x_chip *chip,
  480. int irq_base)
  481. {
  482. struct i2c_client *client = chip->client;
  483. int ret, i, offset = 0;
  484. if (client->irq && irq_base != -1
  485. && (chip->driver_data & PCA_INT)) {
  486. switch (chip->chip_type) {
  487. case PCA953X_TYPE:
  488. offset = PCA953X_INPUT;
  489. break;
  490. case PCA957X_TYPE:
  491. offset = PCA957X_IN;
  492. break;
  493. }
  494. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  495. if (ret)
  496. return ret;
  497. /*
  498. * There is no way to know which GPIO line generated the
  499. * interrupt. We have to rely on the previous read for
  500. * this purpose.
  501. */
  502. for (i = 0; i < NBANK(chip); i++)
  503. chip->irq_stat[i] &= chip->reg_direction[i];
  504. mutex_init(&chip->irq_lock);
  505. ret = devm_request_threaded_irq(&client->dev,
  506. client->irq,
  507. NULL,
  508. pca953x_irq_handler,
  509. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  510. IRQF_SHARED,
  511. dev_name(&client->dev), chip);
  512. if (ret) {
  513. dev_err(&client->dev, "failed to request irq %d\n",
  514. client->irq);
  515. return ret;
  516. }
  517. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  518. &pca953x_irq_chip,
  519. irq_base,
  520. handle_simple_irq,
  521. IRQ_TYPE_NONE);
  522. if (ret) {
  523. dev_err(&client->dev,
  524. "could not connect irqchip to gpiochip\n");
  525. return ret;
  526. }
  527. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  528. &pca953x_irq_chip,
  529. client->irq, NULL);
  530. }
  531. return 0;
  532. }
  533. #else /* CONFIG_GPIO_PCA953X_IRQ */
  534. static int pca953x_irq_setup(struct pca953x_chip *chip,
  535. int irq_base)
  536. {
  537. struct i2c_client *client = chip->client;
  538. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  539. dev_warn(&client->dev, "interrupt support not compiled in\n");
  540. return 0;
  541. }
  542. #endif
  543. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  544. {
  545. int ret;
  546. u8 val[MAX_BANK];
  547. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  548. if (ret)
  549. goto out;
  550. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  551. chip->reg_direction);
  552. if (ret)
  553. goto out;
  554. /* set platform specific polarity inversion */
  555. if (invert)
  556. memset(val, 0xFF, NBANK(chip));
  557. else
  558. memset(val, 0, NBANK(chip));
  559. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  560. out:
  561. return ret;
  562. }
  563. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  564. {
  565. int ret;
  566. u8 val[MAX_BANK];
  567. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  568. if (ret)
  569. goto out;
  570. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  571. if (ret)
  572. goto out;
  573. /* set platform specific polarity inversion */
  574. if (invert)
  575. memset(val, 0xFF, NBANK(chip));
  576. else
  577. memset(val, 0, NBANK(chip));
  578. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  579. if (ret)
  580. goto out;
  581. /* To enable register 6, 7 to control pull up and pull down */
  582. memset(val, 0x02, NBANK(chip));
  583. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  584. if (ret)
  585. goto out;
  586. return 0;
  587. out:
  588. return ret;
  589. }
  590. static const struct of_device_id pca953x_dt_ids[];
  591. static int pca953x_probe(struct i2c_client *client,
  592. const struct i2c_device_id *id)
  593. {
  594. struct pca953x_platform_data *pdata;
  595. struct pca953x_chip *chip;
  596. int irq_base = 0;
  597. int ret;
  598. u32 invert = 0;
  599. chip = devm_kzalloc(&client->dev,
  600. sizeof(struct pca953x_chip), GFP_KERNEL);
  601. if (chip == NULL)
  602. return -ENOMEM;
  603. pdata = dev_get_platdata(&client->dev);
  604. if (pdata) {
  605. irq_base = pdata->irq_base;
  606. chip->gpio_start = pdata->gpio_base;
  607. invert = pdata->invert;
  608. chip->names = pdata->names;
  609. } else {
  610. chip->gpio_start = -1;
  611. irq_base = 0;
  612. }
  613. chip->client = client;
  614. if (id) {
  615. chip->driver_data = id->driver_data;
  616. } else {
  617. const struct acpi_device_id *id;
  618. const struct of_device_id *match;
  619. match = of_match_device(pca953x_dt_ids, &client->dev);
  620. if (match) {
  621. chip->driver_data = (int)(uintptr_t)match->data;
  622. } else {
  623. id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  624. if (!id)
  625. return -ENODEV;
  626. chip->driver_data = id->driver_data;
  627. }
  628. }
  629. chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
  630. mutex_init(&chip->i2c_lock);
  631. /* initialize cached registers from their original values.
  632. * we can't share this chip with another i2c master.
  633. */
  634. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  635. if (chip->chip_type == PCA953X_TYPE)
  636. ret = device_pca953x_init(chip, invert);
  637. else
  638. ret = device_pca957x_init(chip, invert);
  639. if (ret)
  640. return ret;
  641. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  642. if (ret)
  643. return ret;
  644. ret = pca953x_irq_setup(chip, irq_base);
  645. if (ret)
  646. return ret;
  647. if (pdata && pdata->setup) {
  648. ret = pdata->setup(client, chip->gpio_chip.base,
  649. chip->gpio_chip.ngpio, pdata->context);
  650. if (ret < 0)
  651. dev_warn(&client->dev, "setup failed, %d\n", ret);
  652. }
  653. i2c_set_clientdata(client, chip);
  654. return 0;
  655. }
  656. static int pca953x_remove(struct i2c_client *client)
  657. {
  658. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  659. struct pca953x_chip *chip = i2c_get_clientdata(client);
  660. int ret = 0;
  661. if (pdata && pdata->teardown) {
  662. ret = pdata->teardown(client, chip->gpio_chip.base,
  663. chip->gpio_chip.ngpio, pdata->context);
  664. if (ret < 0) {
  665. dev_err(&client->dev, "%s failed, %d\n",
  666. "teardown", ret);
  667. return ret;
  668. }
  669. }
  670. return 0;
  671. }
  672. /* convenience to stop overlong match-table lines */
  673. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  674. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  675. static const struct of_device_id pca953x_dt_ids[] = {
  676. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  677. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  678. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  679. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  680. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  681. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  682. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  683. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  684. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  685. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  686. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  687. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  688. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  689. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  690. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  691. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  692. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  693. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  694. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  695. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  696. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  697. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  698. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  699. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  700. { }
  701. };
  702. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  703. static struct i2c_driver pca953x_driver = {
  704. .driver = {
  705. .name = "pca953x",
  706. .of_match_table = pca953x_dt_ids,
  707. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  708. },
  709. .probe = pca953x_probe,
  710. .remove = pca953x_remove,
  711. .id_table = pca953x_id,
  712. };
  713. static int __init pca953x_init(void)
  714. {
  715. return i2c_add_driver(&pca953x_driver);
  716. }
  717. /* register after i2c postcore initcall and before
  718. * subsys initcalls that may rely on these GPIOs
  719. */
  720. subsys_initcall(pca953x_init);
  721. static void __exit pca953x_exit(void)
  722. {
  723. i2c_del_driver(&pca953x_driver);
  724. }
  725. module_exit(pca953x_exit);
  726. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  727. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  728. MODULE_LICENSE("GPL");