dove.dtsi 16 KB

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  1. /include/ "skeleton.dtsi"
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/interrupt-controller/irq.h>
  4. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  5. / {
  6. compatible = "marvell,dove";
  7. model = "Marvell Armada 88AP510 SoC";
  8. interrupt-parent = <&intc>;
  9. aliases {
  10. gpio0 = &gpio0;
  11. gpio1 = &gpio1;
  12. gpio2 = &gpio2;
  13. };
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. cpu0: cpu@0 {
  18. compatible = "marvell,pj4a", "marvell,sheeva-v7";
  19. device_type = "cpu";
  20. next-level-cache = <&l2>;
  21. reg = <0>;
  22. };
  23. };
  24. l2: l2-cache {
  25. compatible = "marvell,tauros2-cache";
  26. marvell,tauros2-cache-features = <0>;
  27. };
  28. i2c-mux {
  29. compatible = "i2c-mux-pinctrl";
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. i2c-parent = <&i2c>;
  33. pinctrl-names = "i2c0", "i2c1", "i2c2";
  34. pinctrl-0 = <&pmx_i2cmux_0>;
  35. pinctrl-1 = <&pmx_i2cmux_1>;
  36. pinctrl-2 = <&pmx_i2cmux_2>;
  37. i2c0: i2c@0 {
  38. reg = <0>;
  39. #address-cells = <1>;
  40. #size-cells = <0>;
  41. status = "okay";
  42. };
  43. i2c1: i2c@1 {
  44. reg = <1>;
  45. #address-cells = <1>;
  46. #size-cells = <0>;
  47. /* Requires pmx_i2c1 on i2c controller node */
  48. status = "disabled";
  49. };
  50. i2c2: i2c@2 {
  51. reg = <2>;
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. /* Requires pmx_i2c2 on i2c controller node */
  55. status = "disabled";
  56. };
  57. };
  58. mbus {
  59. compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
  60. #address-cells = <2>;
  61. #size-cells = <1>;
  62. controller = <&mbusc>;
  63. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
  64. pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
  65. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
  66. MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
  67. MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
  68. MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
  69. MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
  70. pcie: pcie-controller {
  71. compatible = "marvell,dove-pcie";
  72. status = "disabled";
  73. device_type = "pci";
  74. #address-cells = <3>;
  75. #size-cells = <2>;
  76. msi-parent = <&intc>;
  77. bus-range = <0x00 0xff>;
  78. ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
  79. 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
  80. 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
  81. 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
  82. 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
  83. 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
  84. pcie0: pcie-port@0 {
  85. device_type = "pci";
  86. status = "disabled";
  87. assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  88. reg = <0x0800 0 0 0 0>;
  89. clocks = <&gate_clk 4>;
  90. marvell,pcie-port = <0>;
  91. #address-cells = <3>;
  92. #size-cells = <2>;
  93. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  94. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  95. #interrupt-cells = <1>;
  96. interrupt-map-mask = <0 0 0 0>;
  97. interrupt-map = <0 0 0 0 &intc 16>;
  98. };
  99. pcie1: pcie-port@1 {
  100. device_type = "pci";
  101. status = "disabled";
  102. assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
  103. reg = <0x1000 0 0 0 0>;
  104. clocks = <&gate_clk 5>;
  105. marvell,pcie-port = <1>;
  106. #address-cells = <3>;
  107. #size-cells = <2>;
  108. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  109. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  110. #interrupt-cells = <1>;
  111. interrupt-map-mask = <0 0 0 0>;
  112. interrupt-map = <0 0 0 0 &intc 18>;
  113. };
  114. };
  115. internal-regs {
  116. compatible = "simple-bus";
  117. #address-cells = <1>;
  118. #size-cells = <1>;
  119. ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
  120. 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
  121. 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
  122. 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
  123. spi0: spi-ctrl@10600 {
  124. compatible = "marvell,orion-spi";
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. cell-index = <0>;
  128. interrupts = <6>;
  129. reg = <0x10600 0x28>;
  130. clocks = <&core_clk 0>;
  131. pinctrl-0 = <&pmx_spi0>;
  132. pinctrl-names = "default";
  133. status = "disabled";
  134. };
  135. i2c: i2c-ctrl@11000 {
  136. compatible = "marvell,mv64xxx-i2c";
  137. reg = <0x11000 0x20>;
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. interrupts = <11>;
  141. clock-frequency = <400000>;
  142. timeout-ms = <1000>;
  143. clocks = <&core_clk 0>;
  144. status = "okay";
  145. };
  146. uart0: serial@12000 {
  147. compatible = "ns16550a";
  148. reg = <0x12000 0x100>;
  149. reg-shift = <2>;
  150. interrupts = <7>;
  151. clocks = <&core_clk 0>;
  152. status = "disabled";
  153. };
  154. uart1: serial@12100 {
  155. compatible = "ns16550a";
  156. reg = <0x12100 0x100>;
  157. reg-shift = <2>;
  158. interrupts = <8>;
  159. clocks = <&core_clk 0>;
  160. pinctrl-0 = <&pmx_uart1>;
  161. pinctrl-names = "default";
  162. status = "disabled";
  163. };
  164. uart2: serial@12200 {
  165. compatible = "ns16550a";
  166. reg = <0x12200 0x100>;
  167. reg-shift = <2>;
  168. interrupts = <9>;
  169. clocks = <&core_clk 0>;
  170. status = "disabled";
  171. };
  172. uart3: serial@12300 {
  173. compatible = "ns16550a";
  174. reg = <0x12300 0x100>;
  175. reg-shift = <2>;
  176. interrupts = <10>;
  177. clocks = <&core_clk 0>;
  178. status = "disabled";
  179. };
  180. spi1: spi-ctrl@14600 {
  181. compatible = "marvell,orion-spi";
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. cell-index = <1>;
  185. interrupts = <5>;
  186. reg = <0x14600 0x28>;
  187. clocks = <&core_clk 0>;
  188. status = "disabled";
  189. };
  190. mbusc: mbus-ctrl@20000 {
  191. compatible = "marvell,mbus-controller";
  192. reg = <0x20000 0x80>, <0x800100 0x8>;
  193. };
  194. sysc: system-ctrl@20000 {
  195. compatible = "marvell,orion-system-controller";
  196. reg = <0x20000 0x110>;
  197. };
  198. bridge_intc: bridge-interrupt-ctrl@20110 {
  199. compatible = "marvell,orion-bridge-intc";
  200. interrupt-controller;
  201. #interrupt-cells = <1>;
  202. reg = <0x20110 0x8>;
  203. interrupts = <0>;
  204. marvell,#interrupts = <5>;
  205. };
  206. intc: main-interrupt-ctrl@20200 {
  207. compatible = "marvell,orion-intc";
  208. interrupt-controller;
  209. #interrupt-cells = <1>;
  210. reg = <0x20200 0x10>, <0x20210 0x10>;
  211. };
  212. timer: timer@20300 {
  213. compatible = "marvell,orion-timer";
  214. reg = <0x20300 0x20>;
  215. interrupt-parent = <&bridge_intc>;
  216. interrupts = <1>, <2>;
  217. clocks = <&core_clk 0>;
  218. };
  219. watchdog@20300 {
  220. compatible = "marvell,orion-wdt";
  221. reg = <0x20300 0x28>, <0x20108 0x4>;
  222. interrupt-parent = <&bridge_intc>;
  223. interrupts = <3>;
  224. clocks = <&core_clk 0>;
  225. };
  226. crypto: crypto-engine@30000 {
  227. compatible = "marvell,orion-crypto";
  228. reg = <0x30000 0x10000>,
  229. <0xffffe000 0x800>;
  230. reg-names = "regs", "sram";
  231. interrupts = <31>;
  232. clocks = <&gate_clk 15>;
  233. status = "okay";
  234. };
  235. ehci0: usb-host@50000 {
  236. compatible = "marvell,orion-ehci";
  237. reg = <0x50000 0x1000>;
  238. interrupts = <24>;
  239. clocks = <&gate_clk 0>;
  240. status = "okay";
  241. };
  242. ehci1: usb-host@51000 {
  243. compatible = "marvell,orion-ehci";
  244. reg = <0x51000 0x1000>;
  245. interrupts = <25>;
  246. clocks = <&gate_clk 1>;
  247. status = "okay";
  248. };
  249. xor0: dma-engine@60800 {
  250. compatible = "marvell,orion-xor";
  251. reg = <0x60800 0x100
  252. 0x60a00 0x100>;
  253. clocks = <&gate_clk 23>;
  254. status = "okay";
  255. channel0 {
  256. interrupts = <39>;
  257. dmacap,memcpy;
  258. dmacap,xor;
  259. };
  260. channel1 {
  261. interrupts = <40>;
  262. dmacap,memcpy;
  263. dmacap,xor;
  264. };
  265. };
  266. xor1: dma-engine@60900 {
  267. compatible = "marvell,orion-xor";
  268. reg = <0x60900 0x100
  269. 0x60b00 0x100>;
  270. clocks = <&gate_clk 24>;
  271. status = "okay";
  272. channel0 {
  273. interrupts = <42>;
  274. dmacap,memcpy;
  275. dmacap,xor;
  276. };
  277. channel1 {
  278. interrupts = <43>;
  279. dmacap,memcpy;
  280. dmacap,xor;
  281. };
  282. };
  283. sdio1: sdio-host@90000 {
  284. compatible = "marvell,dove-sdhci";
  285. reg = <0x90000 0x100>;
  286. interrupts = <36>, <38>;
  287. clocks = <&gate_clk 9>;
  288. pinctrl-0 = <&pmx_sdio1>;
  289. pinctrl-names = "default";
  290. status = "disabled";
  291. };
  292. eth: ethernet-ctrl@72000 {
  293. compatible = "marvell,orion-eth";
  294. #address-cells = <1>;
  295. #size-cells = <0>;
  296. reg = <0x72000 0x4000>;
  297. clocks = <&gate_clk 2>;
  298. marvell,tx-checksum-limit = <1600>;
  299. status = "disabled";
  300. ethernet-port@0 {
  301. compatible = "marvell,orion-eth-port";
  302. reg = <0>;
  303. interrupts = <29>;
  304. /* overwrite MAC address in bootloader */
  305. local-mac-address = [00 00 00 00 00 00];
  306. phy-handle = <&ethphy>;
  307. };
  308. };
  309. mdio: mdio-bus@72004 {
  310. compatible = "marvell,orion-mdio";
  311. #address-cells = <1>;
  312. #size-cells = <0>;
  313. reg = <0x72004 0x84>;
  314. interrupts = <30>;
  315. clocks = <&gate_clk 2>;
  316. status = "disabled";
  317. ethphy: ethernet-phy {
  318. /* set phy address in board file */
  319. };
  320. };
  321. sdio0: sdio-host@92000 {
  322. compatible = "marvell,dove-sdhci";
  323. reg = <0x92000 0x100>;
  324. interrupts = <35>, <37>;
  325. clocks = <&gate_clk 8>;
  326. pinctrl-0 = <&pmx_sdio0>;
  327. pinctrl-names = "default";
  328. status = "disabled";
  329. };
  330. sata0: sata-host@a0000 {
  331. compatible = "marvell,orion-sata";
  332. reg = <0xa0000 0x2400>;
  333. interrupts = <62>;
  334. clocks = <&gate_clk 3>;
  335. phys = <&sata_phy0>;
  336. phy-names = "port0";
  337. nr-ports = <1>;
  338. status = "disabled";
  339. };
  340. sata_phy0: sata-phy@a2000 {
  341. compatible = "marvell,mvebu-sata-phy";
  342. reg = <0xa2000 0x0334>;
  343. clocks = <&gate_clk 3>;
  344. clock-names = "sata";
  345. #phy-cells = <0>;
  346. status = "ok";
  347. };
  348. audio0: audio-controller@b0000 {
  349. compatible = "marvell,dove-audio";
  350. reg = <0xb0000 0x2210>;
  351. interrupts = <19>, <20>;
  352. clocks = <&gate_clk 12>;
  353. clock-names = "internal";
  354. status = "disabled";
  355. };
  356. audio1: audio-controller@b4000 {
  357. compatible = "marvell,dove-audio";
  358. reg = <0xb4000 0x2210>;
  359. interrupts = <21>, <22>;
  360. clocks = <&gate_clk 13>;
  361. clock-names = "internal";
  362. status = "disabled";
  363. };
  364. thermal: thermal-diode@d001c {
  365. compatible = "marvell,dove-thermal";
  366. reg = <0xd001c 0x0c>, <0xd005c 0x08>;
  367. };
  368. gate_clk: clock-gating-ctrl@d0038 {
  369. compatible = "marvell,dove-gating-clock";
  370. reg = <0xd0038 0x4>;
  371. clocks = <&core_clk 0>;
  372. #clock-cells = <1>;
  373. };
  374. pinctrl: pin-ctrl@d0200 {
  375. compatible = "marvell,dove-pinctrl";
  376. reg = <0xd0200 0x14>,
  377. <0xd0440 0x04>;
  378. clocks = <&gate_clk 22>;
  379. pmx_gpio_0: pmx-gpio-0 {
  380. marvell,pins = "mpp0";
  381. marvell,function = "gpio";
  382. };
  383. pmx_gpio_1: pmx-gpio-1 {
  384. marvell,pins = "mpp1";
  385. marvell,function = "gpio";
  386. };
  387. pmx_gpio_2: pmx-gpio-2 {
  388. marvell,pins = "mpp2";
  389. marvell,function = "gpio";
  390. };
  391. pmx_gpio_3: pmx-gpio-3 {
  392. marvell,pins = "mpp3";
  393. marvell,function = "gpio";
  394. };
  395. pmx_gpio_4: pmx-gpio-4 {
  396. marvell,pins = "mpp4";
  397. marvell,function = "gpio";
  398. };
  399. pmx_gpio_5: pmx-gpio-5 {
  400. marvell,pins = "mpp5";
  401. marvell,function = "gpio";
  402. };
  403. pmx_gpio_6: pmx-gpio-6 {
  404. marvell,pins = "mpp6";
  405. marvell,function = "gpio";
  406. };
  407. pmx_gpio_7: pmx-gpio-7 {
  408. marvell,pins = "mpp7";
  409. marvell,function = "gpio";
  410. };
  411. pmx_gpio_8: pmx-gpio-8 {
  412. marvell,pins = "mpp8";
  413. marvell,function = "gpio";
  414. };
  415. pmx_gpio_9: pmx-gpio-9 {
  416. marvell,pins = "mpp9";
  417. marvell,function = "gpio";
  418. };
  419. pmx_pcie1_clkreq: pmx-pcie1-clkreq {
  420. marvell,pins = "mpp9";
  421. marvell,function = "pex1";
  422. };
  423. pmx_gpio_10: pmx-gpio-10 {
  424. marvell,pins = "mpp10";
  425. marvell,function = "gpio";
  426. };
  427. pmx_gpio_11: pmx-gpio-11 {
  428. marvell,pins = "mpp11";
  429. marvell,function = "gpio";
  430. };
  431. pmx_pcie0_clkreq: pmx-pcie0-clkreq {
  432. marvell,pins = "mpp11";
  433. marvell,function = "pex0";
  434. };
  435. pmx_gpio_12: pmx-gpio-12 {
  436. marvell,pins = "mpp12";
  437. marvell,function = "gpio";
  438. };
  439. pmx_gpio_13: pmx-gpio-13 {
  440. marvell,pins = "mpp13";
  441. marvell,function = "gpio";
  442. };
  443. pmx_audio1_extclk: pmx-audio1-extclk {
  444. marvell,pins = "mpp13";
  445. marvell,function = "audio1";
  446. };
  447. pmx_gpio_14: pmx-gpio-14 {
  448. marvell,pins = "mpp14";
  449. marvell,function = "gpio";
  450. };
  451. pmx_gpio_15: pmx-gpio-15 {
  452. marvell,pins = "mpp15";
  453. marvell,function = "gpio";
  454. };
  455. pmx_gpio_16: pmx-gpio-16 {
  456. marvell,pins = "mpp16";
  457. marvell,function = "gpio";
  458. };
  459. pmx_gpio_17: pmx-gpio-17 {
  460. marvell,pins = "mpp17";
  461. marvell,function = "gpio";
  462. };
  463. pmx_gpio_18: pmx-gpio-18 {
  464. marvell,pins = "mpp18";
  465. marvell,function = "gpio";
  466. };
  467. pmx_gpio_19: pmx-gpio-19 {
  468. marvell,pins = "mpp19";
  469. marvell,function = "gpio";
  470. };
  471. pmx_gpio_20: pmx-gpio-20 {
  472. marvell,pins = "mpp20";
  473. marvell,function = "gpio";
  474. };
  475. pmx_gpio_21: pmx-gpio-21 {
  476. marvell,pins = "mpp21";
  477. marvell,function = "gpio";
  478. };
  479. pmx_camera: pmx-camera {
  480. marvell,pins = "mpp_camera";
  481. marvell,function = "camera";
  482. };
  483. pmx_camera_gpio: pmx-camera-gpio {
  484. marvell,pins = "mpp_camera";
  485. marvell,function = "gpio";
  486. };
  487. pmx_sdio0: pmx-sdio0 {
  488. marvell,pins = "mpp_sdio0";
  489. marvell,function = "sdio0";
  490. };
  491. pmx_sdio0_gpio: pmx-sdio0-gpio {
  492. marvell,pins = "mpp_sdio0";
  493. marvell,function = "gpio";
  494. };
  495. pmx_sdio1: pmx-sdio1 {
  496. marvell,pins = "mpp_sdio1";
  497. marvell,function = "sdio1";
  498. };
  499. pmx_sdio1_gpio: pmx-sdio1-gpio {
  500. marvell,pins = "mpp_sdio1";
  501. marvell,function = "gpio";
  502. };
  503. pmx_audio1_gpio: pmx-audio1-gpio {
  504. marvell,pins = "mpp_audio1";
  505. marvell,function = "gpio";
  506. };
  507. pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
  508. marvell,pins = "mpp_audio1";
  509. marvell,function = "i2s1/spdifo";
  510. };
  511. pmx_spi0: pmx-spi0 {
  512. marvell,pins = "mpp_spi0";
  513. marvell,function = "spi0";
  514. };
  515. pmx_spi0_gpio: pmx-spi0-gpio {
  516. marvell,pins = "mpp_spi0";
  517. marvell,function = "gpio";
  518. };
  519. pmx_spi1_4_7: pmx-spi1-4-7 {
  520. marvell,pins = "mpp4", "mpp5",
  521. "mpp6", "mpp7";
  522. marvell,function = "spi1";
  523. };
  524. pmx_spi1_20_23: pmx-spi1-20-23 {
  525. marvell,pins = "mpp20", "mpp21",
  526. "mpp22", "mpp23";
  527. marvell,function = "spi1";
  528. };
  529. pmx_uart1: pmx-uart1 {
  530. marvell,pins = "mpp_uart1";
  531. marvell,function = "uart1";
  532. };
  533. pmx_uart1_gpio: pmx-uart1-gpio {
  534. marvell,pins = "mpp_uart1";
  535. marvell,function = "gpio";
  536. };
  537. pmx_nand: pmx-nand {
  538. marvell,pins = "mpp_nand";
  539. marvell,function = "nand";
  540. };
  541. pmx_nand_gpo: pmx-nand-gpo {
  542. marvell,pins = "mpp_nand";
  543. marvell,function = "gpo";
  544. };
  545. pmx_i2c1: pmx-i2c1 {
  546. marvell,pins = "mpp17", "mpp19";
  547. marvell,function = "twsi";
  548. };
  549. pmx_i2c2: pmx-i2c2 {
  550. marvell,pins = "mpp_audio1";
  551. marvell,function = "twsi";
  552. };
  553. pmx_ssp_i2c2: pmx-ssp-i2c2 {
  554. marvell,pins = "mpp_audio1";
  555. marvell,function = "ssp/twsi";
  556. };
  557. pmx_i2cmux_0: pmx-i2cmux-0 {
  558. marvell,pins = "twsi";
  559. marvell,function = "twsi-opt1";
  560. };
  561. pmx_i2cmux_1: pmx-i2cmux-1 {
  562. marvell,pins = "twsi";
  563. marvell,function = "twsi-opt2";
  564. };
  565. pmx_i2cmux_2: pmx-i2cmux-2 {
  566. marvell,pins = "twsi";
  567. marvell,function = "twsi-opt3";
  568. };
  569. };
  570. core_clk: core-clocks@d0214 {
  571. compatible = "marvell,dove-core-clock";
  572. reg = <0xd0214 0x4>;
  573. #clock-cells = <1>;
  574. };
  575. gpio0: gpio-ctrl@d0400 {
  576. compatible = "marvell,orion-gpio";
  577. #gpio-cells = <2>;
  578. gpio-controller;
  579. reg = <0xd0400 0x20>;
  580. ngpios = <32>;
  581. interrupt-controller;
  582. #interrupt-cells = <2>;
  583. interrupts = <12>, <13>, <14>, <60>;
  584. };
  585. gpio1: gpio-ctrl@d0420 {
  586. compatible = "marvell,orion-gpio";
  587. #gpio-cells = <2>;
  588. gpio-controller;
  589. reg = <0xd0420 0x20>;
  590. ngpios = <32>;
  591. interrupt-controller;
  592. #interrupt-cells = <2>;
  593. interrupts = <61>;
  594. };
  595. rtc: real-time-clock@d8500 {
  596. compatible = "marvell,orion-rtc";
  597. reg = <0xd8500 0x20>;
  598. };
  599. gconf: global-config@e802c {
  600. compatible = "marvell,dove-global-config",
  601. "syscon";
  602. reg = <0xe802c 0x14>;
  603. };
  604. gpio2: gpio-ctrl@e8400 {
  605. compatible = "marvell,orion-gpio";
  606. #gpio-cells = <2>;
  607. gpio-controller;
  608. reg = <0xe8400 0x0c>;
  609. ngpios = <8>;
  610. };
  611. lcd1: lcd-controller@810000 {
  612. compatible = "marvell,dove-lcd";
  613. reg = <0x810000 0x1000>;
  614. interrupts = <46>;
  615. status = "disabled";
  616. };
  617. lcd0: lcd-controller@820000 {
  618. compatible = "marvell,dove-lcd";
  619. reg = <0x820000 0x1000>;
  620. interrupts = <47>;
  621. status = "disabled";
  622. };
  623. };
  624. };
  625. };