amdgpu.h 61 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #ifndef __AMDGPU_H__
  29. #define __AMDGPU_H__
  30. #include <linux/atomic.h>
  31. #include <linux/wait.h>
  32. #include <linux/list.h>
  33. #include <linux/kref.h>
  34. #include <linux/rbtree.h>
  35. #include <linux/hashtable.h>
  36. #include <linux/dma-fence.h>
  37. #include <ttm/ttm_bo_api.h>
  38. #include <ttm/ttm_bo_driver.h>
  39. #include <ttm/ttm_placement.h>
  40. #include <ttm/ttm_module.h>
  41. #include <ttm/ttm_execbuf_util.h>
  42. #include <drm/drmP.h>
  43. #include <drm/drm_gem.h>
  44. #include <drm/amdgpu_drm.h>
  45. #include <kgd_kfd_interface.h>
  46. #include "amd_shared.h"
  47. #include "amdgpu_mode.h"
  48. #include "amdgpu_ih.h"
  49. #include "amdgpu_irq.h"
  50. #include "amdgpu_ucode.h"
  51. #include "amdgpu_ttm.h"
  52. #include "amdgpu_psp.h"
  53. #include "amdgpu_gds.h"
  54. #include "amdgpu_sync.h"
  55. #include "amdgpu_ring.h"
  56. #include "amdgpu_vm.h"
  57. #include "amd_powerplay.h"
  58. #include "amdgpu_dpm.h"
  59. #include "amdgpu_acp.h"
  60. #include "amdgpu_uvd.h"
  61. #include "amdgpu_vce.h"
  62. #include "amdgpu_vcn.h"
  63. #include "gpu_scheduler.h"
  64. #include "amdgpu_virt.h"
  65. /*
  66. * Modules parameters.
  67. */
  68. extern int amdgpu_modeset;
  69. extern int amdgpu_vram_limit;
  70. extern int amdgpu_gart_size;
  71. extern int amdgpu_moverate;
  72. extern int amdgpu_benchmarking;
  73. extern int amdgpu_testing;
  74. extern int amdgpu_audio;
  75. extern int amdgpu_disp_priority;
  76. extern int amdgpu_hw_i2c;
  77. extern int amdgpu_pcie_gen2;
  78. extern int amdgpu_msi;
  79. extern int amdgpu_lockup_timeout;
  80. extern int amdgpu_dpm;
  81. extern int amdgpu_fw_load_type;
  82. extern int amdgpu_aspm;
  83. extern int amdgpu_runtime_pm;
  84. extern unsigned amdgpu_ip_block_mask;
  85. extern int amdgpu_bapm;
  86. extern int amdgpu_deep_color;
  87. extern int amdgpu_vm_size;
  88. extern int amdgpu_vm_block_size;
  89. extern int amdgpu_vm_fault_stop;
  90. extern int amdgpu_vm_debug;
  91. extern int amdgpu_sched_jobs;
  92. extern int amdgpu_sched_hw_submission;
  93. extern int amdgpu_no_evict;
  94. extern int amdgpu_direct_gma_size;
  95. extern unsigned amdgpu_pcie_gen_cap;
  96. extern unsigned amdgpu_pcie_lane_cap;
  97. extern unsigned amdgpu_cg_mask;
  98. extern unsigned amdgpu_pg_mask;
  99. extern char *amdgpu_disable_cu;
  100. extern char *amdgpu_virtual_display;
  101. extern unsigned amdgpu_pp_feature_mask;
  102. extern int amdgpu_vram_page_split;
  103. extern int amdgpu_ngg;
  104. extern int amdgpu_prim_buf_per_se;
  105. extern int amdgpu_pos_buf_per_se;
  106. extern int amdgpu_cntl_sb_buf_per_se;
  107. extern int amdgpu_param_buf_per_se;
  108. extern int amdgpu_job_hang_limit;
  109. extern int amdgpu_lbpw;
  110. #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
  111. #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
  112. #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
  113. #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
  114. /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
  115. #define AMDGPU_IB_POOL_SIZE 16
  116. #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
  117. #define AMDGPUFB_CONN_LIMIT 4
  118. #define AMDGPU_BIOS_NUM_SCRATCH 16
  119. /* max number of IP instances */
  120. #define AMDGPU_MAX_SDMA_INSTANCES 2
  121. /* hard reset data */
  122. #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
  123. /* reset flags */
  124. #define AMDGPU_RESET_GFX (1 << 0)
  125. #define AMDGPU_RESET_COMPUTE (1 << 1)
  126. #define AMDGPU_RESET_DMA (1 << 2)
  127. #define AMDGPU_RESET_CP (1 << 3)
  128. #define AMDGPU_RESET_GRBM (1 << 4)
  129. #define AMDGPU_RESET_DMA1 (1 << 5)
  130. #define AMDGPU_RESET_RLC (1 << 6)
  131. #define AMDGPU_RESET_SEM (1 << 7)
  132. #define AMDGPU_RESET_IH (1 << 8)
  133. #define AMDGPU_RESET_VMC (1 << 9)
  134. #define AMDGPU_RESET_MC (1 << 10)
  135. #define AMDGPU_RESET_DISPLAY (1 << 11)
  136. #define AMDGPU_RESET_UVD (1 << 12)
  137. #define AMDGPU_RESET_VCE (1 << 13)
  138. #define AMDGPU_RESET_VCE1 (1 << 14)
  139. /* GFX current status */
  140. #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
  141. #define AMDGPU_GFX_SAFE_MODE 0x00000001L
  142. #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
  143. #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
  144. #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
  145. /* max cursor sizes (in pixels) */
  146. #define CIK_CURSOR_WIDTH 128
  147. #define CIK_CURSOR_HEIGHT 128
  148. struct amdgpu_device;
  149. struct amdgpu_ib;
  150. struct amdgpu_cs_parser;
  151. struct amdgpu_job;
  152. struct amdgpu_irq_src;
  153. struct amdgpu_fpriv;
  154. enum amdgpu_cp_irq {
  155. AMDGPU_CP_IRQ_GFX_EOP = 0,
  156. AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
  157. AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
  158. AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
  159. AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
  160. AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
  161. AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
  162. AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
  163. AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
  164. AMDGPU_CP_IRQ_LAST
  165. };
  166. enum amdgpu_sdma_irq {
  167. AMDGPU_SDMA_IRQ_TRAP0 = 0,
  168. AMDGPU_SDMA_IRQ_TRAP1,
  169. AMDGPU_SDMA_IRQ_LAST
  170. };
  171. enum amdgpu_thermal_irq {
  172. AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
  173. AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
  174. AMDGPU_THERMAL_IRQ_LAST
  175. };
  176. enum amdgpu_kiq_irq {
  177. AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
  178. AMDGPU_CP_KIQ_IRQ_LAST
  179. };
  180. int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
  181. enum amd_ip_block_type block_type,
  182. enum amd_clockgating_state state);
  183. int amdgpu_set_powergating_state(struct amdgpu_device *adev,
  184. enum amd_ip_block_type block_type,
  185. enum amd_powergating_state state);
  186. void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
  187. int amdgpu_wait_for_idle(struct amdgpu_device *adev,
  188. enum amd_ip_block_type block_type);
  189. bool amdgpu_is_idle(struct amdgpu_device *adev,
  190. enum amd_ip_block_type block_type);
  191. #define AMDGPU_MAX_IP_NUM 16
  192. struct amdgpu_ip_block_status {
  193. bool valid;
  194. bool sw;
  195. bool hw;
  196. bool late_initialized;
  197. bool hang;
  198. };
  199. struct amdgpu_ip_block_version {
  200. const enum amd_ip_block_type type;
  201. const u32 major;
  202. const u32 minor;
  203. const u32 rev;
  204. const struct amd_ip_funcs *funcs;
  205. };
  206. struct amdgpu_ip_block {
  207. struct amdgpu_ip_block_status status;
  208. const struct amdgpu_ip_block_version *version;
  209. };
  210. int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
  211. enum amd_ip_block_type type,
  212. u32 major, u32 minor);
  213. struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
  214. enum amd_ip_block_type type);
  215. int amdgpu_ip_block_add(struct amdgpu_device *adev,
  216. const struct amdgpu_ip_block_version *ip_block_version);
  217. /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
  218. struct amdgpu_buffer_funcs {
  219. /* maximum bytes in a single operation */
  220. uint32_t copy_max_bytes;
  221. /* number of dw to reserve per operation */
  222. unsigned copy_num_dw;
  223. /* used for buffer migration */
  224. void (*emit_copy_buffer)(struct amdgpu_ib *ib,
  225. /* src addr in bytes */
  226. uint64_t src_offset,
  227. /* dst addr in bytes */
  228. uint64_t dst_offset,
  229. /* number of byte to transfer */
  230. uint32_t byte_count);
  231. /* maximum bytes in a single operation */
  232. uint32_t fill_max_bytes;
  233. /* number of dw to reserve per operation */
  234. unsigned fill_num_dw;
  235. /* used for buffer clearing */
  236. void (*emit_fill_buffer)(struct amdgpu_ib *ib,
  237. /* value to write to memory */
  238. uint32_t src_data,
  239. /* dst addr in bytes */
  240. uint64_t dst_offset,
  241. /* number of byte to fill */
  242. uint32_t byte_count);
  243. };
  244. /* provided by hw blocks that can write ptes, e.g., sdma */
  245. struct amdgpu_vm_pte_funcs {
  246. /* copy pte entries from GART */
  247. void (*copy_pte)(struct amdgpu_ib *ib,
  248. uint64_t pe, uint64_t src,
  249. unsigned count);
  250. /* write pte one entry at a time with addr mapping */
  251. void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
  252. uint64_t value, unsigned count,
  253. uint32_t incr);
  254. /* for linear pte/pde updates without addr mapping */
  255. void (*set_pte_pde)(struct amdgpu_ib *ib,
  256. uint64_t pe,
  257. uint64_t addr, unsigned count,
  258. uint32_t incr, uint64_t flags);
  259. };
  260. /* provided by the gmc block */
  261. struct amdgpu_gart_funcs {
  262. /* flush the vm tlb via mmio */
  263. void (*flush_gpu_tlb)(struct amdgpu_device *adev,
  264. uint32_t vmid);
  265. /* write pte/pde updates using the cpu */
  266. int (*set_pte_pde)(struct amdgpu_device *adev,
  267. void *cpu_pt_addr, /* cpu addr of page table */
  268. uint32_t gpu_page_idx, /* pte/pde to update */
  269. uint64_t addr, /* addr to write into pte/pde */
  270. uint64_t flags); /* access flags */
  271. /* enable/disable PRT support */
  272. void (*set_prt)(struct amdgpu_device *adev, bool enable);
  273. /* set pte flags based per asic */
  274. uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
  275. uint32_t flags);
  276. /* get the pde for a given mc addr */
  277. u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
  278. uint32_t (*get_invalidate_req)(unsigned int vm_id);
  279. };
  280. /* provided by the ih block */
  281. struct amdgpu_ih_funcs {
  282. /* ring read/write ptr handling, called from interrupt context */
  283. u32 (*get_wptr)(struct amdgpu_device *adev);
  284. void (*decode_iv)(struct amdgpu_device *adev,
  285. struct amdgpu_iv_entry *entry);
  286. void (*set_rptr)(struct amdgpu_device *adev);
  287. };
  288. /*
  289. * BIOS.
  290. */
  291. bool amdgpu_get_bios(struct amdgpu_device *adev);
  292. bool amdgpu_read_bios(struct amdgpu_device *adev);
  293. /*
  294. * Dummy page
  295. */
  296. struct amdgpu_dummy_page {
  297. struct page *page;
  298. dma_addr_t addr;
  299. };
  300. int amdgpu_dummy_page_init(struct amdgpu_device *adev);
  301. void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
  302. /*
  303. * Clocks
  304. */
  305. #define AMDGPU_MAX_PPLL 3
  306. struct amdgpu_clock {
  307. struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
  308. struct amdgpu_pll spll;
  309. struct amdgpu_pll mpll;
  310. /* 10 Khz units */
  311. uint32_t default_mclk;
  312. uint32_t default_sclk;
  313. uint32_t default_dispclk;
  314. uint32_t current_dispclk;
  315. uint32_t dp_extclk;
  316. uint32_t max_pixel_clock;
  317. };
  318. /*
  319. * BO.
  320. */
  321. struct amdgpu_bo_list_entry {
  322. struct amdgpu_bo *robj;
  323. struct ttm_validate_buffer tv;
  324. struct amdgpu_bo_va *bo_va;
  325. uint32_t priority;
  326. struct page **user_pages;
  327. int user_invalidated;
  328. };
  329. struct amdgpu_bo_va_mapping {
  330. struct list_head list;
  331. struct rb_node rb;
  332. uint64_t start;
  333. uint64_t last;
  334. uint64_t __subtree_last;
  335. uint64_t offset;
  336. uint64_t flags;
  337. };
  338. /* bo virtual addresses in a specific vm */
  339. struct amdgpu_bo_va {
  340. /* protected by bo being reserved */
  341. struct list_head bo_list;
  342. struct dma_fence *last_pt_update;
  343. unsigned ref_count;
  344. /* protected by vm mutex and spinlock */
  345. struct list_head vm_status;
  346. /* mappings for this bo_va */
  347. struct list_head invalids;
  348. struct list_head valids;
  349. /* constant after initialization */
  350. struct amdgpu_vm *vm;
  351. struct amdgpu_bo *bo;
  352. };
  353. #define AMDGPU_GEM_DOMAIN_MAX 0x3
  354. struct amdgpu_bo {
  355. /* Protected by tbo.reserved */
  356. u32 prefered_domains;
  357. u32 allowed_domains;
  358. struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
  359. struct ttm_placement placement;
  360. struct ttm_buffer_object tbo;
  361. struct ttm_bo_kmap_obj kmap;
  362. u64 flags;
  363. unsigned pin_count;
  364. void *kptr;
  365. u64 tiling_flags;
  366. u64 metadata_flags;
  367. void *metadata;
  368. u32 metadata_size;
  369. unsigned prime_shared_count;
  370. /* list of all virtual address to which this bo
  371. * is associated to
  372. */
  373. struct list_head va;
  374. /* Constant after initialization */
  375. struct drm_gem_object gem_base;
  376. struct amdgpu_bo *parent;
  377. struct amdgpu_bo *shadow;
  378. struct ttm_bo_kmap_obj dma_buf_vmap;
  379. struct amdgpu_mn *mn;
  380. struct list_head mn_list;
  381. struct list_head shadow_list;
  382. };
  383. #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
  384. void amdgpu_gem_object_free(struct drm_gem_object *obj);
  385. int amdgpu_gem_object_open(struct drm_gem_object *obj,
  386. struct drm_file *file_priv);
  387. void amdgpu_gem_object_close(struct drm_gem_object *obj,
  388. struct drm_file *file_priv);
  389. unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
  390. struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
  391. struct drm_gem_object *
  392. amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
  393. struct dma_buf_attachment *attach,
  394. struct sg_table *sg);
  395. struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
  396. struct drm_gem_object *gobj,
  397. int flags);
  398. int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
  399. void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
  400. struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
  401. void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
  402. void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  403. int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
  404. /* sub-allocation manager, it has to be protected by another lock.
  405. * By conception this is an helper for other part of the driver
  406. * like the indirect buffer or semaphore, which both have their
  407. * locking.
  408. *
  409. * Principe is simple, we keep a list of sub allocation in offset
  410. * order (first entry has offset == 0, last entry has the highest
  411. * offset).
  412. *
  413. * When allocating new object we first check if there is room at
  414. * the end total_size - (last_object_offset + last_object_size) >=
  415. * alloc_size. If so we allocate new object there.
  416. *
  417. * When there is not enough room at the end, we start waiting for
  418. * each sub object until we reach object_offset+object_size >=
  419. * alloc_size, this object then become the sub object we return.
  420. *
  421. * Alignment can't be bigger than page size.
  422. *
  423. * Hole are not considered for allocation to keep things simple.
  424. * Assumption is that there won't be hole (all object on same
  425. * alignment).
  426. */
  427. #define AMDGPU_SA_NUM_FENCE_LISTS 32
  428. struct amdgpu_sa_manager {
  429. wait_queue_head_t wq;
  430. struct amdgpu_bo *bo;
  431. struct list_head *hole;
  432. struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
  433. struct list_head olist;
  434. unsigned size;
  435. uint64_t gpu_addr;
  436. void *cpu_ptr;
  437. uint32_t domain;
  438. uint32_t align;
  439. };
  440. /* sub-allocation buffer */
  441. struct amdgpu_sa_bo {
  442. struct list_head olist;
  443. struct list_head flist;
  444. struct amdgpu_sa_manager *manager;
  445. unsigned soffset;
  446. unsigned eoffset;
  447. struct dma_fence *fence;
  448. };
  449. /*
  450. * GEM objects.
  451. */
  452. void amdgpu_gem_force_release(struct amdgpu_device *adev);
  453. int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  454. int alignment, u32 initial_domain,
  455. u64 flags, bool kernel,
  456. struct drm_gem_object **obj);
  457. int amdgpu_mode_dumb_create(struct drm_file *file_priv,
  458. struct drm_device *dev,
  459. struct drm_mode_create_dumb *args);
  460. int amdgpu_mode_dumb_mmap(struct drm_file *filp,
  461. struct drm_device *dev,
  462. uint32_t handle, uint64_t *offset_p);
  463. int amdgpu_fence_slab_init(void);
  464. void amdgpu_fence_slab_fini(void);
  465. /*
  466. * GART structures, functions & helpers
  467. */
  468. struct amdgpu_mc;
  469. #define AMDGPU_GPU_PAGE_SIZE 4096
  470. #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
  471. #define AMDGPU_GPU_PAGE_SHIFT 12
  472. #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
  473. struct amdgpu_gart {
  474. dma_addr_t table_addr;
  475. struct amdgpu_bo *robj;
  476. void *ptr;
  477. unsigned num_gpu_pages;
  478. unsigned num_cpu_pages;
  479. unsigned table_size;
  480. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  481. struct page **pages;
  482. #endif
  483. bool ready;
  484. /* Asic default pte flags */
  485. uint64_t gart_pte_flags;
  486. const struct amdgpu_gart_funcs *gart_funcs;
  487. };
  488. int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
  489. void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
  490. int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
  491. void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
  492. int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
  493. void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
  494. int amdgpu_gart_init(struct amdgpu_device *adev);
  495. void amdgpu_gart_fini(struct amdgpu_device *adev);
  496. int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
  497. int pages);
  498. int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
  499. int pages, struct page **pagelist,
  500. dma_addr_t *dma_addr, uint64_t flags);
  501. int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
  502. /*
  503. * VMHUB structures, functions & helpers
  504. */
  505. struct amdgpu_vmhub {
  506. uint32_t ctx0_ptb_addr_lo32;
  507. uint32_t ctx0_ptb_addr_hi32;
  508. uint32_t vm_inv_eng0_req;
  509. uint32_t vm_inv_eng0_ack;
  510. uint32_t vm_context0_cntl;
  511. uint32_t vm_l2_pro_fault_status;
  512. uint32_t vm_l2_pro_fault_cntl;
  513. };
  514. /*
  515. * GPU MC structures, functions & helpers
  516. */
  517. struct amdgpu_mc {
  518. resource_size_t aper_size;
  519. resource_size_t aper_base;
  520. resource_size_t agp_base;
  521. /* for some chips with <= 32MB we need to lie
  522. * about vram size near mc fb location */
  523. u64 mc_vram_size;
  524. u64 visible_vram_size;
  525. u64 gtt_size;
  526. u64 gtt_start;
  527. u64 gtt_end;
  528. u64 vram_start;
  529. u64 vram_end;
  530. unsigned vram_width;
  531. u64 real_vram_size;
  532. int vram_mtrr;
  533. u64 gtt_base_align;
  534. u64 mc_mask;
  535. const struct firmware *fw; /* MC firmware */
  536. uint32_t fw_version;
  537. struct amdgpu_irq_src vm_fault;
  538. uint32_t vram_type;
  539. uint32_t srbm_soft_reset;
  540. struct amdgpu_mode_mc_save save;
  541. bool prt_warning;
  542. /* apertures */
  543. u64 shared_aperture_start;
  544. u64 shared_aperture_end;
  545. u64 private_aperture_start;
  546. u64 private_aperture_end;
  547. /* protects concurrent invalidation */
  548. spinlock_t invalidate_lock;
  549. };
  550. /*
  551. * GPU doorbell structures, functions & helpers
  552. */
  553. typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
  554. {
  555. AMDGPU_DOORBELL_KIQ = 0x000,
  556. AMDGPU_DOORBELL_HIQ = 0x001,
  557. AMDGPU_DOORBELL_DIQ = 0x002,
  558. AMDGPU_DOORBELL_MEC_RING0 = 0x010,
  559. AMDGPU_DOORBELL_MEC_RING1 = 0x011,
  560. AMDGPU_DOORBELL_MEC_RING2 = 0x012,
  561. AMDGPU_DOORBELL_MEC_RING3 = 0x013,
  562. AMDGPU_DOORBELL_MEC_RING4 = 0x014,
  563. AMDGPU_DOORBELL_MEC_RING5 = 0x015,
  564. AMDGPU_DOORBELL_MEC_RING6 = 0x016,
  565. AMDGPU_DOORBELL_MEC_RING7 = 0x017,
  566. AMDGPU_DOORBELL_GFX_RING0 = 0x020,
  567. AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
  568. AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
  569. AMDGPU_DOORBELL_IH = 0x1E8,
  570. AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
  571. AMDGPU_DOORBELL_INVALID = 0xFFFF
  572. } AMDGPU_DOORBELL_ASSIGNMENT;
  573. struct amdgpu_doorbell {
  574. /* doorbell mmio */
  575. resource_size_t base;
  576. resource_size_t size;
  577. u32 __iomem *ptr;
  578. u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
  579. };
  580. /*
  581. * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
  582. */
  583. typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
  584. {
  585. /*
  586. * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
  587. * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
  588. * Compute related doorbells are allocated from 0x00 to 0x8a
  589. */
  590. /* kernel scheduling */
  591. AMDGPU_DOORBELL64_KIQ = 0x00,
  592. /* HSA interface queue and debug queue */
  593. AMDGPU_DOORBELL64_HIQ = 0x01,
  594. AMDGPU_DOORBELL64_DIQ = 0x02,
  595. /* Compute engines */
  596. AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
  597. AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
  598. AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
  599. AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
  600. AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
  601. AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
  602. AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
  603. AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
  604. /* User queue doorbell range (128 doorbells) */
  605. AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
  606. AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
  607. /* Graphics engine */
  608. AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
  609. /*
  610. * Other graphics doorbells can be allocated here: from 0x8c to 0xef
  611. * Graphics voltage island aperture 1
  612. * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
  613. */
  614. /* sDMA engines */
  615. AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
  616. AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
  617. AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
  618. AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
  619. /* Interrupt handler */
  620. AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
  621. AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
  622. AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
  623. /* VCN engine use 32 bits doorbell */
  624. AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
  625. AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
  626. AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
  627. AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
  628. /* overlap the doorbell assignment with VCN as they are mutually exclusive
  629. * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
  630. */
  631. AMDGPU_DOORBELL64_RING0_1 = 0xF8,
  632. AMDGPU_DOORBELL64_RING2_3 = 0xF9,
  633. AMDGPU_DOORBELL64_RING4_5 = 0xFA,
  634. AMDGPU_DOORBELL64_RING6_7 = 0xFB,
  635. AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
  636. AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
  637. AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
  638. AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
  639. AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
  640. AMDGPU_DOORBELL64_INVALID = 0xFFFF
  641. } AMDGPU_DOORBELL64_ASSIGNMENT;
  642. void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
  643. phys_addr_t *aperture_base,
  644. size_t *aperture_size,
  645. size_t *start_offset);
  646. /*
  647. * IRQS.
  648. */
  649. struct amdgpu_flip_work {
  650. struct delayed_work flip_work;
  651. struct work_struct unpin_work;
  652. struct amdgpu_device *adev;
  653. int crtc_id;
  654. u32 target_vblank;
  655. uint64_t base;
  656. struct drm_pending_vblank_event *event;
  657. struct amdgpu_bo *old_abo;
  658. struct dma_fence *excl;
  659. unsigned shared_count;
  660. struct dma_fence **shared;
  661. struct dma_fence_cb cb;
  662. bool async;
  663. };
  664. /*
  665. * CP & rings.
  666. */
  667. struct amdgpu_ib {
  668. struct amdgpu_sa_bo *sa_bo;
  669. uint32_t length_dw;
  670. uint64_t gpu_addr;
  671. uint32_t *ptr;
  672. uint32_t flags;
  673. };
  674. extern const struct amd_sched_backend_ops amdgpu_sched_ops;
  675. int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  676. struct amdgpu_job **job, struct amdgpu_vm *vm);
  677. int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  678. struct amdgpu_job **job);
  679. void amdgpu_job_free_resources(struct amdgpu_job *job);
  680. void amdgpu_job_free(struct amdgpu_job *job);
  681. int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
  682. struct amd_sched_entity *entity, void *owner,
  683. struct dma_fence **f);
  684. /*
  685. * context related structures
  686. */
  687. struct amdgpu_ctx_ring {
  688. uint64_t sequence;
  689. struct dma_fence **fences;
  690. struct amd_sched_entity entity;
  691. };
  692. struct amdgpu_ctx {
  693. struct kref refcount;
  694. struct amdgpu_device *adev;
  695. unsigned reset_counter;
  696. spinlock_t ring_lock;
  697. struct dma_fence **fences;
  698. struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
  699. bool preamble_presented;
  700. };
  701. struct amdgpu_ctx_mgr {
  702. struct amdgpu_device *adev;
  703. struct mutex lock;
  704. /* protected by lock */
  705. struct idr ctx_handles;
  706. };
  707. struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
  708. int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
  709. uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
  710. struct dma_fence *fence);
  711. struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
  712. struct amdgpu_ring *ring, uint64_t seq);
  713. int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
  714. struct drm_file *filp);
  715. void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
  716. void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
  717. /*
  718. * file private structure
  719. */
  720. struct amdgpu_fpriv {
  721. struct amdgpu_vm vm;
  722. struct amdgpu_bo_va *prt_va;
  723. struct mutex bo_list_lock;
  724. struct idr bo_list_handles;
  725. struct amdgpu_ctx_mgr ctx_mgr;
  726. u32 vram_lost_counter;
  727. };
  728. /*
  729. * residency list
  730. */
  731. struct amdgpu_bo_list {
  732. struct mutex lock;
  733. struct amdgpu_bo *gds_obj;
  734. struct amdgpu_bo *gws_obj;
  735. struct amdgpu_bo *oa_obj;
  736. unsigned first_userptr;
  737. unsigned num_entries;
  738. struct amdgpu_bo_list_entry *array;
  739. };
  740. struct amdgpu_bo_list *
  741. amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
  742. void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
  743. struct list_head *validated);
  744. void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
  745. void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
  746. /*
  747. * GFX stuff
  748. */
  749. #include "clearstate_defs.h"
  750. struct amdgpu_rlc_funcs {
  751. void (*enter_safe_mode)(struct amdgpu_device *adev);
  752. void (*exit_safe_mode)(struct amdgpu_device *adev);
  753. };
  754. struct amdgpu_rlc {
  755. /* for power gating */
  756. struct amdgpu_bo *save_restore_obj;
  757. uint64_t save_restore_gpu_addr;
  758. volatile uint32_t *sr_ptr;
  759. const u32 *reg_list;
  760. u32 reg_list_size;
  761. /* for clear state */
  762. struct amdgpu_bo *clear_state_obj;
  763. uint64_t clear_state_gpu_addr;
  764. volatile uint32_t *cs_ptr;
  765. const struct cs_section_def *cs_data;
  766. u32 clear_state_size;
  767. /* for cp tables */
  768. struct amdgpu_bo *cp_table_obj;
  769. uint64_t cp_table_gpu_addr;
  770. volatile uint32_t *cp_table_ptr;
  771. u32 cp_table_size;
  772. /* safe mode for updating CG/PG state */
  773. bool in_safe_mode;
  774. const struct amdgpu_rlc_funcs *funcs;
  775. /* for firmware data */
  776. u32 save_and_restore_offset;
  777. u32 clear_state_descriptor_offset;
  778. u32 avail_scratch_ram_locations;
  779. u32 reg_restore_list_size;
  780. u32 reg_list_format_start;
  781. u32 reg_list_format_separate_start;
  782. u32 starting_offsets_start;
  783. u32 reg_list_format_size_bytes;
  784. u32 reg_list_size_bytes;
  785. u32 *register_list_format;
  786. u32 *register_restore;
  787. };
  788. #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
  789. struct amdgpu_mec {
  790. struct amdgpu_bo *hpd_eop_obj;
  791. u64 hpd_eop_gpu_addr;
  792. struct amdgpu_bo *mec_fw_obj;
  793. u64 mec_fw_gpu_addr;
  794. u32 num_mec;
  795. u32 num_pipe_per_mec;
  796. u32 num_queue_per_pipe;
  797. void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
  798. /* These are the resources for which amdgpu takes ownership */
  799. DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
  800. };
  801. struct amdgpu_kiq {
  802. u64 eop_gpu_addr;
  803. struct amdgpu_bo *eop_obj;
  804. struct mutex ring_mutex;
  805. struct amdgpu_ring ring;
  806. struct amdgpu_irq_src irq;
  807. };
  808. /*
  809. * GPU scratch registers structures, functions & helpers
  810. */
  811. struct amdgpu_scratch {
  812. unsigned num_reg;
  813. uint32_t reg_base;
  814. uint32_t free_mask;
  815. };
  816. /*
  817. * GFX configurations
  818. */
  819. #define AMDGPU_GFX_MAX_SE 4
  820. #define AMDGPU_GFX_MAX_SH_PER_SE 2
  821. struct amdgpu_rb_config {
  822. uint32_t rb_backend_disable;
  823. uint32_t user_rb_backend_disable;
  824. uint32_t raster_config;
  825. uint32_t raster_config_1;
  826. };
  827. struct gb_addr_config {
  828. uint16_t pipe_interleave_size;
  829. uint8_t num_pipes;
  830. uint8_t max_compress_frags;
  831. uint8_t num_banks;
  832. uint8_t num_se;
  833. uint8_t num_rb_per_se;
  834. };
  835. struct amdgpu_gfx_config {
  836. unsigned max_shader_engines;
  837. unsigned max_tile_pipes;
  838. unsigned max_cu_per_sh;
  839. unsigned max_sh_per_se;
  840. unsigned max_backends_per_se;
  841. unsigned max_texture_channel_caches;
  842. unsigned max_gprs;
  843. unsigned max_gs_threads;
  844. unsigned max_hw_contexts;
  845. unsigned sc_prim_fifo_size_frontend;
  846. unsigned sc_prim_fifo_size_backend;
  847. unsigned sc_hiz_tile_fifo_size;
  848. unsigned sc_earlyz_tile_fifo_size;
  849. unsigned num_tile_pipes;
  850. unsigned backend_enable_mask;
  851. unsigned mem_max_burst_length_bytes;
  852. unsigned mem_row_size_in_kb;
  853. unsigned shader_engine_tile_size;
  854. unsigned num_gpus;
  855. unsigned multi_gpu_tile_size;
  856. unsigned mc_arb_ramcfg;
  857. unsigned gb_addr_config;
  858. unsigned num_rbs;
  859. unsigned gs_vgt_table_depth;
  860. unsigned gs_prim_buffer_depth;
  861. uint32_t tile_mode_array[32];
  862. uint32_t macrotile_mode_array[16];
  863. struct gb_addr_config gb_addr_config_fields;
  864. struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
  865. /* gfx configure feature */
  866. uint32_t double_offchip_lds_buf;
  867. };
  868. struct amdgpu_cu_info {
  869. uint32_t number; /* total active CU number */
  870. uint32_t ao_cu_mask;
  871. uint32_t wave_front_size;
  872. uint32_t bitmap[4][4];
  873. };
  874. struct amdgpu_gfx_funcs {
  875. /* get the gpu clock counter */
  876. uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
  877. void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
  878. void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
  879. void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
  880. void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
  881. };
  882. struct amdgpu_ngg_buf {
  883. struct amdgpu_bo *bo;
  884. uint64_t gpu_addr;
  885. uint32_t size;
  886. uint32_t bo_size;
  887. };
  888. enum {
  889. NGG_PRIM = 0,
  890. NGG_POS,
  891. NGG_CNTL,
  892. NGG_PARAM,
  893. NGG_BUF_MAX
  894. };
  895. struct amdgpu_ngg {
  896. struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
  897. uint32_t gds_reserve_addr;
  898. uint32_t gds_reserve_size;
  899. bool init;
  900. };
  901. struct amdgpu_gfx {
  902. struct mutex gpu_clock_mutex;
  903. struct amdgpu_gfx_config config;
  904. struct amdgpu_rlc rlc;
  905. struct amdgpu_mec mec;
  906. struct amdgpu_kiq kiq;
  907. struct amdgpu_scratch scratch;
  908. const struct firmware *me_fw; /* ME firmware */
  909. uint32_t me_fw_version;
  910. const struct firmware *pfp_fw; /* PFP firmware */
  911. uint32_t pfp_fw_version;
  912. const struct firmware *ce_fw; /* CE firmware */
  913. uint32_t ce_fw_version;
  914. const struct firmware *rlc_fw; /* RLC firmware */
  915. uint32_t rlc_fw_version;
  916. const struct firmware *mec_fw; /* MEC firmware */
  917. uint32_t mec_fw_version;
  918. const struct firmware *mec2_fw; /* MEC2 firmware */
  919. uint32_t mec2_fw_version;
  920. uint32_t me_feature_version;
  921. uint32_t ce_feature_version;
  922. uint32_t pfp_feature_version;
  923. uint32_t rlc_feature_version;
  924. uint32_t mec_feature_version;
  925. uint32_t mec2_feature_version;
  926. struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
  927. unsigned num_gfx_rings;
  928. struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
  929. unsigned num_compute_rings;
  930. struct amdgpu_irq_src eop_irq;
  931. struct amdgpu_irq_src priv_reg_irq;
  932. struct amdgpu_irq_src priv_inst_irq;
  933. /* gfx status */
  934. uint32_t gfx_current_status;
  935. /* ce ram size*/
  936. unsigned ce_ram_size;
  937. struct amdgpu_cu_info cu_info;
  938. const struct amdgpu_gfx_funcs *funcs;
  939. /* reset mask */
  940. uint32_t grbm_soft_reset;
  941. uint32_t srbm_soft_reset;
  942. bool in_reset;
  943. /* s3/s4 mask */
  944. bool in_suspend;
  945. /* NGG */
  946. struct amdgpu_ngg ngg;
  947. };
  948. int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  949. unsigned size, struct amdgpu_ib *ib);
  950. void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
  951. struct dma_fence *f);
  952. int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
  953. struct amdgpu_ib *ibs, struct amdgpu_job *job,
  954. struct dma_fence **f);
  955. int amdgpu_ib_pool_init(struct amdgpu_device *adev);
  956. void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
  957. int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
  958. /*
  959. * CS.
  960. */
  961. struct amdgpu_cs_chunk {
  962. uint32_t chunk_id;
  963. uint32_t length_dw;
  964. void *kdata;
  965. };
  966. struct amdgpu_cs_parser {
  967. struct amdgpu_device *adev;
  968. struct drm_file *filp;
  969. struct amdgpu_ctx *ctx;
  970. /* chunks */
  971. unsigned nchunks;
  972. struct amdgpu_cs_chunk *chunks;
  973. /* scheduler job object */
  974. struct amdgpu_job *job;
  975. /* buffer objects */
  976. struct ww_acquire_ctx ticket;
  977. struct amdgpu_bo_list *bo_list;
  978. struct amdgpu_bo_list_entry vm_pd;
  979. struct list_head validated;
  980. struct dma_fence *fence;
  981. uint64_t bytes_moved_threshold;
  982. uint64_t bytes_moved;
  983. struct amdgpu_bo_list_entry *evictable;
  984. /* user fence */
  985. struct amdgpu_bo_list_entry uf_entry;
  986. };
  987. #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
  988. #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
  989. #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
  990. struct amdgpu_job {
  991. struct amd_sched_job base;
  992. struct amdgpu_device *adev;
  993. struct amdgpu_vm *vm;
  994. struct amdgpu_ring *ring;
  995. struct amdgpu_sync sync;
  996. struct amdgpu_sync dep_sync;
  997. struct amdgpu_sync sched_sync;
  998. struct amdgpu_ib *ibs;
  999. struct dma_fence *fence; /* the hw fence */
  1000. uint32_t preamble_status;
  1001. uint32_t num_ibs;
  1002. void *owner;
  1003. uint64_t fence_ctx; /* the fence_context this job uses */
  1004. bool vm_needs_flush;
  1005. unsigned vm_id;
  1006. uint64_t vm_pd_addr;
  1007. uint32_t gds_base, gds_size;
  1008. uint32_t gws_base, gws_size;
  1009. uint32_t oa_base, oa_size;
  1010. /* user fence handling */
  1011. uint64_t uf_addr;
  1012. uint64_t uf_sequence;
  1013. };
  1014. #define to_amdgpu_job(sched_job) \
  1015. container_of((sched_job), struct amdgpu_job, base)
  1016. static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
  1017. uint32_t ib_idx, int idx)
  1018. {
  1019. return p->job->ibs[ib_idx].ptr[idx];
  1020. }
  1021. static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
  1022. uint32_t ib_idx, int idx,
  1023. uint32_t value)
  1024. {
  1025. p->job->ibs[ib_idx].ptr[idx] = value;
  1026. }
  1027. /*
  1028. * Writeback
  1029. */
  1030. #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
  1031. struct amdgpu_wb {
  1032. struct amdgpu_bo *wb_obj;
  1033. volatile uint32_t *wb;
  1034. uint64_t gpu_addr;
  1035. u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
  1036. unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
  1037. };
  1038. int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
  1039. void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
  1040. int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
  1041. void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
  1042. void amdgpu_get_pcie_info(struct amdgpu_device *adev);
  1043. /*
  1044. * SDMA
  1045. */
  1046. struct amdgpu_sdma_instance {
  1047. /* SDMA firmware */
  1048. const struct firmware *fw;
  1049. uint32_t fw_version;
  1050. uint32_t feature_version;
  1051. struct amdgpu_ring ring;
  1052. bool burst_nop;
  1053. };
  1054. struct amdgpu_sdma {
  1055. struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
  1056. #ifdef CONFIG_DRM_AMDGPU_SI
  1057. //SI DMA has a difference trap irq number for the second engine
  1058. struct amdgpu_irq_src trap_irq_1;
  1059. #endif
  1060. struct amdgpu_irq_src trap_irq;
  1061. struct amdgpu_irq_src illegal_inst_irq;
  1062. int num_instances;
  1063. uint32_t srbm_soft_reset;
  1064. };
  1065. /*
  1066. * Firmware
  1067. */
  1068. enum amdgpu_firmware_load_type {
  1069. AMDGPU_FW_LOAD_DIRECT = 0,
  1070. AMDGPU_FW_LOAD_SMU,
  1071. AMDGPU_FW_LOAD_PSP,
  1072. };
  1073. struct amdgpu_firmware {
  1074. struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
  1075. enum amdgpu_firmware_load_type load_type;
  1076. struct amdgpu_bo *fw_buf;
  1077. unsigned int fw_size;
  1078. unsigned int max_ucodes;
  1079. /* firmwares are loaded by psp instead of smu from vega10 */
  1080. const struct amdgpu_psp_funcs *funcs;
  1081. struct amdgpu_bo *rbuf;
  1082. struct mutex mutex;
  1083. };
  1084. /*
  1085. * Benchmarking
  1086. */
  1087. void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
  1088. /*
  1089. * Testing
  1090. */
  1091. void amdgpu_test_moves(struct amdgpu_device *adev);
  1092. /*
  1093. * MMU Notifier
  1094. */
  1095. #if defined(CONFIG_MMU_NOTIFIER)
  1096. int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
  1097. void amdgpu_mn_unregister(struct amdgpu_bo *bo);
  1098. #else
  1099. static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
  1100. {
  1101. return -ENODEV;
  1102. }
  1103. static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
  1104. #endif
  1105. /*
  1106. * Debugfs
  1107. */
  1108. struct amdgpu_debugfs {
  1109. const struct drm_info_list *files;
  1110. unsigned num_files;
  1111. };
  1112. int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
  1113. const struct drm_info_list *files,
  1114. unsigned nfiles);
  1115. int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
  1116. #if defined(CONFIG_DEBUG_FS)
  1117. int amdgpu_debugfs_init(struct drm_minor *minor);
  1118. #endif
  1119. int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
  1120. /*
  1121. * amdgpu smumgr functions
  1122. */
  1123. struct amdgpu_smumgr_funcs {
  1124. int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
  1125. int (*request_smu_load_fw)(struct amdgpu_device *adev);
  1126. int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
  1127. };
  1128. /*
  1129. * amdgpu smumgr
  1130. */
  1131. struct amdgpu_smumgr {
  1132. struct amdgpu_bo *toc_buf;
  1133. struct amdgpu_bo *smu_buf;
  1134. /* asic priv smu data */
  1135. void *priv;
  1136. spinlock_t smu_lock;
  1137. /* smumgr functions */
  1138. const struct amdgpu_smumgr_funcs *smumgr_funcs;
  1139. /* ucode loading complete flag */
  1140. uint32_t fw_flags;
  1141. };
  1142. /*
  1143. * ASIC specific register table accessible by UMD
  1144. */
  1145. struct amdgpu_allowed_register_entry {
  1146. uint32_t reg_offset;
  1147. bool grbm_indexed;
  1148. };
  1149. /*
  1150. * ASIC specific functions.
  1151. */
  1152. struct amdgpu_asic_funcs {
  1153. bool (*read_disabled_bios)(struct amdgpu_device *adev);
  1154. bool (*read_bios_from_rom)(struct amdgpu_device *adev,
  1155. u8 *bios, u32 length_bytes);
  1156. int (*read_register)(struct amdgpu_device *adev, u32 se_num,
  1157. u32 sh_num, u32 reg_offset, u32 *value);
  1158. void (*set_vga_state)(struct amdgpu_device *adev, bool state);
  1159. int (*reset)(struct amdgpu_device *adev);
  1160. /* get the reference clock */
  1161. u32 (*get_xclk)(struct amdgpu_device *adev);
  1162. /* MM block clocks */
  1163. int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
  1164. int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
  1165. /* static power management */
  1166. int (*get_pcie_lanes)(struct amdgpu_device *adev);
  1167. void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
  1168. /* get config memsize register */
  1169. u32 (*get_config_memsize)(struct amdgpu_device *adev);
  1170. };
  1171. /*
  1172. * IOCTL.
  1173. */
  1174. int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
  1175. struct drm_file *filp);
  1176. int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
  1177. struct drm_file *filp);
  1178. int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
  1179. struct drm_file *filp);
  1180. int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
  1181. struct drm_file *filp);
  1182. int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1183. struct drm_file *filp);
  1184. int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
  1185. struct drm_file *filp);
  1186. int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
  1187. struct drm_file *filp);
  1188. int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
  1189. struct drm_file *filp);
  1190. int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
  1191. int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
  1192. int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
  1193. struct drm_file *filp);
  1194. int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
  1195. struct drm_file *filp);
  1196. /* VRAM scratch page for HDP bug, default vram page */
  1197. struct amdgpu_vram_scratch {
  1198. struct amdgpu_bo *robj;
  1199. volatile uint32_t *ptr;
  1200. u64 gpu_addr;
  1201. };
  1202. /*
  1203. * ACPI
  1204. */
  1205. struct amdgpu_atif_notification_cfg {
  1206. bool enabled;
  1207. int command_code;
  1208. };
  1209. struct amdgpu_atif_notifications {
  1210. bool display_switch;
  1211. bool expansion_mode_change;
  1212. bool thermal_state;
  1213. bool forced_power_state;
  1214. bool system_power_state;
  1215. bool display_conf_change;
  1216. bool px_gfx_switch;
  1217. bool brightness_change;
  1218. bool dgpu_display_event;
  1219. };
  1220. struct amdgpu_atif_functions {
  1221. bool system_params;
  1222. bool sbios_requests;
  1223. bool select_active_disp;
  1224. bool lid_state;
  1225. bool get_tv_standard;
  1226. bool set_tv_standard;
  1227. bool get_panel_expansion_mode;
  1228. bool set_panel_expansion_mode;
  1229. bool temperature_change;
  1230. bool graphics_device_types;
  1231. };
  1232. struct amdgpu_atif {
  1233. struct amdgpu_atif_notifications notifications;
  1234. struct amdgpu_atif_functions functions;
  1235. struct amdgpu_atif_notification_cfg notification_cfg;
  1236. struct amdgpu_encoder *encoder_for_bl;
  1237. };
  1238. struct amdgpu_atcs_functions {
  1239. bool get_ext_state;
  1240. bool pcie_perf_req;
  1241. bool pcie_dev_rdy;
  1242. bool pcie_bus_width;
  1243. };
  1244. struct amdgpu_atcs {
  1245. struct amdgpu_atcs_functions functions;
  1246. };
  1247. /*
  1248. * CGS
  1249. */
  1250. struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
  1251. void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
  1252. /*
  1253. * Core structure, functions and helpers.
  1254. */
  1255. typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
  1256. typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
  1257. typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
  1258. typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
  1259. #define AMDGPU_RESET_MAGIC_NUM 64
  1260. struct amdgpu_device {
  1261. struct device *dev;
  1262. struct drm_device *ddev;
  1263. struct pci_dev *pdev;
  1264. #ifdef CONFIG_DRM_AMD_ACP
  1265. struct amdgpu_acp acp;
  1266. #endif
  1267. /* ASIC */
  1268. enum amd_asic_type asic_type;
  1269. uint32_t family;
  1270. uint32_t rev_id;
  1271. uint32_t external_rev_id;
  1272. unsigned long flags;
  1273. int usec_timeout;
  1274. const struct amdgpu_asic_funcs *asic_funcs;
  1275. bool shutdown;
  1276. bool need_dma32;
  1277. bool accel_working;
  1278. struct work_struct reset_work;
  1279. struct notifier_block acpi_nb;
  1280. struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
  1281. struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
  1282. unsigned debugfs_count;
  1283. #if defined(CONFIG_DEBUG_FS)
  1284. struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
  1285. #endif
  1286. struct amdgpu_atif atif;
  1287. struct amdgpu_atcs atcs;
  1288. struct mutex srbm_mutex;
  1289. /* GRBM index mutex. Protects concurrent access to GRBM index */
  1290. struct mutex grbm_idx_mutex;
  1291. struct dev_pm_domain vga_pm_domain;
  1292. bool have_disp_power_ref;
  1293. /* BIOS */
  1294. bool is_atom_fw;
  1295. uint8_t *bios;
  1296. uint32_t bios_size;
  1297. struct amdgpu_bo *stollen_vga_memory;
  1298. uint32_t bios_scratch_reg_offset;
  1299. uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
  1300. /* Register/doorbell mmio */
  1301. resource_size_t rmmio_base;
  1302. resource_size_t rmmio_size;
  1303. void __iomem *rmmio;
  1304. /* protects concurrent MM_INDEX/DATA based register access */
  1305. spinlock_t mmio_idx_lock;
  1306. /* protects concurrent SMC based register access */
  1307. spinlock_t smc_idx_lock;
  1308. amdgpu_rreg_t smc_rreg;
  1309. amdgpu_wreg_t smc_wreg;
  1310. /* protects concurrent PCIE register access */
  1311. spinlock_t pcie_idx_lock;
  1312. amdgpu_rreg_t pcie_rreg;
  1313. amdgpu_wreg_t pcie_wreg;
  1314. amdgpu_rreg_t pciep_rreg;
  1315. amdgpu_wreg_t pciep_wreg;
  1316. /* protects concurrent UVD register access */
  1317. spinlock_t uvd_ctx_idx_lock;
  1318. amdgpu_rreg_t uvd_ctx_rreg;
  1319. amdgpu_wreg_t uvd_ctx_wreg;
  1320. /* protects concurrent DIDT register access */
  1321. spinlock_t didt_idx_lock;
  1322. amdgpu_rreg_t didt_rreg;
  1323. amdgpu_wreg_t didt_wreg;
  1324. /* protects concurrent gc_cac register access */
  1325. spinlock_t gc_cac_idx_lock;
  1326. amdgpu_rreg_t gc_cac_rreg;
  1327. amdgpu_wreg_t gc_cac_wreg;
  1328. /* protects concurrent ENDPOINT (audio) register access */
  1329. spinlock_t audio_endpt_idx_lock;
  1330. amdgpu_block_rreg_t audio_endpt_rreg;
  1331. amdgpu_block_wreg_t audio_endpt_wreg;
  1332. void __iomem *rio_mem;
  1333. resource_size_t rio_mem_size;
  1334. struct amdgpu_doorbell doorbell;
  1335. /* clock/pll info */
  1336. struct amdgpu_clock clock;
  1337. /* MC */
  1338. struct amdgpu_mc mc;
  1339. struct amdgpu_gart gart;
  1340. struct amdgpu_dummy_page dummy_page;
  1341. struct amdgpu_vm_manager vm_manager;
  1342. struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
  1343. /* memory management */
  1344. struct amdgpu_mman mman;
  1345. struct amdgpu_vram_scratch vram_scratch;
  1346. struct amdgpu_wb wb;
  1347. atomic64_t vram_usage;
  1348. atomic64_t vram_vis_usage;
  1349. atomic64_t gtt_usage;
  1350. atomic64_t num_bytes_moved;
  1351. atomic64_t num_evictions;
  1352. atomic64_t num_vram_cpu_page_faults;
  1353. atomic_t gpu_reset_counter;
  1354. atomic_t vram_lost_counter;
  1355. /* data for buffer migration throttling */
  1356. struct {
  1357. spinlock_t lock;
  1358. s64 last_update_us;
  1359. s64 accum_us; /* accumulated microseconds */
  1360. u32 log2_max_MBps;
  1361. } mm_stats;
  1362. /* display */
  1363. bool enable_virtual_display;
  1364. struct amdgpu_mode_info mode_info;
  1365. struct work_struct hotplug_work;
  1366. struct amdgpu_irq_src crtc_irq;
  1367. struct amdgpu_irq_src pageflip_irq;
  1368. struct amdgpu_irq_src hpd_irq;
  1369. /* rings */
  1370. u64 fence_context;
  1371. unsigned num_rings;
  1372. struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
  1373. bool ib_pool_ready;
  1374. struct amdgpu_sa_manager ring_tmp_bo;
  1375. /* interrupts */
  1376. struct amdgpu_irq irq;
  1377. /* powerplay */
  1378. struct amd_powerplay powerplay;
  1379. bool pp_enabled;
  1380. bool pp_force_state_enabled;
  1381. /* dpm */
  1382. struct amdgpu_pm pm;
  1383. u32 cg_flags;
  1384. u32 pg_flags;
  1385. /* amdgpu smumgr */
  1386. struct amdgpu_smumgr smu;
  1387. /* gfx */
  1388. struct amdgpu_gfx gfx;
  1389. /* sdma */
  1390. struct amdgpu_sdma sdma;
  1391. union {
  1392. struct {
  1393. /* uvd */
  1394. struct amdgpu_uvd uvd;
  1395. /* vce */
  1396. struct amdgpu_vce vce;
  1397. };
  1398. /* vcn */
  1399. struct amdgpu_vcn vcn;
  1400. };
  1401. /* firmwares */
  1402. struct amdgpu_firmware firmware;
  1403. /* PSP */
  1404. struct psp_context psp;
  1405. /* GDS */
  1406. struct amdgpu_gds gds;
  1407. struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
  1408. int num_ip_blocks;
  1409. struct mutex mn_lock;
  1410. DECLARE_HASHTABLE(mn_hash, 7);
  1411. /* tracking pinned memory */
  1412. u64 vram_pin_size;
  1413. u64 invisible_pin_size;
  1414. u64 gart_pin_size;
  1415. /* amdkfd interface */
  1416. struct kfd_dev *kfd;
  1417. /* delayed work_func for deferring clockgating during resume */
  1418. struct delayed_work late_init_work;
  1419. struct amdgpu_virt virt;
  1420. /* link all shadow bo */
  1421. struct list_head shadow_list;
  1422. struct mutex shadow_list_lock;
  1423. /* link all gtt */
  1424. spinlock_t gtt_list_lock;
  1425. struct list_head gtt_list;
  1426. /* record hw reset is performed */
  1427. bool has_hw_reset;
  1428. u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
  1429. };
  1430. static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
  1431. {
  1432. return container_of(bdev, struct amdgpu_device, mman.bdev);
  1433. }
  1434. bool amdgpu_device_is_px(struct drm_device *dev);
  1435. int amdgpu_device_init(struct amdgpu_device *adev,
  1436. struct drm_device *ddev,
  1437. struct pci_dev *pdev,
  1438. uint32_t flags);
  1439. void amdgpu_device_fini(struct amdgpu_device *adev);
  1440. int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
  1441. uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  1442. uint32_t acc_flags);
  1443. void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  1444. uint32_t acc_flags);
  1445. u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
  1446. void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
  1447. u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
  1448. void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
  1449. u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
  1450. void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
  1451. /*
  1452. * Registers read & write functions.
  1453. */
  1454. #define AMDGPU_REGS_IDX (1<<0)
  1455. #define AMDGPU_REGS_NO_KIQ (1<<1)
  1456. #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
  1457. #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
  1458. #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
  1459. #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
  1460. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
  1461. #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
  1462. #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
  1463. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1464. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1465. #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
  1466. #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
  1467. #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
  1468. #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
  1469. #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
  1470. #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
  1471. #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
  1472. #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
  1473. #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
  1474. #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
  1475. #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
  1476. #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
  1477. #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
  1478. #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
  1479. #define WREG32_P(reg, val, mask) \
  1480. do { \
  1481. uint32_t tmp_ = RREG32(reg); \
  1482. tmp_ &= (mask); \
  1483. tmp_ |= ((val) & ~(mask)); \
  1484. WREG32(reg, tmp_); \
  1485. } while (0)
  1486. #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
  1487. #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
  1488. #define WREG32_PLL_P(reg, val, mask) \
  1489. do { \
  1490. uint32_t tmp_ = RREG32_PLL(reg); \
  1491. tmp_ &= (mask); \
  1492. tmp_ |= ((val) & ~(mask)); \
  1493. WREG32_PLL(reg, tmp_); \
  1494. } while (0)
  1495. #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
  1496. #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
  1497. #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
  1498. #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
  1499. #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
  1500. #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
  1501. #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
  1502. #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
  1503. #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
  1504. #define REG_SET_FIELD(orig_val, reg, field, field_val) \
  1505. (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
  1506. (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
  1507. #define REG_GET_FIELD(value, reg, field) \
  1508. (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
  1509. #define WREG32_FIELD(reg, field, val) \
  1510. WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  1511. #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
  1512. WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  1513. /*
  1514. * BIOS helpers.
  1515. */
  1516. #define RBIOS8(i) (adev->bios[i])
  1517. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  1518. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  1519. /*
  1520. * RING helpers.
  1521. */
  1522. static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
  1523. {
  1524. if (ring->count_dw <= 0)
  1525. DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
  1526. ring->ring[ring->wptr++ & ring->buf_mask] = v;
  1527. ring->wptr &= ring->ptr_mask;
  1528. ring->count_dw--;
  1529. }
  1530. static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
  1531. {
  1532. unsigned occupied, chunk1, chunk2;
  1533. void *dst;
  1534. if (unlikely(ring->count_dw < count_dw)) {
  1535. DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
  1536. return;
  1537. }
  1538. occupied = ring->wptr & ring->buf_mask;
  1539. dst = (void *)&ring->ring[occupied];
  1540. chunk1 = ring->buf_mask + 1 - occupied;
  1541. chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
  1542. chunk2 = count_dw - chunk1;
  1543. chunk1 <<= 2;
  1544. chunk2 <<= 2;
  1545. if (chunk1)
  1546. memcpy(dst, src, chunk1);
  1547. if (chunk2) {
  1548. src += chunk1;
  1549. dst = (void *)ring->ring;
  1550. memcpy(dst, src, chunk2);
  1551. }
  1552. ring->wptr += count_dw;
  1553. ring->wptr &= ring->ptr_mask;
  1554. ring->count_dw -= count_dw;
  1555. }
  1556. static inline struct amdgpu_sdma_instance *
  1557. amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
  1558. {
  1559. struct amdgpu_device *adev = ring->adev;
  1560. int i;
  1561. for (i = 0; i < adev->sdma.num_instances; i++)
  1562. if (&adev->sdma.instance[i].ring == ring)
  1563. break;
  1564. if (i < AMDGPU_MAX_SDMA_INSTANCES)
  1565. return &adev->sdma.instance[i];
  1566. else
  1567. return NULL;
  1568. }
  1569. /*
  1570. * ASICs macro.
  1571. */
  1572. #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
  1573. #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
  1574. #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
  1575. #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
  1576. #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
  1577. #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
  1578. #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
  1579. #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
  1580. #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
  1581. #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
  1582. #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
  1583. #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
  1584. #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
  1585. #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
  1586. #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
  1587. #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
  1588. #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
  1589. #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
  1590. #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
  1591. #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
  1592. #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
  1593. #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
  1594. #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
  1595. #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
  1596. #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
  1597. #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
  1598. #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
  1599. #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
  1600. #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
  1601. #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
  1602. #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
  1603. #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
  1604. #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
  1605. #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
  1606. #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
  1607. #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
  1608. #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
  1609. #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
  1610. #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
  1611. #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
  1612. #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
  1613. #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
  1614. #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
  1615. #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
  1616. #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
  1617. #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
  1618. #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
  1619. #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
  1620. #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
  1621. #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
  1622. #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
  1623. #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
  1624. #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
  1625. #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
  1626. #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
  1627. #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
  1628. #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
  1629. #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
  1630. #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
  1631. #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
  1632. #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
  1633. #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
  1634. #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
  1635. #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
  1636. /* Common functions */
  1637. int amdgpu_gpu_reset(struct amdgpu_device *adev);
  1638. bool amdgpu_need_backup(struct amdgpu_device *adev);
  1639. void amdgpu_pci_config_reset(struct amdgpu_device *adev);
  1640. bool amdgpu_need_post(struct amdgpu_device *adev);
  1641. void amdgpu_update_display_priority(struct amdgpu_device *adev);
  1642. int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
  1643. int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  1644. u32 ip_instance, u32 ring,
  1645. struct amdgpu_ring **out_ring);
  1646. void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
  1647. void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
  1648. bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
  1649. int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
  1650. int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
  1651. uint32_t flags);
  1652. bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
  1653. struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
  1654. bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
  1655. unsigned long end);
  1656. bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
  1657. int *last_invalidated);
  1658. bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
  1659. uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
  1660. struct ttm_mem_reg *mem);
  1661. void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
  1662. void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
  1663. void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
  1664. int amdgpu_ttm_init(struct amdgpu_device *adev);
  1665. void amdgpu_ttm_fini(struct amdgpu_device *adev);
  1666. void amdgpu_program_register_sequence(struct amdgpu_device *adev,
  1667. const u32 *registers,
  1668. const u32 array_size);
  1669. bool amdgpu_device_is_px(struct drm_device *dev);
  1670. /* atpx handler */
  1671. #if defined(CONFIG_VGA_SWITCHEROO)
  1672. void amdgpu_register_atpx_handler(void);
  1673. void amdgpu_unregister_atpx_handler(void);
  1674. bool amdgpu_has_atpx_dgpu_power_cntl(void);
  1675. bool amdgpu_is_atpx_hybrid(void);
  1676. bool amdgpu_atpx_dgpu_req_power_for_displays(void);
  1677. bool amdgpu_has_atpx(void);
  1678. #else
  1679. static inline void amdgpu_register_atpx_handler(void) {}
  1680. static inline void amdgpu_unregister_atpx_handler(void) {}
  1681. static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
  1682. static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
  1683. static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
  1684. static inline bool amdgpu_has_atpx(void) { return false; }
  1685. #endif
  1686. /*
  1687. * KMS
  1688. */
  1689. extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
  1690. extern const int amdgpu_max_kms_ioctl;
  1691. bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
  1692. struct amdgpu_fpriv *fpriv);
  1693. int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
  1694. void amdgpu_driver_unload_kms(struct drm_device *dev);
  1695. void amdgpu_driver_lastclose_kms(struct drm_device *dev);
  1696. int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
  1697. void amdgpu_driver_postclose_kms(struct drm_device *dev,
  1698. struct drm_file *file_priv);
  1699. int amdgpu_suspend(struct amdgpu_device *adev);
  1700. int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
  1701. int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
  1702. u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
  1703. int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
  1704. void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
  1705. long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
  1706. unsigned long arg);
  1707. /*
  1708. * functions used by amdgpu_encoder.c
  1709. */
  1710. struct amdgpu_afmt_acr {
  1711. u32 clock;
  1712. int n_32khz;
  1713. int cts_32khz;
  1714. int n_44_1khz;
  1715. int cts_44_1khz;
  1716. int n_48khz;
  1717. int cts_48khz;
  1718. };
  1719. struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
  1720. /* amdgpu_acpi.c */
  1721. #if defined(CONFIG_ACPI)
  1722. int amdgpu_acpi_init(struct amdgpu_device *adev);
  1723. void amdgpu_acpi_fini(struct amdgpu_device *adev);
  1724. bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
  1725. int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
  1726. u8 perf_req, bool advertise);
  1727. int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
  1728. #else
  1729. static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
  1730. static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
  1731. #endif
  1732. struct amdgpu_bo_va_mapping *
  1733. amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
  1734. uint64_t addr, struct amdgpu_bo **bo);
  1735. int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
  1736. #include "amdgpu_object.h"
  1737. #endif