smc_wr.c 16 KB

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  1. /*
  2. * Shared Memory Communications over RDMA (SMC-R) and RoCE
  3. *
  4. * Work Requests exploiting Infiniband API
  5. *
  6. * Work requests (WR) of type ib_post_send or ib_post_recv respectively
  7. * are submitted to either RC SQ or RC RQ respectively
  8. * (reliably connected send/receive queue)
  9. * and become work queue entries (WQEs).
  10. * While an SQ WR/WQE is pending, we track it until transmission completion.
  11. * Through a send or receive completion queue (CQ) respectively,
  12. * we get completion queue entries (CQEs) [aka work completions (WCs)].
  13. * Since the CQ callback is called from IRQ context, we split work by using
  14. * bottom halves implemented by tasklets.
  15. *
  16. * SMC uses this to exchange LLC (link layer control)
  17. * and CDC (connection data control) messages.
  18. *
  19. * Copyright IBM Corp. 2016
  20. *
  21. * Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
  22. */
  23. #include <linux/atomic.h>
  24. #include <linux/hashtable.h>
  25. #include <linux/wait.h>
  26. #include <rdma/ib_verbs.h>
  27. #include <asm/div64.h>
  28. #include "smc.h"
  29. #include "smc_wr.h"
  30. #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
  31. #define SMC_WR_RX_HASH_BITS 4
  32. static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
  33. static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
  34. struct smc_wr_tx_pend { /* control data for a pending send request */
  35. u64 wr_id; /* work request id sent */
  36. smc_wr_tx_handler handler;
  37. enum ib_wc_status wc_status; /* CQE status */
  38. struct smc_link *link;
  39. u32 idx;
  40. struct smc_wr_tx_pend_priv priv;
  41. };
  42. /******************************** send queue *********************************/
  43. /*------------------------------- completion --------------------------------*/
  44. static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
  45. {
  46. u32 i;
  47. for (i = 0; i < link->wr_tx_cnt; i++) {
  48. if (link->wr_tx_pends[i].wr_id == wr_id)
  49. return i;
  50. }
  51. return link->wr_tx_cnt;
  52. }
  53. static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
  54. {
  55. struct smc_wr_tx_pend pnd_snd;
  56. struct smc_link *link;
  57. u32 pnd_snd_idx;
  58. int i;
  59. link = wc->qp->qp_context;
  60. pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
  61. if (pnd_snd_idx == link->wr_tx_cnt)
  62. return;
  63. link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
  64. memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx], sizeof(pnd_snd));
  65. /* clear the full struct smc_wr_tx_pend including .priv */
  66. memset(&link->wr_tx_pends[pnd_snd_idx], 0,
  67. sizeof(link->wr_tx_pends[pnd_snd_idx]));
  68. memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
  69. sizeof(link->wr_tx_bufs[pnd_snd_idx]));
  70. if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
  71. return;
  72. if (wc->status) {
  73. struct smc_link_group *lgr;
  74. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  75. /* clear full struct smc_wr_tx_pend including .priv */
  76. memset(&link->wr_tx_pends[i], 0,
  77. sizeof(link->wr_tx_pends[i]));
  78. memset(&link->wr_tx_bufs[i], 0,
  79. sizeof(link->wr_tx_bufs[i]));
  80. clear_bit(i, link->wr_tx_mask);
  81. }
  82. /* terminate connections of this link group abnormally */
  83. lgr = container_of(link, struct smc_link_group,
  84. lnk[SMC_SINGLE_LINK]);
  85. smc_lgr_terminate(lgr);
  86. }
  87. if (pnd_snd.handler)
  88. pnd_snd.handler(&pnd_snd.priv, link, wc->status);
  89. wake_up(&link->wr_tx_wait);
  90. }
  91. static void smc_wr_tx_tasklet_fn(unsigned long data)
  92. {
  93. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  94. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  95. int i = 0, rc;
  96. int polled = 0;
  97. again:
  98. polled++;
  99. do {
  100. rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
  101. if (polled == 1) {
  102. ib_req_notify_cq(dev->roce_cq_send,
  103. IB_CQ_NEXT_COMP |
  104. IB_CQ_REPORT_MISSED_EVENTS);
  105. }
  106. if (!rc)
  107. break;
  108. for (i = 0; i < rc; i++)
  109. smc_wr_tx_process_cqe(&wc[i]);
  110. } while (rc > 0);
  111. if (polled == 1)
  112. goto again;
  113. }
  114. void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  115. {
  116. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  117. tasklet_schedule(&dev->send_tasklet);
  118. }
  119. /*---------------------------- request submission ---------------------------*/
  120. static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
  121. {
  122. *idx = link->wr_tx_cnt;
  123. for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
  124. if (!test_and_set_bit(*idx, link->wr_tx_mask))
  125. return 0;
  126. }
  127. *idx = link->wr_tx_cnt;
  128. return -EBUSY;
  129. }
  130. /**
  131. * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
  132. * and sets info for pending transmit tracking
  133. * @link: Pointer to smc_link used to later send the message.
  134. * @handler: Send completion handler function pointer.
  135. * @wr_buf: Out value returns pointer to message buffer.
  136. * @wr_pend_priv: Out value returns pointer serving as handler context.
  137. *
  138. * Return: 0 on success, or -errno on error.
  139. */
  140. int smc_wr_tx_get_free_slot(struct smc_link *link,
  141. smc_wr_tx_handler handler,
  142. struct smc_wr_buf **wr_buf,
  143. struct smc_wr_tx_pend_priv **wr_pend_priv)
  144. {
  145. struct smc_wr_tx_pend *wr_pend;
  146. struct ib_send_wr *wr_ib;
  147. u64 wr_id;
  148. u32 idx;
  149. int rc;
  150. *wr_buf = NULL;
  151. *wr_pend_priv = NULL;
  152. if (in_softirq()) {
  153. rc = smc_wr_tx_get_free_slot_index(link, &idx);
  154. if (rc)
  155. return rc;
  156. } else {
  157. rc = wait_event_interruptible_timeout(
  158. link->wr_tx_wait,
  159. (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
  160. SMC_WR_TX_WAIT_FREE_SLOT_TIME);
  161. if (!rc) {
  162. /* timeout - terminate connections */
  163. struct smc_link_group *lgr;
  164. lgr = container_of(link, struct smc_link_group,
  165. lnk[SMC_SINGLE_LINK]);
  166. smc_lgr_terminate(lgr);
  167. return -EPIPE;
  168. }
  169. if (rc == -ERESTARTSYS)
  170. return -EINTR;
  171. if (idx == link->wr_tx_cnt)
  172. return -EPIPE;
  173. }
  174. wr_id = smc_wr_tx_get_next_wr_id(link);
  175. wr_pend = &link->wr_tx_pends[idx];
  176. wr_pend->wr_id = wr_id;
  177. wr_pend->handler = handler;
  178. wr_pend->link = link;
  179. wr_pend->idx = idx;
  180. wr_ib = &link->wr_tx_ibs[idx];
  181. wr_ib->wr_id = wr_id;
  182. *wr_buf = &link->wr_tx_bufs[idx];
  183. *wr_pend_priv = &wr_pend->priv;
  184. return 0;
  185. }
  186. int smc_wr_tx_put_slot(struct smc_link *link,
  187. struct smc_wr_tx_pend_priv *wr_pend_priv)
  188. {
  189. struct smc_wr_tx_pend *pend;
  190. pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
  191. if (pend->idx < link->wr_tx_cnt) {
  192. /* clear the full struct smc_wr_tx_pend including .priv */
  193. memset(&link->wr_tx_pends[pend->idx], 0,
  194. sizeof(link->wr_tx_pends[pend->idx]));
  195. memset(&link->wr_tx_bufs[pend->idx], 0,
  196. sizeof(link->wr_tx_bufs[pend->idx]));
  197. test_and_clear_bit(pend->idx, link->wr_tx_mask);
  198. return 1;
  199. }
  200. return 0;
  201. }
  202. /* Send prepared WR slot via ib_post_send.
  203. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  204. */
  205. int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
  206. {
  207. struct ib_send_wr *failed_wr = NULL;
  208. struct smc_wr_tx_pend *pend;
  209. int rc;
  210. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  211. IB_CQ_SOLICITED_MASK | IB_CQ_REPORT_MISSED_EVENTS);
  212. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  213. rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx],
  214. &failed_wr);
  215. if (rc)
  216. smc_wr_tx_put_slot(link, priv);
  217. return rc;
  218. }
  219. void smc_wr_tx_dismiss_slots(struct smc_link *link, u8 wr_rx_hdr_type,
  220. smc_wr_tx_filter filter,
  221. smc_wr_tx_dismisser dismisser,
  222. unsigned long data)
  223. {
  224. struct smc_wr_tx_pend_priv *tx_pend;
  225. struct smc_wr_rx_hdr *wr_rx;
  226. int i;
  227. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  228. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[i];
  229. if (wr_rx->type != wr_rx_hdr_type)
  230. continue;
  231. tx_pend = &link->wr_tx_pends[i].priv;
  232. if (filter(tx_pend, data))
  233. dismisser(tx_pend);
  234. }
  235. }
  236. bool smc_wr_tx_has_pending(struct smc_link *link, u8 wr_rx_hdr_type,
  237. smc_wr_tx_filter filter, unsigned long data)
  238. {
  239. struct smc_wr_tx_pend_priv *tx_pend;
  240. struct smc_wr_rx_hdr *wr_rx;
  241. int i;
  242. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  243. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[i];
  244. if (wr_rx->type != wr_rx_hdr_type)
  245. continue;
  246. tx_pend = &link->wr_tx_pends[i].priv;
  247. if (filter(tx_pend, data))
  248. return true;
  249. }
  250. return false;
  251. }
  252. /****************************** receive queue ********************************/
  253. int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
  254. {
  255. struct smc_wr_rx_handler *h_iter;
  256. int rc = 0;
  257. spin_lock(&smc_wr_rx_hash_lock);
  258. hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
  259. if (h_iter->type == handler->type) {
  260. rc = -EEXIST;
  261. goto out_unlock;
  262. }
  263. }
  264. hash_add(smc_wr_rx_hash, &handler->list, handler->type);
  265. out_unlock:
  266. spin_unlock(&smc_wr_rx_hash_lock);
  267. return rc;
  268. }
  269. /* Demultiplex a received work request based on the message type to its handler.
  270. * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
  271. * and not being modified any more afterwards so we don't need to lock it.
  272. */
  273. static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
  274. {
  275. struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
  276. struct smc_wr_rx_handler *handler;
  277. struct smc_wr_rx_hdr *wr_rx;
  278. u64 temp_wr_id;
  279. u32 index;
  280. if (wc->byte_len < sizeof(*wr_rx))
  281. return; /* short message */
  282. temp_wr_id = wc->wr_id;
  283. index = do_div(temp_wr_id, link->wr_rx_cnt);
  284. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
  285. hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
  286. if (handler->type == wr_rx->type)
  287. handler->handler(wc, wr_rx);
  288. }
  289. }
  290. static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
  291. {
  292. struct smc_link *link;
  293. int i;
  294. for (i = 0; i < num; i++) {
  295. link = wc[i].qp->qp_context;
  296. if (wc[i].status == IB_WC_SUCCESS) {
  297. smc_wr_rx_demultiplex(&wc[i]);
  298. smc_wr_rx_post(link); /* refill WR RX */
  299. } else {
  300. struct smc_link_group *lgr;
  301. /* handle status errors */
  302. switch (wc[i].status) {
  303. case IB_WC_RETRY_EXC_ERR:
  304. case IB_WC_RNR_RETRY_EXC_ERR:
  305. case IB_WC_WR_FLUSH_ERR:
  306. /* terminate connections of this link group
  307. * abnormally
  308. */
  309. lgr = container_of(link, struct smc_link_group,
  310. lnk[SMC_SINGLE_LINK]);
  311. smc_lgr_terminate(lgr);
  312. break;
  313. default:
  314. smc_wr_rx_post(link); /* refill WR RX */
  315. break;
  316. }
  317. }
  318. }
  319. }
  320. static void smc_wr_rx_tasklet_fn(unsigned long data)
  321. {
  322. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  323. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  324. int polled = 0;
  325. int rc;
  326. again:
  327. polled++;
  328. do {
  329. memset(&wc, 0, sizeof(wc));
  330. rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
  331. if (polled == 1) {
  332. ib_req_notify_cq(dev->roce_cq_recv,
  333. IB_CQ_SOLICITED_MASK
  334. | IB_CQ_REPORT_MISSED_EVENTS);
  335. }
  336. if (!rc)
  337. break;
  338. smc_wr_rx_process_cqes(&wc[0], rc);
  339. } while (rc > 0);
  340. if (polled == 1)
  341. goto again;
  342. }
  343. void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  344. {
  345. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  346. tasklet_schedule(&dev->recv_tasklet);
  347. }
  348. int smc_wr_rx_post_init(struct smc_link *link)
  349. {
  350. u32 i;
  351. int rc = 0;
  352. for (i = 0; i < link->wr_rx_cnt; i++)
  353. rc = smc_wr_rx_post(link);
  354. return rc;
  355. }
  356. /***************************** init, exit, misc ******************************/
  357. void smc_wr_remember_qp_attr(struct smc_link *lnk)
  358. {
  359. struct ib_qp_attr *attr = &lnk->qp_attr;
  360. struct ib_qp_init_attr init_attr;
  361. memset(attr, 0, sizeof(*attr));
  362. memset(&init_attr, 0, sizeof(init_attr));
  363. ib_query_qp(lnk->roce_qp, attr,
  364. IB_QP_STATE |
  365. IB_QP_CUR_STATE |
  366. IB_QP_PKEY_INDEX |
  367. IB_QP_PORT |
  368. IB_QP_QKEY |
  369. IB_QP_AV |
  370. IB_QP_PATH_MTU |
  371. IB_QP_TIMEOUT |
  372. IB_QP_RETRY_CNT |
  373. IB_QP_RNR_RETRY |
  374. IB_QP_RQ_PSN |
  375. IB_QP_ALT_PATH |
  376. IB_QP_MIN_RNR_TIMER |
  377. IB_QP_SQ_PSN |
  378. IB_QP_PATH_MIG_STATE |
  379. IB_QP_CAP |
  380. IB_QP_DEST_QPN,
  381. &init_attr);
  382. lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
  383. lnk->qp_attr.cap.max_send_wr);
  384. lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
  385. lnk->qp_attr.cap.max_recv_wr);
  386. }
  387. static void smc_wr_init_sge(struct smc_link *lnk)
  388. {
  389. u32 i;
  390. for (i = 0; i < lnk->wr_tx_cnt; i++) {
  391. lnk->wr_tx_sges[i].addr =
  392. lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
  393. lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
  394. lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  395. lnk->wr_tx_ibs[i].next = NULL;
  396. lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
  397. lnk->wr_tx_ibs[i].num_sge = 1;
  398. lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
  399. lnk->wr_tx_ibs[i].send_flags =
  400. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  401. }
  402. for (i = 0; i < lnk->wr_rx_cnt; i++) {
  403. lnk->wr_rx_sges[i].addr =
  404. lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
  405. lnk->wr_rx_sges[i].length = SMC_WR_BUF_SIZE;
  406. lnk->wr_rx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  407. lnk->wr_rx_ibs[i].next = NULL;
  408. lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[i];
  409. lnk->wr_rx_ibs[i].num_sge = 1;
  410. }
  411. }
  412. void smc_wr_free_link(struct smc_link *lnk)
  413. {
  414. struct ib_device *ibdev;
  415. memset(lnk->wr_tx_mask, 0,
  416. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  417. if (!lnk->smcibdev)
  418. return;
  419. ibdev = lnk->smcibdev->ibdev;
  420. if (lnk->wr_rx_dma_addr) {
  421. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  422. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  423. DMA_FROM_DEVICE);
  424. lnk->wr_rx_dma_addr = 0;
  425. }
  426. if (lnk->wr_tx_dma_addr) {
  427. ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
  428. SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  429. DMA_TO_DEVICE);
  430. lnk->wr_tx_dma_addr = 0;
  431. }
  432. }
  433. void smc_wr_free_link_mem(struct smc_link *lnk)
  434. {
  435. kfree(lnk->wr_tx_pends);
  436. lnk->wr_tx_pends = NULL;
  437. kfree(lnk->wr_tx_mask);
  438. lnk->wr_tx_mask = NULL;
  439. kfree(lnk->wr_tx_sges);
  440. lnk->wr_tx_sges = NULL;
  441. kfree(lnk->wr_rx_sges);
  442. lnk->wr_rx_sges = NULL;
  443. kfree(lnk->wr_rx_ibs);
  444. lnk->wr_rx_ibs = NULL;
  445. kfree(lnk->wr_tx_ibs);
  446. lnk->wr_tx_ibs = NULL;
  447. kfree(lnk->wr_tx_bufs);
  448. lnk->wr_tx_bufs = NULL;
  449. kfree(lnk->wr_rx_bufs);
  450. lnk->wr_rx_bufs = NULL;
  451. }
  452. int smc_wr_alloc_link_mem(struct smc_link *link)
  453. {
  454. /* allocate link related memory */
  455. link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
  456. if (!link->wr_tx_bufs)
  457. goto no_mem;
  458. link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
  459. GFP_KERNEL);
  460. if (!link->wr_rx_bufs)
  461. goto no_mem_wr_tx_bufs;
  462. link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
  463. GFP_KERNEL);
  464. if (!link->wr_tx_ibs)
  465. goto no_mem_wr_rx_bufs;
  466. link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
  467. sizeof(link->wr_rx_ibs[0]),
  468. GFP_KERNEL);
  469. if (!link->wr_rx_ibs)
  470. goto no_mem_wr_tx_ibs;
  471. link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
  472. GFP_KERNEL);
  473. if (!link->wr_tx_sges)
  474. goto no_mem_wr_rx_ibs;
  475. link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
  476. sizeof(link->wr_rx_sges[0]),
  477. GFP_KERNEL);
  478. if (!link->wr_rx_sges)
  479. goto no_mem_wr_tx_sges;
  480. link->wr_tx_mask = kzalloc(
  481. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*link->wr_tx_mask),
  482. GFP_KERNEL);
  483. if (!link->wr_tx_mask)
  484. goto no_mem_wr_rx_sges;
  485. link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
  486. sizeof(link->wr_tx_pends[0]),
  487. GFP_KERNEL);
  488. if (!link->wr_tx_pends)
  489. goto no_mem_wr_tx_mask;
  490. return 0;
  491. no_mem_wr_tx_mask:
  492. kfree(link->wr_tx_mask);
  493. no_mem_wr_rx_sges:
  494. kfree(link->wr_rx_sges);
  495. no_mem_wr_tx_sges:
  496. kfree(link->wr_tx_sges);
  497. no_mem_wr_rx_ibs:
  498. kfree(link->wr_rx_ibs);
  499. no_mem_wr_tx_ibs:
  500. kfree(link->wr_tx_ibs);
  501. no_mem_wr_rx_bufs:
  502. kfree(link->wr_rx_bufs);
  503. no_mem_wr_tx_bufs:
  504. kfree(link->wr_tx_bufs);
  505. no_mem:
  506. return -ENOMEM;
  507. }
  508. void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
  509. {
  510. tasklet_kill(&smcibdev->recv_tasklet);
  511. tasklet_kill(&smcibdev->send_tasklet);
  512. }
  513. void smc_wr_add_dev(struct smc_ib_device *smcibdev)
  514. {
  515. tasklet_init(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn,
  516. (unsigned long)smcibdev);
  517. tasklet_init(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn,
  518. (unsigned long)smcibdev);
  519. }
  520. int smc_wr_create_link(struct smc_link *lnk)
  521. {
  522. struct ib_device *ibdev = lnk->smcibdev->ibdev;
  523. int rc = 0;
  524. smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
  525. lnk->wr_rx_id = 0;
  526. lnk->wr_rx_dma_addr = ib_dma_map_single(
  527. ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  528. DMA_FROM_DEVICE);
  529. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
  530. lnk->wr_rx_dma_addr = 0;
  531. rc = -EIO;
  532. goto out;
  533. }
  534. lnk->wr_tx_dma_addr = ib_dma_map_single(
  535. ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  536. DMA_TO_DEVICE);
  537. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
  538. rc = -EIO;
  539. goto dma_unmap;
  540. }
  541. smc_wr_init_sge(lnk);
  542. memset(lnk->wr_tx_mask, 0,
  543. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  544. return rc;
  545. dma_unmap:
  546. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  547. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  548. DMA_FROM_DEVICE);
  549. lnk->wr_rx_dma_addr = 0;
  550. out:
  551. return rc;
  552. }