pci-xgene.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * APM X-Gene PCIe Driver
  4. *
  5. * Copyright (c) 2014 Applied Micro Circuits Corporation.
  6. *
  7. * Author: Tanmay Inamdar <tinamdar@apm.com>.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/memblock.h>
  14. #include <linux/init.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_pci.h>
  19. #include <linux/pci.h>
  20. #include <linux/pci-acpi.h>
  21. #include <linux/pci-ecam.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/slab.h>
  24. #define PCIECORE_CTLANDSTATUS 0x50
  25. #define PIM1_1L 0x80
  26. #define IBAR2 0x98
  27. #define IR2MSK 0x9c
  28. #define PIM2_1L 0xa0
  29. #define IBAR3L 0xb4
  30. #define IR3MSKL 0xbc
  31. #define PIM3_1L 0xc4
  32. #define OMR1BARL 0x100
  33. #define OMR2BARL 0x118
  34. #define OMR3BARL 0x130
  35. #define CFGBARL 0x154
  36. #define CFGBARH 0x158
  37. #define CFGCTL 0x15c
  38. #define RTDID 0x160
  39. #define BRIDGE_CFG_0 0x2000
  40. #define BRIDGE_CFG_4 0x2010
  41. #define BRIDGE_STATUS_0 0x2600
  42. #define LINK_UP_MASK 0x00000100
  43. #define AXI_EP_CFG_ACCESS 0x10000
  44. #define EN_COHERENCY 0xF0000000
  45. #define EN_REG 0x00000001
  46. #define OB_LO_IO 0x00000002
  47. #define XGENE_PCIE_VENDORID 0x10E8
  48. #define XGENE_PCIE_DEVICEID 0xE004
  49. #define SZ_1T (SZ_1G*1024ULL)
  50. #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
  51. #define XGENE_V1_PCI_EXP_CAP 0x40
  52. /* PCIe IP version */
  53. #define XGENE_PCIE_IP_VER_UNKN 0
  54. #define XGENE_PCIE_IP_VER_1 1
  55. #define XGENE_PCIE_IP_VER_2 2
  56. #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
  57. struct xgene_pcie_port {
  58. struct device_node *node;
  59. struct device *dev;
  60. struct clk *clk;
  61. void __iomem *csr_base;
  62. void __iomem *cfg_base;
  63. unsigned long cfg_addr;
  64. bool link_up;
  65. u32 version;
  66. };
  67. static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
  68. {
  69. return readl(port->csr_base + reg);
  70. }
  71. static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
  72. {
  73. writel(val, port->csr_base + reg);
  74. }
  75. static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
  76. {
  77. return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
  78. }
  79. static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
  80. {
  81. struct pci_config_window *cfg;
  82. if (acpi_disabled)
  83. return (struct xgene_pcie_port *)(bus->sysdata);
  84. cfg = bus->sysdata;
  85. return (struct xgene_pcie_port *)(cfg->priv);
  86. }
  87. /*
  88. * When the address bit [17:16] is 2'b01, the Configuration access will be
  89. * treated as Type 1 and it will be forwarded to external PCIe device.
  90. */
  91. static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
  92. {
  93. struct xgene_pcie_port *port = pcie_bus_to_port(bus);
  94. if (bus->number >= (bus->primary + 1))
  95. return port->cfg_base + AXI_EP_CFG_ACCESS;
  96. return port->cfg_base;
  97. }
  98. /*
  99. * For Configuration request, RTDID register is used as Bus Number,
  100. * Device Number and Function number of the header fields.
  101. */
  102. static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
  103. {
  104. struct xgene_pcie_port *port = pcie_bus_to_port(bus);
  105. unsigned int b, d, f;
  106. u32 rtdid_val = 0;
  107. b = bus->number;
  108. d = PCI_SLOT(devfn);
  109. f = PCI_FUNC(devfn);
  110. if (!pci_is_root_bus(bus))
  111. rtdid_val = (b << 8) | (d << 3) | f;
  112. xgene_pcie_writel(port, RTDID, rtdid_val);
  113. /* read the register back to ensure flush */
  114. xgene_pcie_readl(port, RTDID);
  115. }
  116. /*
  117. * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
  118. * the translation from PCI bus to native BUS. Entire DDR region
  119. * is mapped into PCIe space using these registers, so it can be
  120. * reached by DMA from EP devices. The BAR0/1 of bridge should be
  121. * hidden during enumeration to avoid the sizing and resource allocation
  122. * by PCIe core.
  123. */
  124. static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
  125. {
  126. if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
  127. (offset == PCI_BASE_ADDRESS_1)))
  128. return true;
  129. return false;
  130. }
  131. static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
  132. int offset)
  133. {
  134. if ((pci_is_root_bus(bus) && devfn != 0) ||
  135. xgene_pcie_hide_rc_bars(bus, offset))
  136. return NULL;
  137. xgene_pcie_set_rtdid_reg(bus, devfn);
  138. return xgene_pcie_get_cfg_base(bus) + offset;
  139. }
  140. static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
  141. int where, int size, u32 *val)
  142. {
  143. struct xgene_pcie_port *port = pcie_bus_to_port(bus);
  144. if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
  145. PCIBIOS_SUCCESSFUL)
  146. return PCIBIOS_DEVICE_NOT_FOUND;
  147. /*
  148. * The v1 controller has a bug in its Configuration Request
  149. * Retry Status (CRS) logic: when CRS is enabled and we read the
  150. * Vendor and Device ID of a non-existent device, the controller
  151. * fabricates return data of 0xFFFF0001 ("device exists but is not
  152. * ready") instead of 0xFFFFFFFF ("device does not exist"). This
  153. * causes the PCI core to retry the read until it times out.
  154. * Avoid this by not claiming to support CRS.
  155. */
  156. if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
  157. ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
  158. *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
  159. if (size <= 2)
  160. *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
  161. return PCIBIOS_SUCCESSFUL;
  162. }
  163. #endif
  164. #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
  165. static int xgene_get_csr_resource(struct acpi_device *adev,
  166. struct resource *res)
  167. {
  168. struct device *dev = &adev->dev;
  169. struct resource_entry *entry;
  170. struct list_head list;
  171. unsigned long flags;
  172. int ret;
  173. INIT_LIST_HEAD(&list);
  174. flags = IORESOURCE_MEM;
  175. ret = acpi_dev_get_resources(adev, &list,
  176. acpi_dev_filter_resource_type_cb,
  177. (void *) flags);
  178. if (ret < 0) {
  179. dev_err(dev, "failed to parse _CRS method, error code %d\n",
  180. ret);
  181. return ret;
  182. }
  183. if (ret == 0) {
  184. dev_err(dev, "no IO and memory resources present in _CRS\n");
  185. return -EINVAL;
  186. }
  187. entry = list_first_entry(&list, struct resource_entry, node);
  188. *res = *entry->res;
  189. acpi_dev_free_resource_list(&list);
  190. return 0;
  191. }
  192. static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
  193. {
  194. struct device *dev = cfg->parent;
  195. struct acpi_device *adev = to_acpi_device(dev);
  196. struct xgene_pcie_port *port;
  197. struct resource csr;
  198. int ret;
  199. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  200. if (!port)
  201. return -ENOMEM;
  202. ret = xgene_get_csr_resource(adev, &csr);
  203. if (ret) {
  204. dev_err(dev, "can't get CSR resource\n");
  205. return ret;
  206. }
  207. port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
  208. if (IS_ERR(port->csr_base))
  209. return PTR_ERR(port->csr_base);
  210. port->cfg_base = cfg->win;
  211. port->version = ipversion;
  212. cfg->priv = port;
  213. return 0;
  214. }
  215. static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
  216. {
  217. return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
  218. }
  219. struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
  220. .bus_shift = 16,
  221. .init = xgene_v1_pcie_ecam_init,
  222. .pci_ops = {
  223. .map_bus = xgene_pcie_map_bus,
  224. .read = xgene_pcie_config_read32,
  225. .write = pci_generic_config_write,
  226. }
  227. };
  228. static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
  229. {
  230. return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
  231. }
  232. struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
  233. .bus_shift = 16,
  234. .init = xgene_v2_pcie_ecam_init,
  235. .pci_ops = {
  236. .map_bus = xgene_pcie_map_bus,
  237. .read = xgene_pcie_config_read32,
  238. .write = pci_generic_config_write,
  239. }
  240. };
  241. #endif
  242. #if defined(CONFIG_PCI_XGENE)
  243. static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
  244. u32 flags, u64 size)
  245. {
  246. u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
  247. u32 val32 = 0;
  248. u32 val;
  249. val32 = xgene_pcie_readl(port, addr);
  250. val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
  251. xgene_pcie_writel(port, addr, val);
  252. val32 = xgene_pcie_readl(port, addr + 0x04);
  253. val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
  254. xgene_pcie_writel(port, addr + 0x04, val);
  255. val32 = xgene_pcie_readl(port, addr + 0x04);
  256. val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
  257. xgene_pcie_writel(port, addr + 0x04, val);
  258. val32 = xgene_pcie_readl(port, addr + 0x08);
  259. val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
  260. xgene_pcie_writel(port, addr + 0x08, val);
  261. return mask;
  262. }
  263. static void xgene_pcie_linkup(struct xgene_pcie_port *port,
  264. u32 *lanes, u32 *speed)
  265. {
  266. u32 val32;
  267. port->link_up = false;
  268. val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
  269. if (val32 & LINK_UP_MASK) {
  270. port->link_up = true;
  271. *speed = PIPE_PHY_RATE_RD(val32);
  272. val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
  273. *lanes = val32 >> 26;
  274. }
  275. }
  276. static int xgene_pcie_init_port(struct xgene_pcie_port *port)
  277. {
  278. struct device *dev = port->dev;
  279. int rc;
  280. port->clk = clk_get(dev, NULL);
  281. if (IS_ERR(port->clk)) {
  282. dev_err(dev, "clock not available\n");
  283. return -ENODEV;
  284. }
  285. rc = clk_prepare_enable(port->clk);
  286. if (rc) {
  287. dev_err(dev, "clock enable failed\n");
  288. return rc;
  289. }
  290. return 0;
  291. }
  292. static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
  293. struct platform_device *pdev)
  294. {
  295. struct device *dev = port->dev;
  296. struct resource *res;
  297. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
  298. port->csr_base = devm_pci_remap_cfg_resource(dev, res);
  299. if (IS_ERR(port->csr_base))
  300. return PTR_ERR(port->csr_base);
  301. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
  302. port->cfg_base = devm_ioremap_resource(dev, res);
  303. if (IS_ERR(port->cfg_base))
  304. return PTR_ERR(port->cfg_base);
  305. port->cfg_addr = res->start;
  306. return 0;
  307. }
  308. static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
  309. struct resource *res, u32 offset,
  310. u64 cpu_addr, u64 pci_addr)
  311. {
  312. struct device *dev = port->dev;
  313. resource_size_t size = resource_size(res);
  314. u64 restype = resource_type(res);
  315. u64 mask = 0;
  316. u32 min_size;
  317. u32 flag = EN_REG;
  318. if (restype == IORESOURCE_MEM) {
  319. min_size = SZ_128M;
  320. } else {
  321. min_size = 128;
  322. flag |= OB_LO_IO;
  323. }
  324. if (size >= min_size)
  325. mask = ~(size - 1) | flag;
  326. else
  327. dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
  328. (u64)size, min_size);
  329. xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
  330. xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
  331. xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
  332. xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
  333. xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
  334. xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
  335. }
  336. static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
  337. {
  338. u64 addr = port->cfg_addr;
  339. xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
  340. xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
  341. xgene_pcie_writel(port, CFGCTL, EN_REG);
  342. }
  343. static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
  344. struct list_head *res,
  345. resource_size_t io_base)
  346. {
  347. struct resource_entry *window;
  348. struct device *dev = port->dev;
  349. int ret;
  350. resource_list_for_each_entry(window, res) {
  351. struct resource *res = window->res;
  352. u64 restype = resource_type(res);
  353. dev_dbg(dev, "%pR\n", res);
  354. switch (restype) {
  355. case IORESOURCE_IO:
  356. xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
  357. res->start - window->offset);
  358. ret = pci_remap_iospace(res, io_base);
  359. if (ret < 0)
  360. return ret;
  361. break;
  362. case IORESOURCE_MEM:
  363. if (res->flags & IORESOURCE_PREFETCH)
  364. xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
  365. res->start,
  366. res->start -
  367. window->offset);
  368. else
  369. xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
  370. res->start,
  371. res->start -
  372. window->offset);
  373. break;
  374. case IORESOURCE_BUS:
  375. break;
  376. default:
  377. dev_err(dev, "invalid resource %pR\n", res);
  378. return -EINVAL;
  379. }
  380. }
  381. xgene_pcie_setup_cfg_reg(port);
  382. return 0;
  383. }
  384. static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
  385. u64 pim, u64 size)
  386. {
  387. xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
  388. xgene_pcie_writel(port, pim_reg + 0x04,
  389. upper_32_bits(pim) | EN_COHERENCY);
  390. xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
  391. xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
  392. }
  393. /*
  394. * X-Gene PCIe support maximum 3 inbound memory regions
  395. * This function helps to select a region based on size of region
  396. */
  397. static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
  398. {
  399. if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
  400. *ib_reg_mask |= (1 << 1);
  401. return 1;
  402. }
  403. if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
  404. *ib_reg_mask |= (1 << 0);
  405. return 0;
  406. }
  407. if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
  408. *ib_reg_mask |= (1 << 2);
  409. return 2;
  410. }
  411. return -EINVAL;
  412. }
  413. static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
  414. struct of_pci_range *range, u8 *ib_reg_mask)
  415. {
  416. void __iomem *cfg_base = port->cfg_base;
  417. struct device *dev = port->dev;
  418. void *bar_addr;
  419. u32 pim_reg;
  420. u64 cpu_addr = range->cpu_addr;
  421. u64 pci_addr = range->pci_addr;
  422. u64 size = range->size;
  423. u64 mask = ~(size - 1) | EN_REG;
  424. u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
  425. u32 bar_low;
  426. int region;
  427. region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
  428. if (region < 0) {
  429. dev_warn(dev, "invalid pcie dma-range config\n");
  430. return;
  431. }
  432. if (range->flags & IORESOURCE_PREFETCH)
  433. flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
  434. bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
  435. switch (region) {
  436. case 0:
  437. xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
  438. bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
  439. writel(bar_low, bar_addr);
  440. writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
  441. pim_reg = PIM1_1L;
  442. break;
  443. case 1:
  444. xgene_pcie_writel(port, IBAR2, bar_low);
  445. xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
  446. pim_reg = PIM2_1L;
  447. break;
  448. case 2:
  449. xgene_pcie_writel(port, IBAR3L, bar_low);
  450. xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
  451. xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
  452. xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
  453. pim_reg = PIM3_1L;
  454. break;
  455. }
  456. xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
  457. }
  458. static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
  459. {
  460. struct device_node *np = port->node;
  461. struct of_pci_range range;
  462. struct of_pci_range_parser parser;
  463. struct device *dev = port->dev;
  464. u8 ib_reg_mask = 0;
  465. if (of_pci_dma_range_parser_init(&parser, np)) {
  466. dev_err(dev, "missing dma-ranges property\n");
  467. return -EINVAL;
  468. }
  469. /* Get the dma-ranges from DT */
  470. for_each_of_pci_range(&parser, &range) {
  471. u64 end = range.cpu_addr + range.size - 1;
  472. dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
  473. range.flags, range.cpu_addr, end, range.pci_addr);
  474. xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
  475. }
  476. return 0;
  477. }
  478. /* clear BAR configuration which was done by firmware */
  479. static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
  480. {
  481. int i;
  482. for (i = PIM1_1L; i <= CFGCTL; i += 4)
  483. xgene_pcie_writel(port, i, 0);
  484. }
  485. static int xgene_pcie_setup(struct xgene_pcie_port *port, struct list_head *res,
  486. resource_size_t io_base)
  487. {
  488. struct device *dev = port->dev;
  489. u32 val, lanes = 0, speed = 0;
  490. int ret;
  491. xgene_pcie_clear_config(port);
  492. /* setup the vendor and device IDs correctly */
  493. val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
  494. xgene_pcie_writel(port, BRIDGE_CFG_0, val);
  495. ret = xgene_pcie_map_ranges(port, res, io_base);
  496. if (ret)
  497. return ret;
  498. ret = xgene_pcie_parse_map_dma_ranges(port);
  499. if (ret)
  500. return ret;
  501. xgene_pcie_linkup(port, &lanes, &speed);
  502. if (!port->link_up)
  503. dev_info(dev, "(rc) link down\n");
  504. else
  505. dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
  506. return 0;
  507. }
  508. static struct pci_ops xgene_pcie_ops = {
  509. .map_bus = xgene_pcie_map_bus,
  510. .read = xgene_pcie_config_read32,
  511. .write = pci_generic_config_write32,
  512. };
  513. static int xgene_pcie_probe(struct platform_device *pdev)
  514. {
  515. struct device *dev = &pdev->dev;
  516. struct device_node *dn = dev->of_node;
  517. struct xgene_pcie_port *port;
  518. resource_size_t iobase = 0;
  519. struct pci_bus *bus, *child;
  520. struct pci_host_bridge *bridge;
  521. int ret;
  522. LIST_HEAD(res);
  523. bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
  524. if (!bridge)
  525. return -ENOMEM;
  526. port = pci_host_bridge_priv(bridge);
  527. port->node = of_node_get(dn);
  528. port->dev = dev;
  529. port->version = XGENE_PCIE_IP_VER_UNKN;
  530. if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
  531. port->version = XGENE_PCIE_IP_VER_1;
  532. ret = xgene_pcie_map_reg(port, pdev);
  533. if (ret)
  534. return ret;
  535. ret = xgene_pcie_init_port(port);
  536. if (ret)
  537. return ret;
  538. ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
  539. if (ret)
  540. return ret;
  541. ret = devm_request_pci_bus_resources(dev, &res);
  542. if (ret)
  543. goto error;
  544. ret = xgene_pcie_setup(port, &res, iobase);
  545. if (ret)
  546. goto error;
  547. list_splice_init(&res, &bridge->windows);
  548. bridge->dev.parent = dev;
  549. bridge->sysdata = port;
  550. bridge->busnr = 0;
  551. bridge->ops = &xgene_pcie_ops;
  552. bridge->map_irq = of_irq_parse_and_map_pci;
  553. bridge->swizzle_irq = pci_common_swizzle;
  554. ret = pci_scan_root_bus_bridge(bridge);
  555. if (ret < 0)
  556. goto error;
  557. bus = bridge->bus;
  558. pci_scan_child_bus(bus);
  559. pci_assign_unassigned_bus_resources(bus);
  560. list_for_each_entry(child, &bus->children, node)
  561. pcie_bus_configure_settings(child);
  562. pci_bus_add_devices(bus);
  563. return 0;
  564. error:
  565. pci_free_resource_list(&res);
  566. return ret;
  567. }
  568. static const struct of_device_id xgene_pcie_match_table[] = {
  569. {.compatible = "apm,xgene-pcie",},
  570. {},
  571. };
  572. static struct platform_driver xgene_pcie_driver = {
  573. .driver = {
  574. .name = "xgene-pcie",
  575. .of_match_table = of_match_ptr(xgene_pcie_match_table),
  576. .suppress_bind_attrs = true,
  577. },
  578. .probe = xgene_pcie_probe,
  579. };
  580. builtin_platform_driver(xgene_pcie_driver);
  581. #endif