fpga-mgr.c 15 KB

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  1. /*
  2. * FPGA Manager Core
  3. *
  4. * Copyright (C) 2013-2015 Altera Corporation
  5. *
  6. * With code from the mailing list:
  7. * Copyright (C) 2013 Xilinx, Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms and conditions of the GNU General Public License,
  11. * version 2, as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope it will be useful, but WITHOUT
  14. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16. * more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along with
  19. * this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include <linux/firmware.h>
  22. #include <linux/fpga/fpga-mgr.h>
  23. #include <linux/idr.h>
  24. #include <linux/module.h>
  25. #include <linux/of.h>
  26. #include <linux/mutex.h>
  27. #include <linux/slab.h>
  28. #include <linux/scatterlist.h>
  29. #include <linux/highmem.h>
  30. static DEFINE_IDA(fpga_mgr_ida);
  31. static struct class *fpga_mgr_class;
  32. /*
  33. * Call the low level driver's write_init function. This will do the
  34. * device-specific things to get the FPGA into the state where it is ready to
  35. * receive an FPGA image. The low level driver only gets to see the first
  36. * initial_header_size bytes in the buffer.
  37. */
  38. static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
  39. struct fpga_image_info *info,
  40. const char *buf, size_t count)
  41. {
  42. int ret;
  43. mgr->state = FPGA_MGR_STATE_WRITE_INIT;
  44. if (!mgr->mops->initial_header_size)
  45. ret = mgr->mops->write_init(mgr, info, NULL, 0);
  46. else
  47. ret = mgr->mops->write_init(
  48. mgr, info, buf, min(mgr->mops->initial_header_size, count));
  49. if (ret) {
  50. dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
  51. mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
  52. return ret;
  53. }
  54. return 0;
  55. }
  56. static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
  57. struct fpga_image_info *info,
  58. struct sg_table *sgt)
  59. {
  60. struct sg_mapping_iter miter;
  61. size_t len;
  62. char *buf;
  63. int ret;
  64. if (!mgr->mops->initial_header_size)
  65. return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
  66. /*
  67. * First try to use miter to map the first fragment to access the
  68. * header, this is the typical path.
  69. */
  70. sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
  71. if (sg_miter_next(&miter) &&
  72. miter.length >= mgr->mops->initial_header_size) {
  73. ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
  74. miter.length);
  75. sg_miter_stop(&miter);
  76. return ret;
  77. }
  78. sg_miter_stop(&miter);
  79. /* Otherwise copy the fragments into temporary memory. */
  80. buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
  81. if (!buf)
  82. return -ENOMEM;
  83. len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
  84. mgr->mops->initial_header_size);
  85. ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
  86. kfree(buf);
  87. return ret;
  88. }
  89. /*
  90. * After all the FPGA image has been written, do the device specific steps to
  91. * finish and set the FPGA into operating mode.
  92. */
  93. static int fpga_mgr_write_complete(struct fpga_manager *mgr,
  94. struct fpga_image_info *info)
  95. {
  96. int ret;
  97. mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
  98. ret = mgr->mops->write_complete(mgr, info);
  99. if (ret) {
  100. dev_err(&mgr->dev, "Error after writing image data to FPGA\n");
  101. mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
  102. return ret;
  103. }
  104. mgr->state = FPGA_MGR_STATE_OPERATING;
  105. return 0;
  106. }
  107. /**
  108. * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list
  109. * @mgr: fpga manager
  110. * @info: fpga image specific information
  111. * @sgt: scatterlist table
  112. *
  113. * Step the low level fpga manager through the device-specific steps of getting
  114. * an FPGA ready to be configured, writing the image to it, then doing whatever
  115. * post-configuration steps necessary. This code assumes the caller got the
  116. * mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is
  117. * not an error code.
  118. *
  119. * This is the preferred entry point for FPGA programming, it does not require
  120. * any contiguous kernel memory.
  121. *
  122. * Return: 0 on success, negative error code otherwise.
  123. */
  124. int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
  125. struct sg_table *sgt)
  126. {
  127. int ret;
  128. ret = fpga_mgr_write_init_sg(mgr, info, sgt);
  129. if (ret)
  130. return ret;
  131. /* Write the FPGA image to the FPGA. */
  132. mgr->state = FPGA_MGR_STATE_WRITE;
  133. if (mgr->mops->write_sg) {
  134. ret = mgr->mops->write_sg(mgr, sgt);
  135. } else {
  136. struct sg_mapping_iter miter;
  137. sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
  138. while (sg_miter_next(&miter)) {
  139. ret = mgr->mops->write(mgr, miter.addr, miter.length);
  140. if (ret)
  141. break;
  142. }
  143. sg_miter_stop(&miter);
  144. }
  145. if (ret) {
  146. dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
  147. mgr->state = FPGA_MGR_STATE_WRITE_ERR;
  148. return ret;
  149. }
  150. return fpga_mgr_write_complete(mgr, info);
  151. }
  152. EXPORT_SYMBOL_GPL(fpga_mgr_buf_load_sg);
  153. static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
  154. struct fpga_image_info *info,
  155. const char *buf, size_t count)
  156. {
  157. int ret;
  158. ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
  159. if (ret)
  160. return ret;
  161. /*
  162. * Write the FPGA image to the FPGA.
  163. */
  164. mgr->state = FPGA_MGR_STATE_WRITE;
  165. ret = mgr->mops->write(mgr, buf, count);
  166. if (ret) {
  167. dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
  168. mgr->state = FPGA_MGR_STATE_WRITE_ERR;
  169. return ret;
  170. }
  171. return fpga_mgr_write_complete(mgr, info);
  172. }
  173. /**
  174. * fpga_mgr_buf_load - load fpga from image in buffer
  175. * @mgr: fpga manager
  176. * @flags: flags setting fpga confuration modes
  177. * @buf: buffer contain fpga image
  178. * @count: byte count of buf
  179. *
  180. * Step the low level fpga manager through the device-specific steps of getting
  181. * an FPGA ready to be configured, writing the image to it, then doing whatever
  182. * post-configuration steps necessary. This code assumes the caller got the
  183. * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
  184. *
  185. * Return: 0 on success, negative error code otherwise.
  186. */
  187. int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
  188. const char *buf, size_t count)
  189. {
  190. struct page **pages;
  191. struct sg_table sgt;
  192. const void *p;
  193. int nr_pages;
  194. int index;
  195. int rc;
  196. /*
  197. * This is just a fast path if the caller has already created a
  198. * contiguous kernel buffer and the driver doesn't require SG, non-SG
  199. * drivers will still work on the slow path.
  200. */
  201. if (mgr->mops->write)
  202. return fpga_mgr_buf_load_mapped(mgr, info, buf, count);
  203. /*
  204. * Convert the linear kernel pointer into a sg_table of pages for use
  205. * by the driver.
  206. */
  207. nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) -
  208. (unsigned long)buf / PAGE_SIZE;
  209. pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
  210. if (!pages)
  211. return -ENOMEM;
  212. p = buf - offset_in_page(buf);
  213. for (index = 0; index < nr_pages; index++) {
  214. if (is_vmalloc_addr(p))
  215. pages[index] = vmalloc_to_page(p);
  216. else
  217. pages[index] = kmap_to_page((void *)p);
  218. if (!pages[index]) {
  219. kfree(pages);
  220. return -EFAULT;
  221. }
  222. p += PAGE_SIZE;
  223. }
  224. /*
  225. * The temporary pages list is used to code share the merging algorithm
  226. * in sg_alloc_table_from_pages
  227. */
  228. rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf),
  229. count, GFP_KERNEL);
  230. kfree(pages);
  231. if (rc)
  232. return rc;
  233. rc = fpga_mgr_buf_load_sg(mgr, info, &sgt);
  234. sg_free_table(&sgt);
  235. return rc;
  236. }
  237. EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
  238. /**
  239. * fpga_mgr_firmware_load - request firmware and load to fpga
  240. * @mgr: fpga manager
  241. * @info: fpga image specific information
  242. * @image_name: name of image file on the firmware search path
  243. *
  244. * Request an FPGA image using the firmware class, then write out to the FPGA.
  245. * Update the state before each step to provide info on what step failed if
  246. * there is a failure. This code assumes the caller got the mgr pointer
  247. * from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error
  248. * code.
  249. *
  250. * Return: 0 on success, negative error code otherwise.
  251. */
  252. int fpga_mgr_firmware_load(struct fpga_manager *mgr,
  253. struct fpga_image_info *info,
  254. const char *image_name)
  255. {
  256. struct device *dev = &mgr->dev;
  257. const struct firmware *fw;
  258. int ret;
  259. dev_info(dev, "writing %s to %s\n", image_name, mgr->name);
  260. mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ;
  261. ret = request_firmware(&fw, image_name, dev);
  262. if (ret) {
  263. mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR;
  264. dev_err(dev, "Error requesting firmware %s\n", image_name);
  265. return ret;
  266. }
  267. ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
  268. release_firmware(fw);
  269. return ret;
  270. }
  271. EXPORT_SYMBOL_GPL(fpga_mgr_firmware_load);
  272. static const char * const state_str[] = {
  273. [FPGA_MGR_STATE_UNKNOWN] = "unknown",
  274. [FPGA_MGR_STATE_POWER_OFF] = "power off",
  275. [FPGA_MGR_STATE_POWER_UP] = "power up",
  276. [FPGA_MGR_STATE_RESET] = "reset",
  277. /* requesting FPGA image from firmware */
  278. [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
  279. [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
  280. /* Preparing FPGA to receive image */
  281. [FPGA_MGR_STATE_WRITE_INIT] = "write init",
  282. [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
  283. /* Writing image to FPGA */
  284. [FPGA_MGR_STATE_WRITE] = "write",
  285. [FPGA_MGR_STATE_WRITE_ERR] = "write error",
  286. /* Finishing configuration after image has been written */
  287. [FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete",
  288. [FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error",
  289. /* FPGA reports to be in normal operating mode */
  290. [FPGA_MGR_STATE_OPERATING] = "operating",
  291. };
  292. static ssize_t name_show(struct device *dev,
  293. struct device_attribute *attr, char *buf)
  294. {
  295. struct fpga_manager *mgr = to_fpga_manager(dev);
  296. return sprintf(buf, "%s\n", mgr->name);
  297. }
  298. static ssize_t state_show(struct device *dev,
  299. struct device_attribute *attr, char *buf)
  300. {
  301. struct fpga_manager *mgr = to_fpga_manager(dev);
  302. return sprintf(buf, "%s\n", state_str[mgr->state]);
  303. }
  304. static DEVICE_ATTR_RO(name);
  305. static DEVICE_ATTR_RO(state);
  306. static struct attribute *fpga_mgr_attrs[] = {
  307. &dev_attr_name.attr,
  308. &dev_attr_state.attr,
  309. NULL,
  310. };
  311. ATTRIBUTE_GROUPS(fpga_mgr);
  312. static struct fpga_manager *__fpga_mgr_get(struct device *dev)
  313. {
  314. struct fpga_manager *mgr;
  315. int ret = -ENODEV;
  316. mgr = to_fpga_manager(dev);
  317. if (!mgr)
  318. goto err_dev;
  319. /* Get exclusive use of fpga manager */
  320. if (!mutex_trylock(&mgr->ref_mutex)) {
  321. ret = -EBUSY;
  322. goto err_dev;
  323. }
  324. if (!try_module_get(dev->parent->driver->owner))
  325. goto err_ll_mod;
  326. return mgr;
  327. err_ll_mod:
  328. mutex_unlock(&mgr->ref_mutex);
  329. err_dev:
  330. put_device(dev);
  331. return ERR_PTR(ret);
  332. }
  333. static int fpga_mgr_dev_match(struct device *dev, const void *data)
  334. {
  335. return dev->parent == data;
  336. }
  337. /**
  338. * fpga_mgr_get - get an exclusive reference to a fpga mgr
  339. * @dev: parent device that fpga mgr was registered with
  340. *
  341. * Given a device, get an exclusive reference to a fpga mgr.
  342. *
  343. * Return: fpga manager struct or IS_ERR() condition containing error code.
  344. */
  345. struct fpga_manager *fpga_mgr_get(struct device *dev)
  346. {
  347. struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
  348. fpga_mgr_dev_match);
  349. if (!mgr_dev)
  350. return ERR_PTR(-ENODEV);
  351. return __fpga_mgr_get(mgr_dev);
  352. }
  353. EXPORT_SYMBOL_GPL(fpga_mgr_get);
  354. static int fpga_mgr_of_node_match(struct device *dev, const void *data)
  355. {
  356. return dev->of_node == data;
  357. }
  358. /**
  359. * of_fpga_mgr_get - get an exclusive reference to a fpga mgr
  360. * @node: device node
  361. *
  362. * Given a device node, get an exclusive reference to a fpga mgr.
  363. *
  364. * Return: fpga manager struct or IS_ERR() condition containing error code.
  365. */
  366. struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
  367. {
  368. struct device *dev;
  369. dev = class_find_device(fpga_mgr_class, NULL, node,
  370. fpga_mgr_of_node_match);
  371. if (!dev)
  372. return ERR_PTR(-ENODEV);
  373. return __fpga_mgr_get(dev);
  374. }
  375. EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
  376. /**
  377. * fpga_mgr_put - release a reference to a fpga manager
  378. * @mgr: fpga manager structure
  379. */
  380. void fpga_mgr_put(struct fpga_manager *mgr)
  381. {
  382. module_put(mgr->dev.parent->driver->owner);
  383. mutex_unlock(&mgr->ref_mutex);
  384. put_device(&mgr->dev);
  385. }
  386. EXPORT_SYMBOL_GPL(fpga_mgr_put);
  387. /**
  388. * fpga_mgr_register - register a low level fpga manager driver
  389. * @dev: fpga manager device from pdev
  390. * @name: fpga manager name
  391. * @mops: pointer to structure of fpga manager ops
  392. * @priv: fpga manager private data
  393. *
  394. * Return: 0 on success, negative error code otherwise.
  395. */
  396. int fpga_mgr_register(struct device *dev, const char *name,
  397. const struct fpga_manager_ops *mops,
  398. void *priv)
  399. {
  400. struct fpga_manager *mgr;
  401. int id, ret;
  402. if (!mops || !mops->write_complete || !mops->state ||
  403. !mops->write_init || (!mops->write && !mops->write_sg) ||
  404. (mops->write && mops->write_sg)) {
  405. dev_err(dev, "Attempt to register without fpga_manager_ops\n");
  406. return -EINVAL;
  407. }
  408. if (!name || !strlen(name)) {
  409. dev_err(dev, "Attempt to register with no name!\n");
  410. return -EINVAL;
  411. }
  412. mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  413. if (!mgr)
  414. return -ENOMEM;
  415. id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
  416. if (id < 0) {
  417. ret = id;
  418. goto error_kfree;
  419. }
  420. mutex_init(&mgr->ref_mutex);
  421. mgr->name = name;
  422. mgr->mops = mops;
  423. mgr->priv = priv;
  424. /*
  425. * Initialize framework state by requesting low level driver read state
  426. * from device. FPGA may be in reset mode or may have been programmed
  427. * by bootloader or EEPROM.
  428. */
  429. mgr->state = mgr->mops->state(mgr);
  430. device_initialize(&mgr->dev);
  431. mgr->dev.class = fpga_mgr_class;
  432. mgr->dev.parent = dev;
  433. mgr->dev.of_node = dev->of_node;
  434. mgr->dev.id = id;
  435. dev_set_drvdata(dev, mgr);
  436. ret = dev_set_name(&mgr->dev, "fpga%d", id);
  437. if (ret)
  438. goto error_device;
  439. ret = device_add(&mgr->dev);
  440. if (ret)
  441. goto error_device;
  442. dev_info(&mgr->dev, "%s registered\n", mgr->name);
  443. return 0;
  444. error_device:
  445. ida_simple_remove(&fpga_mgr_ida, id);
  446. error_kfree:
  447. kfree(mgr);
  448. return ret;
  449. }
  450. EXPORT_SYMBOL_GPL(fpga_mgr_register);
  451. /**
  452. * fpga_mgr_unregister - unregister a low level fpga manager driver
  453. * @dev: fpga manager device from pdev
  454. */
  455. void fpga_mgr_unregister(struct device *dev)
  456. {
  457. struct fpga_manager *mgr = dev_get_drvdata(dev);
  458. dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
  459. /*
  460. * If the low level driver provides a method for putting fpga into
  461. * a desired state upon unregister, do it.
  462. */
  463. if (mgr->mops->fpga_remove)
  464. mgr->mops->fpga_remove(mgr);
  465. device_unregister(&mgr->dev);
  466. }
  467. EXPORT_SYMBOL_GPL(fpga_mgr_unregister);
  468. static void fpga_mgr_dev_release(struct device *dev)
  469. {
  470. struct fpga_manager *mgr = to_fpga_manager(dev);
  471. ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
  472. kfree(mgr);
  473. }
  474. static int __init fpga_mgr_class_init(void)
  475. {
  476. pr_info("FPGA manager framework\n");
  477. fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager");
  478. if (IS_ERR(fpga_mgr_class))
  479. return PTR_ERR(fpga_mgr_class);
  480. fpga_mgr_class->dev_groups = fpga_mgr_groups;
  481. fpga_mgr_class->dev_release = fpga_mgr_dev_release;
  482. return 0;
  483. }
  484. static void __exit fpga_mgr_class_exit(void)
  485. {
  486. class_destroy(fpga_mgr_class);
  487. ida_destroy(&fpga_mgr_ida);
  488. }
  489. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  490. MODULE_DESCRIPTION("FPGA manager framework");
  491. MODULE_LICENSE("GPL v2");
  492. subsys_initcall(fpga_mgr_class_init);
  493. module_exit(fpga_mgr_class_exit);