amdgpu_ring.c 10 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. * Christian König
  28. */
  29. #include <linux/seq_file.h>
  30. #include <linux/slab.h>
  31. #include <linux/debugfs.h>
  32. #include <drm/drmP.h>
  33. #include <drm/amdgpu_drm.h>
  34. #include "amdgpu.h"
  35. #include "atom.h"
  36. /*
  37. * Rings
  38. * Most engines on the GPU are fed via ring buffers. Ring
  39. * buffers are areas of GPU accessible memory that the host
  40. * writes commands into and the GPU reads commands out of.
  41. * There is a rptr (read pointer) that determines where the
  42. * GPU is currently reading, and a wptr (write pointer)
  43. * which determines where the host has written. When the
  44. * pointers are equal, the ring is idle. When the host
  45. * writes commands to the ring buffer, it increments the
  46. * wptr. The GPU then starts fetching commands and executes
  47. * them until the pointers are equal again.
  48. */
  49. static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
  50. struct amdgpu_ring *ring);
  51. static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
  52. /**
  53. * amdgpu_ring_alloc - allocate space on the ring buffer
  54. *
  55. * @adev: amdgpu_device pointer
  56. * @ring: amdgpu_ring structure holding ring information
  57. * @ndw: number of dwords to allocate in the ring buffer
  58. *
  59. * Allocate @ndw dwords in the ring buffer (all asics).
  60. * Returns 0 on success, error on failure.
  61. */
  62. int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
  63. {
  64. /* Align requested size with padding so unlock_commit can
  65. * pad safely */
  66. ndw = (ndw + ring->align_mask) & ~ring->align_mask;
  67. /* Make sure we aren't trying to allocate more space
  68. * than the maximum for one submission
  69. */
  70. if (WARN_ON_ONCE(ndw > ring->max_dw))
  71. return -ENOMEM;
  72. ring->count_dw = ndw;
  73. ring->wptr_old = ring->wptr;
  74. if (ring->funcs->begin_use)
  75. ring->funcs->begin_use(ring);
  76. return 0;
  77. }
  78. /** amdgpu_ring_insert_nop - insert NOP packets
  79. *
  80. * @ring: amdgpu_ring structure holding ring information
  81. * @count: the number of NOP packets to insert
  82. *
  83. * This is the generic insert_nop function for rings except SDMA
  84. */
  85. void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  86. {
  87. int i;
  88. for (i = 0; i < count; i++)
  89. amdgpu_ring_write(ring, ring->nop);
  90. }
  91. /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
  92. *
  93. * @ring: amdgpu_ring structure holding ring information
  94. * @ib: IB to add NOP packets to
  95. *
  96. * This is the generic pad_ib function for rings except SDMA
  97. */
  98. void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
  99. {
  100. while (ib->length_dw & ring->align_mask)
  101. ib->ptr[ib->length_dw++] = ring->nop;
  102. }
  103. /**
  104. * amdgpu_ring_commit - tell the GPU to execute the new
  105. * commands on the ring buffer
  106. *
  107. * @adev: amdgpu_device pointer
  108. * @ring: amdgpu_ring structure holding ring information
  109. *
  110. * Update the wptr (write pointer) to tell the GPU to
  111. * execute new commands on the ring buffer (all asics).
  112. */
  113. void amdgpu_ring_commit(struct amdgpu_ring *ring)
  114. {
  115. uint32_t count;
  116. /* We pad to match fetch size */
  117. count = ring->align_mask + 1 - (ring->wptr & ring->align_mask);
  118. count %= ring->align_mask + 1;
  119. ring->funcs->insert_nop(ring, count);
  120. mb();
  121. amdgpu_ring_set_wptr(ring);
  122. if (ring->funcs->end_use)
  123. ring->funcs->end_use(ring);
  124. }
  125. /**
  126. * amdgpu_ring_undo - reset the wptr
  127. *
  128. * @ring: amdgpu_ring structure holding ring information
  129. *
  130. * Reset the driver's copy of the wptr (all asics).
  131. */
  132. void amdgpu_ring_undo(struct amdgpu_ring *ring)
  133. {
  134. ring->wptr = ring->wptr_old;
  135. if (ring->funcs->end_use)
  136. ring->funcs->end_use(ring);
  137. }
  138. /**
  139. * amdgpu_ring_init - init driver ring struct.
  140. *
  141. * @adev: amdgpu_device pointer
  142. * @ring: amdgpu_ring structure holding ring information
  143. * @max_ndw: maximum number of dw for ring alloc
  144. * @nop: nop packet for this ring
  145. *
  146. * Initialize the driver information for the selected ring (all asics).
  147. * Returns 0 on success, error on failure.
  148. */
  149. int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
  150. unsigned max_dw, u32 nop, u32 align_mask,
  151. struct amdgpu_irq_src *irq_src, unsigned irq_type,
  152. enum amdgpu_ring_type ring_type)
  153. {
  154. int r;
  155. if (ring->adev == NULL) {
  156. if (adev->num_rings >= AMDGPU_MAX_RINGS)
  157. return -EINVAL;
  158. ring->adev = adev;
  159. ring->idx = adev->num_rings++;
  160. adev->rings[ring->idx] = ring;
  161. r = amdgpu_fence_driver_init_ring(ring,
  162. amdgpu_sched_hw_submission);
  163. if (r)
  164. return r;
  165. }
  166. r = amdgpu_wb_get(adev, &ring->rptr_offs);
  167. if (r) {
  168. dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
  169. return r;
  170. }
  171. r = amdgpu_wb_get(adev, &ring->wptr_offs);
  172. if (r) {
  173. dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
  174. return r;
  175. }
  176. r = amdgpu_wb_get(adev, &ring->fence_offs);
  177. if (r) {
  178. dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
  179. return r;
  180. }
  181. r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
  182. if (r) {
  183. dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
  184. return r;
  185. }
  186. ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
  187. ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
  188. r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
  189. if (r) {
  190. dev_err(adev->dev, "failed initializing fences (%d).\n", r);
  191. return r;
  192. }
  193. ring->ring_size = roundup_pow_of_two(max_dw * 4 *
  194. amdgpu_sched_hw_submission);
  195. ring->align_mask = align_mask;
  196. ring->nop = nop;
  197. ring->type = ring_type;
  198. /* Allocate ring buffer */
  199. if (ring->ring_obj == NULL) {
  200. r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true,
  201. AMDGPU_GEM_DOMAIN_GTT, 0,
  202. NULL, NULL, &ring->ring_obj);
  203. if (r) {
  204. dev_err(adev->dev, "(%d) ring create failed\n", r);
  205. return r;
  206. }
  207. r = amdgpu_bo_reserve(ring->ring_obj, false);
  208. if (unlikely(r != 0))
  209. return r;
  210. r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT,
  211. &ring->gpu_addr);
  212. if (r) {
  213. amdgpu_bo_unreserve(ring->ring_obj);
  214. dev_err(adev->dev, "(%d) ring pin failed\n", r);
  215. return r;
  216. }
  217. r = amdgpu_bo_kmap(ring->ring_obj,
  218. (void **)&ring->ring);
  219. memset((void *)ring->ring, 0, ring->ring_size);
  220. amdgpu_bo_unreserve(ring->ring_obj);
  221. if (r) {
  222. dev_err(adev->dev, "(%d) ring map failed\n", r);
  223. return r;
  224. }
  225. }
  226. ring->ptr_mask = (ring->ring_size / 4) - 1;
  227. ring->max_dw = max_dw;
  228. if (amdgpu_debugfs_ring_init(adev, ring)) {
  229. DRM_ERROR("Failed to register debugfs file for rings !\n");
  230. }
  231. return 0;
  232. }
  233. /**
  234. * amdgpu_ring_fini - tear down the driver ring struct.
  235. *
  236. * @adev: amdgpu_device pointer
  237. * @ring: amdgpu_ring structure holding ring information
  238. *
  239. * Tear down the driver information for the selected ring (all asics).
  240. */
  241. void amdgpu_ring_fini(struct amdgpu_ring *ring)
  242. {
  243. int r;
  244. struct amdgpu_bo *ring_obj;
  245. ring_obj = ring->ring_obj;
  246. ring->ready = false;
  247. ring->ring = NULL;
  248. ring->ring_obj = NULL;
  249. amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
  250. amdgpu_wb_free(ring->adev, ring->fence_offs);
  251. amdgpu_wb_free(ring->adev, ring->rptr_offs);
  252. amdgpu_wb_free(ring->adev, ring->wptr_offs);
  253. if (ring_obj) {
  254. r = amdgpu_bo_reserve(ring_obj, false);
  255. if (likely(r == 0)) {
  256. amdgpu_bo_kunmap(ring_obj);
  257. amdgpu_bo_unpin(ring_obj);
  258. amdgpu_bo_unreserve(ring_obj);
  259. }
  260. amdgpu_bo_unref(&ring_obj);
  261. }
  262. amdgpu_debugfs_ring_fini(ring);
  263. }
  264. /*
  265. * Debugfs info
  266. */
  267. #if defined(CONFIG_DEBUG_FS)
  268. /* Layout of file is 12 bytes consisting of
  269. * - rptr
  270. * - wptr
  271. * - driver's copy of wptr
  272. *
  273. * followed by n-words of ring data
  274. */
  275. static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
  276. size_t size, loff_t *pos)
  277. {
  278. struct amdgpu_ring *ring = (struct amdgpu_ring*)f->f_inode->i_private;
  279. int r, i;
  280. uint32_t value, result, early[3];
  281. if (*pos & 3 || size & 3)
  282. return -EINVAL;
  283. result = 0;
  284. if (*pos < 12) {
  285. early[0] = amdgpu_ring_get_rptr(ring);
  286. early[1] = amdgpu_ring_get_wptr(ring);
  287. early[2] = ring->wptr;
  288. for (i = *pos / 4; i < 3 && size; i++) {
  289. r = put_user(early[i], (uint32_t *)buf);
  290. if (r)
  291. return r;
  292. buf += 4;
  293. result += 4;
  294. size -= 4;
  295. *pos += 4;
  296. }
  297. }
  298. while (size) {
  299. if (*pos >= (ring->ring_size + 12))
  300. return result;
  301. value = ring->ring[(*pos - 12)/4];
  302. r = put_user(value, (uint32_t*)buf);
  303. if (r)
  304. return r;
  305. buf += 4;
  306. result += 4;
  307. size -= 4;
  308. *pos += 4;
  309. }
  310. return result;
  311. }
  312. static const struct file_operations amdgpu_debugfs_ring_fops = {
  313. .owner = THIS_MODULE,
  314. .read = amdgpu_debugfs_ring_read,
  315. .llseek = default_llseek
  316. };
  317. #endif
  318. static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
  319. struct amdgpu_ring *ring)
  320. {
  321. #if defined(CONFIG_DEBUG_FS)
  322. struct drm_minor *minor = adev->ddev->primary;
  323. struct dentry *ent, *root = minor->debugfs_root;
  324. char name[32];
  325. sprintf(name, "amdgpu_ring_%s", ring->name);
  326. ent = debugfs_create_file(name,
  327. S_IFREG | S_IRUGO, root,
  328. ring, &amdgpu_debugfs_ring_fops);
  329. if (IS_ERR(ent))
  330. return PTR_ERR(ent);
  331. i_size_write(ent->d_inode, ring->ring_size + 12);
  332. ring->ent = ent;
  333. #endif
  334. return 0;
  335. }
  336. static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
  337. {
  338. #if defined(CONFIG_DEBUG_FS)
  339. debugfs_remove(ring->ent);
  340. #endif
  341. }