clk.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. */
  8. #include <linux/init.h>
  9. #include <linux/export.h>
  10. #include <linux/mutex.h>
  11. #include <linux/err.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <bcm63xx_cpu.h>
  15. #include <bcm63xx_io.h>
  16. #include <bcm63xx_regs.h>
  17. #include <bcm63xx_reset.h>
  18. struct clk {
  19. void (*set)(struct clk *, int);
  20. unsigned int rate;
  21. unsigned int usage;
  22. int id;
  23. };
  24. static DEFINE_MUTEX(clocks_mutex);
  25. static void clk_enable_unlocked(struct clk *clk)
  26. {
  27. if (clk->set && (clk->usage++) == 0)
  28. clk->set(clk, 1);
  29. }
  30. static void clk_disable_unlocked(struct clk *clk)
  31. {
  32. if (clk->set && (--clk->usage) == 0)
  33. clk->set(clk, 0);
  34. }
  35. static void bcm_hwclock_set(u32 mask, int enable)
  36. {
  37. u32 reg;
  38. reg = bcm_perf_readl(PERF_CKCTL_REG);
  39. if (enable)
  40. reg |= mask;
  41. else
  42. reg &= ~mask;
  43. bcm_perf_writel(reg, PERF_CKCTL_REG);
  44. }
  45. /*
  46. * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
  47. */
  48. static void enet_misc_set(struct clk *clk, int enable)
  49. {
  50. u32 mask;
  51. if (BCMCPU_IS_6338())
  52. mask = CKCTL_6338_ENET_EN;
  53. else if (BCMCPU_IS_6345())
  54. mask = CKCTL_6345_ENET_EN;
  55. else if (BCMCPU_IS_6348())
  56. mask = CKCTL_6348_ENET_EN;
  57. else
  58. /* BCMCPU_IS_6358 */
  59. mask = CKCTL_6358_EMUSB_EN;
  60. bcm_hwclock_set(mask, enable);
  61. }
  62. static struct clk clk_enet_misc = {
  63. .set = enet_misc_set,
  64. };
  65. /*
  66. * Ethernet MAC clocks: only revelant on 6358, silently enable misc
  67. * clocks
  68. */
  69. static void enetx_set(struct clk *clk, int enable)
  70. {
  71. if (enable)
  72. clk_enable_unlocked(&clk_enet_misc);
  73. else
  74. clk_disable_unlocked(&clk_enet_misc);
  75. if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
  76. u32 mask;
  77. if (clk->id == 0)
  78. mask = CKCTL_6358_ENET0_EN;
  79. else
  80. mask = CKCTL_6358_ENET1_EN;
  81. bcm_hwclock_set(mask, enable);
  82. }
  83. }
  84. static struct clk clk_enet0 = {
  85. .id = 0,
  86. .set = enetx_set,
  87. };
  88. static struct clk clk_enet1 = {
  89. .id = 1,
  90. .set = enetx_set,
  91. };
  92. /*
  93. * Ethernet PHY clock
  94. */
  95. static void ephy_set(struct clk *clk, int enable)
  96. {
  97. if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
  98. bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
  99. }
  100. static struct clk clk_ephy = {
  101. .set = ephy_set,
  102. };
  103. /*
  104. * Ethernet switch clock
  105. */
  106. static void enetsw_set(struct clk *clk, int enable)
  107. {
  108. if (BCMCPU_IS_6328())
  109. bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
  110. else if (BCMCPU_IS_6362())
  111. bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
  112. else if (BCMCPU_IS_6368())
  113. bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
  114. CKCTL_6368_SWPKT_USB_EN |
  115. CKCTL_6368_SWPKT_SAR_EN,
  116. enable);
  117. else
  118. return;
  119. if (enable) {
  120. /* reset switch core afer clock change */
  121. bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
  122. msleep(10);
  123. bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
  124. msleep(10);
  125. }
  126. }
  127. static struct clk clk_enetsw = {
  128. .set = enetsw_set,
  129. };
  130. /*
  131. * PCM clock
  132. */
  133. static void pcm_set(struct clk *clk, int enable)
  134. {
  135. if (BCMCPU_IS_3368())
  136. bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
  137. if (BCMCPU_IS_6358())
  138. bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
  139. }
  140. static struct clk clk_pcm = {
  141. .set = pcm_set,
  142. };
  143. /*
  144. * USB host clock
  145. */
  146. static void usbh_set(struct clk *clk, int enable)
  147. {
  148. if (BCMCPU_IS_6328())
  149. bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
  150. else if (BCMCPU_IS_6348())
  151. bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
  152. else if (BCMCPU_IS_6362())
  153. bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
  154. else if (BCMCPU_IS_6368())
  155. bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
  156. }
  157. static struct clk clk_usbh = {
  158. .set = usbh_set,
  159. };
  160. /*
  161. * USB device clock
  162. */
  163. static void usbd_set(struct clk *clk, int enable)
  164. {
  165. if (BCMCPU_IS_6328())
  166. bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
  167. else if (BCMCPU_IS_6362())
  168. bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
  169. else if (BCMCPU_IS_6368())
  170. bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
  171. }
  172. static struct clk clk_usbd = {
  173. .set = usbd_set,
  174. };
  175. /*
  176. * SPI clock
  177. */
  178. static void spi_set(struct clk *clk, int enable)
  179. {
  180. u32 mask;
  181. if (BCMCPU_IS_6338())
  182. mask = CKCTL_6338_SPI_EN;
  183. else if (BCMCPU_IS_6348())
  184. mask = CKCTL_6348_SPI_EN;
  185. else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
  186. mask = CKCTL_6358_SPI_EN;
  187. else if (BCMCPU_IS_6362())
  188. mask = CKCTL_6362_SPI_EN;
  189. else
  190. /* BCMCPU_IS_6368 */
  191. mask = CKCTL_6368_SPI_EN;
  192. bcm_hwclock_set(mask, enable);
  193. }
  194. static struct clk clk_spi = {
  195. .set = spi_set,
  196. };
  197. /*
  198. * HSSPI clock
  199. */
  200. static void hsspi_set(struct clk *clk, int enable)
  201. {
  202. u32 mask;
  203. if (BCMCPU_IS_6328())
  204. mask = CKCTL_6328_HSSPI_EN;
  205. else if (BCMCPU_IS_6362())
  206. mask = CKCTL_6362_HSSPI_EN;
  207. else
  208. return;
  209. bcm_hwclock_set(mask, enable);
  210. }
  211. static struct clk clk_hsspi = {
  212. .set = hsspi_set,
  213. };
  214. /*
  215. * XTM clock
  216. */
  217. static void xtm_set(struct clk *clk, int enable)
  218. {
  219. if (!BCMCPU_IS_6368())
  220. return;
  221. bcm_hwclock_set(CKCTL_6368_SAR_EN |
  222. CKCTL_6368_SWPKT_SAR_EN, enable);
  223. if (enable) {
  224. /* reset sar core afer clock change */
  225. bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
  226. mdelay(1);
  227. bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
  228. mdelay(1);
  229. }
  230. }
  231. static struct clk clk_xtm = {
  232. .set = xtm_set,
  233. };
  234. /*
  235. * IPsec clock
  236. */
  237. static void ipsec_set(struct clk *clk, int enable)
  238. {
  239. if (BCMCPU_IS_6362())
  240. bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable);
  241. else if (BCMCPU_IS_6368())
  242. bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
  243. }
  244. static struct clk clk_ipsec = {
  245. .set = ipsec_set,
  246. };
  247. /*
  248. * PCIe clock
  249. */
  250. static void pcie_set(struct clk *clk, int enable)
  251. {
  252. if (BCMCPU_IS_6328())
  253. bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
  254. else if (BCMCPU_IS_6362())
  255. bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
  256. }
  257. static struct clk clk_pcie = {
  258. .set = pcie_set,
  259. };
  260. /*
  261. * Internal peripheral clock
  262. */
  263. static struct clk clk_periph = {
  264. .rate = (50 * 1000 * 1000),
  265. };
  266. /*
  267. * Linux clock API implementation
  268. */
  269. int clk_enable(struct clk *clk)
  270. {
  271. mutex_lock(&clocks_mutex);
  272. clk_enable_unlocked(clk);
  273. mutex_unlock(&clocks_mutex);
  274. return 0;
  275. }
  276. EXPORT_SYMBOL(clk_enable);
  277. void clk_disable(struct clk *clk)
  278. {
  279. if (!clk)
  280. return;
  281. mutex_lock(&clocks_mutex);
  282. clk_disable_unlocked(clk);
  283. mutex_unlock(&clocks_mutex);
  284. }
  285. EXPORT_SYMBOL(clk_disable);
  286. unsigned long clk_get_rate(struct clk *clk)
  287. {
  288. if (!clk)
  289. return 0;
  290. return clk->rate;
  291. }
  292. EXPORT_SYMBOL(clk_get_rate);
  293. int clk_set_rate(struct clk *clk, unsigned long rate)
  294. {
  295. return 0;
  296. }
  297. EXPORT_SYMBOL_GPL(clk_set_rate);
  298. long clk_round_rate(struct clk *clk, unsigned long rate)
  299. {
  300. return 0;
  301. }
  302. EXPORT_SYMBOL_GPL(clk_round_rate);
  303. struct clk *clk_get(struct device *dev, const char *id)
  304. {
  305. if (!strcmp(id, "enet0"))
  306. return &clk_enet0;
  307. if (!strcmp(id, "enet1"))
  308. return &clk_enet1;
  309. if (!strcmp(id, "enetsw"))
  310. return &clk_enetsw;
  311. if (!strcmp(id, "ephy"))
  312. return &clk_ephy;
  313. if (!strcmp(id, "usbh"))
  314. return &clk_usbh;
  315. if (!strcmp(id, "usbd"))
  316. return &clk_usbd;
  317. if (!strcmp(id, "spi"))
  318. return &clk_spi;
  319. if (!strcmp(id, "hsspi"))
  320. return &clk_hsspi;
  321. if (!strcmp(id, "xtm"))
  322. return &clk_xtm;
  323. if (!strcmp(id, "periph"))
  324. return &clk_periph;
  325. if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
  326. return &clk_pcm;
  327. if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
  328. return &clk_ipsec;
  329. if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
  330. return &clk_pcie;
  331. return ERR_PTR(-ENOENT);
  332. }
  333. EXPORT_SYMBOL(clk_get);
  334. void clk_put(struct clk *clk)
  335. {
  336. }
  337. EXPORT_SYMBOL(clk_put);
  338. #define HSSPI_PLL_HZ_6328 133333333
  339. #define HSSPI_PLL_HZ_6362 400000000
  340. static int __init bcm63xx_clk_init(void)
  341. {
  342. switch (bcm63xx_get_cpu_id()) {
  343. case BCM6328_CPU_ID:
  344. clk_hsspi.rate = HSSPI_PLL_HZ_6328;
  345. break;
  346. case BCM6362_CPU_ID:
  347. clk_hsspi.rate = HSSPI_PLL_HZ_6362;
  348. break;
  349. }
  350. return 0;
  351. }
  352. arch_initcall(bcm63xx_clk_init);