fpga-mgr.h 6.2 KB

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  1. /*
  2. * FPGA Framework
  3. *
  4. * Copyright (C) 2013-2016 Altera Corporation
  5. * Copyright (C) 2017 Intel Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef _LINUX_FPGA_MGR_H
  20. #define _LINUX_FPGA_MGR_H
  21. #include <linux/mutex.h>
  22. #include <linux/platform_device.h>
  23. struct fpga_manager;
  24. struct sg_table;
  25. /**
  26. * enum fpga_mgr_states - fpga framework states
  27. * @FPGA_MGR_STATE_UNKNOWN: can't determine state
  28. * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
  29. * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
  30. * @FPGA_MGR_STATE_RESET: FPGA in reset state
  31. * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
  32. * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
  33. * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
  34. * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
  35. * @FPGA_MGR_STATE_WRITE: writing image to FPGA
  36. * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
  37. * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps
  38. * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
  39. * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
  40. */
  41. enum fpga_mgr_states {
  42. /* default FPGA states */
  43. FPGA_MGR_STATE_UNKNOWN,
  44. FPGA_MGR_STATE_POWER_OFF,
  45. FPGA_MGR_STATE_POWER_UP,
  46. FPGA_MGR_STATE_RESET,
  47. /* getting an image for loading */
  48. FPGA_MGR_STATE_FIRMWARE_REQ,
  49. FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
  50. /* write sequence: init, write, complete */
  51. FPGA_MGR_STATE_WRITE_INIT,
  52. FPGA_MGR_STATE_WRITE_INIT_ERR,
  53. FPGA_MGR_STATE_WRITE,
  54. FPGA_MGR_STATE_WRITE_ERR,
  55. FPGA_MGR_STATE_WRITE_COMPLETE,
  56. FPGA_MGR_STATE_WRITE_COMPLETE_ERR,
  57. /* fpga is programmed and operating */
  58. FPGA_MGR_STATE_OPERATING,
  59. };
  60. /*
  61. * FPGA Manager flags
  62. * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
  63. * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
  64. * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
  65. * FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed
  66. */
  67. #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
  68. #define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
  69. #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2)
  70. #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3)
  71. #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4)
  72. /**
  73. * struct fpga_image_info - information specific to a FPGA image
  74. * @flags: boolean flags as defined above
  75. * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
  76. * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
  77. * @config_complete_timeout_us: maximum time for FPGA to switch to operating
  78. * status in the write_complete op.
  79. * @firmware_name: name of FPGA image firmware file
  80. * @sgt: scatter/gather table containing FPGA image
  81. * @buf: contiguous buffer containing FPGA image
  82. * @count: size of buf
  83. * @dev: device that owns this
  84. * @overlay: Device Tree overlay
  85. */
  86. struct fpga_image_info {
  87. u32 flags;
  88. u32 enable_timeout_us;
  89. u32 disable_timeout_us;
  90. u32 config_complete_timeout_us;
  91. char *firmware_name;
  92. struct sg_table *sgt;
  93. const char *buf;
  94. size_t count;
  95. struct device *dev;
  96. #ifdef CONFIG_OF
  97. struct device_node *overlay;
  98. #endif
  99. };
  100. /**
  101. * struct fpga_manager_ops - ops for low level fpga manager drivers
  102. * @initial_header_size: Maximum number of bytes that should be passed into write_init
  103. * @state: returns an enum value of the FPGA's state
  104. * @write_init: prepare the FPGA to receive confuration data
  105. * @write: write count bytes of configuration data to the FPGA
  106. * @write_sg: write the scatter list of configuration data to the FPGA
  107. * @write_complete: set FPGA to operating state after writing is done
  108. * @fpga_remove: optional: Set FPGA into a specific state during driver remove
  109. * @groups: optional attribute groups.
  110. *
  111. * fpga_manager_ops are the low level functions implemented by a specific
  112. * fpga manager driver. The optional ones are tested for NULL before being
  113. * called, so leaving them out is fine.
  114. */
  115. struct fpga_manager_ops {
  116. size_t initial_header_size;
  117. enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
  118. int (*write_init)(struct fpga_manager *mgr,
  119. struct fpga_image_info *info,
  120. const char *buf, size_t count);
  121. int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
  122. int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
  123. int (*write_complete)(struct fpga_manager *mgr,
  124. struct fpga_image_info *info);
  125. void (*fpga_remove)(struct fpga_manager *mgr);
  126. const struct attribute_group **groups;
  127. };
  128. /**
  129. * struct fpga_manager - fpga manager structure
  130. * @name: name of low level fpga manager
  131. * @dev: fpga manager device
  132. * @ref_mutex: only allows one reference to fpga manager
  133. * @state: state of fpga manager
  134. * @mops: pointer to struct of fpga manager ops
  135. * @priv: low level driver private date
  136. */
  137. struct fpga_manager {
  138. const char *name;
  139. struct device dev;
  140. struct mutex ref_mutex;
  141. enum fpga_mgr_states state;
  142. const struct fpga_manager_ops *mops;
  143. void *priv;
  144. };
  145. #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
  146. struct fpga_image_info *fpga_image_info_alloc(struct device *dev);
  147. void fpga_image_info_free(struct fpga_image_info *info);
  148. int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info);
  149. int fpga_mgr_lock(struct fpga_manager *mgr);
  150. void fpga_mgr_unlock(struct fpga_manager *mgr);
  151. struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
  152. struct fpga_manager *fpga_mgr_get(struct device *dev);
  153. void fpga_mgr_put(struct fpga_manager *mgr);
  154. struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
  155. const struct fpga_manager_ops *mops,
  156. void *priv);
  157. void fpga_mgr_free(struct fpga_manager *mgr);
  158. int fpga_mgr_register(struct fpga_manager *mgr);
  159. void fpga_mgr_unregister(struct fpga_manager *mgr);
  160. #endif /*_LINUX_FPGA_MGR_H */