omap_drv.c 18 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/sys_soc.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include "omap_dmm_tiler.h"
  25. #include "omap_drv.h"
  26. #define DRIVER_NAME MODULE_NAME
  27. #define DRIVER_DESC "OMAP DRM"
  28. #define DRIVER_DATE "20110917"
  29. #define DRIVER_MAJOR 1
  30. #define DRIVER_MINOR 0
  31. #define DRIVER_PATCHLEVEL 0
  32. /*
  33. * mode config funcs
  34. */
  35. /* Notes about mapping DSS and DRM entities:
  36. * CRTC: overlay
  37. * encoder: manager.. with some extension to allow one primary CRTC
  38. * and zero or more video CRTC's to be mapped to one encoder?
  39. * connector: dssdev.. manager can be attached/detached from different
  40. * devices
  41. */
  42. static void omap_fb_output_poll_changed(struct drm_device *dev)
  43. {
  44. struct omap_drm_private *priv = dev->dev_private;
  45. DBG("dev=%p", dev);
  46. if (priv->fbdev)
  47. drm_fb_helper_hotplug_event(priv->fbdev);
  48. }
  49. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  50. struct drm_atomic_state *old_state)
  51. {
  52. struct drm_crtc_state *old_crtc_state;
  53. struct drm_crtc *crtc;
  54. unsigned int i;
  55. int ret;
  56. for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  57. if (!crtc->state->enable)
  58. continue;
  59. ret = omap_crtc_wait_pending(crtc);
  60. if (!ret)
  61. dev_warn(dev->dev,
  62. "atomic complete timeout (pipe %u)!\n", i);
  63. }
  64. }
  65. static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  66. {
  67. struct drm_device *dev = old_state->dev;
  68. struct omap_drm_private *priv = dev->dev_private;
  69. priv->dispc_ops->runtime_get();
  70. /* Apply the atomic update. */
  71. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  72. /* With the current dss dispc implementation we have to enable
  73. * the new modeset before we can commit planes. The dispc ovl
  74. * configuration relies on the video mode configuration been
  75. * written into the HW when the ovl configuration is
  76. * calculated.
  77. *
  78. * This approach is not ideal because after a mode change the
  79. * plane update is executed only after the first vblank
  80. * interrupt. The dispc implementation should be fixed so that
  81. * it is able use uncommitted drm state information.
  82. */
  83. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  84. omap_atomic_wait_for_completion(dev, old_state);
  85. drm_atomic_helper_commit_planes(dev, old_state, 0);
  86. drm_atomic_helper_commit_hw_done(old_state);
  87. /*
  88. * Wait for completion of the page flips to ensure that old buffers
  89. * can't be touched by the hardware anymore before cleaning up planes.
  90. */
  91. omap_atomic_wait_for_completion(dev, old_state);
  92. drm_atomic_helper_cleanup_planes(dev, old_state);
  93. priv->dispc_ops->runtime_put();
  94. }
  95. static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
  96. .atomic_commit_tail = omap_atomic_commit_tail,
  97. };
  98. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  99. .fb_create = omap_framebuffer_create,
  100. .output_poll_changed = omap_fb_output_poll_changed,
  101. .atomic_check = drm_atomic_helper_check,
  102. .atomic_commit = drm_atomic_helper_commit,
  103. };
  104. static int get_connector_type(struct omap_dss_device *dssdev)
  105. {
  106. switch (dssdev->type) {
  107. case OMAP_DISPLAY_TYPE_HDMI:
  108. return DRM_MODE_CONNECTOR_HDMIA;
  109. case OMAP_DISPLAY_TYPE_DVI:
  110. return DRM_MODE_CONNECTOR_DVID;
  111. case OMAP_DISPLAY_TYPE_DSI:
  112. return DRM_MODE_CONNECTOR_DSI;
  113. default:
  114. return DRM_MODE_CONNECTOR_Unknown;
  115. }
  116. }
  117. static void omap_disconnect_dssdevs(void)
  118. {
  119. struct omap_dss_device *dssdev = NULL;
  120. for_each_dss_dev(dssdev)
  121. dssdev->driver->disconnect(dssdev);
  122. }
  123. static int omap_connect_dssdevs(void)
  124. {
  125. int r;
  126. struct omap_dss_device *dssdev = NULL;
  127. if (!omapdss_stack_is_ready())
  128. return -EPROBE_DEFER;
  129. for_each_dss_dev(dssdev) {
  130. r = dssdev->driver->connect(dssdev);
  131. if (r == -EPROBE_DEFER) {
  132. omap_dss_put_device(dssdev);
  133. goto cleanup;
  134. } else if (r) {
  135. dev_warn(dssdev->dev, "could not connect display: %s\n",
  136. dssdev->name);
  137. }
  138. }
  139. return 0;
  140. cleanup:
  141. /*
  142. * if we are deferring probe, we disconnect the devices we previously
  143. * connected
  144. */
  145. omap_disconnect_dssdevs();
  146. return r;
  147. }
  148. static int omap_modeset_init_properties(struct drm_device *dev)
  149. {
  150. struct omap_drm_private *priv = dev->dev_private;
  151. unsigned int num_planes = priv->dispc_ops->get_num_ovls();
  152. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
  153. num_planes - 1);
  154. if (!priv->zorder_prop)
  155. return -ENOMEM;
  156. return 0;
  157. }
  158. static int omap_modeset_init(struct drm_device *dev)
  159. {
  160. struct omap_drm_private *priv = dev->dev_private;
  161. struct omap_dss_device *dssdev = NULL;
  162. int num_ovls = priv->dispc_ops->get_num_ovls();
  163. int num_mgrs = priv->dispc_ops->get_num_mgrs();
  164. int num_crtcs, crtc_idx, plane_idx;
  165. int ret;
  166. u32 plane_crtc_mask;
  167. drm_mode_config_init(dev);
  168. ret = omap_modeset_init_properties(dev);
  169. if (ret < 0)
  170. return ret;
  171. /*
  172. * This function creates exactly one connector, encoder, crtc,
  173. * and primary plane per each connected dss-device. Each
  174. * connector->encoder->crtc chain is expected to be separate
  175. * and each crtc is connect to a single dss-channel. If the
  176. * configuration does not match the expectations or exceeds
  177. * the available resources, the configuration is rejected.
  178. */
  179. num_crtcs = 0;
  180. for_each_dss_dev(dssdev)
  181. if (omapdss_device_is_connected(dssdev))
  182. num_crtcs++;
  183. if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
  184. num_crtcs > ARRAY_SIZE(priv->crtcs) ||
  185. num_crtcs > ARRAY_SIZE(priv->planes) ||
  186. num_crtcs > ARRAY_SIZE(priv->encoders) ||
  187. num_crtcs > ARRAY_SIZE(priv->connectors)) {
  188. dev_err(dev->dev, "%s(): Too many connected displays\n",
  189. __func__);
  190. return -EINVAL;
  191. }
  192. /* All planes can be put to any CRTC */
  193. plane_crtc_mask = (1 << num_crtcs) - 1;
  194. dssdev = NULL;
  195. crtc_idx = 0;
  196. plane_idx = 0;
  197. for_each_dss_dev(dssdev) {
  198. struct drm_connector *connector;
  199. struct drm_encoder *encoder;
  200. struct drm_plane *plane;
  201. struct drm_crtc *crtc;
  202. if (!omapdss_device_is_connected(dssdev))
  203. continue;
  204. encoder = omap_encoder_init(dev, dssdev);
  205. if (!encoder)
  206. return -ENOMEM;
  207. connector = omap_connector_init(dev,
  208. get_connector_type(dssdev), dssdev, encoder);
  209. if (!connector)
  210. return -ENOMEM;
  211. plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
  212. plane_crtc_mask);
  213. if (IS_ERR(plane))
  214. return PTR_ERR(plane);
  215. crtc = omap_crtc_init(dev, plane, dssdev);
  216. if (IS_ERR(crtc))
  217. return PTR_ERR(crtc);
  218. drm_mode_connector_attach_encoder(connector, encoder);
  219. encoder->possible_crtcs = (1 << crtc_idx);
  220. priv->crtcs[priv->num_crtcs++] = crtc;
  221. priv->planes[priv->num_planes++] = plane;
  222. priv->encoders[priv->num_encoders++] = encoder;
  223. priv->connectors[priv->num_connectors++] = connector;
  224. plane_idx++;
  225. crtc_idx++;
  226. }
  227. /*
  228. * Create normal planes for the remaining overlays:
  229. */
  230. for (; plane_idx < num_ovls; plane_idx++) {
  231. struct drm_plane *plane;
  232. if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
  233. return -EINVAL;
  234. plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
  235. plane_crtc_mask);
  236. if (IS_ERR(plane))
  237. return PTR_ERR(plane);
  238. priv->planes[priv->num_planes++] = plane;
  239. }
  240. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  241. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  242. priv->num_connectors);
  243. dev->mode_config.min_width = 8;
  244. dev->mode_config.min_height = 2;
  245. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  246. * to fill in these limits properly on different OMAP generations..
  247. */
  248. dev->mode_config.max_width = 2048;
  249. dev->mode_config.max_height = 2048;
  250. dev->mode_config.funcs = &omap_mode_config_funcs;
  251. dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
  252. drm_mode_config_reset(dev);
  253. omap_drm_irq_install(dev);
  254. return 0;
  255. }
  256. /*
  257. * drm ioctl funcs
  258. */
  259. static int ioctl_get_param(struct drm_device *dev, void *data,
  260. struct drm_file *file_priv)
  261. {
  262. struct omap_drm_private *priv = dev->dev_private;
  263. struct drm_omap_param *args = data;
  264. DBG("%p: param=%llu", dev, args->param);
  265. switch (args->param) {
  266. case OMAP_PARAM_CHIPSET_ID:
  267. args->value = priv->omaprev;
  268. break;
  269. default:
  270. DBG("unknown parameter %lld", args->param);
  271. return -EINVAL;
  272. }
  273. return 0;
  274. }
  275. static int ioctl_set_param(struct drm_device *dev, void *data,
  276. struct drm_file *file_priv)
  277. {
  278. struct drm_omap_param *args = data;
  279. switch (args->param) {
  280. default:
  281. DBG("unknown parameter %lld", args->param);
  282. return -EINVAL;
  283. }
  284. return 0;
  285. }
  286. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  287. static int ioctl_gem_new(struct drm_device *dev, void *data,
  288. struct drm_file *file_priv)
  289. {
  290. struct drm_omap_gem_new *args = data;
  291. u32 flags = args->flags & OMAP_BO_USER_MASK;
  292. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  293. args->size.bytes, flags);
  294. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  295. &args->handle);
  296. }
  297. static int ioctl_gem_info(struct drm_device *dev, void *data,
  298. struct drm_file *file_priv)
  299. {
  300. struct drm_omap_gem_info *args = data;
  301. struct drm_gem_object *obj;
  302. int ret = 0;
  303. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  304. obj = drm_gem_object_lookup(file_priv, args->handle);
  305. if (!obj)
  306. return -ENOENT;
  307. args->size = omap_gem_mmap_size(obj);
  308. args->offset = omap_gem_mmap_offset(obj);
  309. drm_gem_object_unreference_unlocked(obj);
  310. return ret;
  311. }
  312. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  313. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
  314. DRM_AUTH | DRM_RENDER_ALLOW),
  315. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
  316. DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
  317. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
  318. DRM_AUTH | DRM_RENDER_ALLOW),
  319. /* Deprecated, to be removed. */
  320. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
  321. DRM_AUTH | DRM_RENDER_ALLOW),
  322. /* Deprecated, to be removed. */
  323. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
  324. DRM_AUTH | DRM_RENDER_ALLOW),
  325. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
  326. DRM_AUTH | DRM_RENDER_ALLOW),
  327. };
  328. /*
  329. * drm driver funcs
  330. */
  331. static int dev_open(struct drm_device *dev, struct drm_file *file)
  332. {
  333. file->driver_priv = NULL;
  334. DBG("open: dev=%p, file=%p", dev, file);
  335. return 0;
  336. }
  337. /**
  338. * lastclose - clean up after all DRM clients have exited
  339. * @dev: DRM device
  340. *
  341. * Take care of cleaning up after all DRM clients have exited. In the
  342. * mode setting case, we want to restore the kernel's initial mode (just
  343. * in case the last client left us in a bad state).
  344. */
  345. static void dev_lastclose(struct drm_device *dev)
  346. {
  347. int i;
  348. /* we don't support vga_switcheroo.. so just make sure the fbdev
  349. * mode is active
  350. */
  351. struct omap_drm_private *priv = dev->dev_private;
  352. int ret;
  353. DBG("lastclose: dev=%p", dev);
  354. /* need to restore default rotation state.. not sure
  355. * if there is a cleaner way to restore properties to
  356. * default state? Maybe a flag that properties should
  357. * automatically be restored to default state on
  358. * lastclose?
  359. */
  360. for (i = 0; i < priv->num_crtcs; i++) {
  361. struct drm_crtc *crtc = priv->crtcs[i];
  362. if (!crtc->primary->rotation_property)
  363. continue;
  364. drm_object_property_set_value(&crtc->base,
  365. crtc->primary->rotation_property,
  366. DRM_MODE_ROTATE_0);
  367. }
  368. for (i = 0; i < priv->num_planes; i++) {
  369. struct drm_plane *plane = priv->planes[i];
  370. if (!plane->rotation_property)
  371. continue;
  372. drm_object_property_set_value(&plane->base,
  373. plane->rotation_property,
  374. DRM_MODE_ROTATE_0);
  375. }
  376. if (priv->fbdev) {
  377. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  378. if (ret)
  379. DBG("failed to restore crtc mode");
  380. }
  381. }
  382. static const struct vm_operations_struct omap_gem_vm_ops = {
  383. .fault = omap_gem_fault,
  384. .open = drm_gem_vm_open,
  385. .close = drm_gem_vm_close,
  386. };
  387. static const struct file_operations omapdriver_fops = {
  388. .owner = THIS_MODULE,
  389. .open = drm_open,
  390. .unlocked_ioctl = drm_ioctl,
  391. .release = drm_release,
  392. .mmap = omap_gem_mmap,
  393. .poll = drm_poll,
  394. .read = drm_read,
  395. .llseek = noop_llseek,
  396. };
  397. static struct drm_driver omap_drm_driver = {
  398. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  399. DRIVER_ATOMIC | DRIVER_RENDER,
  400. .open = dev_open,
  401. .lastclose = dev_lastclose,
  402. #ifdef CONFIG_DEBUG_FS
  403. .debugfs_init = omap_debugfs_init,
  404. #endif
  405. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  406. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  407. .gem_prime_export = omap_gem_prime_export,
  408. .gem_prime_import = omap_gem_prime_import,
  409. .gem_free_object = omap_gem_free_object,
  410. .gem_vm_ops = &omap_gem_vm_ops,
  411. .dumb_create = omap_gem_dumb_create,
  412. .dumb_map_offset = omap_gem_dumb_map_offset,
  413. .dumb_destroy = drm_gem_dumb_destroy,
  414. .ioctls = ioctls,
  415. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  416. .fops = &omapdriver_fops,
  417. .name = DRIVER_NAME,
  418. .desc = DRIVER_DESC,
  419. .date = DRIVER_DATE,
  420. .major = DRIVER_MAJOR,
  421. .minor = DRIVER_MINOR,
  422. .patchlevel = DRIVER_PATCHLEVEL,
  423. };
  424. static const struct soc_device_attribute omapdrm_soc_devices[] = {
  425. { .family = "OMAP3", .data = (void *)0x3430 },
  426. { .family = "OMAP4", .data = (void *)0x4430 },
  427. { .family = "OMAP5", .data = (void *)0x5430 },
  428. { .family = "DRA7", .data = (void *)0x0752 },
  429. { /* sentinel */ }
  430. };
  431. static int pdev_probe(struct platform_device *pdev)
  432. {
  433. const struct soc_device_attribute *soc;
  434. struct omap_drm_private *priv;
  435. struct drm_device *ddev;
  436. unsigned int i;
  437. int ret;
  438. DBG("%s", pdev->name);
  439. if (omapdss_is_initialized() == false)
  440. return -EPROBE_DEFER;
  441. omap_crtc_pre_init();
  442. ret = omap_connect_dssdevs();
  443. if (ret)
  444. goto err_crtc_uninit;
  445. /* Allocate and initialize the driver private structure. */
  446. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  447. if (!priv) {
  448. ret = -ENOMEM;
  449. goto err_disconnect_dssdevs;
  450. }
  451. priv->dispc_ops = dispc_get_ops();
  452. soc = soc_device_match(omapdrm_soc_devices);
  453. priv->omaprev = soc ? (unsigned int)soc->data : 0;
  454. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  455. spin_lock_init(&priv->list_lock);
  456. INIT_LIST_HEAD(&priv->obj_list);
  457. /* Allocate and initialize the DRM device. */
  458. ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev);
  459. if (IS_ERR(ddev)) {
  460. ret = PTR_ERR(ddev);
  461. goto err_free_priv;
  462. }
  463. ddev->dev_private = priv;
  464. platform_set_drvdata(pdev, ddev);
  465. omap_gem_init(ddev);
  466. ret = omap_modeset_init(ddev);
  467. if (ret) {
  468. dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  469. goto err_free_drm_dev;
  470. }
  471. /* Initialize vblank handling, start with all CRTCs disabled. */
  472. ret = drm_vblank_init(ddev, priv->num_crtcs);
  473. if (ret) {
  474. dev_err(&pdev->dev, "could not init vblank\n");
  475. goto err_cleanup_modeset;
  476. }
  477. for (i = 0; i < priv->num_crtcs; i++)
  478. drm_crtc_vblank_off(priv->crtcs[i]);
  479. priv->fbdev = omap_fbdev_init(ddev);
  480. drm_kms_helper_poll_init(ddev);
  481. /*
  482. * Register the DRM device with the core and the connectors with
  483. * sysfs.
  484. */
  485. ret = drm_dev_register(ddev, 0);
  486. if (ret)
  487. goto err_cleanup_helpers;
  488. return 0;
  489. err_cleanup_helpers:
  490. drm_kms_helper_poll_fini(ddev);
  491. if (priv->fbdev)
  492. omap_fbdev_free(ddev);
  493. err_cleanup_modeset:
  494. drm_mode_config_cleanup(ddev);
  495. omap_drm_irq_uninstall(ddev);
  496. err_free_drm_dev:
  497. omap_gem_deinit(ddev);
  498. drm_dev_unref(ddev);
  499. err_free_priv:
  500. destroy_workqueue(priv->wq);
  501. kfree(priv);
  502. err_disconnect_dssdevs:
  503. omap_disconnect_dssdevs();
  504. err_crtc_uninit:
  505. omap_crtc_pre_uninit();
  506. return ret;
  507. }
  508. static int pdev_remove(struct platform_device *pdev)
  509. {
  510. struct drm_device *ddev = platform_get_drvdata(pdev);
  511. struct omap_drm_private *priv = ddev->dev_private;
  512. DBG("");
  513. drm_dev_unregister(ddev);
  514. drm_kms_helper_poll_fini(ddev);
  515. if (priv->fbdev)
  516. omap_fbdev_free(ddev);
  517. drm_atomic_helper_shutdown(ddev);
  518. drm_mode_config_cleanup(ddev);
  519. omap_drm_irq_uninstall(ddev);
  520. omap_gem_deinit(ddev);
  521. drm_dev_unref(ddev);
  522. destroy_workqueue(priv->wq);
  523. kfree(priv);
  524. omap_disconnect_dssdevs();
  525. omap_crtc_pre_uninit();
  526. return 0;
  527. }
  528. #ifdef CONFIG_PM_SLEEP
  529. static int omap_drm_suspend_all_displays(void)
  530. {
  531. struct omap_dss_device *dssdev = NULL;
  532. for_each_dss_dev(dssdev) {
  533. if (!dssdev->driver)
  534. continue;
  535. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  536. dssdev->driver->disable(dssdev);
  537. dssdev->activate_after_resume = true;
  538. } else {
  539. dssdev->activate_after_resume = false;
  540. }
  541. }
  542. return 0;
  543. }
  544. static int omap_drm_resume_all_displays(void)
  545. {
  546. struct omap_dss_device *dssdev = NULL;
  547. for_each_dss_dev(dssdev) {
  548. if (!dssdev->driver)
  549. continue;
  550. if (dssdev->activate_after_resume) {
  551. dssdev->driver->enable(dssdev);
  552. dssdev->activate_after_resume = false;
  553. }
  554. }
  555. return 0;
  556. }
  557. static int omap_drm_suspend(struct device *dev)
  558. {
  559. struct drm_device *drm_dev = dev_get_drvdata(dev);
  560. drm_kms_helper_poll_disable(drm_dev);
  561. drm_modeset_lock_all(drm_dev);
  562. omap_drm_suspend_all_displays();
  563. drm_modeset_unlock_all(drm_dev);
  564. return 0;
  565. }
  566. static int omap_drm_resume(struct device *dev)
  567. {
  568. struct drm_device *drm_dev = dev_get_drvdata(dev);
  569. drm_modeset_lock_all(drm_dev);
  570. omap_drm_resume_all_displays();
  571. drm_modeset_unlock_all(drm_dev);
  572. drm_kms_helper_poll_enable(drm_dev);
  573. return omap_gem_resume(dev);
  574. }
  575. #endif
  576. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  577. static struct platform_driver pdev = {
  578. .driver = {
  579. .name = DRIVER_NAME,
  580. .pm = &omapdrm_pm_ops,
  581. },
  582. .probe = pdev_probe,
  583. .remove = pdev_remove,
  584. };
  585. static struct platform_driver * const drivers[] = {
  586. &omap_dmm_driver,
  587. &pdev,
  588. };
  589. static int __init omap_drm_init(void)
  590. {
  591. DBG("init");
  592. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  593. }
  594. static void __exit omap_drm_fini(void)
  595. {
  596. DBG("fini");
  597. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  598. }
  599. /* need late_initcall() so we load after dss_driver's are loaded */
  600. late_initcall(omap_drm_init);
  601. module_exit(omap_drm_fini);
  602. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  603. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  604. MODULE_ALIAS("platform:" DRIVER_NAME);
  605. MODULE_LICENSE("GPL v2");