pcie-cadence-host.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017 Cadence
  3. // Cadence PCIe host controller driver.
  4. // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
  5. #include <linux/kernel.h>
  6. #include <linux/of_address.h>
  7. #include <linux/of_pci.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm_runtime.h>
  10. #include "pcie-cadence.h"
  11. /**
  12. * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
  13. * @pcie: Cadence PCIe controller
  14. * @dev: pointer to PCIe device
  15. * @cfg_res: start/end offsets in the physical system memory to map PCI
  16. * configuration space accesses
  17. * @bus_range: first/last buses behind the PCIe host controller
  18. * @cfg_base: IO mapped window to access the PCI configuration space of a
  19. * single function at a time
  20. * @max_regions: maximum number of regions supported by the hardware
  21. * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
  22. * translation (nbits sets into the "no BAR match" register)
  23. * @vendor_id: PCI vendor ID
  24. * @device_id: PCI device ID
  25. */
  26. struct cdns_pcie_rc {
  27. struct cdns_pcie pcie;
  28. struct device *dev;
  29. struct resource *cfg_res;
  30. struct resource *bus_range;
  31. void __iomem *cfg_base;
  32. u32 max_regions;
  33. u32 no_bar_nbits;
  34. u16 vendor_id;
  35. u16 device_id;
  36. };
  37. static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
  38. int where)
  39. {
  40. struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
  41. struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
  42. struct cdns_pcie *pcie = &rc->pcie;
  43. unsigned int busn = bus->number;
  44. u32 addr0, desc0;
  45. if (busn == rc->bus_range->start) {
  46. /*
  47. * Only the root port (devfn == 0) is connected to this bus.
  48. * All other PCI devices are behind some bridge hence on another
  49. * bus.
  50. */
  51. if (devfn)
  52. return NULL;
  53. return pcie->reg_base + (where & 0xfff);
  54. }
  55. /* Update Output registers for AXI region 0. */
  56. addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
  57. CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
  58. CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn);
  59. cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
  60. /* Configuration Type 0 or Type 1 access. */
  61. desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
  62. CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
  63. /*
  64. * The bus number was already set once for all in desc1 by
  65. * cdns_pcie_host_init_address_translation().
  66. */
  67. if (busn == rc->bus_range->start + 1)
  68. desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
  69. else
  70. desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
  71. cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
  72. return rc->cfg_base + (where & 0xfff);
  73. }
  74. static struct pci_ops cdns_pcie_host_ops = {
  75. .map_bus = cdns_pci_map_bus,
  76. .read = pci_generic_config_read,
  77. .write = pci_generic_config_write,
  78. };
  79. static const struct of_device_id cdns_pcie_host_of_match[] = {
  80. { .compatible = "cdns,cdns-pcie-host" },
  81. { },
  82. };
  83. static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
  84. {
  85. struct cdns_pcie *pcie = &rc->pcie;
  86. u32 value, ctrl;
  87. /*
  88. * Set the root complex BAR configuration register:
  89. * - disable both BAR0 and BAR1.
  90. * - enable Prefetchable Memory Base and Limit registers in type 1
  91. * config space (64 bits).
  92. * - enable IO Base and Limit registers in type 1 config
  93. * space (32 bits).
  94. */
  95. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
  96. value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
  97. CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
  98. CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
  99. CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
  100. CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
  101. CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
  102. cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
  103. /* Set root port configuration space */
  104. if (rc->vendor_id != 0xffff)
  105. cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id);
  106. if (rc->device_id != 0xffff)
  107. cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
  108. cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
  109. cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
  110. cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
  111. return 0;
  112. }
  113. static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
  114. {
  115. struct cdns_pcie *pcie = &rc->pcie;
  116. struct resource *cfg_res = rc->cfg_res;
  117. struct resource *mem_res = pcie->mem_res;
  118. struct resource *bus_range = rc->bus_range;
  119. struct device *dev = rc->dev;
  120. struct device_node *np = dev->of_node;
  121. struct of_pci_range_parser parser;
  122. struct of_pci_range range;
  123. u32 addr0, addr1, desc1;
  124. u64 cpu_addr;
  125. int r, err;
  126. /*
  127. * Reserve region 0 for PCI configure space accesses:
  128. * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
  129. * cdns_pci_map_bus(), other region registers are set here once for all.
  130. */
  131. addr1 = 0; /* Should be programmed to zero. */
  132. desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);
  133. cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
  134. cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
  135. cpu_addr = cfg_res->start - mem_res->start;
  136. addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
  137. (lower_32_bits(cpu_addr) & GENMASK(31, 8));
  138. addr1 = upper_32_bits(cpu_addr);
  139. cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
  140. cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
  141. err = of_pci_range_parser_init(&parser, np);
  142. if (err)
  143. return err;
  144. r = 1;
  145. for_each_of_pci_range(&parser, &range) {
  146. bool is_io;
  147. if (r >= rc->max_regions)
  148. break;
  149. if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
  150. is_io = false;
  151. else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
  152. is_io = true;
  153. else
  154. continue;
  155. cdns_pcie_set_outbound_region(pcie, 0, r, is_io,
  156. range.cpu_addr,
  157. range.pci_addr,
  158. range.size);
  159. r++;
  160. }
  161. /*
  162. * Set Root Port no BAR match Inbound Translation registers:
  163. * needed for MSI and DMA.
  164. * Root Port BAR0 and BAR1 are disabled, hence no need to set their
  165. * inbound translation registers.
  166. */
  167. addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->no_bar_nbits);
  168. addr1 = 0;
  169. cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(RP_NO_BAR), addr0);
  170. cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(RP_NO_BAR), addr1);
  171. return 0;
  172. }
  173. static int cdns_pcie_host_init(struct device *dev,
  174. struct list_head *resources,
  175. struct cdns_pcie_rc *rc)
  176. {
  177. struct resource *bus_range = NULL;
  178. int err;
  179. /* Parse our PCI ranges and request their resources */
  180. err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
  181. if (err)
  182. return err;
  183. rc->bus_range = bus_range;
  184. rc->pcie.bus = bus_range->start;
  185. err = cdns_pcie_host_init_root_port(rc);
  186. if (err)
  187. goto err_out;
  188. err = cdns_pcie_host_init_address_translation(rc);
  189. if (err)
  190. goto err_out;
  191. return 0;
  192. err_out:
  193. pci_free_resource_list(resources);
  194. return err;
  195. }
  196. static int cdns_pcie_host_probe(struct platform_device *pdev)
  197. {
  198. const char *type;
  199. struct device *dev = &pdev->dev;
  200. struct device_node *np = dev->of_node;
  201. struct pci_host_bridge *bridge;
  202. struct list_head resources;
  203. struct cdns_pcie_rc *rc;
  204. struct cdns_pcie *pcie;
  205. struct resource *res;
  206. int ret;
  207. bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
  208. if (!bridge)
  209. return -ENOMEM;
  210. rc = pci_host_bridge_priv(bridge);
  211. rc->dev = dev;
  212. pcie = &rc->pcie;
  213. pcie->is_rc = true;
  214. rc->max_regions = 32;
  215. of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
  216. rc->no_bar_nbits = 32;
  217. of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
  218. rc->vendor_id = 0xffff;
  219. of_property_read_u16(np, "vendor-id", &rc->vendor_id);
  220. rc->device_id = 0xffff;
  221. of_property_read_u16(np, "device-id", &rc->device_id);
  222. type = of_get_property(np, "device_type", NULL);
  223. if (!type || strcmp(type, "pci")) {
  224. dev_err(dev, "invalid \"device_type\" %s\n", type);
  225. return -EINVAL;
  226. }
  227. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
  228. pcie->reg_base = devm_ioremap_resource(dev, res);
  229. if (IS_ERR(pcie->reg_base)) {
  230. dev_err(dev, "missing \"reg\"\n");
  231. return PTR_ERR(pcie->reg_base);
  232. }
  233. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
  234. rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
  235. if (IS_ERR(rc->cfg_base)) {
  236. dev_err(dev, "missing \"cfg\"\n");
  237. return PTR_ERR(rc->cfg_base);
  238. }
  239. rc->cfg_res = res;
  240. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
  241. if (!res) {
  242. dev_err(dev, "missing \"mem\"\n");
  243. return -EINVAL;
  244. }
  245. pcie->mem_res = res;
  246. pm_runtime_enable(dev);
  247. ret = pm_runtime_get_sync(dev);
  248. if (ret < 0) {
  249. dev_err(dev, "pm_runtime_get_sync() failed\n");
  250. goto err_get_sync;
  251. }
  252. ret = cdns_pcie_host_init(dev, &resources, rc);
  253. if (ret)
  254. goto err_init;
  255. list_splice_init(&resources, &bridge->windows);
  256. bridge->dev.parent = dev;
  257. bridge->busnr = pcie->bus;
  258. bridge->ops = &cdns_pcie_host_ops;
  259. bridge->map_irq = of_irq_parse_and_map_pci;
  260. bridge->swizzle_irq = pci_common_swizzle;
  261. ret = pci_host_probe(bridge);
  262. if (ret < 0)
  263. goto err_host_probe;
  264. return 0;
  265. err_host_probe:
  266. pci_free_resource_list(&resources);
  267. err_init:
  268. pm_runtime_put_sync(dev);
  269. err_get_sync:
  270. pm_runtime_disable(dev);
  271. return ret;
  272. }
  273. static struct platform_driver cdns_pcie_host_driver = {
  274. .driver = {
  275. .name = "cdns-pcie-host",
  276. .of_match_table = cdns_pcie_host_of_match,
  277. },
  278. .probe = cdns_pcie_host_probe,
  279. };
  280. builtin_platform_driver(cdns_pcie_host_driver);