carma-fpga.c 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507
  1. /*
  2. * CARMA DATA-FPGA Access Driver
  3. *
  4. * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. * FPGA Memory Dump Format
  13. *
  14. * FPGA #0 control registers (32 x 32-bit words)
  15. * FPGA #1 control registers (32 x 32-bit words)
  16. * FPGA #2 control registers (32 x 32-bit words)
  17. * FPGA #3 control registers (32 x 32-bit words)
  18. * SYSFPGA control registers (32 x 32-bit words)
  19. * FPGA #0 correlation array (NUM_CORL0 correlation blocks)
  20. * FPGA #1 correlation array (NUM_CORL1 correlation blocks)
  21. * FPGA #2 correlation array (NUM_CORL2 correlation blocks)
  22. * FPGA #3 correlation array (NUM_CORL3 correlation blocks)
  23. *
  24. * Each correlation array consists of:
  25. *
  26. * Correlation Data (2 x NUM_LAGSn x 32-bit words)
  27. * Pipeline Metadata (2 x NUM_METAn x 32-bit words)
  28. * Quantization Counters (2 x NUM_QCNTn x 32-bit words)
  29. *
  30. * The NUM_CORLn, NUM_LAGSn, NUM_METAn, and NUM_QCNTn values come from
  31. * the FPGA configuration registers. They do not change once the FPGA's
  32. * have been programmed, they only change on re-programming.
  33. */
  34. /*
  35. * Basic Description:
  36. *
  37. * This driver is used to capture correlation spectra off of the four data
  38. * processing FPGAs. The FPGAs are often reprogrammed at runtime, therefore
  39. * this driver supports dynamic enable/disable of capture while the device
  40. * remains open.
  41. *
  42. * The nominal capture rate is 64Hz (every 15.625ms). To facilitate this fast
  43. * capture rate, all buffers are pre-allocated to avoid any potentially long
  44. * running memory allocations while capturing.
  45. *
  46. * There are two lists and one pointer which are used to keep track of the
  47. * different states of data buffers.
  48. *
  49. * 1) free list
  50. * This list holds all empty data buffers which are ready to receive data.
  51. *
  52. * 2) inflight pointer
  53. * This pointer holds the currently inflight data buffer. This buffer is having
  54. * data copied into it by the DMA engine.
  55. *
  56. * 3) used list
  57. * This list holds data buffers which have been filled, and are waiting to be
  58. * read by userspace.
  59. *
  60. * All buffers start life on the free list, then move successively to the
  61. * inflight pointer, and then to the used list. After they have been read by
  62. * userspace, they are moved back to the free list. The cycle repeats as long
  63. * as necessary.
  64. *
  65. * It should be noted that all buffers are mapped and ready for DMA when they
  66. * are on any of the three lists. They are only unmapped when they are in the
  67. * process of being read by userspace.
  68. */
  69. /*
  70. * Notes on the IRQ masking scheme:
  71. *
  72. * The IRQ masking scheme here is different than most other hardware. The only
  73. * way for the DATA-FPGAs to detect if the kernel has taken too long to copy
  74. * the data is if the status registers are not cleared before the next
  75. * correlation data dump is ready.
  76. *
  77. * The interrupt line is connected to the status registers, such that when they
  78. * are cleared, the interrupt is de-asserted. Therein lies our problem. We need
  79. * to schedule a long-running DMA operation and return from the interrupt
  80. * handler quickly, but we cannot clear the status registers.
  81. *
  82. * To handle this, the system controller FPGA has the capability to connect the
  83. * interrupt line to a user-controlled GPIO pin. This pin is driven high
  84. * (unasserted) and left that way. To mask the interrupt, we change the
  85. * interrupt source to the GPIO pin. Tada, we hid the interrupt. :)
  86. */
  87. #include <linux/of_address.h>
  88. #include <linux/of_irq.h>
  89. #include <linux/of_platform.h>
  90. #include <linux/dma-mapping.h>
  91. #include <linux/miscdevice.h>
  92. #include <linux/interrupt.h>
  93. #include <linux/dmaengine.h>
  94. #include <linux/seq_file.h>
  95. #include <linux/highmem.h>
  96. #include <linux/debugfs.h>
  97. #include <linux/vmalloc.h>
  98. #include <linux/kernel.h>
  99. #include <linux/module.h>
  100. #include <linux/poll.h>
  101. #include <linux/slab.h>
  102. #include <linux/kref.h>
  103. #include <linux/io.h>
  104. /* system controller registers */
  105. #define SYS_IRQ_SOURCE_CTL 0x24
  106. #define SYS_IRQ_OUTPUT_EN 0x28
  107. #define SYS_IRQ_OUTPUT_DATA 0x2C
  108. #define SYS_IRQ_INPUT_DATA 0x30
  109. #define SYS_FPGA_CONFIG_STATUS 0x44
  110. /* GPIO IRQ line assignment */
  111. #define IRQ_CORL_DONE 0x10
  112. /* FPGA registers */
  113. #define MMAP_REG_VERSION 0x00
  114. #define MMAP_REG_CORL_CONF1 0x08
  115. #define MMAP_REG_CORL_CONF2 0x0C
  116. #define MMAP_REG_STATUS 0x48
  117. #define SYS_FPGA_BLOCK 0xF0000000
  118. #define DATA_FPGA_START 0x400000
  119. #define DATA_FPGA_SIZE 0x80000
  120. static const char drv_name[] = "carma-fpga";
  121. #define NUM_FPGA 4
  122. #define MIN_DATA_BUFS 8
  123. #define MAX_DATA_BUFS 64
  124. struct fpga_info {
  125. unsigned int num_lag_ram;
  126. unsigned int blk_size;
  127. };
  128. struct data_buf {
  129. struct list_head entry;
  130. void *vaddr;
  131. struct scatterlist *sglist;
  132. int sglen;
  133. int nr_pages;
  134. size_t size;
  135. };
  136. struct fpga_device {
  137. /* character device */
  138. struct miscdevice miscdev;
  139. struct device *dev;
  140. struct mutex mutex;
  141. /* reference count */
  142. struct kref ref;
  143. /* FPGA registers and information */
  144. struct fpga_info info[NUM_FPGA];
  145. void __iomem *regs;
  146. int irq;
  147. /* FPGA Physical Address/Size Information */
  148. resource_size_t phys_addr;
  149. size_t phys_size;
  150. /* DMA structures */
  151. struct sg_table corl_table;
  152. unsigned int corl_nents;
  153. struct dma_chan *chan;
  154. /* Protection for all members below */
  155. spinlock_t lock;
  156. /* Device enable/disable flag */
  157. bool enabled;
  158. /* Correlation data buffers */
  159. wait_queue_head_t wait;
  160. struct list_head free;
  161. struct list_head used;
  162. struct data_buf *inflight;
  163. /* Information about data buffers */
  164. unsigned int num_dropped;
  165. unsigned int num_buffers;
  166. size_t bufsize;
  167. struct dentry *dbg_entry;
  168. };
  169. struct fpga_reader {
  170. struct fpga_device *priv;
  171. struct data_buf *buf;
  172. off_t buf_start;
  173. };
  174. static void fpga_device_release(struct kref *ref)
  175. {
  176. struct fpga_device *priv = container_of(ref, struct fpga_device, ref);
  177. /* the last reader has exited, cleanup the last bits */
  178. mutex_destroy(&priv->mutex);
  179. kfree(priv);
  180. }
  181. /*
  182. * Data Buffer Allocation Helpers
  183. */
  184. static int carma_dma_init(struct data_buf *buf, int nr_pages)
  185. {
  186. struct page *pg;
  187. int i;
  188. buf->vaddr = vmalloc_32(nr_pages << PAGE_SHIFT);
  189. if (NULL == buf->vaddr) {
  190. pr_debug("vmalloc_32(%d pages) failed\n", nr_pages);
  191. return -ENOMEM;
  192. }
  193. pr_debug("vmalloc is at addr 0x%08lx, size=%d\n",
  194. (unsigned long)buf->vaddr,
  195. nr_pages << PAGE_SHIFT);
  196. memset(buf->vaddr, 0, nr_pages << PAGE_SHIFT);
  197. buf->nr_pages = nr_pages;
  198. buf->sglist = vzalloc(buf->nr_pages * sizeof(*buf->sglist));
  199. if (NULL == buf->sglist)
  200. goto vzalloc_err;
  201. sg_init_table(buf->sglist, buf->nr_pages);
  202. for (i = 0; i < buf->nr_pages; i++) {
  203. pg = vmalloc_to_page(buf->vaddr + i * PAGE_SIZE);
  204. if (NULL == pg)
  205. goto vmalloc_to_page_err;
  206. sg_set_page(&buf->sglist[i], pg, PAGE_SIZE, 0);
  207. }
  208. return 0;
  209. vmalloc_to_page_err:
  210. vfree(buf->sglist);
  211. buf->sglist = NULL;
  212. vzalloc_err:
  213. vfree(buf->vaddr);
  214. buf->vaddr = NULL;
  215. return -ENOMEM;
  216. }
  217. static int carma_dma_map(struct device *dev, struct data_buf *buf)
  218. {
  219. buf->sglen = dma_map_sg(dev, buf->sglist,
  220. buf->nr_pages, DMA_FROM_DEVICE);
  221. if (0 == buf->sglen) {
  222. pr_warn("%s: dma_map_sg failed\n", __func__);
  223. return -ENOMEM;
  224. }
  225. return 0;
  226. }
  227. static int carma_dma_unmap(struct device *dev, struct data_buf *buf)
  228. {
  229. if (!buf->sglen)
  230. return 0;
  231. dma_unmap_sg(dev, buf->sglist, buf->sglen, DMA_FROM_DEVICE);
  232. buf->sglen = 0;
  233. return 0;
  234. }
  235. /**
  236. * data_free_buffer() - free a single data buffer and all allocated memory
  237. * @buf: the buffer to free
  238. *
  239. * This will free all of the pages allocated to the given data buffer, and
  240. * then free the structure itself
  241. */
  242. static void data_free_buffer(struct data_buf *buf)
  243. {
  244. /* It is ok to free a NULL buffer */
  245. if (!buf)
  246. return;
  247. /* free all memory */
  248. vfree(buf->sglist);
  249. vfree(buf->vaddr);
  250. kfree(buf);
  251. }
  252. /**
  253. * data_alloc_buffer() - allocate and fill a data buffer with pages
  254. * @bytes: the number of bytes required
  255. *
  256. * This allocates all space needed for a data buffer. It must be mapped before
  257. * use in a DMA transaction using carma_dma_map().
  258. *
  259. * Returns NULL on failure
  260. */
  261. static struct data_buf *data_alloc_buffer(const size_t bytes)
  262. {
  263. unsigned int nr_pages;
  264. struct data_buf *buf;
  265. int ret;
  266. /* calculate the number of pages necessary */
  267. nr_pages = DIV_ROUND_UP(bytes, PAGE_SIZE);
  268. /* allocate the buffer structure */
  269. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  270. if (!buf)
  271. goto out_return;
  272. /* initialize internal fields */
  273. INIT_LIST_HEAD(&buf->entry);
  274. buf->size = bytes;
  275. /* allocate the buffer */
  276. ret = carma_dma_init(buf, nr_pages);
  277. if (ret)
  278. goto out_free_buf;
  279. return buf;
  280. out_free_buf:
  281. kfree(buf);
  282. out_return:
  283. return NULL;
  284. }
  285. /**
  286. * data_free_buffers() - free all allocated buffers
  287. * @priv: the driver's private data structure
  288. *
  289. * Free all buffers allocated by the driver (except those currently in the
  290. * process of being read by userspace).
  291. *
  292. * LOCKING: must hold dev->mutex
  293. * CONTEXT: user
  294. */
  295. static void data_free_buffers(struct fpga_device *priv)
  296. {
  297. struct data_buf *buf, *tmp;
  298. /* the device should be stopped, no DMA in progress */
  299. BUG_ON(priv->inflight != NULL);
  300. list_for_each_entry_safe(buf, tmp, &priv->free, entry) {
  301. list_del_init(&buf->entry);
  302. carma_dma_unmap(priv->dev, buf);
  303. data_free_buffer(buf);
  304. }
  305. list_for_each_entry_safe(buf, tmp, &priv->used, entry) {
  306. list_del_init(&buf->entry);
  307. carma_dma_unmap(priv->dev, buf);
  308. data_free_buffer(buf);
  309. }
  310. priv->num_buffers = 0;
  311. priv->bufsize = 0;
  312. }
  313. /**
  314. * data_alloc_buffers() - allocate 1 seconds worth of data buffers
  315. * @priv: the driver's private data structure
  316. *
  317. * Allocate enough buffers for a whole second worth of data
  318. *
  319. * This routine will attempt to degrade nicely by succeeding even if a full
  320. * second worth of data buffers could not be allocated, as long as a minimum
  321. * number were allocated. In this case, it will print a message to the kernel
  322. * log.
  323. *
  324. * The device must not be modifying any lists when this is called.
  325. *
  326. * CONTEXT: user
  327. * LOCKING: must hold dev->mutex
  328. *
  329. * Returns 0 on success, -ERRNO otherwise
  330. */
  331. static int data_alloc_buffers(struct fpga_device *priv)
  332. {
  333. struct data_buf *buf;
  334. int i, ret;
  335. for (i = 0; i < MAX_DATA_BUFS; i++) {
  336. /* allocate a buffer */
  337. buf = data_alloc_buffer(priv->bufsize);
  338. if (!buf)
  339. break;
  340. /* map it for DMA */
  341. ret = carma_dma_map(priv->dev, buf);
  342. if (ret) {
  343. data_free_buffer(buf);
  344. break;
  345. }
  346. /* add it to the list of free buffers */
  347. list_add_tail(&buf->entry, &priv->free);
  348. priv->num_buffers++;
  349. }
  350. /* Make sure we allocated the minimum required number of buffers */
  351. if (priv->num_buffers < MIN_DATA_BUFS) {
  352. dev_err(priv->dev, "Unable to allocate enough data buffers\n");
  353. data_free_buffers(priv);
  354. return -ENOMEM;
  355. }
  356. /* Warn if we are running in a degraded state, but do not fail */
  357. if (priv->num_buffers < MAX_DATA_BUFS) {
  358. dev_warn(priv->dev,
  359. "Unable to allocate %d buffers, using %d buffers instead\n",
  360. MAX_DATA_BUFS, i);
  361. }
  362. return 0;
  363. }
  364. /*
  365. * DMA Operations Helpers
  366. */
  367. /**
  368. * fpga_start_addr() - get the physical address a DATA-FPGA
  369. * @priv: the driver's private data structure
  370. * @fpga: the DATA-FPGA number (zero based)
  371. */
  372. static dma_addr_t fpga_start_addr(struct fpga_device *priv, unsigned int fpga)
  373. {
  374. return priv->phys_addr + 0x400000 + (0x80000 * fpga);
  375. }
  376. /**
  377. * fpga_block_addr() - get the physical address of a correlation data block
  378. * @priv: the driver's private data structure
  379. * @fpga: the DATA-FPGA number (zero based)
  380. * @blknum: the correlation block number (zero based)
  381. */
  382. static dma_addr_t fpga_block_addr(struct fpga_device *priv, unsigned int fpga,
  383. unsigned int blknum)
  384. {
  385. return fpga_start_addr(priv, fpga) + (0x10000 * (1 + blknum));
  386. }
  387. #define REG_BLOCK_SIZE (32 * 4)
  388. /**
  389. * data_setup_corl_table() - create the scatterlist for correlation dumps
  390. * @priv: the driver's private data structure
  391. *
  392. * Create the scatterlist for transferring a correlation dump from the
  393. * DATA FPGAs. This structure will be reused for each buffer than needs
  394. * to be filled with correlation data.
  395. *
  396. * Returns 0 on success, -ERRNO otherwise
  397. */
  398. static int data_setup_corl_table(struct fpga_device *priv)
  399. {
  400. struct sg_table *table = &priv->corl_table;
  401. struct scatterlist *sg;
  402. struct fpga_info *info;
  403. int i, j, ret;
  404. /* Calculate the number of entries needed */
  405. priv->corl_nents = (1 + NUM_FPGA) * REG_BLOCK_SIZE;
  406. for (i = 0; i < NUM_FPGA; i++)
  407. priv->corl_nents += priv->info[i].num_lag_ram;
  408. /* Allocate the scatterlist table */
  409. ret = sg_alloc_table(table, priv->corl_nents, GFP_KERNEL);
  410. if (ret) {
  411. dev_err(priv->dev, "unable to allocate DMA table\n");
  412. return ret;
  413. }
  414. /* Add the DATA FPGA registers to the scatterlist */
  415. sg = table->sgl;
  416. for (i = 0; i < NUM_FPGA; i++) {
  417. sg_dma_address(sg) = fpga_start_addr(priv, i);
  418. sg_dma_len(sg) = REG_BLOCK_SIZE;
  419. sg = sg_next(sg);
  420. }
  421. /* Add the SYS-FPGA registers to the scatterlist */
  422. sg_dma_address(sg) = SYS_FPGA_BLOCK;
  423. sg_dma_len(sg) = REG_BLOCK_SIZE;
  424. sg = sg_next(sg);
  425. /* Add the FPGA correlation data blocks to the scatterlist */
  426. for (i = 0; i < NUM_FPGA; i++) {
  427. info = &priv->info[i];
  428. for (j = 0; j < info->num_lag_ram; j++) {
  429. sg_dma_address(sg) = fpga_block_addr(priv, i, j);
  430. sg_dma_len(sg) = info->blk_size;
  431. sg = sg_next(sg);
  432. }
  433. }
  434. /*
  435. * All physical addresses and lengths are present in the structure
  436. * now. It can be reused for every FPGA DATA interrupt
  437. */
  438. return 0;
  439. }
  440. /*
  441. * FPGA Register Access Helpers
  442. */
  443. static void fpga_write_reg(struct fpga_device *priv, unsigned int fpga,
  444. unsigned int reg, u32 val)
  445. {
  446. const int fpga_start = DATA_FPGA_START + (fpga * DATA_FPGA_SIZE);
  447. iowrite32be(val, priv->regs + fpga_start + reg);
  448. }
  449. static u32 fpga_read_reg(struct fpga_device *priv, unsigned int fpga,
  450. unsigned int reg)
  451. {
  452. const int fpga_start = DATA_FPGA_START + (fpga * DATA_FPGA_SIZE);
  453. return ioread32be(priv->regs + fpga_start + reg);
  454. }
  455. /**
  456. * data_calculate_bufsize() - calculate the data buffer size required
  457. * @priv: the driver's private data structure
  458. *
  459. * Calculate the total buffer size needed to hold a single block
  460. * of correlation data
  461. *
  462. * CONTEXT: user
  463. *
  464. * Returns 0 on success, -ERRNO otherwise
  465. */
  466. static int data_calculate_bufsize(struct fpga_device *priv)
  467. {
  468. u32 num_corl, num_lags, num_meta, num_qcnt, num_pack;
  469. u32 conf1, conf2, version;
  470. u32 num_lag_ram, blk_size;
  471. int i;
  472. /* Each buffer starts with the 5 FPGA register areas */
  473. priv->bufsize = (1 + NUM_FPGA) * REG_BLOCK_SIZE;
  474. /* Read and store the configuration data for each FPGA */
  475. for (i = 0; i < NUM_FPGA; i++) {
  476. version = fpga_read_reg(priv, i, MMAP_REG_VERSION);
  477. conf1 = fpga_read_reg(priv, i, MMAP_REG_CORL_CONF1);
  478. conf2 = fpga_read_reg(priv, i, MMAP_REG_CORL_CONF2);
  479. /* minor version 2 and later */
  480. if ((version & 0x000000FF) >= 2) {
  481. num_corl = (conf1 & 0x000000F0) >> 4;
  482. num_pack = (conf1 & 0x00000F00) >> 8;
  483. num_lags = (conf1 & 0x00FFF000) >> 12;
  484. num_meta = (conf1 & 0x7F000000) >> 24;
  485. num_qcnt = (conf2 & 0x00000FFF) >> 0;
  486. } else {
  487. num_corl = (conf1 & 0x000000F0) >> 4;
  488. num_pack = 1; /* implied */
  489. num_lags = (conf1 & 0x000FFF00) >> 8;
  490. num_meta = (conf1 & 0x7FF00000) >> 20;
  491. num_qcnt = (conf2 & 0x00000FFF) >> 0;
  492. }
  493. num_lag_ram = (num_corl + num_pack - 1) / num_pack;
  494. blk_size = ((num_pack * num_lags) + num_meta + num_qcnt) * 8;
  495. priv->info[i].num_lag_ram = num_lag_ram;
  496. priv->info[i].blk_size = blk_size;
  497. priv->bufsize += num_lag_ram * blk_size;
  498. dev_dbg(priv->dev, "FPGA %d NUM_CORL: %d\n", i, num_corl);
  499. dev_dbg(priv->dev, "FPGA %d NUM_PACK: %d\n", i, num_pack);
  500. dev_dbg(priv->dev, "FPGA %d NUM_LAGS: %d\n", i, num_lags);
  501. dev_dbg(priv->dev, "FPGA %d NUM_META: %d\n", i, num_meta);
  502. dev_dbg(priv->dev, "FPGA %d NUM_QCNT: %d\n", i, num_qcnt);
  503. dev_dbg(priv->dev, "FPGA %d BLK_SIZE: %d\n", i, blk_size);
  504. }
  505. dev_dbg(priv->dev, "TOTAL BUFFER SIZE: %zu bytes\n", priv->bufsize);
  506. return 0;
  507. }
  508. /*
  509. * Interrupt Handling
  510. */
  511. /**
  512. * data_disable_interrupts() - stop the device from generating interrupts
  513. * @priv: the driver's private data structure
  514. *
  515. * Hide interrupts by switching to GPIO interrupt source
  516. *
  517. * LOCKING: must hold dev->lock
  518. */
  519. static void data_disable_interrupts(struct fpga_device *priv)
  520. {
  521. /* hide the interrupt by switching the IRQ driver to GPIO */
  522. iowrite32be(0x2F, priv->regs + SYS_IRQ_SOURCE_CTL);
  523. }
  524. /**
  525. * data_enable_interrupts() - allow the device to generate interrupts
  526. * @priv: the driver's private data structure
  527. *
  528. * Unhide interrupts by switching to the FPGA interrupt source. At the
  529. * same time, clear the DATA-FPGA status registers.
  530. *
  531. * LOCKING: must hold dev->lock
  532. */
  533. static void data_enable_interrupts(struct fpga_device *priv)
  534. {
  535. /* clear the actual FPGA corl_done interrupt */
  536. fpga_write_reg(priv, 0, MMAP_REG_STATUS, 0x0);
  537. fpga_write_reg(priv, 1, MMAP_REG_STATUS, 0x0);
  538. fpga_write_reg(priv, 2, MMAP_REG_STATUS, 0x0);
  539. fpga_write_reg(priv, 3, MMAP_REG_STATUS, 0x0);
  540. /* flush the writes */
  541. fpga_read_reg(priv, 0, MMAP_REG_STATUS);
  542. fpga_read_reg(priv, 1, MMAP_REG_STATUS);
  543. fpga_read_reg(priv, 2, MMAP_REG_STATUS);
  544. fpga_read_reg(priv, 3, MMAP_REG_STATUS);
  545. /* switch back to the external interrupt source */
  546. iowrite32be(0x3F, priv->regs + SYS_IRQ_SOURCE_CTL);
  547. }
  548. /**
  549. * data_dma_cb() - DMAEngine callback for DMA completion
  550. * @data: the driver's private data structure
  551. *
  552. * Complete a DMA transfer from the DATA-FPGA's
  553. *
  554. * This is called via the DMA callback mechanism, and will handle moving the
  555. * completed DMA transaction to the used list, and then wake any processes
  556. * waiting for new data
  557. *
  558. * CONTEXT: any, softirq expected
  559. */
  560. static void data_dma_cb(void *data)
  561. {
  562. struct fpga_device *priv = data;
  563. unsigned long flags;
  564. spin_lock_irqsave(&priv->lock, flags);
  565. /* If there is no inflight buffer, we've got a bug */
  566. BUG_ON(priv->inflight == NULL);
  567. /* Move the inflight buffer onto the used list */
  568. list_move_tail(&priv->inflight->entry, &priv->used);
  569. priv->inflight = NULL;
  570. /*
  571. * If data dumping is still enabled, then clear the FPGA
  572. * status registers and re-enable FPGA interrupts
  573. */
  574. if (priv->enabled)
  575. data_enable_interrupts(priv);
  576. spin_unlock_irqrestore(&priv->lock, flags);
  577. /*
  578. * We've changed both the inflight and used lists, so we need
  579. * to wake up any processes that are blocking for those events
  580. */
  581. wake_up(&priv->wait);
  582. }
  583. /**
  584. * data_submit_dma() - prepare and submit the required DMA to fill a buffer
  585. * @priv: the driver's private data structure
  586. * @buf: the data buffer
  587. *
  588. * Prepare and submit the necessary DMA transactions to fill a correlation
  589. * data buffer.
  590. *
  591. * LOCKING: must hold dev->lock
  592. * CONTEXT: hardirq only
  593. *
  594. * Returns 0 on success, -ERRNO otherwise
  595. */
  596. static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
  597. {
  598. struct scatterlist *dst_sg, *src_sg;
  599. unsigned int dst_nents, src_nents;
  600. struct dma_chan *chan = priv->chan;
  601. struct dma_async_tx_descriptor *tx;
  602. dma_cookie_t cookie;
  603. dma_addr_t dst, src;
  604. unsigned long dma_flags = 0;
  605. dst_sg = buf->sglist;
  606. dst_nents = buf->sglen;
  607. src_sg = priv->corl_table.sgl;
  608. src_nents = priv->corl_nents;
  609. /*
  610. * All buffers passed to this function should be ready and mapped
  611. * for DMA already. Therefore, we don't need to do anything except
  612. * submit it to the Freescale DMA Engine for processing
  613. */
  614. /* setup the scatterlist to scatterlist transfer */
  615. tx = chan->device->device_prep_dma_sg(chan,
  616. dst_sg, dst_nents,
  617. src_sg, src_nents,
  618. 0);
  619. if (!tx) {
  620. dev_err(priv->dev, "unable to prep scatterlist DMA\n");
  621. return -ENOMEM;
  622. }
  623. /* submit the transaction to the DMA controller */
  624. cookie = tx->tx_submit(tx);
  625. if (dma_submit_error(cookie)) {
  626. dev_err(priv->dev, "unable to submit scatterlist DMA\n");
  627. return -ENOMEM;
  628. }
  629. /* Prepare the re-read of the SYS-FPGA block */
  630. dst = sg_dma_address(dst_sg) + (NUM_FPGA * REG_BLOCK_SIZE);
  631. src = SYS_FPGA_BLOCK;
  632. tx = chan->device->device_prep_dma_memcpy(chan, dst, src,
  633. REG_BLOCK_SIZE,
  634. dma_flags);
  635. if (!tx) {
  636. dev_err(priv->dev, "unable to prep SYS-FPGA DMA\n");
  637. return -ENOMEM;
  638. }
  639. /* Setup the callback */
  640. tx->callback = data_dma_cb;
  641. tx->callback_param = priv;
  642. /* submit the transaction to the DMA controller */
  643. cookie = tx->tx_submit(tx);
  644. if (dma_submit_error(cookie)) {
  645. dev_err(priv->dev, "unable to submit SYS-FPGA DMA\n");
  646. return -ENOMEM;
  647. }
  648. return 0;
  649. }
  650. #define CORL_DONE 0x1
  651. #define CORL_ERR 0x2
  652. static irqreturn_t data_irq(int irq, void *dev_id)
  653. {
  654. struct fpga_device *priv = dev_id;
  655. bool submitted = false;
  656. struct data_buf *buf;
  657. u32 status;
  658. int i;
  659. /* detect spurious interrupts via FPGA status */
  660. for (i = 0; i < 4; i++) {
  661. status = fpga_read_reg(priv, i, MMAP_REG_STATUS);
  662. if (!(status & (CORL_DONE | CORL_ERR))) {
  663. dev_err(priv->dev, "spurious irq detected (FPGA)\n");
  664. return IRQ_NONE;
  665. }
  666. }
  667. /* detect spurious interrupts via raw IRQ pin readback */
  668. status = ioread32be(priv->regs + SYS_IRQ_INPUT_DATA);
  669. if (status & IRQ_CORL_DONE) {
  670. dev_err(priv->dev, "spurious irq detected (IRQ)\n");
  671. return IRQ_NONE;
  672. }
  673. spin_lock(&priv->lock);
  674. /*
  675. * This is an error case that should never happen.
  676. *
  677. * If this driver has a bug and manages to re-enable interrupts while
  678. * a DMA is in progress, then we will hit this statement and should
  679. * start paying attention immediately.
  680. */
  681. BUG_ON(priv->inflight != NULL);
  682. /* hide the interrupt by switching the IRQ driver to GPIO */
  683. data_disable_interrupts(priv);
  684. /* If there are no free buffers, drop this data */
  685. if (list_empty(&priv->free)) {
  686. priv->num_dropped++;
  687. goto out;
  688. }
  689. buf = list_first_entry(&priv->free, struct data_buf, entry);
  690. list_del_init(&buf->entry);
  691. BUG_ON(buf->size != priv->bufsize);
  692. /* Submit a DMA transfer to get the correlation data */
  693. if (data_submit_dma(priv, buf)) {
  694. dev_err(priv->dev, "Unable to setup DMA transfer\n");
  695. list_move_tail(&buf->entry, &priv->free);
  696. goto out;
  697. }
  698. /* Save the buffer for the DMA callback */
  699. priv->inflight = buf;
  700. submitted = true;
  701. /* Start the DMA Engine */
  702. dma_async_issue_pending(priv->chan);
  703. out:
  704. /* If no DMA was submitted, re-enable interrupts */
  705. if (!submitted)
  706. data_enable_interrupts(priv);
  707. spin_unlock(&priv->lock);
  708. return IRQ_HANDLED;
  709. }
  710. /*
  711. * Realtime Device Enable Helpers
  712. */
  713. /**
  714. * data_device_enable() - enable the device for buffered dumping
  715. * @priv: the driver's private data structure
  716. *
  717. * Enable the device for buffered dumping. Allocates buffers and hooks up
  718. * the interrupt handler. When this finishes, data will come pouring in.
  719. *
  720. * LOCKING: must hold dev->mutex
  721. * CONTEXT: user context only
  722. *
  723. * Returns 0 on success, -ERRNO otherwise
  724. */
  725. static int data_device_enable(struct fpga_device *priv)
  726. {
  727. bool enabled;
  728. u32 val;
  729. int ret;
  730. /* multiple enables are safe: they do nothing */
  731. spin_lock_irq(&priv->lock);
  732. enabled = priv->enabled;
  733. spin_unlock_irq(&priv->lock);
  734. if (enabled)
  735. return 0;
  736. /* check that the FPGAs are programmed */
  737. val = ioread32be(priv->regs + SYS_FPGA_CONFIG_STATUS);
  738. if (!(val & (1 << 18))) {
  739. dev_err(priv->dev, "DATA-FPGAs are not enabled\n");
  740. return -ENODATA;
  741. }
  742. /* read the FPGAs to calculate the buffer size */
  743. ret = data_calculate_bufsize(priv);
  744. if (ret) {
  745. dev_err(priv->dev, "unable to calculate buffer size\n");
  746. goto out_error;
  747. }
  748. /* allocate the correlation data buffers */
  749. ret = data_alloc_buffers(priv);
  750. if (ret) {
  751. dev_err(priv->dev, "unable to allocate buffers\n");
  752. goto out_error;
  753. }
  754. /* setup the source scatterlist for dumping correlation data */
  755. ret = data_setup_corl_table(priv);
  756. if (ret) {
  757. dev_err(priv->dev, "unable to setup correlation DMA table\n");
  758. goto out_error;
  759. }
  760. /* prevent the FPGAs from generating interrupts */
  761. data_disable_interrupts(priv);
  762. /* hookup the irq handler */
  763. ret = request_irq(priv->irq, data_irq, IRQF_SHARED, drv_name, priv);
  764. if (ret) {
  765. dev_err(priv->dev, "unable to request IRQ handler\n");
  766. goto out_error;
  767. }
  768. /* allow the DMA callback to re-enable FPGA interrupts */
  769. spin_lock_irq(&priv->lock);
  770. priv->enabled = true;
  771. spin_unlock_irq(&priv->lock);
  772. /* allow the FPGAs to generate interrupts */
  773. data_enable_interrupts(priv);
  774. return 0;
  775. out_error:
  776. sg_free_table(&priv->corl_table);
  777. priv->corl_nents = 0;
  778. data_free_buffers(priv);
  779. return ret;
  780. }
  781. /**
  782. * data_device_disable() - disable the device for buffered dumping
  783. * @priv: the driver's private data structure
  784. *
  785. * Disable the device for buffered dumping. Stops new DMA transactions from
  786. * being generated, waits for all outstanding DMA to complete, and then frees
  787. * all buffers.
  788. *
  789. * LOCKING: must hold dev->mutex
  790. * CONTEXT: user only
  791. *
  792. * Returns 0 on success, -ERRNO otherwise
  793. */
  794. static int data_device_disable(struct fpga_device *priv)
  795. {
  796. spin_lock_irq(&priv->lock);
  797. /* allow multiple disable */
  798. if (!priv->enabled) {
  799. spin_unlock_irq(&priv->lock);
  800. return 0;
  801. }
  802. /*
  803. * Mark the device disabled
  804. *
  805. * This stops DMA callbacks from re-enabling interrupts
  806. */
  807. priv->enabled = false;
  808. /* prevent the FPGAs from generating interrupts */
  809. data_disable_interrupts(priv);
  810. /* wait until all ongoing DMA has finished */
  811. while (priv->inflight != NULL) {
  812. spin_unlock_irq(&priv->lock);
  813. wait_event(priv->wait, priv->inflight == NULL);
  814. spin_lock_irq(&priv->lock);
  815. }
  816. spin_unlock_irq(&priv->lock);
  817. /* unhook the irq handler */
  818. free_irq(priv->irq, priv);
  819. /* free the correlation table */
  820. sg_free_table(&priv->corl_table);
  821. priv->corl_nents = 0;
  822. /* free all buffers: the free and used lists are not being changed */
  823. data_free_buffers(priv);
  824. return 0;
  825. }
  826. /*
  827. * DEBUGFS Interface
  828. */
  829. #ifdef CONFIG_DEBUG_FS
  830. /*
  831. * Count the number of entries in the given list
  832. */
  833. static unsigned int list_num_entries(struct list_head *list)
  834. {
  835. struct list_head *entry;
  836. unsigned int ret = 0;
  837. list_for_each(entry, list)
  838. ret++;
  839. return ret;
  840. }
  841. static int data_debug_show(struct seq_file *f, void *offset)
  842. {
  843. struct fpga_device *priv = f->private;
  844. spin_lock_irq(&priv->lock);
  845. seq_printf(f, "enabled: %d\n", priv->enabled);
  846. seq_printf(f, "bufsize: %d\n", priv->bufsize);
  847. seq_printf(f, "num_buffers: %d\n", priv->num_buffers);
  848. seq_printf(f, "num_free: %d\n", list_num_entries(&priv->free));
  849. seq_printf(f, "inflight: %d\n", priv->inflight != NULL);
  850. seq_printf(f, "num_used: %d\n", list_num_entries(&priv->used));
  851. seq_printf(f, "num_dropped: %d\n", priv->num_dropped);
  852. spin_unlock_irq(&priv->lock);
  853. return 0;
  854. }
  855. static int data_debug_open(struct inode *inode, struct file *file)
  856. {
  857. return single_open(file, data_debug_show, inode->i_private);
  858. }
  859. static const struct file_operations data_debug_fops = {
  860. .owner = THIS_MODULE,
  861. .open = data_debug_open,
  862. .read = seq_read,
  863. .llseek = seq_lseek,
  864. .release = single_release,
  865. };
  866. static int data_debugfs_init(struct fpga_device *priv)
  867. {
  868. priv->dbg_entry = debugfs_create_file(drv_name, S_IRUGO, NULL, priv,
  869. &data_debug_fops);
  870. return PTR_ERR_OR_ZERO(priv->dbg_entry);
  871. }
  872. static void data_debugfs_exit(struct fpga_device *priv)
  873. {
  874. debugfs_remove(priv->dbg_entry);
  875. }
  876. #else
  877. static inline int data_debugfs_init(struct fpga_device *priv)
  878. {
  879. return 0;
  880. }
  881. static inline void data_debugfs_exit(struct fpga_device *priv)
  882. {
  883. }
  884. #endif /* CONFIG_DEBUG_FS */
  885. /*
  886. * SYSFS Attributes
  887. */
  888. static ssize_t data_en_show(struct device *dev, struct device_attribute *attr,
  889. char *buf)
  890. {
  891. struct fpga_device *priv = dev_get_drvdata(dev);
  892. int ret;
  893. spin_lock_irq(&priv->lock);
  894. ret = snprintf(buf, PAGE_SIZE, "%u\n", priv->enabled);
  895. spin_unlock_irq(&priv->lock);
  896. return ret;
  897. }
  898. static ssize_t data_en_set(struct device *dev, struct device_attribute *attr,
  899. const char *buf, size_t count)
  900. {
  901. struct fpga_device *priv = dev_get_drvdata(dev);
  902. unsigned long enable;
  903. int ret;
  904. ret = kstrtoul(buf, 0, &enable);
  905. if (ret) {
  906. dev_err(priv->dev, "unable to parse enable input\n");
  907. return ret;
  908. }
  909. /* protect against concurrent enable/disable */
  910. ret = mutex_lock_interruptible(&priv->mutex);
  911. if (ret)
  912. return ret;
  913. if (enable)
  914. ret = data_device_enable(priv);
  915. else
  916. ret = data_device_disable(priv);
  917. if (ret) {
  918. dev_err(priv->dev, "device %s failed\n",
  919. enable ? "enable" : "disable");
  920. count = ret;
  921. goto out_unlock;
  922. }
  923. out_unlock:
  924. mutex_unlock(&priv->mutex);
  925. return count;
  926. }
  927. static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO, data_en_show, data_en_set);
  928. static struct attribute *data_sysfs_attrs[] = {
  929. &dev_attr_enable.attr,
  930. NULL,
  931. };
  932. static const struct attribute_group rt_sysfs_attr_group = {
  933. .attrs = data_sysfs_attrs,
  934. };
  935. /*
  936. * FPGA Realtime Data Character Device
  937. */
  938. static int data_open(struct inode *inode, struct file *filp)
  939. {
  940. /*
  941. * The miscdevice layer puts our struct miscdevice into the
  942. * filp->private_data field. We use this to find our private
  943. * data and then overwrite it with our own private structure.
  944. */
  945. struct fpga_device *priv = container_of(filp->private_data,
  946. struct fpga_device, miscdev);
  947. struct fpga_reader *reader;
  948. int ret;
  949. /* allocate private data */
  950. reader = kzalloc(sizeof(*reader), GFP_KERNEL);
  951. if (!reader)
  952. return -ENOMEM;
  953. reader->priv = priv;
  954. reader->buf = NULL;
  955. filp->private_data = reader;
  956. ret = nonseekable_open(inode, filp);
  957. if (ret) {
  958. dev_err(priv->dev, "nonseekable-open failed\n");
  959. kfree(reader);
  960. return ret;
  961. }
  962. /*
  963. * success, increase the reference count of the private data structure
  964. * so that it doesn't disappear if the device is unbound
  965. */
  966. kref_get(&priv->ref);
  967. return 0;
  968. }
  969. static int data_release(struct inode *inode, struct file *filp)
  970. {
  971. struct fpga_reader *reader = filp->private_data;
  972. struct fpga_device *priv = reader->priv;
  973. /* free the per-reader structure */
  974. data_free_buffer(reader->buf);
  975. kfree(reader);
  976. filp->private_data = NULL;
  977. /* decrement our reference count to the private data */
  978. kref_put(&priv->ref, fpga_device_release);
  979. return 0;
  980. }
  981. static ssize_t data_read(struct file *filp, char __user *ubuf, size_t count,
  982. loff_t *f_pos)
  983. {
  984. struct fpga_reader *reader = filp->private_data;
  985. struct fpga_device *priv = reader->priv;
  986. struct list_head *used = &priv->used;
  987. bool drop_buffer = false;
  988. struct data_buf *dbuf;
  989. size_t avail;
  990. void *data;
  991. int ret;
  992. /* check if we already have a partial buffer */
  993. if (reader->buf) {
  994. dbuf = reader->buf;
  995. goto have_buffer;
  996. }
  997. spin_lock_irq(&priv->lock);
  998. /* Block until there is at least one buffer on the used list */
  999. while (list_empty(used)) {
  1000. spin_unlock_irq(&priv->lock);
  1001. if (filp->f_flags & O_NONBLOCK)
  1002. return -EAGAIN;
  1003. ret = wait_event_interruptible(priv->wait, !list_empty(used));
  1004. if (ret)
  1005. return ret;
  1006. spin_lock_irq(&priv->lock);
  1007. }
  1008. /* Grab the first buffer off of the used list */
  1009. dbuf = list_first_entry(used, struct data_buf, entry);
  1010. list_del_init(&dbuf->entry);
  1011. spin_unlock_irq(&priv->lock);
  1012. /* Buffers are always mapped: unmap it */
  1013. carma_dma_unmap(priv->dev, dbuf);
  1014. /* save the buffer for later */
  1015. reader->buf = dbuf;
  1016. reader->buf_start = 0;
  1017. have_buffer:
  1018. /* Get the number of bytes available */
  1019. avail = dbuf->size - reader->buf_start;
  1020. data = dbuf->vaddr + reader->buf_start;
  1021. /* Get the number of bytes we can transfer */
  1022. count = min(count, avail);
  1023. /* Copy the data to the userspace buffer */
  1024. if (copy_to_user(ubuf, data, count))
  1025. return -EFAULT;
  1026. /* Update the amount of available space */
  1027. avail -= count;
  1028. /*
  1029. * If there is still some data available, save the buffer for the
  1030. * next userspace call to read() and return
  1031. */
  1032. if (avail > 0) {
  1033. reader->buf_start += count;
  1034. reader->buf = dbuf;
  1035. return count;
  1036. }
  1037. /*
  1038. * Get the buffer ready to be reused for DMA
  1039. *
  1040. * If it fails, we pretend that the read never happed and return
  1041. * -EFAULT to userspace. The read will be retried.
  1042. */
  1043. ret = carma_dma_map(priv->dev, dbuf);
  1044. if (ret) {
  1045. dev_err(priv->dev, "unable to remap buffer for DMA\n");
  1046. return -EFAULT;
  1047. }
  1048. /* Lock against concurrent enable/disable */
  1049. spin_lock_irq(&priv->lock);
  1050. /* the reader is finished with this buffer */
  1051. reader->buf = NULL;
  1052. /*
  1053. * One of two things has happened, the device is disabled, or the
  1054. * device has been reconfigured underneath us. In either case, we
  1055. * should just throw away the buffer.
  1056. *
  1057. * Lockdep complains if this is done under the spinlock, so we
  1058. * handle it during the unlock path.
  1059. */
  1060. if (!priv->enabled || dbuf->size != priv->bufsize) {
  1061. drop_buffer = true;
  1062. goto out_unlock;
  1063. }
  1064. /* The buffer is safe to reuse, so add it back to the free list */
  1065. list_add_tail(&dbuf->entry, &priv->free);
  1066. out_unlock:
  1067. spin_unlock_irq(&priv->lock);
  1068. if (drop_buffer) {
  1069. carma_dma_unmap(priv->dev, dbuf);
  1070. data_free_buffer(dbuf);
  1071. }
  1072. return count;
  1073. }
  1074. static unsigned int data_poll(struct file *filp, struct poll_table_struct *tbl)
  1075. {
  1076. struct fpga_reader *reader = filp->private_data;
  1077. struct fpga_device *priv = reader->priv;
  1078. unsigned int mask = 0;
  1079. poll_wait(filp, &priv->wait, tbl);
  1080. if (!list_empty(&priv->used))
  1081. mask |= POLLIN | POLLRDNORM;
  1082. return mask;
  1083. }
  1084. static int data_mmap(struct file *filp, struct vm_area_struct *vma)
  1085. {
  1086. struct fpga_reader *reader = filp->private_data;
  1087. struct fpga_device *priv = reader->priv;
  1088. unsigned long offset, vsize, psize, addr;
  1089. /* VMA properties */
  1090. offset = vma->vm_pgoff << PAGE_SHIFT;
  1091. vsize = vma->vm_end - vma->vm_start;
  1092. psize = priv->phys_size - offset;
  1093. addr = (priv->phys_addr + offset) >> PAGE_SHIFT;
  1094. /* Check against the FPGA region's physical memory size */
  1095. if (vsize > psize) {
  1096. dev_err(priv->dev, "requested mmap mapping too large\n");
  1097. return -EINVAL;
  1098. }
  1099. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1100. return io_remap_pfn_range(vma, vma->vm_start, addr, vsize,
  1101. vma->vm_page_prot);
  1102. }
  1103. static const struct file_operations data_fops = {
  1104. .owner = THIS_MODULE,
  1105. .open = data_open,
  1106. .release = data_release,
  1107. .read = data_read,
  1108. .poll = data_poll,
  1109. .mmap = data_mmap,
  1110. .llseek = no_llseek,
  1111. };
  1112. /*
  1113. * OpenFirmware Device Subsystem
  1114. */
  1115. static bool dma_filter(struct dma_chan *chan, void *data)
  1116. {
  1117. /*
  1118. * DMA Channel #0 is used for the FPGA Programmer, so ignore it
  1119. *
  1120. * This probably won't survive an unload/load cycle of the Freescale
  1121. * DMAEngine driver, but that won't be a problem
  1122. */
  1123. if (chan->chan_id == 0 && chan->device->dev_id == 0)
  1124. return false;
  1125. return true;
  1126. }
  1127. static int data_of_probe(struct platform_device *op)
  1128. {
  1129. struct device_node *of_node = op->dev.of_node;
  1130. struct device *this_device;
  1131. struct fpga_device *priv;
  1132. struct resource res;
  1133. dma_cap_mask_t mask;
  1134. int ret;
  1135. /* Allocate private data */
  1136. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  1137. if (!priv) {
  1138. dev_err(&op->dev, "Unable to allocate device private data\n");
  1139. ret = -ENOMEM;
  1140. goto out_return;
  1141. }
  1142. platform_set_drvdata(op, priv);
  1143. priv->dev = &op->dev;
  1144. kref_init(&priv->ref);
  1145. mutex_init(&priv->mutex);
  1146. dev_set_drvdata(priv->dev, priv);
  1147. spin_lock_init(&priv->lock);
  1148. INIT_LIST_HEAD(&priv->free);
  1149. INIT_LIST_HEAD(&priv->used);
  1150. init_waitqueue_head(&priv->wait);
  1151. /* Setup the misc device */
  1152. priv->miscdev.minor = MISC_DYNAMIC_MINOR;
  1153. priv->miscdev.name = drv_name;
  1154. priv->miscdev.fops = &data_fops;
  1155. /* Get the physical address of the FPGA registers */
  1156. ret = of_address_to_resource(of_node, 0, &res);
  1157. if (ret) {
  1158. dev_err(&op->dev, "Unable to find FPGA physical address\n");
  1159. ret = -ENODEV;
  1160. goto out_free_priv;
  1161. }
  1162. priv->phys_addr = res.start;
  1163. priv->phys_size = resource_size(&res);
  1164. /* ioremap the registers for use */
  1165. priv->regs = of_iomap(of_node, 0);
  1166. if (!priv->regs) {
  1167. dev_err(&op->dev, "Unable to ioremap registers\n");
  1168. ret = -ENOMEM;
  1169. goto out_free_priv;
  1170. }
  1171. dma_cap_zero(mask);
  1172. dma_cap_set(DMA_MEMCPY, mask);
  1173. dma_cap_set(DMA_INTERRUPT, mask);
  1174. dma_cap_set(DMA_SLAVE, mask);
  1175. dma_cap_set(DMA_SG, mask);
  1176. /* Request a DMA channel */
  1177. priv->chan = dma_request_channel(mask, dma_filter, NULL);
  1178. if (!priv->chan) {
  1179. dev_err(&op->dev, "Unable to request DMA channel\n");
  1180. ret = -ENODEV;
  1181. goto out_unmap_regs;
  1182. }
  1183. /* Find the correct IRQ number */
  1184. priv->irq = irq_of_parse_and_map(of_node, 0);
  1185. if (priv->irq == NO_IRQ) {
  1186. dev_err(&op->dev, "Unable to find IRQ line\n");
  1187. ret = -ENODEV;
  1188. goto out_release_dma;
  1189. }
  1190. /* Drive the GPIO for FPGA IRQ high (no interrupt) */
  1191. iowrite32be(IRQ_CORL_DONE, priv->regs + SYS_IRQ_OUTPUT_DATA);
  1192. /* Register the miscdevice */
  1193. ret = misc_register(&priv->miscdev);
  1194. if (ret) {
  1195. dev_err(&op->dev, "Unable to register miscdevice\n");
  1196. goto out_irq_dispose_mapping;
  1197. }
  1198. /* Create the debugfs files */
  1199. ret = data_debugfs_init(priv);
  1200. if (ret) {
  1201. dev_err(&op->dev, "Unable to create debugfs files\n");
  1202. goto out_misc_deregister;
  1203. }
  1204. /* Create the sysfs files */
  1205. this_device = priv->miscdev.this_device;
  1206. dev_set_drvdata(this_device, priv);
  1207. ret = sysfs_create_group(&this_device->kobj, &rt_sysfs_attr_group);
  1208. if (ret) {
  1209. dev_err(&op->dev, "Unable to create sysfs files\n");
  1210. goto out_data_debugfs_exit;
  1211. }
  1212. dev_info(&op->dev, "CARMA FPGA Realtime Data Driver Loaded\n");
  1213. return 0;
  1214. out_data_debugfs_exit:
  1215. data_debugfs_exit(priv);
  1216. out_misc_deregister:
  1217. misc_deregister(&priv->miscdev);
  1218. out_irq_dispose_mapping:
  1219. irq_dispose_mapping(priv->irq);
  1220. out_release_dma:
  1221. dma_release_channel(priv->chan);
  1222. out_unmap_regs:
  1223. iounmap(priv->regs);
  1224. out_free_priv:
  1225. kref_put(&priv->ref, fpga_device_release);
  1226. out_return:
  1227. return ret;
  1228. }
  1229. static int data_of_remove(struct platform_device *op)
  1230. {
  1231. struct fpga_device *priv = platform_get_drvdata(op);
  1232. struct device *this_device = priv->miscdev.this_device;
  1233. /* remove all sysfs files, now the device cannot be re-enabled */
  1234. sysfs_remove_group(&this_device->kobj, &rt_sysfs_attr_group);
  1235. /* remove all debugfs files */
  1236. data_debugfs_exit(priv);
  1237. /* disable the device from generating data */
  1238. data_device_disable(priv);
  1239. /* remove the character device to stop new readers from appearing */
  1240. misc_deregister(&priv->miscdev);
  1241. /* cleanup everything not needed by readers */
  1242. irq_dispose_mapping(priv->irq);
  1243. dma_release_channel(priv->chan);
  1244. iounmap(priv->regs);
  1245. /* release our reference */
  1246. kref_put(&priv->ref, fpga_device_release);
  1247. return 0;
  1248. }
  1249. static struct of_device_id data_of_match[] = {
  1250. { .compatible = "carma,carma-fpga", },
  1251. {},
  1252. };
  1253. static struct platform_driver data_of_driver = {
  1254. .probe = data_of_probe,
  1255. .remove = data_of_remove,
  1256. .driver = {
  1257. .name = drv_name,
  1258. .of_match_table = data_of_match,
  1259. },
  1260. };
  1261. module_platform_driver(data_of_driver);
  1262. MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
  1263. MODULE_DESCRIPTION("CARMA DATA-FPGA Access Driver");
  1264. MODULE_LICENSE("GPL");