uncompress.h 4.5 KB

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  1. /*
  2. * arch/arm/mach-at91/include/mach/uncompress.h
  3. *
  4. * Copyright (C) 2003 SAN People
  5. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #ifndef __ASM_ARCH_UNCOMPRESS_H
  22. #define __ASM_ARCH_UNCOMPRESS_H
  23. #include <linux/io.h>
  24. #include <linux/atmel_serial.h>
  25. #include <mach/hardware.h>
  26. #include <mach/at91_dbgu.h>
  27. #include <mach/cpu.h>
  28. void __iomem *at91_uart;
  29. static const u32 uarts_rm9200[] = {
  30. AT91_BASE_DBGU0,
  31. AT91RM9200_BASE_US0,
  32. AT91RM9200_BASE_US1,
  33. AT91RM9200_BASE_US2,
  34. AT91RM9200_BASE_US3,
  35. 0,
  36. };
  37. static const u32 uarts_sam9260[] = {
  38. AT91_BASE_DBGU0,
  39. AT91SAM9260_BASE_US0,
  40. AT91SAM9260_BASE_US1,
  41. AT91SAM9260_BASE_US2,
  42. AT91SAM9260_BASE_US3,
  43. AT91SAM9260_BASE_US4,
  44. AT91SAM9260_BASE_US5,
  45. 0,
  46. };
  47. static const u32 uarts_sam9261[] = {
  48. AT91_BASE_DBGU0,
  49. AT91SAM9261_BASE_US0,
  50. AT91SAM9261_BASE_US1,
  51. AT91SAM9261_BASE_US2,
  52. 0,
  53. };
  54. static const u32 uarts_sam9263[] = {
  55. AT91_BASE_DBGU1,
  56. AT91SAM9263_BASE_US0,
  57. AT91SAM9263_BASE_US1,
  58. AT91SAM9263_BASE_US2,
  59. 0,
  60. };
  61. static const u32 uarts_sam9g45[] = {
  62. AT91_BASE_DBGU1,
  63. AT91SAM9G45_BASE_US0,
  64. AT91SAM9G45_BASE_US1,
  65. AT91SAM9G45_BASE_US2,
  66. AT91SAM9G45_BASE_US3,
  67. 0,
  68. };
  69. static const u32 uarts_sam9rl[] = {
  70. AT91_BASE_DBGU0,
  71. AT91SAM9RL_BASE_US0,
  72. AT91SAM9RL_BASE_US1,
  73. AT91SAM9RL_BASE_US2,
  74. AT91SAM9RL_BASE_US3,
  75. 0,
  76. };
  77. static const u32 uarts_sam9x5[] = {
  78. AT91_BASE_DBGU0,
  79. AT91SAM9X5_BASE_USART0,
  80. AT91SAM9X5_BASE_USART1,
  81. AT91SAM9X5_BASE_USART2,
  82. 0,
  83. };
  84. static const u32 uarts_sama5d3[] = {
  85. AT91_BASE_DBGU1,
  86. SAMA5D3_BASE_USART0,
  87. SAMA5D3_BASE_USART1,
  88. SAMA5D3_BASE_USART2,
  89. SAMA5D3_BASE_USART3,
  90. 0,
  91. };
  92. static const u32 uarts_sama5d4[] = {
  93. AT91_BASE_DBGU2,
  94. SAMA5D4_BASE_USART3,
  95. 0,
  96. };
  97. static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
  98. {
  99. u32 cidr, socid;
  100. cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
  101. socid = cidr & ~AT91_CIDR_VERSION;
  102. switch (socid) {
  103. case ARCH_ID_AT91RM9200:
  104. return uarts_rm9200;
  105. case ARCH_ID_AT91SAM9G20:
  106. case ARCH_ID_AT91SAM9260:
  107. return uarts_sam9260;
  108. case ARCH_ID_AT91SAM9261:
  109. return uarts_sam9261;
  110. case ARCH_ID_AT91SAM9263:
  111. return uarts_sam9263;
  112. case ARCH_ID_AT91SAM9G45:
  113. return uarts_sam9g45;
  114. case ARCH_ID_AT91SAM9RL64:
  115. return uarts_sam9rl;
  116. case ARCH_ID_AT91SAM9N12:
  117. case ARCH_ID_AT91SAM9X5:
  118. return uarts_sam9x5;
  119. case ARCH_ID_SAMA5:
  120. cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
  121. if (cidr & ARCH_EXID_SAMA5D3)
  122. return uarts_sama5d3;
  123. else if (cidr & ARCH_EXID_SAMA5D4)
  124. return uarts_sama5d4;
  125. break;
  126. }
  127. /* at91sam9g10 */
  128. if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
  129. return uarts_sam9261;
  130. }
  131. /* at91sam9xe */
  132. else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
  133. return uarts_sam9260;
  134. }
  135. return NULL;
  136. }
  137. static inline void arch_decomp_setup(void)
  138. {
  139. int i = 0;
  140. const u32* usarts;
  141. usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
  142. if (!usarts)
  143. usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
  144. if (!usarts)
  145. usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
  146. if (!usarts) {
  147. at91_uart = NULL;
  148. return;
  149. }
  150. do {
  151. /* physical address */
  152. at91_uart = (void __iomem *)usarts[i];
  153. if (__raw_readl(at91_uart + ATMEL_US_BRGR))
  154. return;
  155. i++;
  156. } while (usarts[i]);
  157. at91_uart = NULL;
  158. }
  159. /*
  160. * The following code assumes the serial port has already been
  161. * initialized by the bootloader. If you didn't setup a port in
  162. * your bootloader then nothing will appear (which might be desired).
  163. *
  164. * This does not append a newline
  165. */
  166. static void putc(int c)
  167. {
  168. if (!at91_uart)
  169. return;
  170. while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
  171. barrier();
  172. __raw_writel(c, at91_uart + ATMEL_US_THR);
  173. }
  174. static inline void flush(void)
  175. {
  176. if (!at91_uart)
  177. return;
  178. /* wait for transmission to complete */
  179. while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
  180. barrier();
  181. }
  182. #endif