qeth_core_main.c 124 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554
  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include "qeth_core.h"
  24. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  25. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  26. /* N P A M L V H */
  27. [QETH_DBF_SETUP] = {"qeth_setup",
  28. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  29. [QETH_DBF_QERR] = {"qeth_qerr",
  30. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_TRACE] = {"qeth_trace",
  32. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_SENSE] = {"qeth_sense",
  36. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  37. [QETH_DBF_MISC] = {"qeth_misc",
  38. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_CTRL] = {"qeth_control",
  40. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  41. };
  42. EXPORT_SYMBOL_GPL(qeth_dbf);
  43. struct qeth_card_list_struct qeth_core_card_list;
  44. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  45. struct kmem_cache *qeth_core_header_cache;
  46. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  47. static struct device *qeth_core_root_dev;
  48. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  49. static struct lock_class_key qdio_out_skb_queue_key;
  50. static void qeth_send_control_data_cb(struct qeth_channel *,
  51. struct qeth_cmd_buffer *);
  52. static int qeth_issue_next_read(struct qeth_card *);
  53. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  54. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  55. static void qeth_free_buffer_pool(struct qeth_card *);
  56. static int qeth_qdio_establish(struct qeth_card *);
  57. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  58. struct qdio_buffer *buffer, int is_tso,
  59. int *next_element_to_fill)
  60. {
  61. struct skb_frag_struct *frag;
  62. int fragno;
  63. unsigned long addr;
  64. int element, cnt, dlen;
  65. fragno = skb_shinfo(skb)->nr_frags;
  66. element = *next_element_to_fill;
  67. dlen = 0;
  68. if (is_tso)
  69. buffer->element[element].flags =
  70. SBAL_FLAGS_MIDDLE_FRAG;
  71. else
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_FIRST_FRAG;
  74. dlen = skb->len - skb->data_len;
  75. if (dlen) {
  76. buffer->element[element].addr = skb->data;
  77. buffer->element[element].length = dlen;
  78. element++;
  79. }
  80. for (cnt = 0; cnt < fragno; cnt++) {
  81. frag = &skb_shinfo(skb)->frags[cnt];
  82. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  83. frag->page_offset;
  84. buffer->element[element].addr = (char *)addr;
  85. buffer->element[element].length = frag->size;
  86. if (cnt < (fragno - 1))
  87. buffer->element[element].flags =
  88. SBAL_FLAGS_MIDDLE_FRAG;
  89. else
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_LAST_FRAG;
  92. element++;
  93. }
  94. *next_element_to_fill = element;
  95. }
  96. static inline const char *qeth_get_cardname(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSAE:
  101. return " Guest LAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return " Guest LAN Hiper";
  104. default:
  105. return " unknown";
  106. }
  107. } else {
  108. switch (card->info.type) {
  109. case QETH_CARD_TYPE_OSAE:
  110. return " OSD Express";
  111. case QETH_CARD_TYPE_IQD:
  112. return " HiperSockets";
  113. case QETH_CARD_TYPE_OSN:
  114. return " OSN QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSAE:
  127. return "GuestLAN QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "GuestLAN Hiper";
  130. default:
  131. return "unknown";
  132. }
  133. } else {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSAE:
  136. switch (card->info.link_type) {
  137. case QETH_LINK_TYPE_FAST_ETH:
  138. return "OSD_100";
  139. case QETH_LINK_TYPE_HSTR:
  140. return "HSTR";
  141. case QETH_LINK_TYPE_GBIT_ETH:
  142. return "OSD_1000";
  143. case QETH_LINK_TYPE_10GBIT_ETH:
  144. return "OSD_10GIG";
  145. case QETH_LINK_TYPE_LANE_ETH100:
  146. return "OSD_FE_LANE";
  147. case QETH_LINK_TYPE_LANE_TR:
  148. return "OSD_TR_LANE";
  149. case QETH_LINK_TYPE_LANE_ETH1000:
  150. return "OSD_GbE_LANE";
  151. case QETH_LINK_TYPE_LANE:
  152. return "OSD_ATM_LANE";
  153. default:
  154. return "OSD_Express";
  155. }
  156. case QETH_CARD_TYPE_IQD:
  157. return "HiperSockets";
  158. case QETH_CARD_TYPE_OSN:
  159. return "OSN";
  160. default:
  161. return "unknown";
  162. }
  163. }
  164. return "n/a";
  165. }
  166. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  167. int clear_start_mask)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&card->thread_mask_lock, flags);
  171. card->thread_allowed_mask = threads;
  172. if (clear_start_mask)
  173. card->thread_start_mask &= threads;
  174. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  175. wake_up(&card->wait_q);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  178. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  179. {
  180. unsigned long flags;
  181. int rc = 0;
  182. spin_lock_irqsave(&card->thread_mask_lock, flags);
  183. rc = (card->thread_running_mask & threads);
  184. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  185. return rc;
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_threads_running);
  188. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  189. {
  190. return wait_event_interruptible(card->wait_q,
  191. qeth_threads_running(card, threads) == 0);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  194. void qeth_clear_working_pool_list(struct qeth_card *card)
  195. {
  196. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  197. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  198. list_for_each_entry_safe(pool_entry, tmp,
  199. &card->qdio.in_buf_pool.entry_list, list){
  200. list_del(&pool_entry->list);
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  204. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  205. {
  206. struct qeth_buffer_pool_entry *pool_entry;
  207. void *ptr;
  208. int i, j;
  209. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  210. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  211. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  212. if (!pool_entry) {
  213. qeth_free_buffer_pool(card);
  214. return -ENOMEM;
  215. }
  216. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  217. ptr = (void *) __get_free_page(GFP_KERNEL);
  218. if (!ptr) {
  219. while (j > 0)
  220. free_page((unsigned long)
  221. pool_entry->elements[--j]);
  222. kfree(pool_entry);
  223. qeth_free_buffer_pool(card);
  224. return -ENOMEM;
  225. }
  226. pool_entry->elements[j] = ptr;
  227. }
  228. list_add(&pool_entry->init_list,
  229. &card->qdio.init_pool.entry_list);
  230. }
  231. return 0;
  232. }
  233. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  234. {
  235. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  236. if ((card->state != CARD_STATE_DOWN) &&
  237. (card->state != CARD_STATE_RECOVER))
  238. return -EPERM;
  239. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  240. qeth_clear_working_pool_list(card);
  241. qeth_free_buffer_pool(card);
  242. card->qdio.in_buf_pool.buf_count = bufcnt;
  243. card->qdio.init_pool.buf_count = bufcnt;
  244. return qeth_alloc_buffer_pool(card);
  245. }
  246. int qeth_set_large_send(struct qeth_card *card,
  247. enum qeth_large_send_types type)
  248. {
  249. int rc = 0;
  250. if (card->dev == NULL) {
  251. card->options.large_send = type;
  252. return 0;
  253. }
  254. if (card->state == CARD_STATE_UP)
  255. netif_tx_disable(card->dev);
  256. card->options.large_send = type;
  257. switch (card->options.large_send) {
  258. case QETH_LARGE_SEND_TSO:
  259. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  260. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  261. NETIF_F_HW_CSUM;
  262. } else {
  263. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  264. NETIF_F_HW_CSUM);
  265. card->options.large_send = QETH_LARGE_SEND_NO;
  266. rc = -EOPNOTSUPP;
  267. }
  268. break;
  269. default: /* includes QETH_LARGE_SEND_NO */
  270. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  271. NETIF_F_HW_CSUM);
  272. break;
  273. }
  274. if (card->state == CARD_STATE_UP)
  275. netif_wake_queue(card->dev);
  276. return rc;
  277. }
  278. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  279. static int qeth_issue_next_read(struct qeth_card *card)
  280. {
  281. int rc;
  282. struct qeth_cmd_buffer *iob;
  283. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  284. if (card->read.state != CH_STATE_UP)
  285. return -EIO;
  286. iob = qeth_get_buffer(&card->read);
  287. if (!iob) {
  288. dev_warn(&card->gdev->dev, "The qeth device driver "
  289. "failed to recover an error on the device\n");
  290. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  291. "available\n", dev_name(&card->gdev->dev));
  292. return -ENOMEM;
  293. }
  294. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  295. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  296. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  297. (addr_t) iob, 0, 0);
  298. if (rc) {
  299. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  300. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  301. atomic_set(&card->read.irq_pending, 0);
  302. qeth_schedule_recovery(card);
  303. wake_up(&card->wait_q);
  304. }
  305. return rc;
  306. }
  307. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  308. {
  309. struct qeth_reply *reply;
  310. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  311. if (reply) {
  312. atomic_set(&reply->refcnt, 1);
  313. atomic_set(&reply->received, 0);
  314. reply->card = card;
  315. };
  316. return reply;
  317. }
  318. static void qeth_get_reply(struct qeth_reply *reply)
  319. {
  320. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  321. atomic_inc(&reply->refcnt);
  322. }
  323. static void qeth_put_reply(struct qeth_reply *reply)
  324. {
  325. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  326. if (atomic_dec_and_test(&reply->refcnt))
  327. kfree(reply);
  328. }
  329. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  330. struct qeth_card *card)
  331. {
  332. char *ipa_name;
  333. int com = cmd->hdr.command;
  334. ipa_name = qeth_get_ipa_cmd_name(com);
  335. if (rc)
  336. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  337. ipa_name, com, QETH_CARD_IFNAME(card),
  338. rc, qeth_get_ipa_msg(rc));
  339. else
  340. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  341. ipa_name, com, QETH_CARD_IFNAME(card));
  342. }
  343. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  344. struct qeth_cmd_buffer *iob)
  345. {
  346. struct qeth_ipa_cmd *cmd = NULL;
  347. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  348. if (IS_IPA(iob->data)) {
  349. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  350. if (IS_IPA_REPLY(cmd)) {
  351. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  352. cmd->hdr.command > IPA_CMD_MODCCID)
  353. qeth_issue_ipa_msg(cmd,
  354. cmd->hdr.return_code, card);
  355. return cmd;
  356. } else {
  357. switch (cmd->hdr.command) {
  358. case IPA_CMD_STOPLAN:
  359. dev_warn(&card->gdev->dev,
  360. "The link for interface %s on CHPID"
  361. " 0x%X failed\n",
  362. QETH_CARD_IFNAME(card),
  363. card->info.chpid);
  364. card->lan_online = 0;
  365. if (card->dev && netif_carrier_ok(card->dev))
  366. netif_carrier_off(card->dev);
  367. return NULL;
  368. case IPA_CMD_STARTLAN:
  369. dev_info(&card->gdev->dev,
  370. "The link for %s on CHPID 0x%X has"
  371. " been restored\n",
  372. QETH_CARD_IFNAME(card),
  373. card->info.chpid);
  374. netif_carrier_on(card->dev);
  375. card->lan_online = 1;
  376. qeth_schedule_recovery(card);
  377. return NULL;
  378. case IPA_CMD_MODCCID:
  379. return cmd;
  380. case IPA_CMD_REGISTER_LOCAL_ADDR:
  381. QETH_DBF_TEXT(TRACE, 3, "irla");
  382. break;
  383. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  384. QETH_DBF_TEXT(TRACE, 3, "urla");
  385. break;
  386. default:
  387. QETH_DBF_MESSAGE(2, "Received data is IPA "
  388. "but not a reply!\n");
  389. break;
  390. }
  391. }
  392. }
  393. return cmd;
  394. }
  395. void qeth_clear_ipacmd_list(struct qeth_card *card)
  396. {
  397. struct qeth_reply *reply, *r;
  398. unsigned long flags;
  399. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  400. spin_lock_irqsave(&card->lock, flags);
  401. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  402. qeth_get_reply(reply);
  403. reply->rc = -EIO;
  404. atomic_inc(&reply->received);
  405. list_del_init(&reply->list);
  406. wake_up(&reply->wait_q);
  407. qeth_put_reply(reply);
  408. }
  409. spin_unlock_irqrestore(&card->lock, flags);
  410. }
  411. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  412. static int qeth_check_idx_response(unsigned char *buffer)
  413. {
  414. if (!buffer)
  415. return 0;
  416. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  417. if ((buffer[2] & 0xc0) == 0xc0) {
  418. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  419. "with cause code 0x%02x%s\n",
  420. buffer[4],
  421. ((buffer[4] == 0x22) ?
  422. " -- try another portname" : ""));
  423. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  424. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  425. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  426. return -EIO;
  427. }
  428. return 0;
  429. }
  430. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  431. __u32 len)
  432. {
  433. struct qeth_card *card;
  434. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  435. card = CARD_FROM_CDEV(channel->ccwdev);
  436. if (channel == &card->read)
  437. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  438. else
  439. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  440. channel->ccw.count = len;
  441. channel->ccw.cda = (__u32) __pa(iob);
  442. }
  443. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. __u8 index;
  446. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  447. index = channel->io_buf_no;
  448. do {
  449. if (channel->iob[index].state == BUF_STATE_FREE) {
  450. channel->iob[index].state = BUF_STATE_LOCKED;
  451. channel->io_buf_no = (channel->io_buf_no + 1) %
  452. QETH_CMD_BUFFER_NO;
  453. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  454. return channel->iob + index;
  455. }
  456. index = (index + 1) % QETH_CMD_BUFFER_NO;
  457. } while (index != channel->io_buf_no);
  458. return NULL;
  459. }
  460. void qeth_release_buffer(struct qeth_channel *channel,
  461. struct qeth_cmd_buffer *iob)
  462. {
  463. unsigned long flags;
  464. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  465. spin_lock_irqsave(&channel->iob_lock, flags);
  466. memset(iob->data, 0, QETH_BUFSIZE);
  467. iob->state = BUF_STATE_FREE;
  468. iob->callback = qeth_send_control_data_cb;
  469. iob->rc = 0;
  470. spin_unlock_irqrestore(&channel->iob_lock, flags);
  471. }
  472. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  473. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  474. {
  475. struct qeth_cmd_buffer *buffer = NULL;
  476. unsigned long flags;
  477. spin_lock_irqsave(&channel->iob_lock, flags);
  478. buffer = __qeth_get_buffer(channel);
  479. spin_unlock_irqrestore(&channel->iob_lock, flags);
  480. return buffer;
  481. }
  482. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  483. {
  484. struct qeth_cmd_buffer *buffer;
  485. wait_event(channel->wait_q,
  486. ((buffer = qeth_get_buffer(channel)) != NULL));
  487. return buffer;
  488. }
  489. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  490. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  491. {
  492. int cnt;
  493. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  494. qeth_release_buffer(channel, &channel->iob[cnt]);
  495. channel->buf_no = 0;
  496. channel->io_buf_no = 0;
  497. }
  498. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  499. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  500. struct qeth_cmd_buffer *iob)
  501. {
  502. struct qeth_card *card;
  503. struct qeth_reply *reply, *r;
  504. struct qeth_ipa_cmd *cmd;
  505. unsigned long flags;
  506. int keep_reply;
  507. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  508. card = CARD_FROM_CDEV(channel->ccwdev);
  509. if (qeth_check_idx_response(iob->data)) {
  510. qeth_clear_ipacmd_list(card);
  511. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  512. dev_err(&card->gdev->dev,
  513. "The qeth device is not configured "
  514. "for the OSI layer required by z/VM\n");
  515. qeth_schedule_recovery(card);
  516. goto out;
  517. }
  518. cmd = qeth_check_ipa_data(card, iob);
  519. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  520. goto out;
  521. /*in case of OSN : check if cmd is set */
  522. if (card->info.type == QETH_CARD_TYPE_OSN &&
  523. cmd &&
  524. cmd->hdr.command != IPA_CMD_STARTLAN &&
  525. card->osn_info.assist_cb != NULL) {
  526. card->osn_info.assist_cb(card->dev, cmd);
  527. goto out;
  528. }
  529. spin_lock_irqsave(&card->lock, flags);
  530. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  531. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  532. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  533. qeth_get_reply(reply);
  534. list_del_init(&reply->list);
  535. spin_unlock_irqrestore(&card->lock, flags);
  536. keep_reply = 0;
  537. if (reply->callback != NULL) {
  538. if (cmd) {
  539. reply->offset = (__u16)((char *)cmd -
  540. (char *)iob->data);
  541. keep_reply = reply->callback(card,
  542. reply,
  543. (unsigned long)cmd);
  544. } else
  545. keep_reply = reply->callback(card,
  546. reply,
  547. (unsigned long)iob);
  548. }
  549. if (cmd)
  550. reply->rc = (u16) cmd->hdr.return_code;
  551. else if (iob->rc)
  552. reply->rc = iob->rc;
  553. if (keep_reply) {
  554. spin_lock_irqsave(&card->lock, flags);
  555. list_add_tail(&reply->list,
  556. &card->cmd_waiter_list);
  557. spin_unlock_irqrestore(&card->lock, flags);
  558. } else {
  559. atomic_inc(&reply->received);
  560. wake_up(&reply->wait_q);
  561. }
  562. qeth_put_reply(reply);
  563. goto out;
  564. }
  565. }
  566. spin_unlock_irqrestore(&card->lock, flags);
  567. out:
  568. memcpy(&card->seqno.pdu_hdr_ack,
  569. QETH_PDU_HEADER_SEQ_NO(iob->data),
  570. QETH_SEQ_NO_LENGTH);
  571. qeth_release_buffer(channel, iob);
  572. }
  573. static int qeth_setup_channel(struct qeth_channel *channel)
  574. {
  575. int cnt;
  576. QETH_DBF_TEXT(SETUP, 2, "setupch");
  577. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  578. channel->iob[cnt].data = (char *)
  579. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  580. if (channel->iob[cnt].data == NULL)
  581. break;
  582. channel->iob[cnt].state = BUF_STATE_FREE;
  583. channel->iob[cnt].channel = channel;
  584. channel->iob[cnt].callback = qeth_send_control_data_cb;
  585. channel->iob[cnt].rc = 0;
  586. }
  587. if (cnt < QETH_CMD_BUFFER_NO) {
  588. while (cnt-- > 0)
  589. kfree(channel->iob[cnt].data);
  590. return -ENOMEM;
  591. }
  592. channel->buf_no = 0;
  593. channel->io_buf_no = 0;
  594. atomic_set(&channel->irq_pending, 0);
  595. spin_lock_init(&channel->iob_lock);
  596. init_waitqueue_head(&channel->wait_q);
  597. return 0;
  598. }
  599. static int qeth_set_thread_start_bit(struct qeth_card *card,
  600. unsigned long thread)
  601. {
  602. unsigned long flags;
  603. spin_lock_irqsave(&card->thread_mask_lock, flags);
  604. if (!(card->thread_allowed_mask & thread) ||
  605. (card->thread_start_mask & thread)) {
  606. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  607. return -EPERM;
  608. }
  609. card->thread_start_mask |= thread;
  610. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  611. return 0;
  612. }
  613. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  614. {
  615. unsigned long flags;
  616. spin_lock_irqsave(&card->thread_mask_lock, flags);
  617. card->thread_start_mask &= ~thread;
  618. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  619. wake_up(&card->wait_q);
  620. }
  621. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  622. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  623. {
  624. unsigned long flags;
  625. spin_lock_irqsave(&card->thread_mask_lock, flags);
  626. card->thread_running_mask &= ~thread;
  627. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  628. wake_up(&card->wait_q);
  629. }
  630. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  631. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  632. {
  633. unsigned long flags;
  634. int rc = 0;
  635. spin_lock_irqsave(&card->thread_mask_lock, flags);
  636. if (card->thread_start_mask & thread) {
  637. if ((card->thread_allowed_mask & thread) &&
  638. !(card->thread_running_mask & thread)) {
  639. rc = 1;
  640. card->thread_start_mask &= ~thread;
  641. card->thread_running_mask |= thread;
  642. } else
  643. rc = -EPERM;
  644. }
  645. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  646. return rc;
  647. }
  648. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  649. {
  650. int rc = 0;
  651. wait_event(card->wait_q,
  652. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  653. return rc;
  654. }
  655. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  656. void qeth_schedule_recovery(struct qeth_card *card)
  657. {
  658. QETH_DBF_TEXT(TRACE, 2, "startrec");
  659. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  660. schedule_work(&card->kernel_thread_starter);
  661. }
  662. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  663. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  664. {
  665. int dstat, cstat;
  666. char *sense;
  667. sense = (char *) irb->ecw;
  668. cstat = irb->scsw.cmd.cstat;
  669. dstat = irb->scsw.cmd.dstat;
  670. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  671. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  672. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  673. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  674. dev_warn(&cdev->dev, "The qeth device driver "
  675. "failed to recover an error on the device\n");
  676. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  677. dev_name(&cdev->dev), dstat, cstat);
  678. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  679. 16, 1, irb, 64, 1);
  680. return 1;
  681. }
  682. if (dstat & DEV_STAT_UNIT_CHECK) {
  683. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  684. SENSE_RESETTING_EVENT_FLAG) {
  685. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  686. return 1;
  687. }
  688. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  689. SENSE_COMMAND_REJECT_FLAG) {
  690. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  691. return 1;
  692. }
  693. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  694. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  695. return 1;
  696. }
  697. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  698. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  699. return 0;
  700. }
  701. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  702. return 1;
  703. }
  704. return 0;
  705. }
  706. static long __qeth_check_irb_error(struct ccw_device *cdev,
  707. unsigned long intparm, struct irb *irb)
  708. {
  709. if (!IS_ERR(irb))
  710. return 0;
  711. switch (PTR_ERR(irb)) {
  712. case -EIO:
  713. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  714. dev_name(&cdev->dev));
  715. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  716. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  717. break;
  718. case -ETIMEDOUT:
  719. dev_warn(&cdev->dev, "A hardware operation timed out"
  720. " on the device\n");
  721. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  722. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  723. if (intparm == QETH_RCD_PARM) {
  724. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  725. if (card && (card->data.ccwdev == cdev)) {
  726. card->data.state = CH_STATE_DOWN;
  727. wake_up(&card->wait_q);
  728. }
  729. }
  730. break;
  731. default:
  732. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  733. dev_name(&cdev->dev), PTR_ERR(irb));
  734. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  735. QETH_DBF_TEXT(TRACE, 2, " rc???");
  736. }
  737. return PTR_ERR(irb);
  738. }
  739. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  740. struct irb *irb)
  741. {
  742. int rc;
  743. int cstat, dstat;
  744. struct qeth_cmd_buffer *buffer;
  745. struct qeth_channel *channel;
  746. struct qeth_card *card;
  747. struct qeth_cmd_buffer *iob;
  748. __u8 index;
  749. QETH_DBF_TEXT(TRACE, 5, "irq");
  750. if (__qeth_check_irb_error(cdev, intparm, irb))
  751. return;
  752. cstat = irb->scsw.cmd.cstat;
  753. dstat = irb->scsw.cmd.dstat;
  754. card = CARD_FROM_CDEV(cdev);
  755. if (!card)
  756. return;
  757. if (card->read.ccwdev == cdev) {
  758. channel = &card->read;
  759. QETH_DBF_TEXT(TRACE, 5, "read");
  760. } else if (card->write.ccwdev == cdev) {
  761. channel = &card->write;
  762. QETH_DBF_TEXT(TRACE, 5, "write");
  763. } else {
  764. channel = &card->data;
  765. QETH_DBF_TEXT(TRACE, 5, "data");
  766. }
  767. atomic_set(&channel->irq_pending, 0);
  768. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  769. channel->state = CH_STATE_STOPPED;
  770. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  771. channel->state = CH_STATE_HALTED;
  772. /*let's wake up immediately on data channel*/
  773. if ((channel == &card->data) && (intparm != 0) &&
  774. (intparm != QETH_RCD_PARM))
  775. goto out;
  776. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  777. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  778. /* we don't have to handle this further */
  779. intparm = 0;
  780. }
  781. if (intparm == QETH_HALT_CHANNEL_PARM) {
  782. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  783. /* we don't have to handle this further */
  784. intparm = 0;
  785. }
  786. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  787. (dstat & DEV_STAT_UNIT_CHECK) ||
  788. (cstat)) {
  789. if (irb->esw.esw0.erw.cons) {
  790. dev_warn(&channel->ccwdev->dev,
  791. "The qeth device driver failed to recover "
  792. "an error on the device\n");
  793. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  794. "0x%X dstat 0x%X\n",
  795. dev_name(&channel->ccwdev->dev), cstat, dstat);
  796. print_hex_dump(KERN_WARNING, "qeth: irb ",
  797. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  798. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  799. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  800. }
  801. if (intparm == QETH_RCD_PARM) {
  802. channel->state = CH_STATE_DOWN;
  803. goto out;
  804. }
  805. rc = qeth_get_problem(cdev, irb);
  806. if (rc) {
  807. qeth_clear_ipacmd_list(card);
  808. qeth_schedule_recovery(card);
  809. goto out;
  810. }
  811. }
  812. if (intparm == QETH_RCD_PARM) {
  813. channel->state = CH_STATE_RCD_DONE;
  814. goto out;
  815. }
  816. if (intparm) {
  817. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  818. buffer->state = BUF_STATE_PROCESSED;
  819. }
  820. if (channel == &card->data)
  821. return;
  822. if (channel == &card->read &&
  823. channel->state == CH_STATE_UP)
  824. qeth_issue_next_read(card);
  825. iob = channel->iob;
  826. index = channel->buf_no;
  827. while (iob[index].state == BUF_STATE_PROCESSED) {
  828. if (iob[index].callback != NULL)
  829. iob[index].callback(channel, iob + index);
  830. index = (index + 1) % QETH_CMD_BUFFER_NO;
  831. }
  832. channel->buf_no = index;
  833. out:
  834. wake_up(&card->wait_q);
  835. return;
  836. }
  837. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  838. struct qeth_qdio_out_buffer *buf)
  839. {
  840. int i;
  841. struct sk_buff *skb;
  842. /* is PCI flag set on buffer? */
  843. if (buf->buffer->element[0].flags & 0x40)
  844. atomic_dec(&queue->set_pci_flags_count);
  845. skb = skb_dequeue(&buf->skb_list);
  846. while (skb) {
  847. atomic_dec(&skb->users);
  848. dev_kfree_skb_any(skb);
  849. skb = skb_dequeue(&buf->skb_list);
  850. }
  851. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  852. if (buf->buffer->element[i].addr && buf->is_header[i])
  853. kmem_cache_free(qeth_core_header_cache,
  854. buf->buffer->element[i].addr);
  855. buf->is_header[i] = 0;
  856. buf->buffer->element[i].length = 0;
  857. buf->buffer->element[i].addr = NULL;
  858. buf->buffer->element[i].flags = 0;
  859. }
  860. buf->buffer->element[15].flags = 0;
  861. buf->next_element_to_fill = 0;
  862. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  863. }
  864. void qeth_clear_qdio_buffers(struct qeth_card *card)
  865. {
  866. int i, j;
  867. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  868. /* clear outbound buffers to free skbs */
  869. for (i = 0; i < card->qdio.no_out_queues; ++i)
  870. if (card->qdio.out_qs[i]) {
  871. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  872. qeth_clear_output_buffer(card->qdio.out_qs[i],
  873. &card->qdio.out_qs[i]->bufs[j]);
  874. }
  875. }
  876. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  877. static void qeth_free_buffer_pool(struct qeth_card *card)
  878. {
  879. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  880. int i = 0;
  881. QETH_DBF_TEXT(TRACE, 5, "freepool");
  882. list_for_each_entry_safe(pool_entry, tmp,
  883. &card->qdio.init_pool.entry_list, init_list){
  884. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  885. free_page((unsigned long)pool_entry->elements[i]);
  886. list_del(&pool_entry->init_list);
  887. kfree(pool_entry);
  888. }
  889. }
  890. static void qeth_free_qdio_buffers(struct qeth_card *card)
  891. {
  892. int i, j;
  893. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  894. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  895. QETH_QDIO_UNINITIALIZED)
  896. return;
  897. kfree(card->qdio.in_q);
  898. card->qdio.in_q = NULL;
  899. /* inbound buffer pool */
  900. qeth_free_buffer_pool(card);
  901. /* free outbound qdio_qs */
  902. if (card->qdio.out_qs) {
  903. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  904. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  905. qeth_clear_output_buffer(card->qdio.out_qs[i],
  906. &card->qdio.out_qs[i]->bufs[j]);
  907. kfree(card->qdio.out_qs[i]);
  908. }
  909. kfree(card->qdio.out_qs);
  910. card->qdio.out_qs = NULL;
  911. }
  912. }
  913. static void qeth_clean_channel(struct qeth_channel *channel)
  914. {
  915. int cnt;
  916. QETH_DBF_TEXT(SETUP, 2, "freech");
  917. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  918. kfree(channel->iob[cnt].data);
  919. }
  920. static int qeth_is_1920_device(struct qeth_card *card)
  921. {
  922. int single_queue = 0;
  923. struct ccw_device *ccwdev;
  924. struct channelPath_dsc {
  925. u8 flags;
  926. u8 lsn;
  927. u8 desc;
  928. u8 chpid;
  929. u8 swla;
  930. u8 zeroes;
  931. u8 chla;
  932. u8 chpp;
  933. } *chp_dsc;
  934. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  935. ccwdev = card->data.ccwdev;
  936. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  937. if (chp_dsc != NULL) {
  938. /* CHPP field bit 6 == 1 -> single queue */
  939. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  940. kfree(chp_dsc);
  941. }
  942. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  943. return single_queue;
  944. }
  945. static void qeth_init_qdio_info(struct qeth_card *card)
  946. {
  947. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  948. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  949. /* inbound */
  950. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  951. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  952. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  953. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  954. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  955. }
  956. static void qeth_set_intial_options(struct qeth_card *card)
  957. {
  958. card->options.route4.type = NO_ROUTER;
  959. card->options.route6.type = NO_ROUTER;
  960. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  961. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  962. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  963. card->options.fake_broadcast = 0;
  964. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  965. card->options.performance_stats = 0;
  966. card->options.rx_sg_cb = QETH_RX_SG_CB;
  967. }
  968. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  969. {
  970. unsigned long flags;
  971. int rc = 0;
  972. spin_lock_irqsave(&card->thread_mask_lock, flags);
  973. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  974. (u8) card->thread_start_mask,
  975. (u8) card->thread_allowed_mask,
  976. (u8) card->thread_running_mask);
  977. rc = (card->thread_start_mask & thread);
  978. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  979. return rc;
  980. }
  981. static void qeth_start_kernel_thread(struct work_struct *work)
  982. {
  983. struct qeth_card *card = container_of(work, struct qeth_card,
  984. kernel_thread_starter);
  985. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  986. if (card->read.state != CH_STATE_UP &&
  987. card->write.state != CH_STATE_UP)
  988. return;
  989. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  990. kthread_run(card->discipline.recover, (void *) card,
  991. "qeth_recover");
  992. }
  993. static int qeth_setup_card(struct qeth_card *card)
  994. {
  995. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  996. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  997. card->read.state = CH_STATE_DOWN;
  998. card->write.state = CH_STATE_DOWN;
  999. card->data.state = CH_STATE_DOWN;
  1000. card->state = CARD_STATE_DOWN;
  1001. card->lan_online = 0;
  1002. card->use_hard_stop = 0;
  1003. card->dev = NULL;
  1004. spin_lock_init(&card->vlanlock);
  1005. spin_lock_init(&card->mclock);
  1006. card->vlangrp = NULL;
  1007. spin_lock_init(&card->lock);
  1008. spin_lock_init(&card->ip_lock);
  1009. spin_lock_init(&card->thread_mask_lock);
  1010. card->thread_start_mask = 0;
  1011. card->thread_allowed_mask = 0;
  1012. card->thread_running_mask = 0;
  1013. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1014. INIT_LIST_HEAD(&card->ip_list);
  1015. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1016. if (!card->ip_tbd_list) {
  1017. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1018. return -ENOMEM;
  1019. }
  1020. INIT_LIST_HEAD(card->ip_tbd_list);
  1021. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1022. init_waitqueue_head(&card->wait_q);
  1023. /* intial options */
  1024. qeth_set_intial_options(card);
  1025. /* IP address takeover */
  1026. INIT_LIST_HEAD(&card->ipato.entries);
  1027. card->ipato.enabled = 0;
  1028. card->ipato.invert4 = 0;
  1029. card->ipato.invert6 = 0;
  1030. if (card->info.type == QETH_CARD_TYPE_IQD)
  1031. card->options.checksum_type = NO_CHECKSUMMING;
  1032. /* init QDIO stuff */
  1033. qeth_init_qdio_info(card);
  1034. return 0;
  1035. }
  1036. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1037. {
  1038. struct qeth_card *card = container_of(slr, struct qeth_card,
  1039. qeth_service_level);
  1040. seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
  1041. card->info.mcl_level);
  1042. }
  1043. static struct qeth_card *qeth_alloc_card(void)
  1044. {
  1045. struct qeth_card *card;
  1046. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1047. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1048. if (!card)
  1049. return NULL;
  1050. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1051. if (qeth_setup_channel(&card->read)) {
  1052. kfree(card);
  1053. return NULL;
  1054. }
  1055. if (qeth_setup_channel(&card->write)) {
  1056. qeth_clean_channel(&card->read);
  1057. kfree(card);
  1058. return NULL;
  1059. }
  1060. card->options.layer2 = -1;
  1061. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1062. register_service_level(&card->qeth_service_level);
  1063. return card;
  1064. }
  1065. static int qeth_determine_card_type(struct qeth_card *card)
  1066. {
  1067. int i = 0;
  1068. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1069. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1070. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1071. while (known_devices[i][4]) {
  1072. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1073. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1074. card->info.type = known_devices[i][4];
  1075. card->qdio.no_out_queues = known_devices[i][8];
  1076. card->info.is_multicast_different = known_devices[i][9];
  1077. if (qeth_is_1920_device(card)) {
  1078. dev_info(&card->gdev->dev,
  1079. "Priority Queueing not supported\n");
  1080. card->qdio.no_out_queues = 1;
  1081. card->qdio.default_out_queue = 0;
  1082. }
  1083. return 0;
  1084. }
  1085. i++;
  1086. }
  1087. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1088. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1089. "unknown type\n");
  1090. return -ENOENT;
  1091. }
  1092. static int qeth_clear_channel(struct qeth_channel *channel)
  1093. {
  1094. unsigned long flags;
  1095. struct qeth_card *card;
  1096. int rc;
  1097. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1098. card = CARD_FROM_CDEV(channel->ccwdev);
  1099. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1100. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1101. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1102. if (rc)
  1103. return rc;
  1104. rc = wait_event_interruptible_timeout(card->wait_q,
  1105. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1106. if (rc == -ERESTARTSYS)
  1107. return rc;
  1108. if (channel->state != CH_STATE_STOPPED)
  1109. return -ETIME;
  1110. channel->state = CH_STATE_DOWN;
  1111. return 0;
  1112. }
  1113. static int qeth_halt_channel(struct qeth_channel *channel)
  1114. {
  1115. unsigned long flags;
  1116. struct qeth_card *card;
  1117. int rc;
  1118. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1119. card = CARD_FROM_CDEV(channel->ccwdev);
  1120. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1121. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1122. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1123. if (rc)
  1124. return rc;
  1125. rc = wait_event_interruptible_timeout(card->wait_q,
  1126. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1127. if (rc == -ERESTARTSYS)
  1128. return rc;
  1129. if (channel->state != CH_STATE_HALTED)
  1130. return -ETIME;
  1131. return 0;
  1132. }
  1133. static int qeth_halt_channels(struct qeth_card *card)
  1134. {
  1135. int rc1 = 0, rc2 = 0, rc3 = 0;
  1136. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1137. rc1 = qeth_halt_channel(&card->read);
  1138. rc2 = qeth_halt_channel(&card->write);
  1139. rc3 = qeth_halt_channel(&card->data);
  1140. if (rc1)
  1141. return rc1;
  1142. if (rc2)
  1143. return rc2;
  1144. return rc3;
  1145. }
  1146. static int qeth_clear_channels(struct qeth_card *card)
  1147. {
  1148. int rc1 = 0, rc2 = 0, rc3 = 0;
  1149. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1150. rc1 = qeth_clear_channel(&card->read);
  1151. rc2 = qeth_clear_channel(&card->write);
  1152. rc3 = qeth_clear_channel(&card->data);
  1153. if (rc1)
  1154. return rc1;
  1155. if (rc2)
  1156. return rc2;
  1157. return rc3;
  1158. }
  1159. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1160. {
  1161. int rc = 0;
  1162. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1163. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1164. if (halt)
  1165. rc = qeth_halt_channels(card);
  1166. if (rc)
  1167. return rc;
  1168. return qeth_clear_channels(card);
  1169. }
  1170. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1171. {
  1172. int rc = 0;
  1173. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1174. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1175. QETH_QDIO_CLEANING)) {
  1176. case QETH_QDIO_ESTABLISHED:
  1177. if (card->info.type == QETH_CARD_TYPE_IQD)
  1178. rc = qdio_cleanup(CARD_DDEV(card),
  1179. QDIO_FLAG_CLEANUP_USING_HALT);
  1180. else
  1181. rc = qdio_cleanup(CARD_DDEV(card),
  1182. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1183. if (rc)
  1184. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1185. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1186. break;
  1187. case QETH_QDIO_CLEANING:
  1188. return rc;
  1189. default:
  1190. break;
  1191. }
  1192. rc = qeth_clear_halt_card(card, use_halt);
  1193. if (rc)
  1194. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1195. card->state = CARD_STATE_DOWN;
  1196. return rc;
  1197. }
  1198. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1199. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1200. int *length)
  1201. {
  1202. struct ciw *ciw;
  1203. char *rcd_buf;
  1204. int ret;
  1205. struct qeth_channel *channel = &card->data;
  1206. unsigned long flags;
  1207. /*
  1208. * scan for RCD command in extended SenseID data
  1209. */
  1210. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1211. if (!ciw || ciw->cmd == 0)
  1212. return -EOPNOTSUPP;
  1213. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1214. if (!rcd_buf)
  1215. return -ENOMEM;
  1216. channel->ccw.cmd_code = ciw->cmd;
  1217. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1218. channel->ccw.count = ciw->count;
  1219. channel->ccw.flags = CCW_FLAG_SLI;
  1220. channel->state = CH_STATE_RCD;
  1221. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1222. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1223. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1224. QETH_RCD_TIMEOUT);
  1225. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1226. if (!ret)
  1227. wait_event(card->wait_q,
  1228. (channel->state == CH_STATE_RCD_DONE ||
  1229. channel->state == CH_STATE_DOWN));
  1230. if (channel->state == CH_STATE_DOWN)
  1231. ret = -EIO;
  1232. else
  1233. channel->state = CH_STATE_DOWN;
  1234. if (ret) {
  1235. kfree(rcd_buf);
  1236. *buffer = NULL;
  1237. *length = 0;
  1238. } else {
  1239. *length = ciw->count;
  1240. *buffer = rcd_buf;
  1241. }
  1242. return ret;
  1243. }
  1244. static int qeth_get_unitaddr(struct qeth_card *card)
  1245. {
  1246. int length;
  1247. char *prcd;
  1248. int rc;
  1249. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1250. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1251. if (rc) {
  1252. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1253. dev_name(&card->gdev->dev), rc);
  1254. return rc;
  1255. }
  1256. card->info.chpid = prcd[30];
  1257. card->info.unit_addr2 = prcd[31];
  1258. card->info.cula = prcd[63];
  1259. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1260. (prcd[0x11] == _ascebc['M']));
  1261. kfree(prcd);
  1262. return 0;
  1263. }
  1264. static void qeth_init_tokens(struct qeth_card *card)
  1265. {
  1266. card->token.issuer_rm_w = 0x00010103UL;
  1267. card->token.cm_filter_w = 0x00010108UL;
  1268. card->token.cm_connection_w = 0x0001010aUL;
  1269. card->token.ulp_filter_w = 0x0001010bUL;
  1270. card->token.ulp_connection_w = 0x0001010dUL;
  1271. }
  1272. static void qeth_init_func_level(struct qeth_card *card)
  1273. {
  1274. if (card->ipato.enabled) {
  1275. if (card->info.type == QETH_CARD_TYPE_IQD)
  1276. card->info.func_level =
  1277. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1278. else
  1279. card->info.func_level =
  1280. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1281. } else {
  1282. if (card->info.type == QETH_CARD_TYPE_IQD)
  1283. /*FIXME:why do we have same values for dis and ena for
  1284. osae??? */
  1285. card->info.func_level =
  1286. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1287. else
  1288. card->info.func_level =
  1289. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1290. }
  1291. }
  1292. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1293. void (*idx_reply_cb)(struct qeth_channel *,
  1294. struct qeth_cmd_buffer *))
  1295. {
  1296. struct qeth_cmd_buffer *iob;
  1297. unsigned long flags;
  1298. int rc;
  1299. struct qeth_card *card;
  1300. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1301. card = CARD_FROM_CDEV(channel->ccwdev);
  1302. iob = qeth_get_buffer(channel);
  1303. iob->callback = idx_reply_cb;
  1304. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1305. channel->ccw.count = QETH_BUFSIZE;
  1306. channel->ccw.cda = (__u32) __pa(iob->data);
  1307. wait_event(card->wait_q,
  1308. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1309. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1310. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1311. rc = ccw_device_start(channel->ccwdev,
  1312. &channel->ccw, (addr_t) iob, 0, 0);
  1313. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1314. if (rc) {
  1315. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1316. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1317. atomic_set(&channel->irq_pending, 0);
  1318. wake_up(&card->wait_q);
  1319. return rc;
  1320. }
  1321. rc = wait_event_interruptible_timeout(card->wait_q,
  1322. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1323. if (rc == -ERESTARTSYS)
  1324. return rc;
  1325. if (channel->state != CH_STATE_UP) {
  1326. rc = -ETIME;
  1327. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1328. qeth_clear_cmd_buffers(channel);
  1329. } else
  1330. rc = 0;
  1331. return rc;
  1332. }
  1333. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1334. void (*idx_reply_cb)(struct qeth_channel *,
  1335. struct qeth_cmd_buffer *))
  1336. {
  1337. struct qeth_card *card;
  1338. struct qeth_cmd_buffer *iob;
  1339. unsigned long flags;
  1340. __u16 temp;
  1341. __u8 tmp;
  1342. int rc;
  1343. struct ccw_dev_id temp_devid;
  1344. card = CARD_FROM_CDEV(channel->ccwdev);
  1345. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1346. iob = qeth_get_buffer(channel);
  1347. iob->callback = idx_reply_cb;
  1348. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1349. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1350. channel->ccw.cda = (__u32) __pa(iob->data);
  1351. if (channel == &card->write) {
  1352. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1353. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1354. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1355. card->seqno.trans_hdr++;
  1356. } else {
  1357. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1358. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1359. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1360. }
  1361. tmp = ((__u8)card->info.portno) | 0x80;
  1362. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1363. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1364. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1365. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1366. &card->info.func_level, sizeof(__u16));
  1367. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1368. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1369. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1370. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1371. wait_event(card->wait_q,
  1372. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1373. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1374. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1375. rc = ccw_device_start(channel->ccwdev,
  1376. &channel->ccw, (addr_t) iob, 0, 0);
  1377. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1378. if (rc) {
  1379. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1380. rc);
  1381. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1382. atomic_set(&channel->irq_pending, 0);
  1383. wake_up(&card->wait_q);
  1384. return rc;
  1385. }
  1386. rc = wait_event_interruptible_timeout(card->wait_q,
  1387. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1388. if (rc == -ERESTARTSYS)
  1389. return rc;
  1390. if (channel->state != CH_STATE_ACTIVATING) {
  1391. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1392. " failed to recover an error on the device\n");
  1393. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1394. dev_name(&channel->ccwdev->dev));
  1395. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1396. qeth_clear_cmd_buffers(channel);
  1397. return -ETIME;
  1398. }
  1399. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1400. }
  1401. static int qeth_peer_func_level(int level)
  1402. {
  1403. if ((level & 0xff) == 8)
  1404. return (level & 0xff) + 0x400;
  1405. if (((level >> 8) & 3) == 1)
  1406. return (level & 0xff) + 0x200;
  1407. return level;
  1408. }
  1409. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1410. struct qeth_cmd_buffer *iob)
  1411. {
  1412. struct qeth_card *card;
  1413. __u16 temp;
  1414. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1415. if (channel->state == CH_STATE_DOWN) {
  1416. channel->state = CH_STATE_ACTIVATING;
  1417. goto out;
  1418. }
  1419. card = CARD_FROM_CDEV(channel->ccwdev);
  1420. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1421. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1422. dev_err(&card->write.ccwdev->dev,
  1423. "The adapter is used exclusively by another "
  1424. "host\n");
  1425. else
  1426. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1427. " negative reply\n",
  1428. dev_name(&card->write.ccwdev->dev));
  1429. goto out;
  1430. }
  1431. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1432. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1433. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1434. "function level mismatch (sent: 0x%x, received: "
  1435. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1436. card->info.func_level, temp);
  1437. goto out;
  1438. }
  1439. channel->state = CH_STATE_UP;
  1440. out:
  1441. qeth_release_buffer(channel, iob);
  1442. }
  1443. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1444. struct qeth_cmd_buffer *iob)
  1445. {
  1446. struct qeth_card *card;
  1447. __u16 temp;
  1448. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1449. if (channel->state == CH_STATE_DOWN) {
  1450. channel->state = CH_STATE_ACTIVATING;
  1451. goto out;
  1452. }
  1453. card = CARD_FROM_CDEV(channel->ccwdev);
  1454. if (qeth_check_idx_response(iob->data))
  1455. goto out;
  1456. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1457. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1458. dev_err(&card->write.ccwdev->dev,
  1459. "The adapter is used exclusively by another "
  1460. "host\n");
  1461. else
  1462. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1463. " negative reply\n",
  1464. dev_name(&card->read.ccwdev->dev));
  1465. goto out;
  1466. }
  1467. /**
  1468. * temporary fix for microcode bug
  1469. * to revert it,replace OR by AND
  1470. */
  1471. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1472. (card->info.type == QETH_CARD_TYPE_OSAE))
  1473. card->info.portname_required = 1;
  1474. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1475. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1476. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1477. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1478. dev_name(&card->read.ccwdev->dev),
  1479. card->info.func_level, temp);
  1480. goto out;
  1481. }
  1482. memcpy(&card->token.issuer_rm_r,
  1483. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1484. QETH_MPC_TOKEN_LENGTH);
  1485. memcpy(&card->info.mcl_level[0],
  1486. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1487. channel->state = CH_STATE_UP;
  1488. out:
  1489. qeth_release_buffer(channel, iob);
  1490. }
  1491. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1492. struct qeth_cmd_buffer *iob)
  1493. {
  1494. qeth_setup_ccw(&card->write, iob->data, len);
  1495. iob->callback = qeth_release_buffer;
  1496. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1497. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1498. card->seqno.trans_hdr++;
  1499. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1500. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1501. card->seqno.pdu_hdr++;
  1502. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1503. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1504. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1505. }
  1506. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1507. int qeth_send_control_data(struct qeth_card *card, int len,
  1508. struct qeth_cmd_buffer *iob,
  1509. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1510. unsigned long),
  1511. void *reply_param)
  1512. {
  1513. int rc;
  1514. unsigned long flags;
  1515. struct qeth_reply *reply = NULL;
  1516. unsigned long timeout, event_timeout;
  1517. struct qeth_ipa_cmd *cmd;
  1518. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1519. reply = qeth_alloc_reply(card);
  1520. if (!reply) {
  1521. return -ENOMEM;
  1522. }
  1523. reply->callback = reply_cb;
  1524. reply->param = reply_param;
  1525. if (card->state == CARD_STATE_DOWN)
  1526. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1527. else
  1528. reply->seqno = card->seqno.ipa++;
  1529. init_waitqueue_head(&reply->wait_q);
  1530. spin_lock_irqsave(&card->lock, flags);
  1531. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1532. spin_unlock_irqrestore(&card->lock, flags);
  1533. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1534. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1535. qeth_prepare_control_data(card, len, iob);
  1536. if (IS_IPA(iob->data))
  1537. event_timeout = QETH_IPA_TIMEOUT;
  1538. else
  1539. event_timeout = QETH_TIMEOUT;
  1540. timeout = jiffies + event_timeout;
  1541. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1542. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1543. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1544. (addr_t) iob, 0, 0);
  1545. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1546. if (rc) {
  1547. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1548. "ccw_device_start rc = %i\n",
  1549. dev_name(&card->write.ccwdev->dev), rc);
  1550. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1551. spin_lock_irqsave(&card->lock, flags);
  1552. list_del_init(&reply->list);
  1553. qeth_put_reply(reply);
  1554. spin_unlock_irqrestore(&card->lock, flags);
  1555. qeth_release_buffer(iob->channel, iob);
  1556. atomic_set(&card->write.irq_pending, 0);
  1557. wake_up(&card->wait_q);
  1558. return rc;
  1559. }
  1560. /* we have only one long running ipassist, since we can ensure
  1561. process context of this command we can sleep */
  1562. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1563. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1564. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1565. if (!wait_event_timeout(reply->wait_q,
  1566. atomic_read(&reply->received), event_timeout))
  1567. goto time_err;
  1568. } else {
  1569. while (!atomic_read(&reply->received)) {
  1570. if (time_after(jiffies, timeout))
  1571. goto time_err;
  1572. cpu_relax();
  1573. };
  1574. }
  1575. rc = reply->rc;
  1576. qeth_put_reply(reply);
  1577. return rc;
  1578. time_err:
  1579. spin_lock_irqsave(&reply->card->lock, flags);
  1580. list_del_init(&reply->list);
  1581. spin_unlock_irqrestore(&reply->card->lock, flags);
  1582. reply->rc = -ETIME;
  1583. atomic_inc(&reply->received);
  1584. wake_up(&reply->wait_q);
  1585. rc = reply->rc;
  1586. qeth_put_reply(reply);
  1587. return rc;
  1588. }
  1589. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1590. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1591. unsigned long data)
  1592. {
  1593. struct qeth_cmd_buffer *iob;
  1594. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1595. iob = (struct qeth_cmd_buffer *) data;
  1596. memcpy(&card->token.cm_filter_r,
  1597. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1598. QETH_MPC_TOKEN_LENGTH);
  1599. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1600. return 0;
  1601. }
  1602. static int qeth_cm_enable(struct qeth_card *card)
  1603. {
  1604. int rc;
  1605. struct qeth_cmd_buffer *iob;
  1606. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1607. iob = qeth_wait_for_buffer(&card->write);
  1608. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1609. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1610. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1611. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1612. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1613. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1614. qeth_cm_enable_cb, NULL);
  1615. return rc;
  1616. }
  1617. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1618. unsigned long data)
  1619. {
  1620. struct qeth_cmd_buffer *iob;
  1621. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1622. iob = (struct qeth_cmd_buffer *) data;
  1623. memcpy(&card->token.cm_connection_r,
  1624. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1625. QETH_MPC_TOKEN_LENGTH);
  1626. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1627. return 0;
  1628. }
  1629. static int qeth_cm_setup(struct qeth_card *card)
  1630. {
  1631. int rc;
  1632. struct qeth_cmd_buffer *iob;
  1633. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1634. iob = qeth_wait_for_buffer(&card->write);
  1635. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1636. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1637. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1638. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1639. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1640. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1641. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1642. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1643. qeth_cm_setup_cb, NULL);
  1644. return rc;
  1645. }
  1646. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1647. {
  1648. switch (card->info.type) {
  1649. case QETH_CARD_TYPE_UNKNOWN:
  1650. return 1500;
  1651. case QETH_CARD_TYPE_IQD:
  1652. return card->info.max_mtu;
  1653. case QETH_CARD_TYPE_OSAE:
  1654. switch (card->info.link_type) {
  1655. case QETH_LINK_TYPE_HSTR:
  1656. case QETH_LINK_TYPE_LANE_TR:
  1657. return 2000;
  1658. default:
  1659. return 1492;
  1660. }
  1661. default:
  1662. return 1500;
  1663. }
  1664. }
  1665. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1666. {
  1667. switch (cardtype) {
  1668. case QETH_CARD_TYPE_UNKNOWN:
  1669. case QETH_CARD_TYPE_OSAE:
  1670. case QETH_CARD_TYPE_OSN:
  1671. return 61440;
  1672. case QETH_CARD_TYPE_IQD:
  1673. return 57344;
  1674. default:
  1675. return 1500;
  1676. }
  1677. }
  1678. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1679. {
  1680. switch (cardtype) {
  1681. case QETH_CARD_TYPE_IQD:
  1682. return 1;
  1683. default:
  1684. return 0;
  1685. }
  1686. }
  1687. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1688. {
  1689. switch (framesize) {
  1690. case 0x4000:
  1691. return 8192;
  1692. case 0x6000:
  1693. return 16384;
  1694. case 0xa000:
  1695. return 32768;
  1696. case 0xffff:
  1697. return 57344;
  1698. default:
  1699. return 0;
  1700. }
  1701. }
  1702. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1703. {
  1704. switch (card->info.type) {
  1705. case QETH_CARD_TYPE_OSAE:
  1706. return ((mtu >= 576) && (mtu <= 61440));
  1707. case QETH_CARD_TYPE_IQD:
  1708. return ((mtu >= 576) &&
  1709. (mtu <= card->info.max_mtu + 4096 - 32));
  1710. case QETH_CARD_TYPE_OSN:
  1711. case QETH_CARD_TYPE_UNKNOWN:
  1712. default:
  1713. return 1;
  1714. }
  1715. }
  1716. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1717. unsigned long data)
  1718. {
  1719. __u16 mtu, framesize;
  1720. __u16 len;
  1721. __u8 link_type;
  1722. struct qeth_cmd_buffer *iob;
  1723. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1724. iob = (struct qeth_cmd_buffer *) data;
  1725. memcpy(&card->token.ulp_filter_r,
  1726. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1727. QETH_MPC_TOKEN_LENGTH);
  1728. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1729. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1730. mtu = qeth_get_mtu_outof_framesize(framesize);
  1731. if (!mtu) {
  1732. iob->rc = -EINVAL;
  1733. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1734. return 0;
  1735. }
  1736. card->info.max_mtu = mtu;
  1737. card->info.initial_mtu = mtu;
  1738. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1739. } else {
  1740. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1741. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1742. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1743. }
  1744. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1745. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1746. memcpy(&link_type,
  1747. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1748. card->info.link_type = link_type;
  1749. } else
  1750. card->info.link_type = 0;
  1751. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1752. return 0;
  1753. }
  1754. static int qeth_ulp_enable(struct qeth_card *card)
  1755. {
  1756. int rc;
  1757. char prot_type;
  1758. struct qeth_cmd_buffer *iob;
  1759. /*FIXME: trace view callbacks*/
  1760. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1761. iob = qeth_wait_for_buffer(&card->write);
  1762. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1763. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1764. (__u8) card->info.portno;
  1765. if (card->options.layer2)
  1766. if (card->info.type == QETH_CARD_TYPE_OSN)
  1767. prot_type = QETH_PROT_OSN2;
  1768. else
  1769. prot_type = QETH_PROT_LAYER2;
  1770. else
  1771. prot_type = QETH_PROT_TCPIP;
  1772. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1773. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1774. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1775. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1776. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1777. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1778. card->info.portname, 9);
  1779. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1780. qeth_ulp_enable_cb, NULL);
  1781. return rc;
  1782. }
  1783. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1784. unsigned long data)
  1785. {
  1786. struct qeth_cmd_buffer *iob;
  1787. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1788. iob = (struct qeth_cmd_buffer *) data;
  1789. memcpy(&card->token.ulp_connection_r,
  1790. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1791. QETH_MPC_TOKEN_LENGTH);
  1792. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1793. return 0;
  1794. }
  1795. static int qeth_ulp_setup(struct qeth_card *card)
  1796. {
  1797. int rc;
  1798. __u16 temp;
  1799. struct qeth_cmd_buffer *iob;
  1800. struct ccw_dev_id dev_id;
  1801. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1802. iob = qeth_wait_for_buffer(&card->write);
  1803. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1804. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1805. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1806. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1807. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1808. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1809. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1810. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1811. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1812. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1813. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1814. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1815. qeth_ulp_setup_cb, NULL);
  1816. return rc;
  1817. }
  1818. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1819. {
  1820. int i, j;
  1821. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1822. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1823. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1824. return 0;
  1825. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1826. GFP_KERNEL);
  1827. if (!card->qdio.in_q)
  1828. goto out_nomem;
  1829. QETH_DBF_TEXT(SETUP, 2, "inq");
  1830. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1831. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1832. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1833. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1834. card->qdio.in_q->bufs[i].buffer =
  1835. &card->qdio.in_q->qdio_bufs[i];
  1836. /* inbound buffer pool */
  1837. if (qeth_alloc_buffer_pool(card))
  1838. goto out_freeinq;
  1839. /* outbound */
  1840. card->qdio.out_qs =
  1841. kmalloc(card->qdio.no_out_queues *
  1842. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1843. if (!card->qdio.out_qs)
  1844. goto out_freepool;
  1845. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1846. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1847. GFP_KERNEL);
  1848. if (!card->qdio.out_qs[i])
  1849. goto out_freeoutq;
  1850. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1851. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1852. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1853. card->qdio.out_qs[i]->queue_no = i;
  1854. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1855. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1856. card->qdio.out_qs[i]->bufs[j].buffer =
  1857. &card->qdio.out_qs[i]->qdio_bufs[j];
  1858. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1859. skb_list);
  1860. lockdep_set_class(
  1861. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1862. &qdio_out_skb_queue_key);
  1863. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1864. }
  1865. }
  1866. return 0;
  1867. out_freeoutq:
  1868. while (i > 0)
  1869. kfree(card->qdio.out_qs[--i]);
  1870. kfree(card->qdio.out_qs);
  1871. card->qdio.out_qs = NULL;
  1872. out_freepool:
  1873. qeth_free_buffer_pool(card);
  1874. out_freeinq:
  1875. kfree(card->qdio.in_q);
  1876. card->qdio.in_q = NULL;
  1877. out_nomem:
  1878. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1879. return -ENOMEM;
  1880. }
  1881. static void qeth_create_qib_param_field(struct qeth_card *card,
  1882. char *param_field)
  1883. {
  1884. param_field[0] = _ascebc['P'];
  1885. param_field[1] = _ascebc['C'];
  1886. param_field[2] = _ascebc['I'];
  1887. param_field[3] = _ascebc['T'];
  1888. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1889. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1890. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1891. }
  1892. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1893. char *param_field)
  1894. {
  1895. param_field[16] = _ascebc['B'];
  1896. param_field[17] = _ascebc['L'];
  1897. param_field[18] = _ascebc['K'];
  1898. param_field[19] = _ascebc['T'];
  1899. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1900. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1901. *((unsigned int *) (&param_field[28])) =
  1902. card->info.blkt.inter_packet_jumbo;
  1903. }
  1904. static int qeth_qdio_activate(struct qeth_card *card)
  1905. {
  1906. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1907. return qdio_activate(CARD_DDEV(card));
  1908. }
  1909. static int qeth_dm_act(struct qeth_card *card)
  1910. {
  1911. int rc;
  1912. struct qeth_cmd_buffer *iob;
  1913. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1914. iob = qeth_wait_for_buffer(&card->write);
  1915. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1916. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1917. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1918. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1919. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1920. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1921. return rc;
  1922. }
  1923. static int qeth_mpc_initialize(struct qeth_card *card)
  1924. {
  1925. int rc;
  1926. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1927. rc = qeth_issue_next_read(card);
  1928. if (rc) {
  1929. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1930. return rc;
  1931. }
  1932. rc = qeth_cm_enable(card);
  1933. if (rc) {
  1934. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1935. goto out_qdio;
  1936. }
  1937. rc = qeth_cm_setup(card);
  1938. if (rc) {
  1939. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1940. goto out_qdio;
  1941. }
  1942. rc = qeth_ulp_enable(card);
  1943. if (rc) {
  1944. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1945. goto out_qdio;
  1946. }
  1947. rc = qeth_ulp_setup(card);
  1948. if (rc) {
  1949. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1950. goto out_qdio;
  1951. }
  1952. rc = qeth_alloc_qdio_buffers(card);
  1953. if (rc) {
  1954. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1955. goto out_qdio;
  1956. }
  1957. rc = qeth_qdio_establish(card);
  1958. if (rc) {
  1959. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1960. qeth_free_qdio_buffers(card);
  1961. goto out_qdio;
  1962. }
  1963. rc = qeth_qdio_activate(card);
  1964. if (rc) {
  1965. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1966. goto out_qdio;
  1967. }
  1968. rc = qeth_dm_act(card);
  1969. if (rc) {
  1970. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1971. goto out_qdio;
  1972. }
  1973. return 0;
  1974. out_qdio:
  1975. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1976. return rc;
  1977. }
  1978. static void qeth_print_status_with_portname(struct qeth_card *card)
  1979. {
  1980. char dbf_text[15];
  1981. int i;
  1982. sprintf(dbf_text, "%s", card->info.portname + 1);
  1983. for (i = 0; i < 8; i++)
  1984. dbf_text[i] =
  1985. (char) _ebcasc[(__u8) dbf_text[i]];
  1986. dbf_text[8] = 0;
  1987. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1988. "with link type %s (portname: %s)\n",
  1989. qeth_get_cardname(card),
  1990. (card->info.mcl_level[0]) ? " (level: " : "",
  1991. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1992. (card->info.mcl_level[0]) ? ")" : "",
  1993. qeth_get_cardname_short(card),
  1994. dbf_text);
  1995. }
  1996. static void qeth_print_status_no_portname(struct qeth_card *card)
  1997. {
  1998. if (card->info.portname[0])
  1999. dev_info(&card->gdev->dev, "Device is a%s "
  2000. "card%s%s%s\nwith link type %s "
  2001. "(no portname needed by interface).\n",
  2002. qeth_get_cardname(card),
  2003. (card->info.mcl_level[0]) ? " (level: " : "",
  2004. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2005. (card->info.mcl_level[0]) ? ")" : "",
  2006. qeth_get_cardname_short(card));
  2007. else
  2008. dev_info(&card->gdev->dev, "Device is a%s "
  2009. "card%s%s%s\nwith link type %s.\n",
  2010. qeth_get_cardname(card),
  2011. (card->info.mcl_level[0]) ? " (level: " : "",
  2012. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2013. (card->info.mcl_level[0]) ? ")" : "",
  2014. qeth_get_cardname_short(card));
  2015. }
  2016. void qeth_print_status_message(struct qeth_card *card)
  2017. {
  2018. switch (card->info.type) {
  2019. case QETH_CARD_TYPE_OSAE:
  2020. /* VM will use a non-zero first character
  2021. * to indicate a HiperSockets like reporting
  2022. * of the level OSA sets the first character to zero
  2023. * */
  2024. if (!card->info.mcl_level[0]) {
  2025. sprintf(card->info.mcl_level, "%02x%02x",
  2026. card->info.mcl_level[2],
  2027. card->info.mcl_level[3]);
  2028. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2029. break;
  2030. }
  2031. /* fallthrough */
  2032. case QETH_CARD_TYPE_IQD:
  2033. if ((card->info.guestlan) ||
  2034. (card->info.mcl_level[0] & 0x80)) {
  2035. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2036. card->info.mcl_level[0]];
  2037. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2038. card->info.mcl_level[1]];
  2039. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2040. card->info.mcl_level[2]];
  2041. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2042. card->info.mcl_level[3]];
  2043. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2044. }
  2045. break;
  2046. default:
  2047. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2048. }
  2049. if (card->info.portname_required)
  2050. qeth_print_status_with_portname(card);
  2051. else
  2052. qeth_print_status_no_portname(card);
  2053. }
  2054. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2055. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2056. {
  2057. struct qeth_buffer_pool_entry *entry;
  2058. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2059. list_for_each_entry(entry,
  2060. &card->qdio.init_pool.entry_list, init_list) {
  2061. qeth_put_buffer_pool_entry(card, entry);
  2062. }
  2063. }
  2064. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2065. struct qeth_card *card)
  2066. {
  2067. struct list_head *plh;
  2068. struct qeth_buffer_pool_entry *entry;
  2069. int i, free;
  2070. struct page *page;
  2071. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2072. return NULL;
  2073. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2074. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2075. free = 1;
  2076. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2077. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2078. free = 0;
  2079. break;
  2080. }
  2081. }
  2082. if (free) {
  2083. list_del_init(&entry->list);
  2084. return entry;
  2085. }
  2086. }
  2087. /* no free buffer in pool so take first one and swap pages */
  2088. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2089. struct qeth_buffer_pool_entry, list);
  2090. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2091. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2092. page = alloc_page(GFP_ATOMIC);
  2093. if (!page) {
  2094. return NULL;
  2095. } else {
  2096. free_page((unsigned long)entry->elements[i]);
  2097. entry->elements[i] = page_address(page);
  2098. if (card->options.performance_stats)
  2099. card->perf_stats.sg_alloc_page_rx++;
  2100. }
  2101. }
  2102. }
  2103. list_del_init(&entry->list);
  2104. return entry;
  2105. }
  2106. static int qeth_init_input_buffer(struct qeth_card *card,
  2107. struct qeth_qdio_buffer *buf)
  2108. {
  2109. struct qeth_buffer_pool_entry *pool_entry;
  2110. int i;
  2111. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2112. if (!pool_entry)
  2113. return 1;
  2114. /*
  2115. * since the buffer is accessed only from the input_tasklet
  2116. * there shouldn't be a need to synchronize; also, since we use
  2117. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2118. * buffers
  2119. */
  2120. buf->pool_entry = pool_entry;
  2121. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2122. buf->buffer->element[i].length = PAGE_SIZE;
  2123. buf->buffer->element[i].addr = pool_entry->elements[i];
  2124. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2125. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2126. else
  2127. buf->buffer->element[i].flags = 0;
  2128. }
  2129. return 0;
  2130. }
  2131. int qeth_init_qdio_queues(struct qeth_card *card)
  2132. {
  2133. int i, j;
  2134. int rc;
  2135. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2136. /* inbound queue */
  2137. memset(card->qdio.in_q->qdio_bufs, 0,
  2138. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2139. qeth_initialize_working_pool_list(card);
  2140. /*give only as many buffers to hardware as we have buffer pool entries*/
  2141. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2142. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2143. card->qdio.in_q->next_buf_to_init =
  2144. card->qdio.in_buf_pool.buf_count - 1;
  2145. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2146. card->qdio.in_buf_pool.buf_count - 1);
  2147. if (rc) {
  2148. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2149. return rc;
  2150. }
  2151. /* outbound queue */
  2152. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2153. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2154. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2155. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2156. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2157. &card->qdio.out_qs[i]->bufs[j]);
  2158. }
  2159. card->qdio.out_qs[i]->card = card;
  2160. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2161. card->qdio.out_qs[i]->do_pack = 0;
  2162. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2163. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2164. atomic_set(&card->qdio.out_qs[i]->state,
  2165. QETH_OUT_Q_UNLOCKED);
  2166. }
  2167. return 0;
  2168. }
  2169. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2170. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2171. {
  2172. switch (link_type) {
  2173. case QETH_LINK_TYPE_HSTR:
  2174. return 2;
  2175. default:
  2176. return 1;
  2177. }
  2178. }
  2179. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2180. struct qeth_ipa_cmd *cmd, __u8 command,
  2181. enum qeth_prot_versions prot)
  2182. {
  2183. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2184. cmd->hdr.command = command;
  2185. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2186. cmd->hdr.seqno = card->seqno.ipa;
  2187. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2188. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2189. if (card->options.layer2)
  2190. cmd->hdr.prim_version_no = 2;
  2191. else
  2192. cmd->hdr.prim_version_no = 1;
  2193. cmd->hdr.param_count = 1;
  2194. cmd->hdr.prot_version = prot;
  2195. cmd->hdr.ipa_supported = 0;
  2196. cmd->hdr.ipa_enabled = 0;
  2197. }
  2198. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2199. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2200. {
  2201. struct qeth_cmd_buffer *iob;
  2202. struct qeth_ipa_cmd *cmd;
  2203. iob = qeth_wait_for_buffer(&card->write);
  2204. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2205. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2206. return iob;
  2207. }
  2208. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2209. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2210. char prot_type)
  2211. {
  2212. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2213. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2214. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2215. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2216. }
  2217. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2218. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2219. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2220. unsigned long),
  2221. void *reply_param)
  2222. {
  2223. int rc;
  2224. char prot_type;
  2225. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2226. if (card->options.layer2)
  2227. if (card->info.type == QETH_CARD_TYPE_OSN)
  2228. prot_type = QETH_PROT_OSN2;
  2229. else
  2230. prot_type = QETH_PROT_LAYER2;
  2231. else
  2232. prot_type = QETH_PROT_TCPIP;
  2233. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2234. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2235. iob, reply_cb, reply_param);
  2236. return rc;
  2237. }
  2238. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2239. static int qeth_send_startstoplan(struct qeth_card *card,
  2240. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2241. {
  2242. int rc;
  2243. struct qeth_cmd_buffer *iob;
  2244. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2245. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2246. return rc;
  2247. }
  2248. int qeth_send_startlan(struct qeth_card *card)
  2249. {
  2250. int rc;
  2251. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2252. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2253. return rc;
  2254. }
  2255. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2256. int qeth_send_stoplan(struct qeth_card *card)
  2257. {
  2258. int rc = 0;
  2259. /*
  2260. * TODO: according to the IPA format document page 14,
  2261. * TCP/IP (we!) never issue a STOPLAN
  2262. * is this right ?!?
  2263. */
  2264. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2265. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2266. return rc;
  2267. }
  2268. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2269. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2270. struct qeth_reply *reply, unsigned long data)
  2271. {
  2272. struct qeth_ipa_cmd *cmd;
  2273. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2274. cmd = (struct qeth_ipa_cmd *) data;
  2275. if (cmd->hdr.return_code == 0)
  2276. cmd->hdr.return_code =
  2277. cmd->data.setadapterparms.hdr.return_code;
  2278. return 0;
  2279. }
  2280. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2281. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2282. struct qeth_reply *reply, unsigned long data)
  2283. {
  2284. struct qeth_ipa_cmd *cmd;
  2285. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2286. cmd = (struct qeth_ipa_cmd *) data;
  2287. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2288. card->info.link_type =
  2289. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2290. card->options.adp.supported_funcs =
  2291. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2292. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2293. }
  2294. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2295. __u32 command, __u32 cmdlen)
  2296. {
  2297. struct qeth_cmd_buffer *iob;
  2298. struct qeth_ipa_cmd *cmd;
  2299. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2300. QETH_PROT_IPV4);
  2301. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2302. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2303. cmd->data.setadapterparms.hdr.command_code = command;
  2304. cmd->data.setadapterparms.hdr.used_total = 1;
  2305. cmd->data.setadapterparms.hdr.seq_no = 1;
  2306. return iob;
  2307. }
  2308. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2309. int qeth_query_setadapterparms(struct qeth_card *card)
  2310. {
  2311. int rc;
  2312. struct qeth_cmd_buffer *iob;
  2313. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2314. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2315. sizeof(struct qeth_ipacmd_setadpparms));
  2316. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2317. return rc;
  2318. }
  2319. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2320. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2321. const char *dbftext)
  2322. {
  2323. if (qdio_error) {
  2324. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2325. QETH_DBF_TEXT(QERR, 2, dbftext);
  2326. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2327. buf->element[15].flags & 0xff);
  2328. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2329. buf->element[14].flags & 0xff);
  2330. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2331. return 1;
  2332. }
  2333. return 0;
  2334. }
  2335. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2336. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2337. {
  2338. struct qeth_qdio_q *queue = card->qdio.in_q;
  2339. int count;
  2340. int i;
  2341. int rc;
  2342. int newcount = 0;
  2343. count = (index < queue->next_buf_to_init)?
  2344. card->qdio.in_buf_pool.buf_count -
  2345. (queue->next_buf_to_init - index) :
  2346. card->qdio.in_buf_pool.buf_count -
  2347. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2348. /* only requeue at a certain threshold to avoid SIGAs */
  2349. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2350. for (i = queue->next_buf_to_init;
  2351. i < queue->next_buf_to_init + count; ++i) {
  2352. if (qeth_init_input_buffer(card,
  2353. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2354. break;
  2355. } else {
  2356. newcount++;
  2357. }
  2358. }
  2359. if (newcount < count) {
  2360. /* we are in memory shortage so we switch back to
  2361. traditional skb allocation and drop packages */
  2362. atomic_set(&card->force_alloc_skb, 3);
  2363. count = newcount;
  2364. } else {
  2365. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2366. }
  2367. /*
  2368. * according to old code it should be avoided to requeue all
  2369. * 128 buffers in order to benefit from PCI avoidance.
  2370. * this function keeps at least one buffer (the buffer at
  2371. * 'index') un-requeued -> this buffer is the first buffer that
  2372. * will be requeued the next time
  2373. */
  2374. if (card->options.performance_stats) {
  2375. card->perf_stats.inbound_do_qdio_cnt++;
  2376. card->perf_stats.inbound_do_qdio_start_time =
  2377. qeth_get_micros();
  2378. }
  2379. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2380. queue->next_buf_to_init, count);
  2381. if (card->options.performance_stats)
  2382. card->perf_stats.inbound_do_qdio_time +=
  2383. qeth_get_micros() -
  2384. card->perf_stats.inbound_do_qdio_start_time;
  2385. if (rc) {
  2386. dev_warn(&card->gdev->dev,
  2387. "QDIO reported an error, rc=%i\n", rc);
  2388. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2389. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2390. }
  2391. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2392. QDIO_MAX_BUFFERS_PER_Q;
  2393. }
  2394. }
  2395. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2396. static int qeth_handle_send_error(struct qeth_card *card,
  2397. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2398. {
  2399. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2400. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2401. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2402. if (!qdio_err)
  2403. return QETH_SEND_ERROR_NONE;
  2404. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2405. return QETH_SEND_ERROR_RETRY;
  2406. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2407. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2408. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2409. (u16)qdio_err, (u8)sbalf15);
  2410. return QETH_SEND_ERROR_LINK_FAILURE;
  2411. }
  2412. /*
  2413. * Switched to packing state if the number of used buffers on a queue
  2414. * reaches a certain limit.
  2415. */
  2416. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2417. {
  2418. if (!queue->do_pack) {
  2419. if (atomic_read(&queue->used_buffers)
  2420. >= QETH_HIGH_WATERMARK_PACK){
  2421. /* switch non-PACKING -> PACKING */
  2422. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2423. if (queue->card->options.performance_stats)
  2424. queue->card->perf_stats.sc_dp_p++;
  2425. queue->do_pack = 1;
  2426. }
  2427. }
  2428. }
  2429. /*
  2430. * Switches from packing to non-packing mode. If there is a packing
  2431. * buffer on the queue this buffer will be prepared to be flushed.
  2432. * In that case 1 is returned to inform the caller. If no buffer
  2433. * has to be flushed, zero is returned.
  2434. */
  2435. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2436. {
  2437. struct qeth_qdio_out_buffer *buffer;
  2438. int flush_count = 0;
  2439. if (queue->do_pack) {
  2440. if (atomic_read(&queue->used_buffers)
  2441. <= QETH_LOW_WATERMARK_PACK) {
  2442. /* switch PACKING -> non-PACKING */
  2443. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2444. if (queue->card->options.performance_stats)
  2445. queue->card->perf_stats.sc_p_dp++;
  2446. queue->do_pack = 0;
  2447. /* flush packing buffers */
  2448. buffer = &queue->bufs[queue->next_buf_to_fill];
  2449. if ((atomic_read(&buffer->state) ==
  2450. QETH_QDIO_BUF_EMPTY) &&
  2451. (buffer->next_element_to_fill > 0)) {
  2452. atomic_set(&buffer->state,
  2453. QETH_QDIO_BUF_PRIMED);
  2454. flush_count++;
  2455. queue->next_buf_to_fill =
  2456. (queue->next_buf_to_fill + 1) %
  2457. QDIO_MAX_BUFFERS_PER_Q;
  2458. }
  2459. }
  2460. }
  2461. return flush_count;
  2462. }
  2463. /*
  2464. * Called to flush a packing buffer if no more pci flags are on the queue.
  2465. * Checks if there is a packing buffer and prepares it to be flushed.
  2466. * In that case returns 1, otherwise zero.
  2467. */
  2468. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2469. {
  2470. struct qeth_qdio_out_buffer *buffer;
  2471. buffer = &queue->bufs[queue->next_buf_to_fill];
  2472. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2473. (buffer->next_element_to_fill > 0)) {
  2474. /* it's a packing buffer */
  2475. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2476. queue->next_buf_to_fill =
  2477. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2478. return 1;
  2479. }
  2480. return 0;
  2481. }
  2482. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2483. int count)
  2484. {
  2485. struct qeth_qdio_out_buffer *buf;
  2486. int rc;
  2487. int i;
  2488. unsigned int qdio_flags;
  2489. for (i = index; i < index + count; ++i) {
  2490. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2491. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2492. SBAL_FLAGS_LAST_ENTRY;
  2493. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2494. continue;
  2495. if (!queue->do_pack) {
  2496. if ((atomic_read(&queue->used_buffers) >=
  2497. (QETH_HIGH_WATERMARK_PACK -
  2498. QETH_WATERMARK_PACK_FUZZ)) &&
  2499. !atomic_read(&queue->set_pci_flags_count)) {
  2500. /* it's likely that we'll go to packing
  2501. * mode soon */
  2502. atomic_inc(&queue->set_pci_flags_count);
  2503. buf->buffer->element[0].flags |= 0x40;
  2504. }
  2505. } else {
  2506. if (!atomic_read(&queue->set_pci_flags_count)) {
  2507. /*
  2508. * there's no outstanding PCI any more, so we
  2509. * have to request a PCI to be sure the the PCI
  2510. * will wake at some time in the future then we
  2511. * can flush packed buffers that might still be
  2512. * hanging around, which can happen if no
  2513. * further send was requested by the stack
  2514. */
  2515. atomic_inc(&queue->set_pci_flags_count);
  2516. buf->buffer->element[0].flags |= 0x40;
  2517. }
  2518. }
  2519. }
  2520. queue->card->dev->trans_start = jiffies;
  2521. if (queue->card->options.performance_stats) {
  2522. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2523. queue->card->perf_stats.outbound_do_qdio_start_time =
  2524. qeth_get_micros();
  2525. }
  2526. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2527. if (atomic_read(&queue->set_pci_flags_count))
  2528. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2529. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2530. queue->queue_no, index, count);
  2531. if (queue->card->options.performance_stats)
  2532. queue->card->perf_stats.outbound_do_qdio_time +=
  2533. qeth_get_micros() -
  2534. queue->card->perf_stats.outbound_do_qdio_start_time;
  2535. if (rc) {
  2536. queue->card->stats.tx_errors += count;
  2537. /* ignore temporary SIGA errors without busy condition */
  2538. if (rc == QDIO_ERROR_SIGA_TARGET)
  2539. return;
  2540. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2541. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2542. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2543. /* this must not happen under normal circumstances. if it
  2544. * happens something is really wrong -> recover */
  2545. qeth_schedule_recovery(queue->card);
  2546. return;
  2547. }
  2548. atomic_add(count, &queue->used_buffers);
  2549. if (queue->card->options.performance_stats)
  2550. queue->card->perf_stats.bufs_sent += count;
  2551. }
  2552. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2553. {
  2554. int index;
  2555. int flush_cnt = 0;
  2556. int q_was_packing = 0;
  2557. /*
  2558. * check if weed have to switch to non-packing mode or if
  2559. * we have to get a pci flag out on the queue
  2560. */
  2561. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2562. !atomic_read(&queue->set_pci_flags_count)) {
  2563. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2564. QETH_OUT_Q_UNLOCKED) {
  2565. /*
  2566. * If we get in here, there was no action in
  2567. * do_send_packet. So, we check if there is a
  2568. * packing buffer to be flushed here.
  2569. */
  2570. netif_stop_queue(queue->card->dev);
  2571. index = queue->next_buf_to_fill;
  2572. q_was_packing = queue->do_pack;
  2573. /* queue->do_pack may change */
  2574. barrier();
  2575. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2576. if (!flush_cnt &&
  2577. !atomic_read(&queue->set_pci_flags_count))
  2578. flush_cnt +=
  2579. qeth_flush_buffers_on_no_pci(queue);
  2580. if (queue->card->options.performance_stats &&
  2581. q_was_packing)
  2582. queue->card->perf_stats.bufs_sent_pack +=
  2583. flush_cnt;
  2584. if (flush_cnt)
  2585. qeth_flush_buffers(queue, index, flush_cnt);
  2586. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2587. }
  2588. }
  2589. }
  2590. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2591. unsigned int qdio_error, int __queue, int first_element,
  2592. int count, unsigned long card_ptr)
  2593. {
  2594. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2595. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2596. struct qeth_qdio_out_buffer *buffer;
  2597. int i;
  2598. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2599. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2600. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2601. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2602. netif_stop_queue(card->dev);
  2603. qeth_schedule_recovery(card);
  2604. return;
  2605. }
  2606. if (card->options.performance_stats) {
  2607. card->perf_stats.outbound_handler_cnt++;
  2608. card->perf_stats.outbound_handler_start_time =
  2609. qeth_get_micros();
  2610. }
  2611. for (i = first_element; i < (first_element + count); ++i) {
  2612. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2613. qeth_handle_send_error(card, buffer, qdio_error);
  2614. qeth_clear_output_buffer(queue, buffer);
  2615. }
  2616. atomic_sub(count, &queue->used_buffers);
  2617. /* check if we need to do something on this outbound queue */
  2618. if (card->info.type != QETH_CARD_TYPE_IQD)
  2619. qeth_check_outbound_queue(queue);
  2620. netif_wake_queue(queue->card->dev);
  2621. if (card->options.performance_stats)
  2622. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2623. card->perf_stats.outbound_handler_start_time;
  2624. }
  2625. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2626. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2627. {
  2628. int cast_type = RTN_UNSPEC;
  2629. if (card->info.type == QETH_CARD_TYPE_OSN)
  2630. return cast_type;
  2631. if (skb_dst(skb) && skb_dst(skb)->neighbour) {
  2632. cast_type = skb_dst(skb)->neighbour->type;
  2633. if ((cast_type == RTN_BROADCAST) ||
  2634. (cast_type == RTN_MULTICAST) ||
  2635. (cast_type == RTN_ANYCAST))
  2636. return cast_type;
  2637. else
  2638. return RTN_UNSPEC;
  2639. }
  2640. /* try something else */
  2641. if (skb->protocol == ETH_P_IPV6)
  2642. return (skb_network_header(skb)[24] == 0xff) ?
  2643. RTN_MULTICAST : 0;
  2644. else if (skb->protocol == ETH_P_IP)
  2645. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2646. RTN_MULTICAST : 0;
  2647. /* ... */
  2648. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2649. return RTN_BROADCAST;
  2650. else {
  2651. u16 hdr_mac;
  2652. hdr_mac = *((u16 *)skb->data);
  2653. /* tr multicast? */
  2654. switch (card->info.link_type) {
  2655. case QETH_LINK_TYPE_HSTR:
  2656. case QETH_LINK_TYPE_LANE_TR:
  2657. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2658. (hdr_mac == QETH_TR_MAC_C))
  2659. return RTN_MULTICAST;
  2660. break;
  2661. /* eth or so multicast? */
  2662. default:
  2663. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2664. (hdr_mac == QETH_ETH_MAC_V6))
  2665. return RTN_MULTICAST;
  2666. }
  2667. }
  2668. return cast_type;
  2669. }
  2670. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2671. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2672. int ipv, int cast_type)
  2673. {
  2674. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2675. return card->qdio.default_out_queue;
  2676. switch (card->qdio.no_out_queues) {
  2677. case 4:
  2678. if (cast_type && card->info.is_multicast_different)
  2679. return card->info.is_multicast_different &
  2680. (card->qdio.no_out_queues - 1);
  2681. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2682. const u8 tos = ip_hdr(skb)->tos;
  2683. if (card->qdio.do_prio_queueing ==
  2684. QETH_PRIO_Q_ING_TOS) {
  2685. if (tos & IP_TOS_NOTIMPORTANT)
  2686. return 3;
  2687. if (tos & IP_TOS_HIGHRELIABILITY)
  2688. return 2;
  2689. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2690. return 1;
  2691. if (tos & IP_TOS_LOWDELAY)
  2692. return 0;
  2693. }
  2694. if (card->qdio.do_prio_queueing ==
  2695. QETH_PRIO_Q_ING_PREC)
  2696. return 3 - (tos >> 6);
  2697. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2698. /* TODO: IPv6!!! */
  2699. }
  2700. return card->qdio.default_out_queue;
  2701. case 1: /* fallthrough for single-out-queue 1920-device */
  2702. default:
  2703. return card->qdio.default_out_queue;
  2704. }
  2705. }
  2706. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2707. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2708. struct sk_buff *skb, int elems)
  2709. {
  2710. int elements_needed = 0;
  2711. if (skb_shinfo(skb)->nr_frags > 0)
  2712. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2713. if (elements_needed == 0)
  2714. elements_needed = 1 + (((((unsigned long) skb->data) %
  2715. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2716. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2717. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2718. "(Number=%d / Length=%d). Discarded.\n",
  2719. (elements_needed+elems), skb->len);
  2720. return 0;
  2721. }
  2722. return elements_needed;
  2723. }
  2724. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2725. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2726. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2727. int offset)
  2728. {
  2729. int length = skb->len;
  2730. int length_here;
  2731. int element;
  2732. char *data;
  2733. int first_lap ;
  2734. element = *next_element_to_fill;
  2735. data = skb->data;
  2736. first_lap = (is_tso == 0 ? 1 : 0);
  2737. if (offset >= 0) {
  2738. data = skb->data + offset;
  2739. length -= offset;
  2740. first_lap = 0;
  2741. }
  2742. while (length > 0) {
  2743. /* length_here is the remaining amount of data in this page */
  2744. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2745. if (length < length_here)
  2746. length_here = length;
  2747. buffer->element[element].addr = data;
  2748. buffer->element[element].length = length_here;
  2749. length -= length_here;
  2750. if (!length) {
  2751. if (first_lap)
  2752. buffer->element[element].flags = 0;
  2753. else
  2754. buffer->element[element].flags =
  2755. SBAL_FLAGS_LAST_FRAG;
  2756. } else {
  2757. if (first_lap)
  2758. buffer->element[element].flags =
  2759. SBAL_FLAGS_FIRST_FRAG;
  2760. else
  2761. buffer->element[element].flags =
  2762. SBAL_FLAGS_MIDDLE_FRAG;
  2763. }
  2764. data += length_here;
  2765. element++;
  2766. first_lap = 0;
  2767. }
  2768. *next_element_to_fill = element;
  2769. }
  2770. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2771. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2772. struct qeth_hdr *hdr, int offset, int hd_len)
  2773. {
  2774. struct qdio_buffer *buffer;
  2775. int flush_cnt = 0, hdr_len, large_send = 0;
  2776. buffer = buf->buffer;
  2777. atomic_inc(&skb->users);
  2778. skb_queue_tail(&buf->skb_list, skb);
  2779. /*check first on TSO ....*/
  2780. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2781. int element = buf->next_element_to_fill;
  2782. hdr_len = sizeof(struct qeth_hdr_tso) +
  2783. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2784. /*fill first buffer entry only with header information */
  2785. buffer->element[element].addr = skb->data;
  2786. buffer->element[element].length = hdr_len;
  2787. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2788. buf->next_element_to_fill++;
  2789. skb->data += hdr_len;
  2790. skb->len -= hdr_len;
  2791. large_send = 1;
  2792. }
  2793. if (offset >= 0) {
  2794. int element = buf->next_element_to_fill;
  2795. buffer->element[element].addr = hdr;
  2796. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2797. hd_len;
  2798. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2799. buf->is_header[element] = 1;
  2800. buf->next_element_to_fill++;
  2801. }
  2802. if (skb_shinfo(skb)->nr_frags == 0)
  2803. __qeth_fill_buffer(skb, buffer, large_send,
  2804. (int *)&buf->next_element_to_fill, offset);
  2805. else
  2806. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2807. (int *)&buf->next_element_to_fill);
  2808. if (!queue->do_pack) {
  2809. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2810. /* set state to PRIMED -> will be flushed */
  2811. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2812. flush_cnt = 1;
  2813. } else {
  2814. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2815. if (queue->card->options.performance_stats)
  2816. queue->card->perf_stats.skbs_sent_pack++;
  2817. if (buf->next_element_to_fill >=
  2818. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2819. /*
  2820. * packed buffer if full -> set state PRIMED
  2821. * -> will be flushed
  2822. */
  2823. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2824. flush_cnt = 1;
  2825. }
  2826. }
  2827. return flush_cnt;
  2828. }
  2829. int qeth_do_send_packet_fast(struct qeth_card *card,
  2830. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2831. struct qeth_hdr *hdr, int elements_needed,
  2832. int offset, int hd_len)
  2833. {
  2834. struct qeth_qdio_out_buffer *buffer;
  2835. int index;
  2836. /* spin until we get the queue ... */
  2837. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2838. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2839. /* ... now we've got the queue */
  2840. index = queue->next_buf_to_fill;
  2841. buffer = &queue->bufs[queue->next_buf_to_fill];
  2842. /*
  2843. * check if buffer is empty to make sure that we do not 'overtake'
  2844. * ourselves and try to fill a buffer that is already primed
  2845. */
  2846. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2847. goto out;
  2848. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2849. QDIO_MAX_BUFFERS_PER_Q;
  2850. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2851. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2852. qeth_flush_buffers(queue, index, 1);
  2853. return 0;
  2854. out:
  2855. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2856. return -EBUSY;
  2857. }
  2858. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2859. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2860. struct sk_buff *skb, struct qeth_hdr *hdr,
  2861. int elements_needed)
  2862. {
  2863. struct qeth_qdio_out_buffer *buffer;
  2864. int start_index;
  2865. int flush_count = 0;
  2866. int do_pack = 0;
  2867. int tmp;
  2868. int rc = 0;
  2869. /* spin until we get the queue ... */
  2870. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2871. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2872. start_index = queue->next_buf_to_fill;
  2873. buffer = &queue->bufs[queue->next_buf_to_fill];
  2874. /*
  2875. * check if buffer is empty to make sure that we do not 'overtake'
  2876. * ourselves and try to fill a buffer that is already primed
  2877. */
  2878. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2879. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2880. return -EBUSY;
  2881. }
  2882. /* check if we need to switch packing state of this queue */
  2883. qeth_switch_to_packing_if_needed(queue);
  2884. if (queue->do_pack) {
  2885. do_pack = 1;
  2886. /* does packet fit in current buffer? */
  2887. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2888. buffer->next_element_to_fill) < elements_needed) {
  2889. /* ... no -> set state PRIMED */
  2890. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2891. flush_count++;
  2892. queue->next_buf_to_fill =
  2893. (queue->next_buf_to_fill + 1) %
  2894. QDIO_MAX_BUFFERS_PER_Q;
  2895. buffer = &queue->bufs[queue->next_buf_to_fill];
  2896. /* we did a step forward, so check buffer state
  2897. * again */
  2898. if (atomic_read(&buffer->state) !=
  2899. QETH_QDIO_BUF_EMPTY) {
  2900. qeth_flush_buffers(queue, start_index,
  2901. flush_count);
  2902. atomic_set(&queue->state,
  2903. QETH_OUT_Q_UNLOCKED);
  2904. return -EBUSY;
  2905. }
  2906. }
  2907. }
  2908. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2909. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2910. QDIO_MAX_BUFFERS_PER_Q;
  2911. flush_count += tmp;
  2912. if (flush_count)
  2913. qeth_flush_buffers(queue, start_index, flush_count);
  2914. else if (!atomic_read(&queue->set_pci_flags_count))
  2915. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2916. /*
  2917. * queue->state will go from LOCKED -> UNLOCKED or from
  2918. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2919. * (switch packing state or flush buffer to get another pci flag out).
  2920. * In that case we will enter this loop
  2921. */
  2922. while (atomic_dec_return(&queue->state)) {
  2923. flush_count = 0;
  2924. start_index = queue->next_buf_to_fill;
  2925. /* check if we can go back to non-packing state */
  2926. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2927. /*
  2928. * check if we need to flush a packing buffer to get a pci
  2929. * flag out on the queue
  2930. */
  2931. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2932. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2933. if (flush_count)
  2934. qeth_flush_buffers(queue, start_index, flush_count);
  2935. }
  2936. /* at this point the queue is UNLOCKED again */
  2937. if (queue->card->options.performance_stats && do_pack)
  2938. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2939. return rc;
  2940. }
  2941. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2942. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2943. struct qeth_reply *reply, unsigned long data)
  2944. {
  2945. struct qeth_ipa_cmd *cmd;
  2946. struct qeth_ipacmd_setadpparms *setparms;
  2947. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2948. cmd = (struct qeth_ipa_cmd *) data;
  2949. setparms = &(cmd->data.setadapterparms);
  2950. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2951. if (cmd->hdr.return_code) {
  2952. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2953. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2954. }
  2955. card->info.promisc_mode = setparms->data.mode;
  2956. return 0;
  2957. }
  2958. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2959. {
  2960. enum qeth_ipa_promisc_modes mode;
  2961. struct net_device *dev = card->dev;
  2962. struct qeth_cmd_buffer *iob;
  2963. struct qeth_ipa_cmd *cmd;
  2964. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2965. if (((dev->flags & IFF_PROMISC) &&
  2966. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2967. (!(dev->flags & IFF_PROMISC) &&
  2968. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2969. return;
  2970. mode = SET_PROMISC_MODE_OFF;
  2971. if (dev->flags & IFF_PROMISC)
  2972. mode = SET_PROMISC_MODE_ON;
  2973. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2974. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2975. sizeof(struct qeth_ipacmd_setadpparms));
  2976. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2977. cmd->data.setadapterparms.data.mode = mode;
  2978. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2979. }
  2980. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2981. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2982. {
  2983. struct qeth_card *card;
  2984. char dbf_text[15];
  2985. card = dev->ml_priv;
  2986. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2987. sprintf(dbf_text, "%8x", new_mtu);
  2988. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2989. if (new_mtu < 64)
  2990. return -EINVAL;
  2991. if (new_mtu > 65535)
  2992. return -EINVAL;
  2993. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2994. (!qeth_mtu_is_valid(card, new_mtu)))
  2995. return -EINVAL;
  2996. dev->mtu = new_mtu;
  2997. return 0;
  2998. }
  2999. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3000. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3001. {
  3002. struct qeth_card *card;
  3003. card = dev->ml_priv;
  3004. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3005. return &card->stats;
  3006. }
  3007. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3008. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3009. struct qeth_reply *reply, unsigned long data)
  3010. {
  3011. struct qeth_ipa_cmd *cmd;
  3012. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3013. cmd = (struct qeth_ipa_cmd *) data;
  3014. if (!card->options.layer2 ||
  3015. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3016. memcpy(card->dev->dev_addr,
  3017. &cmd->data.setadapterparms.data.change_addr.addr,
  3018. OSA_ADDR_LEN);
  3019. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3020. }
  3021. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3022. return 0;
  3023. }
  3024. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3025. {
  3026. int rc;
  3027. struct qeth_cmd_buffer *iob;
  3028. struct qeth_ipa_cmd *cmd;
  3029. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3030. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3031. sizeof(struct qeth_ipacmd_setadpparms));
  3032. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3033. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3034. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3035. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3036. card->dev->dev_addr, OSA_ADDR_LEN);
  3037. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3038. NULL);
  3039. return rc;
  3040. }
  3041. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3042. void qeth_tx_timeout(struct net_device *dev)
  3043. {
  3044. struct qeth_card *card;
  3045. card = dev->ml_priv;
  3046. card->stats.tx_errors++;
  3047. qeth_schedule_recovery(card);
  3048. }
  3049. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3050. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3051. {
  3052. struct qeth_card *card = dev->ml_priv;
  3053. int rc = 0;
  3054. switch (regnum) {
  3055. case MII_BMCR: /* Basic mode control register */
  3056. rc = BMCR_FULLDPLX;
  3057. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3058. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3059. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3060. rc |= BMCR_SPEED100;
  3061. break;
  3062. case MII_BMSR: /* Basic mode status register */
  3063. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3064. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3065. BMSR_100BASE4;
  3066. break;
  3067. case MII_PHYSID1: /* PHYS ID 1 */
  3068. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3069. dev->dev_addr[2];
  3070. rc = (rc >> 5) & 0xFFFF;
  3071. break;
  3072. case MII_PHYSID2: /* PHYS ID 2 */
  3073. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3074. break;
  3075. case MII_ADVERTISE: /* Advertisement control reg */
  3076. rc = ADVERTISE_ALL;
  3077. break;
  3078. case MII_LPA: /* Link partner ability reg */
  3079. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3080. LPA_100BASE4 | LPA_LPACK;
  3081. break;
  3082. case MII_EXPANSION: /* Expansion register */
  3083. break;
  3084. case MII_DCOUNTER: /* disconnect counter */
  3085. break;
  3086. case MII_FCSCOUNTER: /* false carrier counter */
  3087. break;
  3088. case MII_NWAYTEST: /* N-way auto-neg test register */
  3089. break;
  3090. case MII_RERRCOUNTER: /* rx error counter */
  3091. rc = card->stats.rx_errors;
  3092. break;
  3093. case MII_SREVISION: /* silicon revision */
  3094. break;
  3095. case MII_RESV1: /* reserved 1 */
  3096. break;
  3097. case MII_LBRERROR: /* loopback, rx, bypass error */
  3098. break;
  3099. case MII_PHYADDR: /* physical address */
  3100. break;
  3101. case MII_RESV2: /* reserved 2 */
  3102. break;
  3103. case MII_TPISTATUS: /* TPI status for 10mbps */
  3104. break;
  3105. case MII_NCONFIG: /* network interface config */
  3106. break;
  3107. default:
  3108. break;
  3109. }
  3110. return rc;
  3111. }
  3112. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3113. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3114. struct qeth_cmd_buffer *iob, int len,
  3115. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3116. unsigned long),
  3117. void *reply_param)
  3118. {
  3119. u16 s1, s2;
  3120. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3121. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3122. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3123. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3124. /* adjust PDU length fields in IPA_PDU_HEADER */
  3125. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3126. s2 = (u32) len;
  3127. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3128. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3129. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3130. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3131. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3132. reply_cb, reply_param);
  3133. }
  3134. static int qeth_snmp_command_cb(struct qeth_card *card,
  3135. struct qeth_reply *reply, unsigned long sdata)
  3136. {
  3137. struct qeth_ipa_cmd *cmd;
  3138. struct qeth_arp_query_info *qinfo;
  3139. struct qeth_snmp_cmd *snmp;
  3140. unsigned char *data;
  3141. __u16 data_len;
  3142. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3143. cmd = (struct qeth_ipa_cmd *) sdata;
  3144. data = (unsigned char *)((char *)cmd - reply->offset);
  3145. qinfo = (struct qeth_arp_query_info *) reply->param;
  3146. snmp = &cmd->data.setadapterparms.data.snmp;
  3147. if (cmd->hdr.return_code) {
  3148. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3149. return 0;
  3150. }
  3151. if (cmd->data.setadapterparms.hdr.return_code) {
  3152. cmd->hdr.return_code =
  3153. cmd->data.setadapterparms.hdr.return_code;
  3154. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3155. return 0;
  3156. }
  3157. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3158. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3159. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3160. else
  3161. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3162. /* check if there is enough room in userspace */
  3163. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3164. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3165. cmd->hdr.return_code = -ENOMEM;
  3166. return 0;
  3167. }
  3168. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3169. cmd->data.setadapterparms.hdr.used_total);
  3170. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3171. cmd->data.setadapterparms.hdr.seq_no);
  3172. /*copy entries to user buffer*/
  3173. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3174. memcpy(qinfo->udata + qinfo->udata_offset,
  3175. (char *)snmp,
  3176. data_len + offsetof(struct qeth_snmp_cmd, data));
  3177. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3178. } else {
  3179. memcpy(qinfo->udata + qinfo->udata_offset,
  3180. (char *)&snmp->request, data_len);
  3181. }
  3182. qinfo->udata_offset += data_len;
  3183. /* check if all replies received ... */
  3184. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3185. cmd->data.setadapterparms.hdr.used_total);
  3186. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3187. cmd->data.setadapterparms.hdr.seq_no);
  3188. if (cmd->data.setadapterparms.hdr.seq_no <
  3189. cmd->data.setadapterparms.hdr.used_total)
  3190. return 1;
  3191. return 0;
  3192. }
  3193. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3194. {
  3195. struct qeth_cmd_buffer *iob;
  3196. struct qeth_ipa_cmd *cmd;
  3197. struct qeth_snmp_ureq *ureq;
  3198. int req_len;
  3199. struct qeth_arp_query_info qinfo = {0, };
  3200. int rc = 0;
  3201. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3202. if (card->info.guestlan)
  3203. return -EOPNOTSUPP;
  3204. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3205. (!card->options.layer2)) {
  3206. return -EOPNOTSUPP;
  3207. }
  3208. /* skip 4 bytes (data_len struct member) to get req_len */
  3209. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3210. return -EFAULT;
  3211. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3212. if (!ureq) {
  3213. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3214. return -ENOMEM;
  3215. }
  3216. if (copy_from_user(ureq, udata,
  3217. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3218. kfree(ureq);
  3219. return -EFAULT;
  3220. }
  3221. qinfo.udata_len = ureq->hdr.data_len;
  3222. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3223. if (!qinfo.udata) {
  3224. kfree(ureq);
  3225. return -ENOMEM;
  3226. }
  3227. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3228. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3229. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3230. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3231. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3232. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3233. qeth_snmp_command_cb, (void *)&qinfo);
  3234. if (rc)
  3235. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3236. QETH_CARD_IFNAME(card), rc);
  3237. else {
  3238. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3239. rc = -EFAULT;
  3240. }
  3241. kfree(ureq);
  3242. kfree(qinfo.udata);
  3243. return rc;
  3244. }
  3245. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3246. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3247. {
  3248. switch (card->info.type) {
  3249. case QETH_CARD_TYPE_IQD:
  3250. return 2;
  3251. default:
  3252. return 0;
  3253. }
  3254. }
  3255. static int qeth_qdio_establish(struct qeth_card *card)
  3256. {
  3257. struct qdio_initialize init_data;
  3258. char *qib_param_field;
  3259. struct qdio_buffer **in_sbal_ptrs;
  3260. struct qdio_buffer **out_sbal_ptrs;
  3261. int i, j, k;
  3262. int rc = 0;
  3263. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3264. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3265. GFP_KERNEL);
  3266. if (!qib_param_field)
  3267. return -ENOMEM;
  3268. qeth_create_qib_param_field(card, qib_param_field);
  3269. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3270. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3271. GFP_KERNEL);
  3272. if (!in_sbal_ptrs) {
  3273. kfree(qib_param_field);
  3274. return -ENOMEM;
  3275. }
  3276. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3277. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3278. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3279. out_sbal_ptrs =
  3280. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3281. sizeof(void *), GFP_KERNEL);
  3282. if (!out_sbal_ptrs) {
  3283. kfree(in_sbal_ptrs);
  3284. kfree(qib_param_field);
  3285. return -ENOMEM;
  3286. }
  3287. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3288. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3289. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3290. card->qdio.out_qs[i]->bufs[j].buffer);
  3291. }
  3292. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3293. init_data.cdev = CARD_DDEV(card);
  3294. init_data.q_format = qeth_get_qdio_q_format(card);
  3295. init_data.qib_param_field_format = 0;
  3296. init_data.qib_param_field = qib_param_field;
  3297. init_data.no_input_qs = 1;
  3298. init_data.no_output_qs = card->qdio.no_out_queues;
  3299. init_data.input_handler = card->discipline.input_handler;
  3300. init_data.output_handler = card->discipline.output_handler;
  3301. init_data.int_parm = (unsigned long) card;
  3302. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3303. QDIO_OUTBOUND_0COPY_SBALS |
  3304. QDIO_USE_OUTBOUND_PCIS;
  3305. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3306. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3307. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3308. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3309. rc = qdio_initialize(&init_data);
  3310. if (rc)
  3311. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3312. }
  3313. kfree(out_sbal_ptrs);
  3314. kfree(in_sbal_ptrs);
  3315. kfree(qib_param_field);
  3316. return rc;
  3317. }
  3318. static void qeth_core_free_card(struct qeth_card *card)
  3319. {
  3320. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3321. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3322. qeth_clean_channel(&card->read);
  3323. qeth_clean_channel(&card->write);
  3324. if (card->dev)
  3325. free_netdev(card->dev);
  3326. kfree(card->ip_tbd_list);
  3327. qeth_free_qdio_buffers(card);
  3328. unregister_service_level(&card->qeth_service_level);
  3329. kfree(card);
  3330. }
  3331. static struct ccw_device_id qeth_ids[] = {
  3332. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3333. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3334. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3335. {},
  3336. };
  3337. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3338. static struct ccw_driver qeth_ccw_driver = {
  3339. .name = "qeth",
  3340. .ids = qeth_ids,
  3341. .probe = ccwgroup_probe_ccwdev,
  3342. .remove = ccwgroup_remove_ccwdev,
  3343. };
  3344. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3345. unsigned long driver_id)
  3346. {
  3347. return ccwgroup_create_from_string(root_dev, driver_id,
  3348. &qeth_ccw_driver, 3, buf);
  3349. }
  3350. int qeth_core_hardsetup_card(struct qeth_card *card)
  3351. {
  3352. struct qdio_ssqd_desc *ssqd;
  3353. int retries = 3;
  3354. int mpno = 0;
  3355. int rc;
  3356. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3357. atomic_set(&card->force_alloc_skb, 0);
  3358. retry:
  3359. if (retries < 3) {
  3360. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3361. dev_name(&card->gdev->dev));
  3362. ccw_device_set_offline(CARD_DDEV(card));
  3363. ccw_device_set_offline(CARD_WDEV(card));
  3364. ccw_device_set_offline(CARD_RDEV(card));
  3365. ccw_device_set_online(CARD_RDEV(card));
  3366. ccw_device_set_online(CARD_WDEV(card));
  3367. ccw_device_set_online(CARD_DDEV(card));
  3368. }
  3369. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3370. if (rc == -ERESTARTSYS) {
  3371. QETH_DBF_TEXT(SETUP, 2, "break1");
  3372. return rc;
  3373. } else if (rc) {
  3374. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3375. if (--retries < 0)
  3376. goto out;
  3377. else
  3378. goto retry;
  3379. }
  3380. rc = qeth_get_unitaddr(card);
  3381. if (rc) {
  3382. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3383. return rc;
  3384. }
  3385. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3386. if (!ssqd) {
  3387. rc = -ENOMEM;
  3388. goto out;
  3389. }
  3390. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3391. if (rc == 0)
  3392. mpno = ssqd->pcnt;
  3393. kfree(ssqd);
  3394. if (mpno)
  3395. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3396. if (card->info.portno > mpno) {
  3397. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3398. "\n.", CARD_BUS_ID(card), card->info.portno);
  3399. rc = -ENODEV;
  3400. goto out;
  3401. }
  3402. qeth_init_tokens(card);
  3403. qeth_init_func_level(card);
  3404. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3405. if (rc == -ERESTARTSYS) {
  3406. QETH_DBF_TEXT(SETUP, 2, "break2");
  3407. return rc;
  3408. } else if (rc) {
  3409. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3410. if (--retries < 0)
  3411. goto out;
  3412. else
  3413. goto retry;
  3414. }
  3415. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3416. if (rc == -ERESTARTSYS) {
  3417. QETH_DBF_TEXT(SETUP, 2, "break3");
  3418. return rc;
  3419. } else if (rc) {
  3420. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3421. if (--retries < 0)
  3422. goto out;
  3423. else
  3424. goto retry;
  3425. }
  3426. rc = qeth_mpc_initialize(card);
  3427. if (rc) {
  3428. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3429. goto out;
  3430. }
  3431. return 0;
  3432. out:
  3433. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3434. "an error on the device\n");
  3435. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3436. dev_name(&card->gdev->dev), rc);
  3437. return rc;
  3438. }
  3439. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3440. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3441. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3442. {
  3443. struct page *page = virt_to_page(element->addr);
  3444. if (*pskb == NULL) {
  3445. /* the upper protocol layers assume that there is data in the
  3446. * skb itself. Copy a small amount (64 bytes) to make them
  3447. * happy. */
  3448. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3449. if (!(*pskb))
  3450. return -ENOMEM;
  3451. skb_reserve(*pskb, ETH_HLEN);
  3452. if (data_len <= 64) {
  3453. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3454. data_len);
  3455. } else {
  3456. get_page(page);
  3457. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3458. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3459. data_len - 64);
  3460. (*pskb)->data_len += data_len - 64;
  3461. (*pskb)->len += data_len - 64;
  3462. (*pskb)->truesize += data_len - 64;
  3463. (*pfrag)++;
  3464. }
  3465. } else {
  3466. get_page(page);
  3467. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3468. (*pskb)->data_len += data_len;
  3469. (*pskb)->len += data_len;
  3470. (*pskb)->truesize += data_len;
  3471. (*pfrag)++;
  3472. }
  3473. return 0;
  3474. }
  3475. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3476. struct qdio_buffer *buffer,
  3477. struct qdio_buffer_element **__element, int *__offset,
  3478. struct qeth_hdr **hdr)
  3479. {
  3480. struct qdio_buffer_element *element = *__element;
  3481. int offset = *__offset;
  3482. struct sk_buff *skb = NULL;
  3483. int skb_len;
  3484. void *data_ptr;
  3485. int data_len;
  3486. int headroom = 0;
  3487. int use_rx_sg = 0;
  3488. int frag = 0;
  3489. /* qeth_hdr must not cross element boundaries */
  3490. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3491. if (qeth_is_last_sbale(element))
  3492. return NULL;
  3493. element++;
  3494. offset = 0;
  3495. if (element->length < sizeof(struct qeth_hdr))
  3496. return NULL;
  3497. }
  3498. *hdr = element->addr + offset;
  3499. offset += sizeof(struct qeth_hdr);
  3500. if (card->options.layer2) {
  3501. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3502. skb_len = (*hdr)->hdr.osn.pdu_length;
  3503. headroom = sizeof(struct qeth_hdr);
  3504. } else {
  3505. skb_len = (*hdr)->hdr.l2.pkt_length;
  3506. }
  3507. } else {
  3508. skb_len = (*hdr)->hdr.l3.length;
  3509. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3510. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3511. headroom = TR_HLEN;
  3512. else
  3513. headroom = ETH_HLEN;
  3514. }
  3515. if (!skb_len)
  3516. return NULL;
  3517. if ((skb_len >= card->options.rx_sg_cb) &&
  3518. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3519. (!atomic_read(&card->force_alloc_skb))) {
  3520. use_rx_sg = 1;
  3521. } else {
  3522. skb = dev_alloc_skb(skb_len + headroom);
  3523. if (!skb)
  3524. goto no_mem;
  3525. if (headroom)
  3526. skb_reserve(skb, headroom);
  3527. }
  3528. data_ptr = element->addr + offset;
  3529. while (skb_len) {
  3530. data_len = min(skb_len, (int)(element->length - offset));
  3531. if (data_len) {
  3532. if (use_rx_sg) {
  3533. if (qeth_create_skb_frag(element, &skb, offset,
  3534. &frag, data_len))
  3535. goto no_mem;
  3536. } else {
  3537. memcpy(skb_put(skb, data_len), data_ptr,
  3538. data_len);
  3539. }
  3540. }
  3541. skb_len -= data_len;
  3542. if (skb_len) {
  3543. if (qeth_is_last_sbale(element)) {
  3544. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3545. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3546. CARD_BUS_ID(card));
  3547. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3548. QETH_DBF_TEXT_(QERR, 2, "%s",
  3549. CARD_BUS_ID(card));
  3550. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3551. dev_kfree_skb_any(skb);
  3552. card->stats.rx_errors++;
  3553. return NULL;
  3554. }
  3555. element++;
  3556. offset = 0;
  3557. data_ptr = element->addr;
  3558. } else {
  3559. offset += data_len;
  3560. }
  3561. }
  3562. *__element = element;
  3563. *__offset = offset;
  3564. if (use_rx_sg && card->options.performance_stats) {
  3565. card->perf_stats.sg_skbs_rx++;
  3566. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3567. }
  3568. return skb;
  3569. no_mem:
  3570. if (net_ratelimit()) {
  3571. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3572. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3573. }
  3574. card->stats.rx_dropped++;
  3575. return NULL;
  3576. }
  3577. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3578. static void qeth_unregister_dbf_views(void)
  3579. {
  3580. int x;
  3581. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3582. debug_unregister(qeth_dbf[x].id);
  3583. qeth_dbf[x].id = NULL;
  3584. }
  3585. }
  3586. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3587. {
  3588. char dbf_txt_buf[32];
  3589. va_list args;
  3590. if (level > (qeth_dbf[dbf_nix].id)->level)
  3591. return;
  3592. va_start(args, fmt);
  3593. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3594. va_end(args);
  3595. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3596. }
  3597. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3598. static int qeth_register_dbf_views(void)
  3599. {
  3600. int ret;
  3601. int x;
  3602. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3603. /* register the areas */
  3604. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3605. qeth_dbf[x].pages,
  3606. qeth_dbf[x].areas,
  3607. qeth_dbf[x].len);
  3608. if (qeth_dbf[x].id == NULL) {
  3609. qeth_unregister_dbf_views();
  3610. return -ENOMEM;
  3611. }
  3612. /* register a view */
  3613. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3614. if (ret) {
  3615. qeth_unregister_dbf_views();
  3616. return ret;
  3617. }
  3618. /* set a passing level */
  3619. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3620. }
  3621. return 0;
  3622. }
  3623. int qeth_core_load_discipline(struct qeth_card *card,
  3624. enum qeth_discipline_id discipline)
  3625. {
  3626. int rc = 0;
  3627. switch (discipline) {
  3628. case QETH_DISCIPLINE_LAYER3:
  3629. card->discipline.ccwgdriver = try_then_request_module(
  3630. symbol_get(qeth_l3_ccwgroup_driver),
  3631. "qeth_l3");
  3632. break;
  3633. case QETH_DISCIPLINE_LAYER2:
  3634. card->discipline.ccwgdriver = try_then_request_module(
  3635. symbol_get(qeth_l2_ccwgroup_driver),
  3636. "qeth_l2");
  3637. break;
  3638. }
  3639. if (!card->discipline.ccwgdriver) {
  3640. dev_err(&card->gdev->dev, "There is no kernel module to "
  3641. "support discipline %d\n", discipline);
  3642. rc = -EINVAL;
  3643. }
  3644. return rc;
  3645. }
  3646. void qeth_core_free_discipline(struct qeth_card *card)
  3647. {
  3648. if (card->options.layer2)
  3649. symbol_put(qeth_l2_ccwgroup_driver);
  3650. else
  3651. symbol_put(qeth_l3_ccwgroup_driver);
  3652. card->discipline.ccwgdriver = NULL;
  3653. }
  3654. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3655. {
  3656. struct qeth_card *card;
  3657. struct device *dev;
  3658. int rc;
  3659. unsigned long flags;
  3660. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3661. dev = &gdev->dev;
  3662. if (!get_device(dev))
  3663. return -ENODEV;
  3664. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3665. card = qeth_alloc_card();
  3666. if (!card) {
  3667. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3668. rc = -ENOMEM;
  3669. goto err_dev;
  3670. }
  3671. card->read.ccwdev = gdev->cdev[0];
  3672. card->write.ccwdev = gdev->cdev[1];
  3673. card->data.ccwdev = gdev->cdev[2];
  3674. dev_set_drvdata(&gdev->dev, card);
  3675. card->gdev = gdev;
  3676. gdev->cdev[0]->handler = qeth_irq;
  3677. gdev->cdev[1]->handler = qeth_irq;
  3678. gdev->cdev[2]->handler = qeth_irq;
  3679. rc = qeth_determine_card_type(card);
  3680. if (rc) {
  3681. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3682. goto err_card;
  3683. }
  3684. rc = qeth_setup_card(card);
  3685. if (rc) {
  3686. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3687. goto err_card;
  3688. }
  3689. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3690. rc = qeth_core_create_osn_attributes(dev);
  3691. if (rc)
  3692. goto err_card;
  3693. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3694. if (rc) {
  3695. qeth_core_remove_osn_attributes(dev);
  3696. goto err_card;
  3697. }
  3698. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3699. if (rc) {
  3700. qeth_core_free_discipline(card);
  3701. qeth_core_remove_osn_attributes(dev);
  3702. goto err_card;
  3703. }
  3704. } else {
  3705. rc = qeth_core_create_device_attributes(dev);
  3706. if (rc)
  3707. goto err_card;
  3708. }
  3709. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3710. list_add_tail(&card->list, &qeth_core_card_list.list);
  3711. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3712. return 0;
  3713. err_card:
  3714. qeth_core_free_card(card);
  3715. err_dev:
  3716. put_device(dev);
  3717. return rc;
  3718. }
  3719. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3720. {
  3721. unsigned long flags;
  3722. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3723. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3724. if (card->discipline.ccwgdriver) {
  3725. card->discipline.ccwgdriver->remove(gdev);
  3726. qeth_core_free_discipline(card);
  3727. }
  3728. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3729. qeth_core_remove_osn_attributes(&gdev->dev);
  3730. } else {
  3731. qeth_core_remove_device_attributes(&gdev->dev);
  3732. }
  3733. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3734. list_del(&card->list);
  3735. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3736. qeth_core_free_card(card);
  3737. dev_set_drvdata(&gdev->dev, NULL);
  3738. put_device(&gdev->dev);
  3739. return;
  3740. }
  3741. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3742. {
  3743. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3744. int rc = 0;
  3745. int def_discipline;
  3746. if (!card->discipline.ccwgdriver) {
  3747. if (card->info.type == QETH_CARD_TYPE_IQD)
  3748. def_discipline = QETH_DISCIPLINE_LAYER3;
  3749. else
  3750. def_discipline = QETH_DISCIPLINE_LAYER2;
  3751. rc = qeth_core_load_discipline(card, def_discipline);
  3752. if (rc)
  3753. goto err;
  3754. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3755. if (rc)
  3756. goto err;
  3757. }
  3758. rc = card->discipline.ccwgdriver->set_online(gdev);
  3759. err:
  3760. return rc;
  3761. }
  3762. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3763. {
  3764. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3765. return card->discipline.ccwgdriver->set_offline(gdev);
  3766. }
  3767. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3768. {
  3769. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3770. if (card->discipline.ccwgdriver &&
  3771. card->discipline.ccwgdriver->shutdown)
  3772. card->discipline.ccwgdriver->shutdown(gdev);
  3773. }
  3774. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3775. {
  3776. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3777. if (card->discipline.ccwgdriver &&
  3778. card->discipline.ccwgdriver->prepare)
  3779. return card->discipline.ccwgdriver->prepare(gdev);
  3780. return 0;
  3781. }
  3782. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3783. {
  3784. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3785. if (card->discipline.ccwgdriver &&
  3786. card->discipline.ccwgdriver->complete)
  3787. card->discipline.ccwgdriver->complete(gdev);
  3788. }
  3789. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3790. {
  3791. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3792. if (card->discipline.ccwgdriver &&
  3793. card->discipline.ccwgdriver->freeze)
  3794. return card->discipline.ccwgdriver->freeze(gdev);
  3795. return 0;
  3796. }
  3797. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3798. {
  3799. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3800. if (card->discipline.ccwgdriver &&
  3801. card->discipline.ccwgdriver->thaw)
  3802. return card->discipline.ccwgdriver->thaw(gdev);
  3803. return 0;
  3804. }
  3805. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3806. {
  3807. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3808. if (card->discipline.ccwgdriver &&
  3809. card->discipline.ccwgdriver->restore)
  3810. return card->discipline.ccwgdriver->restore(gdev);
  3811. return 0;
  3812. }
  3813. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3814. .owner = THIS_MODULE,
  3815. .name = "qeth",
  3816. .driver_id = 0xD8C5E3C8,
  3817. .probe = qeth_core_probe_device,
  3818. .remove = qeth_core_remove_device,
  3819. .set_online = qeth_core_set_online,
  3820. .set_offline = qeth_core_set_offline,
  3821. .shutdown = qeth_core_shutdown,
  3822. .prepare = qeth_core_prepare,
  3823. .complete = qeth_core_complete,
  3824. .freeze = qeth_core_freeze,
  3825. .thaw = qeth_core_thaw,
  3826. .restore = qeth_core_restore,
  3827. };
  3828. static ssize_t
  3829. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3830. size_t count)
  3831. {
  3832. int err;
  3833. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3834. qeth_core_ccwgroup_driver.driver_id);
  3835. if (err)
  3836. return err;
  3837. else
  3838. return count;
  3839. }
  3840. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3841. static struct {
  3842. const char str[ETH_GSTRING_LEN];
  3843. } qeth_ethtool_stats_keys[] = {
  3844. /* 0 */{"rx skbs"},
  3845. {"rx buffers"},
  3846. {"tx skbs"},
  3847. {"tx buffers"},
  3848. {"tx skbs no packing"},
  3849. {"tx buffers no packing"},
  3850. {"tx skbs packing"},
  3851. {"tx buffers packing"},
  3852. {"tx sg skbs"},
  3853. {"tx sg frags"},
  3854. /* 10 */{"rx sg skbs"},
  3855. {"rx sg frags"},
  3856. {"rx sg page allocs"},
  3857. {"tx large kbytes"},
  3858. {"tx large count"},
  3859. {"tx pk state ch n->p"},
  3860. {"tx pk state ch p->n"},
  3861. {"tx pk watermark low"},
  3862. {"tx pk watermark high"},
  3863. {"queue 0 buffer usage"},
  3864. /* 20 */{"queue 1 buffer usage"},
  3865. {"queue 2 buffer usage"},
  3866. {"queue 3 buffer usage"},
  3867. {"rx handler time"},
  3868. {"rx handler count"},
  3869. {"rx do_QDIO time"},
  3870. {"rx do_QDIO count"},
  3871. {"tx handler time"},
  3872. {"tx handler count"},
  3873. {"tx time"},
  3874. /* 30 */{"tx count"},
  3875. {"tx do_QDIO time"},
  3876. {"tx do_QDIO count"},
  3877. {"tx csum"},
  3878. };
  3879. int qeth_core_get_stats_count(struct net_device *dev)
  3880. {
  3881. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3882. }
  3883. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3884. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3885. struct ethtool_stats *stats, u64 *data)
  3886. {
  3887. struct qeth_card *card = dev->ml_priv;
  3888. data[0] = card->stats.rx_packets -
  3889. card->perf_stats.initial_rx_packets;
  3890. data[1] = card->perf_stats.bufs_rec;
  3891. data[2] = card->stats.tx_packets -
  3892. card->perf_stats.initial_tx_packets;
  3893. data[3] = card->perf_stats.bufs_sent;
  3894. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3895. - card->perf_stats.skbs_sent_pack;
  3896. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3897. data[6] = card->perf_stats.skbs_sent_pack;
  3898. data[7] = card->perf_stats.bufs_sent_pack;
  3899. data[8] = card->perf_stats.sg_skbs_sent;
  3900. data[9] = card->perf_stats.sg_frags_sent;
  3901. data[10] = card->perf_stats.sg_skbs_rx;
  3902. data[11] = card->perf_stats.sg_frags_rx;
  3903. data[12] = card->perf_stats.sg_alloc_page_rx;
  3904. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3905. data[14] = card->perf_stats.large_send_cnt;
  3906. data[15] = card->perf_stats.sc_dp_p;
  3907. data[16] = card->perf_stats.sc_p_dp;
  3908. data[17] = QETH_LOW_WATERMARK_PACK;
  3909. data[18] = QETH_HIGH_WATERMARK_PACK;
  3910. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3911. data[20] = (card->qdio.no_out_queues > 1) ?
  3912. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3913. data[21] = (card->qdio.no_out_queues > 2) ?
  3914. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3915. data[22] = (card->qdio.no_out_queues > 3) ?
  3916. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3917. data[23] = card->perf_stats.inbound_time;
  3918. data[24] = card->perf_stats.inbound_cnt;
  3919. data[25] = card->perf_stats.inbound_do_qdio_time;
  3920. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3921. data[27] = card->perf_stats.outbound_handler_time;
  3922. data[28] = card->perf_stats.outbound_handler_cnt;
  3923. data[29] = card->perf_stats.outbound_time;
  3924. data[30] = card->perf_stats.outbound_cnt;
  3925. data[31] = card->perf_stats.outbound_do_qdio_time;
  3926. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3927. data[33] = card->perf_stats.tx_csum;
  3928. }
  3929. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3930. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3931. {
  3932. switch (stringset) {
  3933. case ETH_SS_STATS:
  3934. memcpy(data, &qeth_ethtool_stats_keys,
  3935. sizeof(qeth_ethtool_stats_keys));
  3936. break;
  3937. default:
  3938. WARN_ON(1);
  3939. break;
  3940. }
  3941. }
  3942. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3943. void qeth_core_get_drvinfo(struct net_device *dev,
  3944. struct ethtool_drvinfo *info)
  3945. {
  3946. struct qeth_card *card = dev->ml_priv;
  3947. if (card->options.layer2)
  3948. strcpy(info->driver, "qeth_l2");
  3949. else
  3950. strcpy(info->driver, "qeth_l3");
  3951. strcpy(info->version, "1.0");
  3952. strcpy(info->fw_version, card->info.mcl_level);
  3953. sprintf(info->bus_info, "%s/%s/%s",
  3954. CARD_RDEV_ID(card),
  3955. CARD_WDEV_ID(card),
  3956. CARD_DDEV_ID(card));
  3957. }
  3958. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3959. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3960. struct ethtool_cmd *ecmd)
  3961. {
  3962. struct qeth_card *card = netdev->ml_priv;
  3963. enum qeth_link_types link_type;
  3964. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3965. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3966. else
  3967. link_type = card->info.link_type;
  3968. ecmd->transceiver = XCVR_INTERNAL;
  3969. ecmd->supported = SUPPORTED_Autoneg;
  3970. ecmd->advertising = ADVERTISED_Autoneg;
  3971. ecmd->duplex = DUPLEX_FULL;
  3972. ecmd->autoneg = AUTONEG_ENABLE;
  3973. switch (link_type) {
  3974. case QETH_LINK_TYPE_FAST_ETH:
  3975. case QETH_LINK_TYPE_LANE_ETH100:
  3976. ecmd->supported |= SUPPORTED_10baseT_Half |
  3977. SUPPORTED_10baseT_Full |
  3978. SUPPORTED_100baseT_Half |
  3979. SUPPORTED_100baseT_Full |
  3980. SUPPORTED_TP;
  3981. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3982. ADVERTISED_10baseT_Full |
  3983. ADVERTISED_100baseT_Half |
  3984. ADVERTISED_100baseT_Full |
  3985. ADVERTISED_TP;
  3986. ecmd->speed = SPEED_100;
  3987. ecmd->port = PORT_TP;
  3988. break;
  3989. case QETH_LINK_TYPE_GBIT_ETH:
  3990. case QETH_LINK_TYPE_LANE_ETH1000:
  3991. ecmd->supported |= SUPPORTED_10baseT_Half |
  3992. SUPPORTED_10baseT_Full |
  3993. SUPPORTED_100baseT_Half |
  3994. SUPPORTED_100baseT_Full |
  3995. SUPPORTED_1000baseT_Half |
  3996. SUPPORTED_1000baseT_Full |
  3997. SUPPORTED_FIBRE;
  3998. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3999. ADVERTISED_10baseT_Full |
  4000. ADVERTISED_100baseT_Half |
  4001. ADVERTISED_100baseT_Full |
  4002. ADVERTISED_1000baseT_Half |
  4003. ADVERTISED_1000baseT_Full |
  4004. ADVERTISED_FIBRE;
  4005. ecmd->speed = SPEED_1000;
  4006. ecmd->port = PORT_FIBRE;
  4007. break;
  4008. case QETH_LINK_TYPE_10GBIT_ETH:
  4009. ecmd->supported |= SUPPORTED_10baseT_Half |
  4010. SUPPORTED_10baseT_Full |
  4011. SUPPORTED_100baseT_Half |
  4012. SUPPORTED_100baseT_Full |
  4013. SUPPORTED_1000baseT_Half |
  4014. SUPPORTED_1000baseT_Full |
  4015. SUPPORTED_10000baseT_Full |
  4016. SUPPORTED_FIBRE;
  4017. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4018. ADVERTISED_10baseT_Full |
  4019. ADVERTISED_100baseT_Half |
  4020. ADVERTISED_100baseT_Full |
  4021. ADVERTISED_1000baseT_Half |
  4022. ADVERTISED_1000baseT_Full |
  4023. ADVERTISED_10000baseT_Full |
  4024. ADVERTISED_FIBRE;
  4025. ecmd->speed = SPEED_10000;
  4026. ecmd->port = PORT_FIBRE;
  4027. break;
  4028. default:
  4029. ecmd->supported |= SUPPORTED_10baseT_Half |
  4030. SUPPORTED_10baseT_Full |
  4031. SUPPORTED_TP;
  4032. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4033. ADVERTISED_10baseT_Full |
  4034. ADVERTISED_TP;
  4035. ecmd->speed = SPEED_10;
  4036. ecmd->port = PORT_TP;
  4037. }
  4038. return 0;
  4039. }
  4040. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4041. static int __init qeth_core_init(void)
  4042. {
  4043. int rc;
  4044. pr_info("loading core functions\n");
  4045. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4046. rwlock_init(&qeth_core_card_list.rwlock);
  4047. rc = qeth_register_dbf_views();
  4048. if (rc)
  4049. goto out_err;
  4050. rc = ccw_driver_register(&qeth_ccw_driver);
  4051. if (rc)
  4052. goto ccw_err;
  4053. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4054. if (rc)
  4055. goto ccwgroup_err;
  4056. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4057. &driver_attr_group);
  4058. if (rc)
  4059. goto driver_err;
  4060. qeth_core_root_dev = root_device_register("qeth");
  4061. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4062. if (rc)
  4063. goto register_err;
  4064. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4065. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4066. if (!qeth_core_header_cache) {
  4067. rc = -ENOMEM;
  4068. goto slab_err;
  4069. }
  4070. return 0;
  4071. slab_err:
  4072. root_device_unregister(qeth_core_root_dev);
  4073. register_err:
  4074. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4075. &driver_attr_group);
  4076. driver_err:
  4077. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4078. ccwgroup_err:
  4079. ccw_driver_unregister(&qeth_ccw_driver);
  4080. ccw_err:
  4081. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4082. qeth_unregister_dbf_views();
  4083. out_err:
  4084. pr_err("Initializing the qeth device driver failed\n");
  4085. return rc;
  4086. }
  4087. static void __exit qeth_core_exit(void)
  4088. {
  4089. root_device_unregister(qeth_core_root_dev);
  4090. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4091. &driver_attr_group);
  4092. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4093. ccw_driver_unregister(&qeth_ccw_driver);
  4094. kmem_cache_destroy(qeth_core_header_cache);
  4095. qeth_unregister_dbf_views();
  4096. pr_info("core functions removed\n");
  4097. }
  4098. module_init(qeth_core_init);
  4099. module_exit(qeth_core_exit);
  4100. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4101. MODULE_DESCRIPTION("qeth core functions");
  4102. MODULE_LICENSE("GPL");