early_printk_intel_mid.c 2.4 KB

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  1. /*
  2. * early_printk_intel_mid.c - early consoles for Intel MID platforms
  3. *
  4. * Copyright (c) 2008-2010, Intel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; version 2
  9. * of the License.
  10. */
  11. /*
  12. * This file implements early console named hsu.
  13. * hsu is based on a High Speed UART device which only exists in the Medfield
  14. * platform
  15. */
  16. #include <linux/serial_reg.h>
  17. #include <linux/serial_mfd.h>
  18. #include <linux/console.h>
  19. #include <linux/kernel.h>
  20. #include <linux/delay.h>
  21. #include <linux/io.h>
  22. #include <asm/fixmap.h>
  23. #include <asm/pgtable.h>
  24. #include <asm/intel-mid.h>
  25. /*
  26. * Following is the early console based on Medfield HSU (High
  27. * Speed UART) device.
  28. */
  29. #define HSU_PORT_BASE 0xffa28080
  30. static void __iomem *phsu;
  31. void hsu_early_console_init(const char *s)
  32. {
  33. unsigned long paddr, port = 0;
  34. u8 lcr;
  35. /*
  36. * Select the early HSU console port if specified by user in the
  37. * kernel command line.
  38. */
  39. if (*s && !kstrtoul(s, 10, &port))
  40. port = clamp_val(port, 0, 2);
  41. paddr = HSU_PORT_BASE + port * 0x80;
  42. phsu = (void __iomem *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
  43. /* Disable FIFO */
  44. writeb(0x0, phsu + UART_FCR);
  45. /* Set to default 115200 bps, 8n1 */
  46. lcr = readb(phsu + UART_LCR);
  47. writeb((0x80 | lcr), phsu + UART_LCR);
  48. writeb(0x18, phsu + UART_DLL);
  49. writeb(lcr, phsu + UART_LCR);
  50. writel(0x3600, phsu + UART_MUL*4);
  51. writeb(0x8, phsu + UART_MCR);
  52. writeb(0x7, phsu + UART_FCR);
  53. writeb(0x3, phsu + UART_LCR);
  54. /* Clear IRQ status */
  55. readb(phsu + UART_LSR);
  56. readb(phsu + UART_RX);
  57. readb(phsu + UART_IIR);
  58. readb(phsu + UART_MSR);
  59. /* Enable FIFO */
  60. writeb(0x7, phsu + UART_FCR);
  61. }
  62. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  63. static void early_hsu_putc(char ch)
  64. {
  65. unsigned int timeout = 10000; /* 10ms */
  66. u8 status;
  67. while (--timeout) {
  68. status = readb(phsu + UART_LSR);
  69. if (status & BOTH_EMPTY)
  70. break;
  71. udelay(1);
  72. }
  73. /* Only write the char when there was no timeout */
  74. if (timeout)
  75. writeb(ch, phsu + UART_TX);
  76. }
  77. static void early_hsu_write(struct console *con, const char *str, unsigned n)
  78. {
  79. int i;
  80. for (i = 0; i < n && *str; i++) {
  81. if (*str == '\n')
  82. early_hsu_putc('\r');
  83. early_hsu_putc(*str);
  84. str++;
  85. }
  86. }
  87. struct console early_hsu_console = {
  88. .name = "earlyhsu",
  89. .write = early_hsu_write,
  90. .flags = CON_PRINTBUFFER,
  91. .index = -1,
  92. };