aesni-intel_glue.c 45 KB

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  1. /*
  2. * Support for Intel AES-NI instructions. This file contains glue
  3. * code, the real AES implementation is in intel-aes_asm.S.
  4. *
  5. * Copyright (C) 2008, Intel Corp.
  6. * Author: Huang Ying <ying.huang@intel.com>
  7. *
  8. * Added RFC4106 AES-GCM support for 128-bit keys under the AEAD
  9. * interface for 64-bit kernels.
  10. * Authors: Adrian Hoban <adrian.hoban@intel.com>
  11. * Gabriele Paoloni <gabriele.paoloni@intel.com>
  12. * Tadeusz Struk (tadeusz.struk@intel.com)
  13. * Aidan O'Mahony (aidan.o.mahony@intel.com)
  14. * Copyright (c) 2010, Intel Corporation.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. */
  21. #include <linux/hardirq.h>
  22. #include <linux/types.h>
  23. #include <linux/crypto.h>
  24. #include <linux/module.h>
  25. #include <linux/err.h>
  26. #include <crypto/algapi.h>
  27. #include <crypto/aes.h>
  28. #include <crypto/cryptd.h>
  29. #include <crypto/ctr.h>
  30. #include <crypto/b128ops.h>
  31. #include <crypto/lrw.h>
  32. #include <crypto/xts.h>
  33. #include <asm/cpu_device_id.h>
  34. #include <asm/i387.h>
  35. #include <asm/crypto/aes.h>
  36. #include <crypto/ablk_helper.h>
  37. #include <crypto/scatterwalk.h>
  38. #include <crypto/internal/aead.h>
  39. #include <linux/workqueue.h>
  40. #include <linux/spinlock.h>
  41. #ifdef CONFIG_X86_64
  42. #include <asm/crypto/glue_helper.h>
  43. #endif
  44. /* This data is stored at the end of the crypto_tfm struct.
  45. * It's a type of per "session" data storage location.
  46. * This needs to be 16 byte aligned.
  47. */
  48. struct aesni_rfc4106_gcm_ctx {
  49. u8 hash_subkey[16];
  50. struct crypto_aes_ctx aes_key_expanded;
  51. u8 nonce[4];
  52. struct cryptd_aead *cryptd_tfm;
  53. };
  54. struct aesni_gcm_set_hash_subkey_result {
  55. int err;
  56. struct completion completion;
  57. };
  58. struct aesni_hash_subkey_req_data {
  59. u8 iv[16];
  60. struct aesni_gcm_set_hash_subkey_result result;
  61. struct scatterlist sg;
  62. };
  63. #define AESNI_ALIGN (16)
  64. #define AES_BLOCK_MASK (~(AES_BLOCK_SIZE-1))
  65. #define RFC4106_HASH_SUBKEY_SIZE 16
  66. struct aesni_lrw_ctx {
  67. struct lrw_table_ctx lrw_table;
  68. u8 raw_aes_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  69. };
  70. struct aesni_xts_ctx {
  71. u8 raw_tweak_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  72. u8 raw_crypt_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  73. };
  74. asmlinkage int aesni_set_key(struct crypto_aes_ctx *ctx, const u8 *in_key,
  75. unsigned int key_len);
  76. asmlinkage void aesni_enc(struct crypto_aes_ctx *ctx, u8 *out,
  77. const u8 *in);
  78. asmlinkage void aesni_dec(struct crypto_aes_ctx *ctx, u8 *out,
  79. const u8 *in);
  80. asmlinkage void aesni_ecb_enc(struct crypto_aes_ctx *ctx, u8 *out,
  81. const u8 *in, unsigned int len);
  82. asmlinkage void aesni_ecb_dec(struct crypto_aes_ctx *ctx, u8 *out,
  83. const u8 *in, unsigned int len);
  84. asmlinkage void aesni_cbc_enc(struct crypto_aes_ctx *ctx, u8 *out,
  85. const u8 *in, unsigned int len, u8 *iv);
  86. asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
  87. const u8 *in, unsigned int len, u8 *iv);
  88. int crypto_fpu_init(void);
  89. void crypto_fpu_exit(void);
  90. #define AVX_GEN2_OPTSIZE 640
  91. #define AVX_GEN4_OPTSIZE 4096
  92. #ifdef CONFIG_X86_64
  93. static void (*aesni_ctr_enc_tfm)(struct crypto_aes_ctx *ctx, u8 *out,
  94. const u8 *in, unsigned int len, u8 *iv);
  95. asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out,
  96. const u8 *in, unsigned int len, u8 *iv);
  97. asmlinkage void aesni_xts_crypt8(struct crypto_aes_ctx *ctx, u8 *out,
  98. const u8 *in, bool enc, u8 *iv);
  99. /* asmlinkage void aesni_gcm_enc()
  100. * void *ctx, AES Key schedule. Starts on a 16 byte boundary.
  101. * u8 *out, Ciphertext output. Encrypt in-place is allowed.
  102. * const u8 *in, Plaintext input
  103. * unsigned long plaintext_len, Length of data in bytes for encryption.
  104. * u8 *iv, Pre-counter block j0: 4 byte salt (from Security Association)
  105. * concatenated with 8 byte Initialisation Vector (from IPSec ESP
  106. * Payload) concatenated with 0x00000001. 16-byte aligned pointer.
  107. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  108. * const u8 *aad, Additional Authentication Data (AAD)
  109. * unsigned long aad_len, Length of AAD in bytes. With RFC4106 this
  110. * is going to be 8 or 12 bytes
  111. * u8 *auth_tag, Authenticated Tag output.
  112. * unsigned long auth_tag_len), Authenticated Tag Length in bytes.
  113. * Valid values are 16 (most likely), 12 or 8.
  114. */
  115. asmlinkage void aesni_gcm_enc(void *ctx, u8 *out,
  116. const u8 *in, unsigned long plaintext_len, u8 *iv,
  117. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  118. u8 *auth_tag, unsigned long auth_tag_len);
  119. /* asmlinkage void aesni_gcm_dec()
  120. * void *ctx, AES Key schedule. Starts on a 16 byte boundary.
  121. * u8 *out, Plaintext output. Decrypt in-place is allowed.
  122. * const u8 *in, Ciphertext input
  123. * unsigned long ciphertext_len, Length of data in bytes for decryption.
  124. * u8 *iv, Pre-counter block j0: 4 byte salt (from Security Association)
  125. * concatenated with 8 byte Initialisation Vector (from IPSec ESP
  126. * Payload) concatenated with 0x00000001. 16-byte aligned pointer.
  127. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  128. * const u8 *aad, Additional Authentication Data (AAD)
  129. * unsigned long aad_len, Length of AAD in bytes. With RFC4106 this is going
  130. * to be 8 or 12 bytes
  131. * u8 *auth_tag, Authenticated Tag output.
  132. * unsigned long auth_tag_len) Authenticated Tag Length in bytes.
  133. * Valid values are 16 (most likely), 12 or 8.
  134. */
  135. asmlinkage void aesni_gcm_dec(void *ctx, u8 *out,
  136. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  137. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  138. u8 *auth_tag, unsigned long auth_tag_len);
  139. #ifdef CONFIG_AS_AVX
  140. asmlinkage void aes_ctr_enc_128_avx_by8(const u8 *in, u8 *iv,
  141. void *keys, u8 *out, unsigned int num_bytes);
  142. asmlinkage void aes_ctr_enc_192_avx_by8(const u8 *in, u8 *iv,
  143. void *keys, u8 *out, unsigned int num_bytes);
  144. asmlinkage void aes_ctr_enc_256_avx_by8(const u8 *in, u8 *iv,
  145. void *keys, u8 *out, unsigned int num_bytes);
  146. /*
  147. * asmlinkage void aesni_gcm_precomp_avx_gen2()
  148. * gcm_data *my_ctx_data, context data
  149. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  150. */
  151. asmlinkage void aesni_gcm_precomp_avx_gen2(void *my_ctx_data, u8 *hash_subkey);
  152. asmlinkage void aesni_gcm_enc_avx_gen2(void *ctx, u8 *out,
  153. const u8 *in, unsigned long plaintext_len, u8 *iv,
  154. const u8 *aad, unsigned long aad_len,
  155. u8 *auth_tag, unsigned long auth_tag_len);
  156. asmlinkage void aesni_gcm_dec_avx_gen2(void *ctx, u8 *out,
  157. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  158. const u8 *aad, unsigned long aad_len,
  159. u8 *auth_tag, unsigned long auth_tag_len);
  160. static void aesni_gcm_enc_avx(void *ctx, u8 *out,
  161. const u8 *in, unsigned long plaintext_len, u8 *iv,
  162. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  163. u8 *auth_tag, unsigned long auth_tag_len)
  164. {
  165. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  166. if ((plaintext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)){
  167. aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
  168. aad_len, auth_tag, auth_tag_len);
  169. } else {
  170. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  171. aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
  172. aad_len, auth_tag, auth_tag_len);
  173. }
  174. }
  175. static void aesni_gcm_dec_avx(void *ctx, u8 *out,
  176. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  177. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  178. u8 *auth_tag, unsigned long auth_tag_len)
  179. {
  180. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  181. if ((ciphertext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  182. aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey, aad,
  183. aad_len, auth_tag, auth_tag_len);
  184. } else {
  185. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  186. aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
  187. aad_len, auth_tag, auth_tag_len);
  188. }
  189. }
  190. #endif
  191. #ifdef CONFIG_AS_AVX2
  192. /*
  193. * asmlinkage void aesni_gcm_precomp_avx_gen4()
  194. * gcm_data *my_ctx_data, context data
  195. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  196. */
  197. asmlinkage void aesni_gcm_precomp_avx_gen4(void *my_ctx_data, u8 *hash_subkey);
  198. asmlinkage void aesni_gcm_enc_avx_gen4(void *ctx, u8 *out,
  199. const u8 *in, unsigned long plaintext_len, u8 *iv,
  200. const u8 *aad, unsigned long aad_len,
  201. u8 *auth_tag, unsigned long auth_tag_len);
  202. asmlinkage void aesni_gcm_dec_avx_gen4(void *ctx, u8 *out,
  203. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  204. const u8 *aad, unsigned long aad_len,
  205. u8 *auth_tag, unsigned long auth_tag_len);
  206. static void aesni_gcm_enc_avx2(void *ctx, u8 *out,
  207. const u8 *in, unsigned long plaintext_len, u8 *iv,
  208. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  209. u8 *auth_tag, unsigned long auth_tag_len)
  210. {
  211. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  212. if ((plaintext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  213. aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
  214. aad_len, auth_tag, auth_tag_len);
  215. } else if (plaintext_len < AVX_GEN4_OPTSIZE) {
  216. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  217. aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
  218. aad_len, auth_tag, auth_tag_len);
  219. } else {
  220. aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
  221. aesni_gcm_enc_avx_gen4(ctx, out, in, plaintext_len, iv, aad,
  222. aad_len, auth_tag, auth_tag_len);
  223. }
  224. }
  225. static void aesni_gcm_dec_avx2(void *ctx, u8 *out,
  226. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  227. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  228. u8 *auth_tag, unsigned long auth_tag_len)
  229. {
  230. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  231. if ((ciphertext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  232. aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey,
  233. aad, aad_len, auth_tag, auth_tag_len);
  234. } else if (ciphertext_len < AVX_GEN4_OPTSIZE) {
  235. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  236. aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
  237. aad_len, auth_tag, auth_tag_len);
  238. } else {
  239. aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
  240. aesni_gcm_dec_avx_gen4(ctx, out, in, ciphertext_len, iv, aad,
  241. aad_len, auth_tag, auth_tag_len);
  242. }
  243. }
  244. #endif
  245. static void (*aesni_gcm_enc_tfm)(void *ctx, u8 *out,
  246. const u8 *in, unsigned long plaintext_len, u8 *iv,
  247. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  248. u8 *auth_tag, unsigned long auth_tag_len);
  249. static void (*aesni_gcm_dec_tfm)(void *ctx, u8 *out,
  250. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  251. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  252. u8 *auth_tag, unsigned long auth_tag_len);
  253. static inline struct
  254. aesni_rfc4106_gcm_ctx *aesni_rfc4106_gcm_ctx_get(struct crypto_aead *tfm)
  255. {
  256. return
  257. (struct aesni_rfc4106_gcm_ctx *)
  258. PTR_ALIGN((u8 *)
  259. crypto_tfm_ctx(crypto_aead_tfm(tfm)), AESNI_ALIGN);
  260. }
  261. #endif
  262. static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx)
  263. {
  264. unsigned long addr = (unsigned long)raw_ctx;
  265. unsigned long align = AESNI_ALIGN;
  266. if (align <= crypto_tfm_ctx_alignment())
  267. align = 1;
  268. return (struct crypto_aes_ctx *)ALIGN(addr, align);
  269. }
  270. static int aes_set_key_common(struct crypto_tfm *tfm, void *raw_ctx,
  271. const u8 *in_key, unsigned int key_len)
  272. {
  273. struct crypto_aes_ctx *ctx = aes_ctx(raw_ctx);
  274. u32 *flags = &tfm->crt_flags;
  275. int err;
  276. if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
  277. key_len != AES_KEYSIZE_256) {
  278. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  279. return -EINVAL;
  280. }
  281. if (!irq_fpu_usable())
  282. err = crypto_aes_expand_key(ctx, in_key, key_len);
  283. else {
  284. kernel_fpu_begin();
  285. err = aesni_set_key(ctx, in_key, key_len);
  286. kernel_fpu_end();
  287. }
  288. return err;
  289. }
  290. static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
  291. unsigned int key_len)
  292. {
  293. return aes_set_key_common(tfm, crypto_tfm_ctx(tfm), in_key, key_len);
  294. }
  295. static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  296. {
  297. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  298. if (!irq_fpu_usable())
  299. crypto_aes_encrypt_x86(ctx, dst, src);
  300. else {
  301. kernel_fpu_begin();
  302. aesni_enc(ctx, dst, src);
  303. kernel_fpu_end();
  304. }
  305. }
  306. static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  307. {
  308. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  309. if (!irq_fpu_usable())
  310. crypto_aes_decrypt_x86(ctx, dst, src);
  311. else {
  312. kernel_fpu_begin();
  313. aesni_dec(ctx, dst, src);
  314. kernel_fpu_end();
  315. }
  316. }
  317. static void __aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  318. {
  319. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  320. aesni_enc(ctx, dst, src);
  321. }
  322. static void __aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  323. {
  324. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  325. aesni_dec(ctx, dst, src);
  326. }
  327. static int ecb_encrypt(struct blkcipher_desc *desc,
  328. struct scatterlist *dst, struct scatterlist *src,
  329. unsigned int nbytes)
  330. {
  331. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  332. struct blkcipher_walk walk;
  333. int err;
  334. blkcipher_walk_init(&walk, dst, src, nbytes);
  335. err = blkcipher_walk_virt(desc, &walk);
  336. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  337. kernel_fpu_begin();
  338. while ((nbytes = walk.nbytes)) {
  339. aesni_ecb_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  340. nbytes & AES_BLOCK_MASK);
  341. nbytes &= AES_BLOCK_SIZE - 1;
  342. err = blkcipher_walk_done(desc, &walk, nbytes);
  343. }
  344. kernel_fpu_end();
  345. return err;
  346. }
  347. static int ecb_decrypt(struct blkcipher_desc *desc,
  348. struct scatterlist *dst, struct scatterlist *src,
  349. unsigned int nbytes)
  350. {
  351. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  352. struct blkcipher_walk walk;
  353. int err;
  354. blkcipher_walk_init(&walk, dst, src, nbytes);
  355. err = blkcipher_walk_virt(desc, &walk);
  356. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  357. kernel_fpu_begin();
  358. while ((nbytes = walk.nbytes)) {
  359. aesni_ecb_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  360. nbytes & AES_BLOCK_MASK);
  361. nbytes &= AES_BLOCK_SIZE - 1;
  362. err = blkcipher_walk_done(desc, &walk, nbytes);
  363. }
  364. kernel_fpu_end();
  365. return err;
  366. }
  367. static int cbc_encrypt(struct blkcipher_desc *desc,
  368. struct scatterlist *dst, struct scatterlist *src,
  369. unsigned int nbytes)
  370. {
  371. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  372. struct blkcipher_walk walk;
  373. int err;
  374. blkcipher_walk_init(&walk, dst, src, nbytes);
  375. err = blkcipher_walk_virt(desc, &walk);
  376. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  377. kernel_fpu_begin();
  378. while ((nbytes = walk.nbytes)) {
  379. aesni_cbc_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  380. nbytes & AES_BLOCK_MASK, walk.iv);
  381. nbytes &= AES_BLOCK_SIZE - 1;
  382. err = blkcipher_walk_done(desc, &walk, nbytes);
  383. }
  384. kernel_fpu_end();
  385. return err;
  386. }
  387. static int cbc_decrypt(struct blkcipher_desc *desc,
  388. struct scatterlist *dst, struct scatterlist *src,
  389. unsigned int nbytes)
  390. {
  391. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  392. struct blkcipher_walk walk;
  393. int err;
  394. blkcipher_walk_init(&walk, dst, src, nbytes);
  395. err = blkcipher_walk_virt(desc, &walk);
  396. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  397. kernel_fpu_begin();
  398. while ((nbytes = walk.nbytes)) {
  399. aesni_cbc_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  400. nbytes & AES_BLOCK_MASK, walk.iv);
  401. nbytes &= AES_BLOCK_SIZE - 1;
  402. err = blkcipher_walk_done(desc, &walk, nbytes);
  403. }
  404. kernel_fpu_end();
  405. return err;
  406. }
  407. #ifdef CONFIG_X86_64
  408. static void ctr_crypt_final(struct crypto_aes_ctx *ctx,
  409. struct blkcipher_walk *walk)
  410. {
  411. u8 *ctrblk = walk->iv;
  412. u8 keystream[AES_BLOCK_SIZE];
  413. u8 *src = walk->src.virt.addr;
  414. u8 *dst = walk->dst.virt.addr;
  415. unsigned int nbytes = walk->nbytes;
  416. aesni_enc(ctx, keystream, ctrblk);
  417. crypto_xor(keystream, src, nbytes);
  418. memcpy(dst, keystream, nbytes);
  419. crypto_inc(ctrblk, AES_BLOCK_SIZE);
  420. }
  421. #ifdef CONFIG_AS_AVX
  422. static void aesni_ctr_enc_avx_tfm(struct crypto_aes_ctx *ctx, u8 *out,
  423. const u8 *in, unsigned int len, u8 *iv)
  424. {
  425. /*
  426. * based on key length, override with the by8 version
  427. * of ctr mode encryption/decryption for improved performance
  428. * aes_set_key_common() ensures that key length is one of
  429. * {128,192,256}
  430. */
  431. if (ctx->key_length == AES_KEYSIZE_128)
  432. aes_ctr_enc_128_avx_by8(in, iv, (void *)ctx, out, len);
  433. else if (ctx->key_length == AES_KEYSIZE_192)
  434. aes_ctr_enc_192_avx_by8(in, iv, (void *)ctx, out, len);
  435. else
  436. aes_ctr_enc_256_avx_by8(in, iv, (void *)ctx, out, len);
  437. }
  438. #endif
  439. static int ctr_crypt(struct blkcipher_desc *desc,
  440. struct scatterlist *dst, struct scatterlist *src,
  441. unsigned int nbytes)
  442. {
  443. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  444. struct blkcipher_walk walk;
  445. int err;
  446. blkcipher_walk_init(&walk, dst, src, nbytes);
  447. err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE);
  448. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  449. kernel_fpu_begin();
  450. while ((nbytes = walk.nbytes) >= AES_BLOCK_SIZE) {
  451. aesni_ctr_enc_tfm(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  452. nbytes & AES_BLOCK_MASK, walk.iv);
  453. nbytes &= AES_BLOCK_SIZE - 1;
  454. err = blkcipher_walk_done(desc, &walk, nbytes);
  455. }
  456. if (walk.nbytes) {
  457. ctr_crypt_final(ctx, &walk);
  458. err = blkcipher_walk_done(desc, &walk, 0);
  459. }
  460. kernel_fpu_end();
  461. return err;
  462. }
  463. #endif
  464. static int ablk_ecb_init(struct crypto_tfm *tfm)
  465. {
  466. return ablk_init_common(tfm, "__driver-ecb-aes-aesni");
  467. }
  468. static int ablk_cbc_init(struct crypto_tfm *tfm)
  469. {
  470. return ablk_init_common(tfm, "__driver-cbc-aes-aesni");
  471. }
  472. #ifdef CONFIG_X86_64
  473. static int ablk_ctr_init(struct crypto_tfm *tfm)
  474. {
  475. return ablk_init_common(tfm, "__driver-ctr-aes-aesni");
  476. }
  477. #endif
  478. #if IS_ENABLED(CONFIG_CRYPTO_PCBC)
  479. static int ablk_pcbc_init(struct crypto_tfm *tfm)
  480. {
  481. return ablk_init_common(tfm, "fpu(pcbc(__driver-aes-aesni))");
  482. }
  483. #endif
  484. static void lrw_xts_encrypt_callback(void *ctx, u8 *blks, unsigned int nbytes)
  485. {
  486. aesni_ecb_enc(ctx, blks, blks, nbytes);
  487. }
  488. static void lrw_xts_decrypt_callback(void *ctx, u8 *blks, unsigned int nbytes)
  489. {
  490. aesni_ecb_dec(ctx, blks, blks, nbytes);
  491. }
  492. static int lrw_aesni_setkey(struct crypto_tfm *tfm, const u8 *key,
  493. unsigned int keylen)
  494. {
  495. struct aesni_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
  496. int err;
  497. err = aes_set_key_common(tfm, ctx->raw_aes_ctx, key,
  498. keylen - AES_BLOCK_SIZE);
  499. if (err)
  500. return err;
  501. return lrw_init_table(&ctx->lrw_table, key + keylen - AES_BLOCK_SIZE);
  502. }
  503. static void lrw_aesni_exit_tfm(struct crypto_tfm *tfm)
  504. {
  505. struct aesni_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
  506. lrw_free_table(&ctx->lrw_table);
  507. }
  508. static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  509. struct scatterlist *src, unsigned int nbytes)
  510. {
  511. struct aesni_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  512. be128 buf[8];
  513. struct lrw_crypt_req req = {
  514. .tbuf = buf,
  515. .tbuflen = sizeof(buf),
  516. .table_ctx = &ctx->lrw_table,
  517. .crypt_ctx = aes_ctx(ctx->raw_aes_ctx),
  518. .crypt_fn = lrw_xts_encrypt_callback,
  519. };
  520. int ret;
  521. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  522. kernel_fpu_begin();
  523. ret = lrw_crypt(desc, dst, src, nbytes, &req);
  524. kernel_fpu_end();
  525. return ret;
  526. }
  527. static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  528. struct scatterlist *src, unsigned int nbytes)
  529. {
  530. struct aesni_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  531. be128 buf[8];
  532. struct lrw_crypt_req req = {
  533. .tbuf = buf,
  534. .tbuflen = sizeof(buf),
  535. .table_ctx = &ctx->lrw_table,
  536. .crypt_ctx = aes_ctx(ctx->raw_aes_ctx),
  537. .crypt_fn = lrw_xts_decrypt_callback,
  538. };
  539. int ret;
  540. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  541. kernel_fpu_begin();
  542. ret = lrw_crypt(desc, dst, src, nbytes, &req);
  543. kernel_fpu_end();
  544. return ret;
  545. }
  546. static int xts_aesni_setkey(struct crypto_tfm *tfm, const u8 *key,
  547. unsigned int keylen)
  548. {
  549. struct aesni_xts_ctx *ctx = crypto_tfm_ctx(tfm);
  550. u32 *flags = &tfm->crt_flags;
  551. int err;
  552. /* key consists of keys of equal size concatenated, therefore
  553. * the length must be even
  554. */
  555. if (keylen % 2) {
  556. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  557. return -EINVAL;
  558. }
  559. /* first half of xts-key is for crypt */
  560. err = aes_set_key_common(tfm, ctx->raw_crypt_ctx, key, keylen / 2);
  561. if (err)
  562. return err;
  563. /* second half of xts-key is for tweak */
  564. return aes_set_key_common(tfm, ctx->raw_tweak_ctx, key + keylen / 2,
  565. keylen / 2);
  566. }
  567. static void aesni_xts_tweak(void *ctx, u8 *out, const u8 *in)
  568. {
  569. aesni_enc(ctx, out, in);
  570. }
  571. #ifdef CONFIG_X86_64
  572. static void aesni_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  573. {
  574. glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_enc));
  575. }
  576. static void aesni_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  577. {
  578. glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_dec));
  579. }
  580. static void aesni_xts_enc8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  581. {
  582. aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, true, (u8 *)iv);
  583. }
  584. static void aesni_xts_dec8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  585. {
  586. aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, false, (u8 *)iv);
  587. }
  588. static const struct common_glue_ctx aesni_enc_xts = {
  589. .num_funcs = 2,
  590. .fpu_blocks_limit = 1,
  591. .funcs = { {
  592. .num_blocks = 8,
  593. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc8) }
  594. }, {
  595. .num_blocks = 1,
  596. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc) }
  597. } }
  598. };
  599. static const struct common_glue_ctx aesni_dec_xts = {
  600. .num_funcs = 2,
  601. .fpu_blocks_limit = 1,
  602. .funcs = { {
  603. .num_blocks = 8,
  604. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec8) }
  605. }, {
  606. .num_blocks = 1,
  607. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec) }
  608. } }
  609. };
  610. static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  611. struct scatterlist *src, unsigned int nbytes)
  612. {
  613. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  614. return glue_xts_crypt_128bit(&aesni_enc_xts, desc, dst, src, nbytes,
  615. XTS_TWEAK_CAST(aesni_xts_tweak),
  616. aes_ctx(ctx->raw_tweak_ctx),
  617. aes_ctx(ctx->raw_crypt_ctx));
  618. }
  619. static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  620. struct scatterlist *src, unsigned int nbytes)
  621. {
  622. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  623. return glue_xts_crypt_128bit(&aesni_dec_xts, desc, dst, src, nbytes,
  624. XTS_TWEAK_CAST(aesni_xts_tweak),
  625. aes_ctx(ctx->raw_tweak_ctx),
  626. aes_ctx(ctx->raw_crypt_ctx));
  627. }
  628. #else
  629. static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  630. struct scatterlist *src, unsigned int nbytes)
  631. {
  632. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  633. be128 buf[8];
  634. struct xts_crypt_req req = {
  635. .tbuf = buf,
  636. .tbuflen = sizeof(buf),
  637. .tweak_ctx = aes_ctx(ctx->raw_tweak_ctx),
  638. .tweak_fn = aesni_xts_tweak,
  639. .crypt_ctx = aes_ctx(ctx->raw_crypt_ctx),
  640. .crypt_fn = lrw_xts_encrypt_callback,
  641. };
  642. int ret;
  643. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  644. kernel_fpu_begin();
  645. ret = xts_crypt(desc, dst, src, nbytes, &req);
  646. kernel_fpu_end();
  647. return ret;
  648. }
  649. static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  650. struct scatterlist *src, unsigned int nbytes)
  651. {
  652. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  653. be128 buf[8];
  654. struct xts_crypt_req req = {
  655. .tbuf = buf,
  656. .tbuflen = sizeof(buf),
  657. .tweak_ctx = aes_ctx(ctx->raw_tweak_ctx),
  658. .tweak_fn = aesni_xts_tweak,
  659. .crypt_ctx = aes_ctx(ctx->raw_crypt_ctx),
  660. .crypt_fn = lrw_xts_decrypt_callback,
  661. };
  662. int ret;
  663. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  664. kernel_fpu_begin();
  665. ret = xts_crypt(desc, dst, src, nbytes, &req);
  666. kernel_fpu_end();
  667. return ret;
  668. }
  669. #endif
  670. #ifdef CONFIG_X86_64
  671. static int rfc4106_init(struct crypto_tfm *tfm)
  672. {
  673. struct cryptd_aead *cryptd_tfm;
  674. struct aesni_rfc4106_gcm_ctx *ctx = (struct aesni_rfc4106_gcm_ctx *)
  675. PTR_ALIGN((u8 *)crypto_tfm_ctx(tfm), AESNI_ALIGN);
  676. struct crypto_aead *cryptd_child;
  677. struct aesni_rfc4106_gcm_ctx *child_ctx;
  678. cryptd_tfm = cryptd_alloc_aead("__driver-gcm-aes-aesni", 0, 0);
  679. if (IS_ERR(cryptd_tfm))
  680. return PTR_ERR(cryptd_tfm);
  681. cryptd_child = cryptd_aead_child(cryptd_tfm);
  682. child_ctx = aesni_rfc4106_gcm_ctx_get(cryptd_child);
  683. memcpy(child_ctx, ctx, sizeof(*ctx));
  684. ctx->cryptd_tfm = cryptd_tfm;
  685. tfm->crt_aead.reqsize = sizeof(struct aead_request)
  686. + crypto_aead_reqsize(&cryptd_tfm->base);
  687. return 0;
  688. }
  689. static void rfc4106_exit(struct crypto_tfm *tfm)
  690. {
  691. struct aesni_rfc4106_gcm_ctx *ctx =
  692. (struct aesni_rfc4106_gcm_ctx *)
  693. PTR_ALIGN((u8 *)crypto_tfm_ctx(tfm), AESNI_ALIGN);
  694. if (!IS_ERR(ctx->cryptd_tfm))
  695. cryptd_free_aead(ctx->cryptd_tfm);
  696. return;
  697. }
  698. static void
  699. rfc4106_set_hash_subkey_done(struct crypto_async_request *req, int err)
  700. {
  701. struct aesni_gcm_set_hash_subkey_result *result = req->data;
  702. if (err == -EINPROGRESS)
  703. return;
  704. result->err = err;
  705. complete(&result->completion);
  706. }
  707. static int
  708. rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len)
  709. {
  710. struct crypto_ablkcipher *ctr_tfm;
  711. struct ablkcipher_request *req;
  712. int ret = -EINVAL;
  713. struct aesni_hash_subkey_req_data *req_data;
  714. ctr_tfm = crypto_alloc_ablkcipher("ctr(aes)", 0, 0);
  715. if (IS_ERR(ctr_tfm))
  716. return PTR_ERR(ctr_tfm);
  717. crypto_ablkcipher_clear_flags(ctr_tfm, ~0);
  718. ret = crypto_ablkcipher_setkey(ctr_tfm, key, key_len);
  719. if (ret)
  720. goto out_free_ablkcipher;
  721. ret = -ENOMEM;
  722. req = ablkcipher_request_alloc(ctr_tfm, GFP_KERNEL);
  723. if (!req)
  724. goto out_free_ablkcipher;
  725. req_data = kmalloc(sizeof(*req_data), GFP_KERNEL);
  726. if (!req_data)
  727. goto out_free_request;
  728. memset(req_data->iv, 0, sizeof(req_data->iv));
  729. /* Clear the data in the hash sub key container to zero.*/
  730. /* We want to cipher all zeros to create the hash sub key. */
  731. memset(hash_subkey, 0, RFC4106_HASH_SUBKEY_SIZE);
  732. init_completion(&req_data->result.completion);
  733. sg_init_one(&req_data->sg, hash_subkey, RFC4106_HASH_SUBKEY_SIZE);
  734. ablkcipher_request_set_tfm(req, ctr_tfm);
  735. ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_SLEEP |
  736. CRYPTO_TFM_REQ_MAY_BACKLOG,
  737. rfc4106_set_hash_subkey_done,
  738. &req_data->result);
  739. ablkcipher_request_set_crypt(req, &req_data->sg,
  740. &req_data->sg, RFC4106_HASH_SUBKEY_SIZE, req_data->iv);
  741. ret = crypto_ablkcipher_encrypt(req);
  742. if (ret == -EINPROGRESS || ret == -EBUSY) {
  743. ret = wait_for_completion_interruptible
  744. (&req_data->result.completion);
  745. if (!ret)
  746. ret = req_data->result.err;
  747. }
  748. kfree(req_data);
  749. out_free_request:
  750. ablkcipher_request_free(req);
  751. out_free_ablkcipher:
  752. crypto_free_ablkcipher(ctr_tfm);
  753. return ret;
  754. }
  755. static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
  756. unsigned int key_len)
  757. {
  758. int ret = 0;
  759. struct crypto_tfm *tfm = crypto_aead_tfm(parent);
  760. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent);
  761. struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
  762. struct aesni_rfc4106_gcm_ctx *child_ctx =
  763. aesni_rfc4106_gcm_ctx_get(cryptd_child);
  764. u8 *new_key_align, *new_key_mem = NULL;
  765. if (key_len < 4) {
  766. crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  767. return -EINVAL;
  768. }
  769. /*Account for 4 byte nonce at the end.*/
  770. key_len -= 4;
  771. if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
  772. key_len != AES_KEYSIZE_256) {
  773. crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  774. return -EINVAL;
  775. }
  776. memcpy(ctx->nonce, key + key_len, sizeof(ctx->nonce));
  777. /*This must be on a 16 byte boundary!*/
  778. if ((unsigned long)(&(ctx->aes_key_expanded.key_enc[0])) % AESNI_ALIGN)
  779. return -EINVAL;
  780. if ((unsigned long)key % AESNI_ALIGN) {
  781. /*key is not aligned: use an auxuliar aligned pointer*/
  782. new_key_mem = kmalloc(key_len+AESNI_ALIGN, GFP_KERNEL);
  783. if (!new_key_mem)
  784. return -ENOMEM;
  785. new_key_align = PTR_ALIGN(new_key_mem, AESNI_ALIGN);
  786. memcpy(new_key_align, key, key_len);
  787. key = new_key_align;
  788. }
  789. if (!irq_fpu_usable())
  790. ret = crypto_aes_expand_key(&(ctx->aes_key_expanded),
  791. key, key_len);
  792. else {
  793. kernel_fpu_begin();
  794. ret = aesni_set_key(&(ctx->aes_key_expanded), key, key_len);
  795. kernel_fpu_end();
  796. }
  797. /*This must be on a 16 byte boundary!*/
  798. if ((unsigned long)(&(ctx->hash_subkey[0])) % AESNI_ALIGN) {
  799. ret = -EINVAL;
  800. goto exit;
  801. }
  802. ret = rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len);
  803. memcpy(child_ctx, ctx, sizeof(*ctx));
  804. exit:
  805. kfree(new_key_mem);
  806. return ret;
  807. }
  808. /* This is the Integrity Check Value (aka the authentication tag length and can
  809. * be 8, 12 or 16 bytes long. */
  810. static int rfc4106_set_authsize(struct crypto_aead *parent,
  811. unsigned int authsize)
  812. {
  813. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent);
  814. struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
  815. switch (authsize) {
  816. case 8:
  817. case 12:
  818. case 16:
  819. break;
  820. default:
  821. return -EINVAL;
  822. }
  823. crypto_aead_crt(parent)->authsize = authsize;
  824. crypto_aead_crt(cryptd_child)->authsize = authsize;
  825. return 0;
  826. }
  827. static int rfc4106_encrypt(struct aead_request *req)
  828. {
  829. int ret;
  830. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  831. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  832. if (!irq_fpu_usable()) {
  833. struct aead_request *cryptd_req =
  834. (struct aead_request *) aead_request_ctx(req);
  835. memcpy(cryptd_req, req, sizeof(*req));
  836. aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
  837. return crypto_aead_encrypt(cryptd_req);
  838. } else {
  839. struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
  840. kernel_fpu_begin();
  841. ret = cryptd_child->base.crt_aead.encrypt(req);
  842. kernel_fpu_end();
  843. return ret;
  844. }
  845. }
  846. static int rfc4106_decrypt(struct aead_request *req)
  847. {
  848. int ret;
  849. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  850. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  851. if (!irq_fpu_usable()) {
  852. struct aead_request *cryptd_req =
  853. (struct aead_request *) aead_request_ctx(req);
  854. memcpy(cryptd_req, req, sizeof(*req));
  855. aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
  856. return crypto_aead_decrypt(cryptd_req);
  857. } else {
  858. struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
  859. kernel_fpu_begin();
  860. ret = cryptd_child->base.crt_aead.decrypt(req);
  861. kernel_fpu_end();
  862. return ret;
  863. }
  864. }
  865. static int __driver_rfc4106_encrypt(struct aead_request *req)
  866. {
  867. u8 one_entry_in_sg = 0;
  868. u8 *src, *dst, *assoc;
  869. __be32 counter = cpu_to_be32(1);
  870. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  871. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  872. u32 key_len = ctx->aes_key_expanded.key_length;
  873. void *aes_ctx = &(ctx->aes_key_expanded);
  874. unsigned long auth_tag_len = crypto_aead_authsize(tfm);
  875. u8 iv_tab[16+AESNI_ALIGN];
  876. u8* iv = (u8 *) PTR_ALIGN((u8 *)iv_tab, AESNI_ALIGN);
  877. struct scatter_walk src_sg_walk;
  878. struct scatter_walk assoc_sg_walk;
  879. struct scatter_walk dst_sg_walk;
  880. unsigned int i;
  881. /* Assuming we are supporting rfc4106 64-bit extended */
  882. /* sequence numbers We need to have the AAD length equal */
  883. /* to 8 or 12 bytes */
  884. if (unlikely(req->assoclen != 8 && req->assoclen != 12))
  885. return -EINVAL;
  886. if (unlikely(auth_tag_len != 8 && auth_tag_len != 12 && auth_tag_len != 16))
  887. return -EINVAL;
  888. if (unlikely(key_len != AES_KEYSIZE_128 &&
  889. key_len != AES_KEYSIZE_192 &&
  890. key_len != AES_KEYSIZE_256))
  891. return -EINVAL;
  892. /* IV below built */
  893. for (i = 0; i < 4; i++)
  894. *(iv+i) = ctx->nonce[i];
  895. for (i = 0; i < 8; i++)
  896. *(iv+4+i) = req->iv[i];
  897. *((__be32 *)(iv+12)) = counter;
  898. if ((sg_is_last(req->src)) && (sg_is_last(req->assoc))) {
  899. one_entry_in_sg = 1;
  900. scatterwalk_start(&src_sg_walk, req->src);
  901. scatterwalk_start(&assoc_sg_walk, req->assoc);
  902. src = scatterwalk_map(&src_sg_walk);
  903. assoc = scatterwalk_map(&assoc_sg_walk);
  904. dst = src;
  905. if (unlikely(req->src != req->dst)) {
  906. scatterwalk_start(&dst_sg_walk, req->dst);
  907. dst = scatterwalk_map(&dst_sg_walk);
  908. }
  909. } else {
  910. /* Allocate memory for src, dst, assoc */
  911. src = kmalloc(req->cryptlen + auth_tag_len + req->assoclen,
  912. GFP_ATOMIC);
  913. if (unlikely(!src))
  914. return -ENOMEM;
  915. assoc = (src + req->cryptlen + auth_tag_len);
  916. scatterwalk_map_and_copy(src, req->src, 0, req->cryptlen, 0);
  917. scatterwalk_map_and_copy(assoc, req->assoc, 0,
  918. req->assoclen, 0);
  919. dst = src;
  920. }
  921. aesni_gcm_enc_tfm(aes_ctx, dst, src, (unsigned long)req->cryptlen, iv,
  922. ctx->hash_subkey, assoc, (unsigned long)req->assoclen, dst
  923. + ((unsigned long)req->cryptlen), auth_tag_len);
  924. /* The authTag (aka the Integrity Check Value) needs to be written
  925. * back to the packet. */
  926. if (one_entry_in_sg) {
  927. if (unlikely(req->src != req->dst)) {
  928. scatterwalk_unmap(dst);
  929. scatterwalk_done(&dst_sg_walk, 0, 0);
  930. }
  931. scatterwalk_unmap(src);
  932. scatterwalk_unmap(assoc);
  933. scatterwalk_done(&src_sg_walk, 0, 0);
  934. scatterwalk_done(&assoc_sg_walk, 0, 0);
  935. } else {
  936. scatterwalk_map_and_copy(dst, req->dst, 0,
  937. req->cryptlen + auth_tag_len, 1);
  938. kfree(src);
  939. }
  940. return 0;
  941. }
  942. static int __driver_rfc4106_decrypt(struct aead_request *req)
  943. {
  944. u8 one_entry_in_sg = 0;
  945. u8 *src, *dst, *assoc;
  946. unsigned long tempCipherLen = 0;
  947. __be32 counter = cpu_to_be32(1);
  948. int retval = 0;
  949. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  950. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  951. u32 key_len = ctx->aes_key_expanded.key_length;
  952. void *aes_ctx = &(ctx->aes_key_expanded);
  953. unsigned long auth_tag_len = crypto_aead_authsize(tfm);
  954. u8 iv_and_authTag[32+AESNI_ALIGN];
  955. u8 *iv = (u8 *) PTR_ALIGN((u8 *)iv_and_authTag, AESNI_ALIGN);
  956. u8 *authTag = iv + 16;
  957. struct scatter_walk src_sg_walk;
  958. struct scatter_walk assoc_sg_walk;
  959. struct scatter_walk dst_sg_walk;
  960. unsigned int i;
  961. if (unlikely((req->cryptlen < auth_tag_len) ||
  962. (req->assoclen != 8 && req->assoclen != 12)))
  963. return -EINVAL;
  964. if (unlikely(auth_tag_len != 8 && auth_tag_len != 12 && auth_tag_len != 16))
  965. return -EINVAL;
  966. if (unlikely(key_len != AES_KEYSIZE_128 &&
  967. key_len != AES_KEYSIZE_192 &&
  968. key_len != AES_KEYSIZE_256))
  969. return -EINVAL;
  970. /* Assuming we are supporting rfc4106 64-bit extended */
  971. /* sequence numbers We need to have the AAD length */
  972. /* equal to 8 or 12 bytes */
  973. tempCipherLen = (unsigned long)(req->cryptlen - auth_tag_len);
  974. /* IV below built */
  975. for (i = 0; i < 4; i++)
  976. *(iv+i) = ctx->nonce[i];
  977. for (i = 0; i < 8; i++)
  978. *(iv+4+i) = req->iv[i];
  979. *((__be32 *)(iv+12)) = counter;
  980. if ((sg_is_last(req->src)) && (sg_is_last(req->assoc))) {
  981. one_entry_in_sg = 1;
  982. scatterwalk_start(&src_sg_walk, req->src);
  983. scatterwalk_start(&assoc_sg_walk, req->assoc);
  984. src = scatterwalk_map(&src_sg_walk);
  985. assoc = scatterwalk_map(&assoc_sg_walk);
  986. dst = src;
  987. if (unlikely(req->src != req->dst)) {
  988. scatterwalk_start(&dst_sg_walk, req->dst);
  989. dst = scatterwalk_map(&dst_sg_walk);
  990. }
  991. } else {
  992. /* Allocate memory for src, dst, assoc */
  993. src = kmalloc(req->cryptlen + req->assoclen, GFP_ATOMIC);
  994. if (!src)
  995. return -ENOMEM;
  996. assoc = (src + req->cryptlen + auth_tag_len);
  997. scatterwalk_map_and_copy(src, req->src, 0, req->cryptlen, 0);
  998. scatterwalk_map_and_copy(assoc, req->assoc, 0,
  999. req->assoclen, 0);
  1000. dst = src;
  1001. }
  1002. aesni_gcm_dec_tfm(aes_ctx, dst, src, tempCipherLen, iv,
  1003. ctx->hash_subkey, assoc, (unsigned long)req->assoclen,
  1004. authTag, auth_tag_len);
  1005. /* Compare generated tag with passed in tag. */
  1006. retval = crypto_memneq(src + tempCipherLen, authTag, auth_tag_len) ?
  1007. -EBADMSG : 0;
  1008. if (one_entry_in_sg) {
  1009. if (unlikely(req->src != req->dst)) {
  1010. scatterwalk_unmap(dst);
  1011. scatterwalk_done(&dst_sg_walk, 0, 0);
  1012. }
  1013. scatterwalk_unmap(src);
  1014. scatterwalk_unmap(assoc);
  1015. scatterwalk_done(&src_sg_walk, 0, 0);
  1016. scatterwalk_done(&assoc_sg_walk, 0, 0);
  1017. } else {
  1018. scatterwalk_map_and_copy(dst, req->dst, 0, req->cryptlen, 1);
  1019. kfree(src);
  1020. }
  1021. return retval;
  1022. }
  1023. #endif
  1024. static struct crypto_alg aesni_algs[] = { {
  1025. .cra_name = "aes",
  1026. .cra_driver_name = "aes-aesni",
  1027. .cra_priority = 300,
  1028. .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
  1029. .cra_blocksize = AES_BLOCK_SIZE,
  1030. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1031. AESNI_ALIGN - 1,
  1032. .cra_alignmask = 0,
  1033. .cra_module = THIS_MODULE,
  1034. .cra_u = {
  1035. .cipher = {
  1036. .cia_min_keysize = AES_MIN_KEY_SIZE,
  1037. .cia_max_keysize = AES_MAX_KEY_SIZE,
  1038. .cia_setkey = aes_set_key,
  1039. .cia_encrypt = aes_encrypt,
  1040. .cia_decrypt = aes_decrypt
  1041. }
  1042. }
  1043. }, {
  1044. .cra_name = "__aes-aesni",
  1045. .cra_driver_name = "__driver-aes-aesni",
  1046. .cra_priority = 0,
  1047. .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
  1048. .cra_blocksize = AES_BLOCK_SIZE,
  1049. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1050. AESNI_ALIGN - 1,
  1051. .cra_alignmask = 0,
  1052. .cra_module = THIS_MODULE,
  1053. .cra_u = {
  1054. .cipher = {
  1055. .cia_min_keysize = AES_MIN_KEY_SIZE,
  1056. .cia_max_keysize = AES_MAX_KEY_SIZE,
  1057. .cia_setkey = aes_set_key,
  1058. .cia_encrypt = __aes_encrypt,
  1059. .cia_decrypt = __aes_decrypt
  1060. }
  1061. }
  1062. }, {
  1063. .cra_name = "__ecb-aes-aesni",
  1064. .cra_driver_name = "__driver-ecb-aes-aesni",
  1065. .cra_priority = 0,
  1066. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
  1067. .cra_blocksize = AES_BLOCK_SIZE,
  1068. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1069. AESNI_ALIGN - 1,
  1070. .cra_alignmask = 0,
  1071. .cra_type = &crypto_blkcipher_type,
  1072. .cra_module = THIS_MODULE,
  1073. .cra_u = {
  1074. .blkcipher = {
  1075. .min_keysize = AES_MIN_KEY_SIZE,
  1076. .max_keysize = AES_MAX_KEY_SIZE,
  1077. .setkey = aes_set_key,
  1078. .encrypt = ecb_encrypt,
  1079. .decrypt = ecb_decrypt,
  1080. },
  1081. },
  1082. }, {
  1083. .cra_name = "__cbc-aes-aesni",
  1084. .cra_driver_name = "__driver-cbc-aes-aesni",
  1085. .cra_priority = 0,
  1086. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
  1087. .cra_blocksize = AES_BLOCK_SIZE,
  1088. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1089. AESNI_ALIGN - 1,
  1090. .cra_alignmask = 0,
  1091. .cra_type = &crypto_blkcipher_type,
  1092. .cra_module = THIS_MODULE,
  1093. .cra_u = {
  1094. .blkcipher = {
  1095. .min_keysize = AES_MIN_KEY_SIZE,
  1096. .max_keysize = AES_MAX_KEY_SIZE,
  1097. .setkey = aes_set_key,
  1098. .encrypt = cbc_encrypt,
  1099. .decrypt = cbc_decrypt,
  1100. },
  1101. },
  1102. }, {
  1103. .cra_name = "ecb(aes)",
  1104. .cra_driver_name = "ecb-aes-aesni",
  1105. .cra_priority = 400,
  1106. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1107. .cra_blocksize = AES_BLOCK_SIZE,
  1108. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1109. .cra_alignmask = 0,
  1110. .cra_type = &crypto_ablkcipher_type,
  1111. .cra_module = THIS_MODULE,
  1112. .cra_init = ablk_ecb_init,
  1113. .cra_exit = ablk_exit,
  1114. .cra_u = {
  1115. .ablkcipher = {
  1116. .min_keysize = AES_MIN_KEY_SIZE,
  1117. .max_keysize = AES_MAX_KEY_SIZE,
  1118. .setkey = ablk_set_key,
  1119. .encrypt = ablk_encrypt,
  1120. .decrypt = ablk_decrypt,
  1121. },
  1122. },
  1123. }, {
  1124. .cra_name = "cbc(aes)",
  1125. .cra_driver_name = "cbc-aes-aesni",
  1126. .cra_priority = 400,
  1127. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1128. .cra_blocksize = AES_BLOCK_SIZE,
  1129. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1130. .cra_alignmask = 0,
  1131. .cra_type = &crypto_ablkcipher_type,
  1132. .cra_module = THIS_MODULE,
  1133. .cra_init = ablk_cbc_init,
  1134. .cra_exit = ablk_exit,
  1135. .cra_u = {
  1136. .ablkcipher = {
  1137. .min_keysize = AES_MIN_KEY_SIZE,
  1138. .max_keysize = AES_MAX_KEY_SIZE,
  1139. .ivsize = AES_BLOCK_SIZE,
  1140. .setkey = ablk_set_key,
  1141. .encrypt = ablk_encrypt,
  1142. .decrypt = ablk_decrypt,
  1143. },
  1144. },
  1145. #ifdef CONFIG_X86_64
  1146. }, {
  1147. .cra_name = "__ctr-aes-aesni",
  1148. .cra_driver_name = "__driver-ctr-aes-aesni",
  1149. .cra_priority = 0,
  1150. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
  1151. .cra_blocksize = 1,
  1152. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1153. AESNI_ALIGN - 1,
  1154. .cra_alignmask = 0,
  1155. .cra_type = &crypto_blkcipher_type,
  1156. .cra_module = THIS_MODULE,
  1157. .cra_u = {
  1158. .blkcipher = {
  1159. .min_keysize = AES_MIN_KEY_SIZE,
  1160. .max_keysize = AES_MAX_KEY_SIZE,
  1161. .ivsize = AES_BLOCK_SIZE,
  1162. .setkey = aes_set_key,
  1163. .encrypt = ctr_crypt,
  1164. .decrypt = ctr_crypt,
  1165. },
  1166. },
  1167. }, {
  1168. .cra_name = "ctr(aes)",
  1169. .cra_driver_name = "ctr-aes-aesni",
  1170. .cra_priority = 400,
  1171. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1172. .cra_blocksize = 1,
  1173. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1174. .cra_alignmask = 0,
  1175. .cra_type = &crypto_ablkcipher_type,
  1176. .cra_module = THIS_MODULE,
  1177. .cra_init = ablk_ctr_init,
  1178. .cra_exit = ablk_exit,
  1179. .cra_u = {
  1180. .ablkcipher = {
  1181. .min_keysize = AES_MIN_KEY_SIZE,
  1182. .max_keysize = AES_MAX_KEY_SIZE,
  1183. .ivsize = AES_BLOCK_SIZE,
  1184. .setkey = ablk_set_key,
  1185. .encrypt = ablk_encrypt,
  1186. .decrypt = ablk_encrypt,
  1187. .geniv = "chainiv",
  1188. },
  1189. },
  1190. }, {
  1191. .cra_name = "__gcm-aes-aesni",
  1192. .cra_driver_name = "__driver-gcm-aes-aesni",
  1193. .cra_priority = 0,
  1194. .cra_flags = CRYPTO_ALG_TYPE_AEAD,
  1195. .cra_blocksize = 1,
  1196. .cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) +
  1197. AESNI_ALIGN,
  1198. .cra_alignmask = 0,
  1199. .cra_type = &crypto_aead_type,
  1200. .cra_module = THIS_MODULE,
  1201. .cra_u = {
  1202. .aead = {
  1203. .encrypt = __driver_rfc4106_encrypt,
  1204. .decrypt = __driver_rfc4106_decrypt,
  1205. },
  1206. },
  1207. }, {
  1208. .cra_name = "rfc4106(gcm(aes))",
  1209. .cra_driver_name = "rfc4106-gcm-aesni",
  1210. .cra_priority = 400,
  1211. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1212. .cra_blocksize = 1,
  1213. .cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) +
  1214. AESNI_ALIGN,
  1215. .cra_alignmask = 0,
  1216. .cra_type = &crypto_nivaead_type,
  1217. .cra_module = THIS_MODULE,
  1218. .cra_init = rfc4106_init,
  1219. .cra_exit = rfc4106_exit,
  1220. .cra_u = {
  1221. .aead = {
  1222. .setkey = rfc4106_set_key,
  1223. .setauthsize = rfc4106_set_authsize,
  1224. .encrypt = rfc4106_encrypt,
  1225. .decrypt = rfc4106_decrypt,
  1226. .geniv = "seqiv",
  1227. .ivsize = 8,
  1228. .maxauthsize = 16,
  1229. },
  1230. },
  1231. #endif
  1232. #if IS_ENABLED(CONFIG_CRYPTO_PCBC)
  1233. }, {
  1234. .cra_name = "pcbc(aes)",
  1235. .cra_driver_name = "pcbc-aes-aesni",
  1236. .cra_priority = 400,
  1237. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1238. .cra_blocksize = AES_BLOCK_SIZE,
  1239. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1240. .cra_alignmask = 0,
  1241. .cra_type = &crypto_ablkcipher_type,
  1242. .cra_module = THIS_MODULE,
  1243. .cra_init = ablk_pcbc_init,
  1244. .cra_exit = ablk_exit,
  1245. .cra_u = {
  1246. .ablkcipher = {
  1247. .min_keysize = AES_MIN_KEY_SIZE,
  1248. .max_keysize = AES_MAX_KEY_SIZE,
  1249. .ivsize = AES_BLOCK_SIZE,
  1250. .setkey = ablk_set_key,
  1251. .encrypt = ablk_encrypt,
  1252. .decrypt = ablk_decrypt,
  1253. },
  1254. },
  1255. #endif
  1256. }, {
  1257. .cra_name = "__lrw-aes-aesni",
  1258. .cra_driver_name = "__driver-lrw-aes-aesni",
  1259. .cra_priority = 0,
  1260. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
  1261. .cra_blocksize = AES_BLOCK_SIZE,
  1262. .cra_ctxsize = sizeof(struct aesni_lrw_ctx),
  1263. .cra_alignmask = 0,
  1264. .cra_type = &crypto_blkcipher_type,
  1265. .cra_module = THIS_MODULE,
  1266. .cra_exit = lrw_aesni_exit_tfm,
  1267. .cra_u = {
  1268. .blkcipher = {
  1269. .min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
  1270. .max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
  1271. .ivsize = AES_BLOCK_SIZE,
  1272. .setkey = lrw_aesni_setkey,
  1273. .encrypt = lrw_encrypt,
  1274. .decrypt = lrw_decrypt,
  1275. },
  1276. },
  1277. }, {
  1278. .cra_name = "__xts-aes-aesni",
  1279. .cra_driver_name = "__driver-xts-aes-aesni",
  1280. .cra_priority = 0,
  1281. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
  1282. .cra_blocksize = AES_BLOCK_SIZE,
  1283. .cra_ctxsize = sizeof(struct aesni_xts_ctx),
  1284. .cra_alignmask = 0,
  1285. .cra_type = &crypto_blkcipher_type,
  1286. .cra_module = THIS_MODULE,
  1287. .cra_u = {
  1288. .blkcipher = {
  1289. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1290. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1291. .ivsize = AES_BLOCK_SIZE,
  1292. .setkey = xts_aesni_setkey,
  1293. .encrypt = xts_encrypt,
  1294. .decrypt = xts_decrypt,
  1295. },
  1296. },
  1297. }, {
  1298. .cra_name = "lrw(aes)",
  1299. .cra_driver_name = "lrw-aes-aesni",
  1300. .cra_priority = 400,
  1301. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1302. .cra_blocksize = AES_BLOCK_SIZE,
  1303. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1304. .cra_alignmask = 0,
  1305. .cra_type = &crypto_ablkcipher_type,
  1306. .cra_module = THIS_MODULE,
  1307. .cra_init = ablk_init,
  1308. .cra_exit = ablk_exit,
  1309. .cra_u = {
  1310. .ablkcipher = {
  1311. .min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
  1312. .max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
  1313. .ivsize = AES_BLOCK_SIZE,
  1314. .setkey = ablk_set_key,
  1315. .encrypt = ablk_encrypt,
  1316. .decrypt = ablk_decrypt,
  1317. },
  1318. },
  1319. }, {
  1320. .cra_name = "xts(aes)",
  1321. .cra_driver_name = "xts-aes-aesni",
  1322. .cra_priority = 400,
  1323. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1324. .cra_blocksize = AES_BLOCK_SIZE,
  1325. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1326. .cra_alignmask = 0,
  1327. .cra_type = &crypto_ablkcipher_type,
  1328. .cra_module = THIS_MODULE,
  1329. .cra_init = ablk_init,
  1330. .cra_exit = ablk_exit,
  1331. .cra_u = {
  1332. .ablkcipher = {
  1333. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1334. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1335. .ivsize = AES_BLOCK_SIZE,
  1336. .setkey = ablk_set_key,
  1337. .encrypt = ablk_encrypt,
  1338. .decrypt = ablk_decrypt,
  1339. },
  1340. },
  1341. } };
  1342. static const struct x86_cpu_id aesni_cpu_id[] = {
  1343. X86_FEATURE_MATCH(X86_FEATURE_AES),
  1344. {}
  1345. };
  1346. MODULE_DEVICE_TABLE(x86cpu, aesni_cpu_id);
  1347. static int __init aesni_init(void)
  1348. {
  1349. int err;
  1350. if (!x86_match_cpu(aesni_cpu_id))
  1351. return -ENODEV;
  1352. #ifdef CONFIG_X86_64
  1353. #ifdef CONFIG_AS_AVX2
  1354. if (boot_cpu_has(X86_FEATURE_AVX2)) {
  1355. pr_info("AVX2 version of gcm_enc/dec engaged.\n");
  1356. aesni_gcm_enc_tfm = aesni_gcm_enc_avx2;
  1357. aesni_gcm_dec_tfm = aesni_gcm_dec_avx2;
  1358. } else
  1359. #endif
  1360. #ifdef CONFIG_AS_AVX
  1361. if (boot_cpu_has(X86_FEATURE_AVX)) {
  1362. pr_info("AVX version of gcm_enc/dec engaged.\n");
  1363. aesni_gcm_enc_tfm = aesni_gcm_enc_avx;
  1364. aesni_gcm_dec_tfm = aesni_gcm_dec_avx;
  1365. } else
  1366. #endif
  1367. {
  1368. pr_info("SSE version of gcm_enc/dec engaged.\n");
  1369. aesni_gcm_enc_tfm = aesni_gcm_enc;
  1370. aesni_gcm_dec_tfm = aesni_gcm_dec;
  1371. }
  1372. aesni_ctr_enc_tfm = aesni_ctr_enc;
  1373. #ifdef CONFIG_AS_AVX
  1374. if (cpu_has_avx) {
  1375. /* optimize performance of ctr mode encryption transform */
  1376. aesni_ctr_enc_tfm = aesni_ctr_enc_avx_tfm;
  1377. pr_info("AES CTR mode by8 optimization enabled\n");
  1378. }
  1379. #endif
  1380. #endif
  1381. err = crypto_fpu_init();
  1382. if (err)
  1383. return err;
  1384. return crypto_register_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1385. }
  1386. static void __exit aesni_exit(void)
  1387. {
  1388. crypto_unregister_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1389. crypto_fpu_exit();
  1390. }
  1391. module_init(aesni_init);
  1392. module_exit(aesni_exit);
  1393. MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm, Intel AES-NI instructions optimized");
  1394. MODULE_LICENSE("GPL");
  1395. MODULE_ALIAS_CRYPTO("aes");