udc.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * udc.c - ChipIdea UDC driver
  4. *
  5. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  6. *
  7. * Author: David Lopo
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/delay.h>
  14. #include <linux/device.h>
  15. #include <linux/dmapool.h>
  16. #include <linux/err.h>
  17. #include <linux/irqreturn.h>
  18. #include <linux/kernel.h>
  19. #include <linux/slab.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/usb/ch9.h>
  22. #include <linux/usb/gadget.h>
  23. #include <linux/usb/otg-fsm.h>
  24. #include <linux/usb/chipidea.h>
  25. #include "ci.h"
  26. #include "udc.h"
  27. #include "bits.h"
  28. #include "otg.h"
  29. #include "otg_fsm.h"
  30. /* control endpoint description */
  31. static const struct usb_endpoint_descriptor
  32. ctrl_endpt_out_desc = {
  33. .bLength = USB_DT_ENDPOINT_SIZE,
  34. .bDescriptorType = USB_DT_ENDPOINT,
  35. .bEndpointAddress = USB_DIR_OUT,
  36. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  37. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  38. };
  39. static const struct usb_endpoint_descriptor
  40. ctrl_endpt_in_desc = {
  41. .bLength = USB_DT_ENDPOINT_SIZE,
  42. .bDescriptorType = USB_DT_ENDPOINT,
  43. .bEndpointAddress = USB_DIR_IN,
  44. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  45. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  46. };
  47. /**
  48. * hw_ep_bit: calculates the bit number
  49. * @num: endpoint number
  50. * @dir: endpoint direction
  51. *
  52. * This function returns bit number
  53. */
  54. static inline int hw_ep_bit(int num, int dir)
  55. {
  56. return num + ((dir == TX) ? 16 : 0);
  57. }
  58. static inline int ep_to_bit(struct ci_hdrc *ci, int n)
  59. {
  60. int fill = 16 - ci->hw_ep_max / 2;
  61. if (n >= ci->hw_ep_max / 2)
  62. n += fill;
  63. return n;
  64. }
  65. /**
  66. * hw_device_state: enables/disables interrupts (execute without interruption)
  67. * @dma: 0 => disable, !0 => enable and set dma engine
  68. *
  69. * This function returns an error code
  70. */
  71. static int hw_device_state(struct ci_hdrc *ci, u32 dma)
  72. {
  73. if (dma) {
  74. hw_write(ci, OP_ENDPTLISTADDR, ~0, dma);
  75. /* interrupt, error, port change, reset, sleep/suspend */
  76. hw_write(ci, OP_USBINTR, ~0,
  77. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  78. } else {
  79. hw_write(ci, OP_USBINTR, ~0, 0);
  80. }
  81. return 0;
  82. }
  83. /**
  84. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  85. * @num: endpoint number
  86. * @dir: endpoint direction
  87. *
  88. * This function returns an error code
  89. */
  90. static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
  91. {
  92. int n = hw_ep_bit(num, dir);
  93. do {
  94. /* flush any pending transfer */
  95. hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
  96. while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
  97. cpu_relax();
  98. } while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
  99. return 0;
  100. }
  101. /**
  102. * hw_ep_disable: disables endpoint (execute without interruption)
  103. * @num: endpoint number
  104. * @dir: endpoint direction
  105. *
  106. * This function returns an error code
  107. */
  108. static int hw_ep_disable(struct ci_hdrc *ci, int num, int dir)
  109. {
  110. hw_write(ci, OP_ENDPTCTRL + num,
  111. (dir == TX) ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  112. return 0;
  113. }
  114. /**
  115. * hw_ep_enable: enables endpoint (execute without interruption)
  116. * @num: endpoint number
  117. * @dir: endpoint direction
  118. * @type: endpoint type
  119. *
  120. * This function returns an error code
  121. */
  122. static int hw_ep_enable(struct ci_hdrc *ci, int num, int dir, int type)
  123. {
  124. u32 mask, data;
  125. if (dir == TX) {
  126. mask = ENDPTCTRL_TXT; /* type */
  127. data = type << __ffs(mask);
  128. mask |= ENDPTCTRL_TXS; /* unstall */
  129. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  130. data |= ENDPTCTRL_TXR;
  131. mask |= ENDPTCTRL_TXE; /* enable */
  132. data |= ENDPTCTRL_TXE;
  133. } else {
  134. mask = ENDPTCTRL_RXT; /* type */
  135. data = type << __ffs(mask);
  136. mask |= ENDPTCTRL_RXS; /* unstall */
  137. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  138. data |= ENDPTCTRL_RXR;
  139. mask |= ENDPTCTRL_RXE; /* enable */
  140. data |= ENDPTCTRL_RXE;
  141. }
  142. hw_write(ci, OP_ENDPTCTRL + num, mask, data);
  143. return 0;
  144. }
  145. /**
  146. * hw_ep_get_halt: return endpoint halt status
  147. * @num: endpoint number
  148. * @dir: endpoint direction
  149. *
  150. * This function returns 1 if endpoint halted
  151. */
  152. static int hw_ep_get_halt(struct ci_hdrc *ci, int num, int dir)
  153. {
  154. u32 mask = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  155. return hw_read(ci, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  156. }
  157. /**
  158. * hw_ep_prime: primes endpoint (execute without interruption)
  159. * @num: endpoint number
  160. * @dir: endpoint direction
  161. * @is_ctrl: true if control endpoint
  162. *
  163. * This function returns an error code
  164. */
  165. static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
  166. {
  167. int n = hw_ep_bit(num, dir);
  168. /* Synchronize before ep prime */
  169. wmb();
  170. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  171. return -EAGAIN;
  172. hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
  173. while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  174. cpu_relax();
  175. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  176. return -EAGAIN;
  177. /* status shoult be tested according with manual but it doesn't work */
  178. return 0;
  179. }
  180. /**
  181. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  182. * without interruption)
  183. * @num: endpoint number
  184. * @dir: endpoint direction
  185. * @value: true => stall, false => unstall
  186. *
  187. * This function returns an error code
  188. */
  189. static int hw_ep_set_halt(struct ci_hdrc *ci, int num, int dir, int value)
  190. {
  191. if (value != 0 && value != 1)
  192. return -EINVAL;
  193. do {
  194. enum ci_hw_regs reg = OP_ENDPTCTRL + num;
  195. u32 mask_xs = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  196. u32 mask_xr = (dir == TX) ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  197. /* data toggle - reserved for EP0 but it's in ESS */
  198. hw_write(ci, reg, mask_xs|mask_xr,
  199. value ? mask_xs : mask_xr);
  200. } while (value != hw_ep_get_halt(ci, num, dir));
  201. return 0;
  202. }
  203. /**
  204. * hw_is_port_high_speed: test if port is high speed
  205. *
  206. * This function returns true if high speed port
  207. */
  208. static int hw_port_is_high_speed(struct ci_hdrc *ci)
  209. {
  210. return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :
  211. hw_read(ci, OP_PORTSC, PORTSC_HSP);
  212. }
  213. /**
  214. * hw_test_and_clear_complete: test & clear complete status (execute without
  215. * interruption)
  216. * @n: endpoint number
  217. *
  218. * This function returns complete status
  219. */
  220. static int hw_test_and_clear_complete(struct ci_hdrc *ci, int n)
  221. {
  222. n = ep_to_bit(ci, n);
  223. return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n));
  224. }
  225. /**
  226. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  227. * without interruption)
  228. *
  229. * This function returns active interrutps
  230. */
  231. static u32 hw_test_and_clear_intr_active(struct ci_hdrc *ci)
  232. {
  233. u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci);
  234. hw_write(ci, OP_USBSTS, ~0, reg);
  235. return reg;
  236. }
  237. /**
  238. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  239. * interruption)
  240. *
  241. * This function returns guard value
  242. */
  243. static int hw_test_and_clear_setup_guard(struct ci_hdrc *ci)
  244. {
  245. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, 0);
  246. }
  247. /**
  248. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  249. * interruption)
  250. *
  251. * This function returns guard value
  252. */
  253. static int hw_test_and_set_setup_guard(struct ci_hdrc *ci)
  254. {
  255. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  256. }
  257. /**
  258. * hw_usb_set_address: configures USB address (execute without interruption)
  259. * @value: new USB address
  260. *
  261. * This function explicitly sets the address, without the "USBADRA" (advance)
  262. * feature, which is not supported by older versions of the controller.
  263. */
  264. static void hw_usb_set_address(struct ci_hdrc *ci, u8 value)
  265. {
  266. hw_write(ci, OP_DEVICEADDR, DEVICEADDR_USBADR,
  267. value << __ffs(DEVICEADDR_USBADR));
  268. }
  269. /**
  270. * hw_usb_reset: restart device after a bus reset (execute without
  271. * interruption)
  272. *
  273. * This function returns an error code
  274. */
  275. static int hw_usb_reset(struct ci_hdrc *ci)
  276. {
  277. hw_usb_set_address(ci, 0);
  278. /* ESS flushes only at end?!? */
  279. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  280. /* clear setup token semaphores */
  281. hw_write(ci, OP_ENDPTSETUPSTAT, 0, 0);
  282. /* clear complete status */
  283. hw_write(ci, OP_ENDPTCOMPLETE, 0, 0);
  284. /* wait until all bits cleared */
  285. while (hw_read(ci, OP_ENDPTPRIME, ~0))
  286. udelay(10); /* not RTOS friendly */
  287. /* reset all endpoints ? */
  288. /* reset internal status and wait for further instructions
  289. no need to verify the port reset status (ESS does it) */
  290. return 0;
  291. }
  292. /******************************************************************************
  293. * UTIL block
  294. *****************************************************************************/
  295. static int add_td_to_list(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq,
  296. unsigned length)
  297. {
  298. int i;
  299. u32 temp;
  300. struct td_node *lastnode, *node = kzalloc(sizeof(struct td_node),
  301. GFP_ATOMIC);
  302. if (node == NULL)
  303. return -ENOMEM;
  304. node->ptr = dma_pool_zalloc(hwep->td_pool, GFP_ATOMIC, &node->dma);
  305. if (node->ptr == NULL) {
  306. kfree(node);
  307. return -ENOMEM;
  308. }
  309. node->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
  310. node->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
  311. node->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
  312. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) {
  313. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  314. if (hwreq->req.length == 0
  315. || hwreq->req.length % hwep->ep.maxpacket)
  316. mul++;
  317. node->ptr->token |= cpu_to_le32(mul << __ffs(TD_MULTO));
  318. }
  319. temp = (u32) (hwreq->req.dma + hwreq->req.actual);
  320. if (length) {
  321. node->ptr->page[0] = cpu_to_le32(temp);
  322. for (i = 1; i < TD_PAGE_COUNT; i++) {
  323. u32 page = temp + i * CI_HDRC_PAGE_SIZE;
  324. page &= ~TD_RESERVED_MASK;
  325. node->ptr->page[i] = cpu_to_le32(page);
  326. }
  327. }
  328. hwreq->req.actual += length;
  329. if (!list_empty(&hwreq->tds)) {
  330. /* get the last entry */
  331. lastnode = list_entry(hwreq->tds.prev,
  332. struct td_node, td);
  333. lastnode->ptr->next = cpu_to_le32(node->dma);
  334. }
  335. INIT_LIST_HEAD(&node->td);
  336. list_add_tail(&node->td, &hwreq->tds);
  337. return 0;
  338. }
  339. /**
  340. * _usb_addr: calculates endpoint address from direction & number
  341. * @ep: endpoint
  342. */
  343. static inline u8 _usb_addr(struct ci_hw_ep *ep)
  344. {
  345. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  346. }
  347. /**
  348. * _hardware_enqueue: configures a request at hardware level
  349. * @hwep: endpoint
  350. * @hwreq: request
  351. *
  352. * This function returns an error code
  353. */
  354. static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  355. {
  356. struct ci_hdrc *ci = hwep->ci;
  357. int ret = 0;
  358. unsigned rest = hwreq->req.length;
  359. int pages = TD_PAGE_COUNT;
  360. struct td_node *firstnode, *lastnode;
  361. /* don't queue twice */
  362. if (hwreq->req.status == -EALREADY)
  363. return -EALREADY;
  364. hwreq->req.status = -EALREADY;
  365. ret = usb_gadget_map_request_by_dev(ci->dev->parent,
  366. &hwreq->req, hwep->dir);
  367. if (ret)
  368. return ret;
  369. /*
  370. * The first buffer could be not page aligned.
  371. * In that case we have to span into one extra td.
  372. */
  373. if (hwreq->req.dma % PAGE_SIZE)
  374. pages--;
  375. if (rest == 0) {
  376. ret = add_td_to_list(hwep, hwreq, 0);
  377. if (ret < 0)
  378. goto done;
  379. }
  380. while (rest > 0) {
  381. unsigned count = min(hwreq->req.length - hwreq->req.actual,
  382. (unsigned)(pages * CI_HDRC_PAGE_SIZE));
  383. ret = add_td_to_list(hwep, hwreq, count);
  384. if (ret < 0)
  385. goto done;
  386. rest -= count;
  387. }
  388. if (hwreq->req.zero && hwreq->req.length && hwep->dir == TX
  389. && (hwreq->req.length % hwep->ep.maxpacket == 0)) {
  390. ret = add_td_to_list(hwep, hwreq, 0);
  391. if (ret < 0)
  392. goto done;
  393. }
  394. firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
  395. lastnode = list_entry(hwreq->tds.prev,
  396. struct td_node, td);
  397. lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
  398. if (!hwreq->req.no_interrupt)
  399. lastnode->ptr->token |= cpu_to_le32(TD_IOC);
  400. wmb();
  401. hwreq->req.actual = 0;
  402. if (!list_empty(&hwep->qh.queue)) {
  403. struct ci_hw_req *hwreqprev;
  404. int n = hw_ep_bit(hwep->num, hwep->dir);
  405. int tmp_stat;
  406. struct td_node *prevlastnode;
  407. u32 next = firstnode->dma & TD_ADDR_MASK;
  408. hwreqprev = list_entry(hwep->qh.queue.prev,
  409. struct ci_hw_req, queue);
  410. prevlastnode = list_entry(hwreqprev->tds.prev,
  411. struct td_node, td);
  412. prevlastnode->ptr->next = cpu_to_le32(next);
  413. wmb();
  414. if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  415. goto done;
  416. do {
  417. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  418. tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
  419. } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
  420. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
  421. if (tmp_stat)
  422. goto done;
  423. }
  424. /* QH configuration */
  425. hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
  426. hwep->qh.ptr->td.token &=
  427. cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
  428. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == RX) {
  429. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  430. if (hwreq->req.length == 0
  431. || hwreq->req.length % hwep->ep.maxpacket)
  432. mul++;
  433. hwep->qh.ptr->cap |= cpu_to_le32(mul << __ffs(QH_MULT));
  434. }
  435. ret = hw_ep_prime(ci, hwep->num, hwep->dir,
  436. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  437. done:
  438. return ret;
  439. }
  440. /*
  441. * free_pending_td: remove a pending request for the endpoint
  442. * @hwep: endpoint
  443. */
  444. static void free_pending_td(struct ci_hw_ep *hwep)
  445. {
  446. struct td_node *pending = hwep->pending_td;
  447. dma_pool_free(hwep->td_pool, pending->ptr, pending->dma);
  448. hwep->pending_td = NULL;
  449. kfree(pending);
  450. }
  451. static int reprime_dtd(struct ci_hdrc *ci, struct ci_hw_ep *hwep,
  452. struct td_node *node)
  453. {
  454. hwep->qh.ptr->td.next = cpu_to_le32(node->dma);
  455. hwep->qh.ptr->td.token &=
  456. cpu_to_le32(~(TD_STATUS_HALTED | TD_STATUS_ACTIVE));
  457. return hw_ep_prime(ci, hwep->num, hwep->dir,
  458. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  459. }
  460. /**
  461. * _hardware_dequeue: handles a request at hardware level
  462. * @gadget: gadget
  463. * @hwep: endpoint
  464. *
  465. * This function returns an error code
  466. */
  467. static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  468. {
  469. u32 tmptoken;
  470. struct td_node *node, *tmpnode;
  471. unsigned remaining_length;
  472. unsigned actual = hwreq->req.length;
  473. struct ci_hdrc *ci = hwep->ci;
  474. if (hwreq->req.status != -EALREADY)
  475. return -EINVAL;
  476. hwreq->req.status = 0;
  477. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  478. tmptoken = le32_to_cpu(node->ptr->token);
  479. if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
  480. int n = hw_ep_bit(hwep->num, hwep->dir);
  481. if (ci->rev == CI_REVISION_24)
  482. if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
  483. reprime_dtd(ci, hwep, node);
  484. hwreq->req.status = -EALREADY;
  485. return -EBUSY;
  486. }
  487. remaining_length = (tmptoken & TD_TOTAL_BYTES);
  488. remaining_length >>= __ffs(TD_TOTAL_BYTES);
  489. actual -= remaining_length;
  490. hwreq->req.status = tmptoken & TD_STATUS;
  491. if ((TD_STATUS_HALTED & hwreq->req.status)) {
  492. hwreq->req.status = -EPIPE;
  493. break;
  494. } else if ((TD_STATUS_DT_ERR & hwreq->req.status)) {
  495. hwreq->req.status = -EPROTO;
  496. break;
  497. } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
  498. hwreq->req.status = -EILSEQ;
  499. break;
  500. }
  501. if (remaining_length) {
  502. if (hwep->dir == TX) {
  503. hwreq->req.status = -EPROTO;
  504. break;
  505. }
  506. }
  507. /*
  508. * As the hardware could still address the freed td
  509. * which will run the udc unusable, the cleanup of the
  510. * td has to be delayed by one.
  511. */
  512. if (hwep->pending_td)
  513. free_pending_td(hwep);
  514. hwep->pending_td = node;
  515. list_del_init(&node->td);
  516. }
  517. usb_gadget_unmap_request_by_dev(hwep->ci->dev->parent,
  518. &hwreq->req, hwep->dir);
  519. hwreq->req.actual += actual;
  520. if (hwreq->req.status)
  521. return hwreq->req.status;
  522. return hwreq->req.actual;
  523. }
  524. /**
  525. * _ep_nuke: dequeues all endpoint requests
  526. * @hwep: endpoint
  527. *
  528. * This function returns an error code
  529. * Caller must hold lock
  530. */
  531. static int _ep_nuke(struct ci_hw_ep *hwep)
  532. __releases(hwep->lock)
  533. __acquires(hwep->lock)
  534. {
  535. struct td_node *node, *tmpnode;
  536. if (hwep == NULL)
  537. return -EINVAL;
  538. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  539. while (!list_empty(&hwep->qh.queue)) {
  540. /* pop oldest request */
  541. struct ci_hw_req *hwreq = list_entry(hwep->qh.queue.next,
  542. struct ci_hw_req, queue);
  543. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  544. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  545. list_del_init(&node->td);
  546. node->ptr = NULL;
  547. kfree(node);
  548. }
  549. list_del_init(&hwreq->queue);
  550. hwreq->req.status = -ESHUTDOWN;
  551. if (hwreq->req.complete != NULL) {
  552. spin_unlock(hwep->lock);
  553. usb_gadget_giveback_request(&hwep->ep, &hwreq->req);
  554. spin_lock(hwep->lock);
  555. }
  556. }
  557. if (hwep->pending_td)
  558. free_pending_td(hwep);
  559. return 0;
  560. }
  561. static int _ep_set_halt(struct usb_ep *ep, int value, bool check_transfer)
  562. {
  563. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  564. int direction, retval = 0;
  565. unsigned long flags;
  566. if (ep == NULL || hwep->ep.desc == NULL)
  567. return -EINVAL;
  568. if (usb_endpoint_xfer_isoc(hwep->ep.desc))
  569. return -EOPNOTSUPP;
  570. spin_lock_irqsave(hwep->lock, flags);
  571. if (value && hwep->dir == TX && check_transfer &&
  572. !list_empty(&hwep->qh.queue) &&
  573. !usb_endpoint_xfer_control(hwep->ep.desc)) {
  574. spin_unlock_irqrestore(hwep->lock, flags);
  575. return -EAGAIN;
  576. }
  577. direction = hwep->dir;
  578. do {
  579. retval |= hw_ep_set_halt(hwep->ci, hwep->num, hwep->dir, value);
  580. if (!value)
  581. hwep->wedge = 0;
  582. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  583. hwep->dir = (hwep->dir == TX) ? RX : TX;
  584. } while (hwep->dir != direction);
  585. spin_unlock_irqrestore(hwep->lock, flags);
  586. return retval;
  587. }
  588. /**
  589. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  590. * @gadget: gadget
  591. *
  592. * This function returns an error code
  593. */
  594. static int _gadget_stop_activity(struct usb_gadget *gadget)
  595. {
  596. struct usb_ep *ep;
  597. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  598. unsigned long flags;
  599. spin_lock_irqsave(&ci->lock, flags);
  600. ci->gadget.speed = USB_SPEED_UNKNOWN;
  601. ci->remote_wakeup = 0;
  602. ci->suspended = 0;
  603. spin_unlock_irqrestore(&ci->lock, flags);
  604. /* flush all endpoints */
  605. gadget_for_each_ep(ep, gadget) {
  606. usb_ep_fifo_flush(ep);
  607. }
  608. usb_ep_fifo_flush(&ci->ep0out->ep);
  609. usb_ep_fifo_flush(&ci->ep0in->ep);
  610. /* make sure to disable all endpoints */
  611. gadget_for_each_ep(ep, gadget) {
  612. usb_ep_disable(ep);
  613. }
  614. if (ci->status != NULL) {
  615. usb_ep_free_request(&ci->ep0in->ep, ci->status);
  616. ci->status = NULL;
  617. }
  618. return 0;
  619. }
  620. /******************************************************************************
  621. * ISR block
  622. *****************************************************************************/
  623. /**
  624. * isr_reset_handler: USB reset interrupt handler
  625. * @ci: UDC device
  626. *
  627. * This function resets USB engine after a bus reset occurred
  628. */
  629. static void isr_reset_handler(struct ci_hdrc *ci)
  630. __releases(ci->lock)
  631. __acquires(ci->lock)
  632. {
  633. int retval;
  634. spin_unlock(&ci->lock);
  635. if (ci->gadget.speed != USB_SPEED_UNKNOWN)
  636. usb_gadget_udc_reset(&ci->gadget, ci->driver);
  637. retval = _gadget_stop_activity(&ci->gadget);
  638. if (retval)
  639. goto done;
  640. retval = hw_usb_reset(ci);
  641. if (retval)
  642. goto done;
  643. ci->status = usb_ep_alloc_request(&ci->ep0in->ep, GFP_ATOMIC);
  644. if (ci->status == NULL)
  645. retval = -ENOMEM;
  646. done:
  647. spin_lock(&ci->lock);
  648. if (retval)
  649. dev_err(ci->dev, "error: %i\n", retval);
  650. }
  651. /**
  652. * isr_get_status_complete: get_status request complete function
  653. * @ep: endpoint
  654. * @req: request handled
  655. *
  656. * Caller must release lock
  657. */
  658. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  659. {
  660. if (ep == NULL || req == NULL)
  661. return;
  662. kfree(req->buf);
  663. usb_ep_free_request(ep, req);
  664. }
  665. /**
  666. * _ep_queue: queues (submits) an I/O request to an endpoint
  667. * @ep: endpoint
  668. * @req: request
  669. * @gfp_flags: GFP flags (not used)
  670. *
  671. * Caller must hold lock
  672. * This function returns an error code
  673. */
  674. static int _ep_queue(struct usb_ep *ep, struct usb_request *req,
  675. gfp_t __maybe_unused gfp_flags)
  676. {
  677. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  678. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  679. struct ci_hdrc *ci = hwep->ci;
  680. int retval = 0;
  681. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  682. return -EINVAL;
  683. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  684. if (req->length)
  685. hwep = (ci->ep0_dir == RX) ?
  686. ci->ep0out : ci->ep0in;
  687. if (!list_empty(&hwep->qh.queue)) {
  688. _ep_nuke(hwep);
  689. dev_warn(hwep->ci->dev, "endpoint ctrl %X nuked\n",
  690. _usb_addr(hwep));
  691. }
  692. }
  693. if (usb_endpoint_xfer_isoc(hwep->ep.desc) &&
  694. hwreq->req.length > hwep->ep.mult * hwep->ep.maxpacket) {
  695. dev_err(hwep->ci->dev, "request length too big for isochronous\n");
  696. return -EMSGSIZE;
  697. }
  698. /* first nuke then test link, e.g. previous status has not sent */
  699. if (!list_empty(&hwreq->queue)) {
  700. dev_err(hwep->ci->dev, "request already in queue\n");
  701. return -EBUSY;
  702. }
  703. /* push request */
  704. hwreq->req.status = -EINPROGRESS;
  705. hwreq->req.actual = 0;
  706. retval = _hardware_enqueue(hwep, hwreq);
  707. if (retval == -EALREADY)
  708. retval = 0;
  709. if (!retval)
  710. list_add_tail(&hwreq->queue, &hwep->qh.queue);
  711. return retval;
  712. }
  713. /**
  714. * isr_get_status_response: get_status request response
  715. * @ci: ci struct
  716. * @setup: setup request packet
  717. *
  718. * This function returns an error code
  719. */
  720. static int isr_get_status_response(struct ci_hdrc *ci,
  721. struct usb_ctrlrequest *setup)
  722. __releases(hwep->lock)
  723. __acquires(hwep->lock)
  724. {
  725. struct ci_hw_ep *hwep = ci->ep0in;
  726. struct usb_request *req = NULL;
  727. gfp_t gfp_flags = GFP_ATOMIC;
  728. int dir, num, retval;
  729. if (hwep == NULL || setup == NULL)
  730. return -EINVAL;
  731. spin_unlock(hwep->lock);
  732. req = usb_ep_alloc_request(&hwep->ep, gfp_flags);
  733. spin_lock(hwep->lock);
  734. if (req == NULL)
  735. return -ENOMEM;
  736. req->complete = isr_get_status_complete;
  737. req->length = 2;
  738. req->buf = kzalloc(req->length, gfp_flags);
  739. if (req->buf == NULL) {
  740. retval = -ENOMEM;
  741. goto err_free_req;
  742. }
  743. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  744. *(u16 *)req->buf = (ci->remote_wakeup << 1) |
  745. ci->gadget.is_selfpowered;
  746. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  747. == USB_RECIP_ENDPOINT) {
  748. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  749. TX : RX;
  750. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  751. *(u16 *)req->buf = hw_ep_get_halt(ci, num, dir);
  752. }
  753. /* else do nothing; reserved for future use */
  754. retval = _ep_queue(&hwep->ep, req, gfp_flags);
  755. if (retval)
  756. goto err_free_buf;
  757. return 0;
  758. err_free_buf:
  759. kfree(req->buf);
  760. err_free_req:
  761. spin_unlock(hwep->lock);
  762. usb_ep_free_request(&hwep->ep, req);
  763. spin_lock(hwep->lock);
  764. return retval;
  765. }
  766. /**
  767. * isr_setup_status_complete: setup_status request complete function
  768. * @ep: endpoint
  769. * @req: request handled
  770. *
  771. * Caller must release lock. Put the port in test mode if test mode
  772. * feature is selected.
  773. */
  774. static void
  775. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  776. {
  777. struct ci_hdrc *ci = req->context;
  778. unsigned long flags;
  779. if (ci->setaddr) {
  780. hw_usb_set_address(ci, ci->address);
  781. ci->setaddr = false;
  782. if (ci->address)
  783. usb_gadget_set_state(&ci->gadget, USB_STATE_ADDRESS);
  784. }
  785. spin_lock_irqsave(&ci->lock, flags);
  786. if (ci->test_mode)
  787. hw_port_test_set(ci, ci->test_mode);
  788. spin_unlock_irqrestore(&ci->lock, flags);
  789. }
  790. /**
  791. * isr_setup_status_phase: queues the status phase of a setup transation
  792. * @ci: ci struct
  793. *
  794. * This function returns an error code
  795. */
  796. static int isr_setup_status_phase(struct ci_hdrc *ci)
  797. {
  798. struct ci_hw_ep *hwep;
  799. /*
  800. * Unexpected USB controller behavior, caused by bad signal integrity
  801. * or ground reference problems, can lead to isr_setup_status_phase
  802. * being called with ci->status equal to NULL.
  803. * If this situation occurs, you should review your USB hardware design.
  804. */
  805. if (WARN_ON_ONCE(!ci->status))
  806. return -EPIPE;
  807. hwep = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
  808. ci->status->context = ci;
  809. ci->status->complete = isr_setup_status_complete;
  810. return _ep_queue(&hwep->ep, ci->status, GFP_ATOMIC);
  811. }
  812. /**
  813. * isr_tr_complete_low: transaction complete low level handler
  814. * @hwep: endpoint
  815. *
  816. * This function returns an error code
  817. * Caller must hold lock
  818. */
  819. static int isr_tr_complete_low(struct ci_hw_ep *hwep)
  820. __releases(hwep->lock)
  821. __acquires(hwep->lock)
  822. {
  823. struct ci_hw_req *hwreq, *hwreqtemp;
  824. struct ci_hw_ep *hweptemp = hwep;
  825. int retval = 0;
  826. list_for_each_entry_safe(hwreq, hwreqtemp, &hwep->qh.queue,
  827. queue) {
  828. retval = _hardware_dequeue(hwep, hwreq);
  829. if (retval < 0)
  830. break;
  831. list_del_init(&hwreq->queue);
  832. if (hwreq->req.complete != NULL) {
  833. spin_unlock(hwep->lock);
  834. if ((hwep->type == USB_ENDPOINT_XFER_CONTROL) &&
  835. hwreq->req.length)
  836. hweptemp = hwep->ci->ep0in;
  837. usb_gadget_giveback_request(&hweptemp->ep, &hwreq->req);
  838. spin_lock(hwep->lock);
  839. }
  840. }
  841. if (retval == -EBUSY)
  842. retval = 0;
  843. return retval;
  844. }
  845. static int otg_a_alt_hnp_support(struct ci_hdrc *ci)
  846. {
  847. dev_warn(&ci->gadget.dev,
  848. "connect the device to an alternate port if you want HNP\n");
  849. return isr_setup_status_phase(ci);
  850. }
  851. /**
  852. * isr_setup_packet_handler: setup packet handler
  853. * @ci: UDC descriptor
  854. *
  855. * This function handles setup packet
  856. */
  857. static void isr_setup_packet_handler(struct ci_hdrc *ci)
  858. __releases(ci->lock)
  859. __acquires(ci->lock)
  860. {
  861. struct ci_hw_ep *hwep = &ci->ci_hw_ep[0];
  862. struct usb_ctrlrequest req;
  863. int type, num, dir, err = -EINVAL;
  864. u8 tmode = 0;
  865. /*
  866. * Flush data and handshake transactions of previous
  867. * setup packet.
  868. */
  869. _ep_nuke(ci->ep0out);
  870. _ep_nuke(ci->ep0in);
  871. /* read_setup_packet */
  872. do {
  873. hw_test_and_set_setup_guard(ci);
  874. memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
  875. } while (!hw_test_and_clear_setup_guard(ci));
  876. type = req.bRequestType;
  877. ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  878. switch (req.bRequest) {
  879. case USB_REQ_CLEAR_FEATURE:
  880. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  881. le16_to_cpu(req.wValue) ==
  882. USB_ENDPOINT_HALT) {
  883. if (req.wLength != 0)
  884. break;
  885. num = le16_to_cpu(req.wIndex);
  886. dir = (num & USB_ENDPOINT_DIR_MASK) ? TX : RX;
  887. num &= USB_ENDPOINT_NUMBER_MASK;
  888. if (dir == TX)
  889. num += ci->hw_ep_max / 2;
  890. if (!ci->ci_hw_ep[num].wedge) {
  891. spin_unlock(&ci->lock);
  892. err = usb_ep_clear_halt(
  893. &ci->ci_hw_ep[num].ep);
  894. spin_lock(&ci->lock);
  895. if (err)
  896. break;
  897. }
  898. err = isr_setup_status_phase(ci);
  899. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  900. le16_to_cpu(req.wValue) ==
  901. USB_DEVICE_REMOTE_WAKEUP) {
  902. if (req.wLength != 0)
  903. break;
  904. ci->remote_wakeup = 0;
  905. err = isr_setup_status_phase(ci);
  906. } else {
  907. goto delegate;
  908. }
  909. break;
  910. case USB_REQ_GET_STATUS:
  911. if ((type != (USB_DIR_IN|USB_RECIP_DEVICE) ||
  912. le16_to_cpu(req.wIndex) == OTG_STS_SELECTOR) &&
  913. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  914. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  915. goto delegate;
  916. if (le16_to_cpu(req.wLength) != 2 ||
  917. le16_to_cpu(req.wValue) != 0)
  918. break;
  919. err = isr_get_status_response(ci, &req);
  920. break;
  921. case USB_REQ_SET_ADDRESS:
  922. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  923. goto delegate;
  924. if (le16_to_cpu(req.wLength) != 0 ||
  925. le16_to_cpu(req.wIndex) != 0)
  926. break;
  927. ci->address = (u8)le16_to_cpu(req.wValue);
  928. ci->setaddr = true;
  929. err = isr_setup_status_phase(ci);
  930. break;
  931. case USB_REQ_SET_FEATURE:
  932. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  933. le16_to_cpu(req.wValue) ==
  934. USB_ENDPOINT_HALT) {
  935. if (req.wLength != 0)
  936. break;
  937. num = le16_to_cpu(req.wIndex);
  938. dir = (num & USB_ENDPOINT_DIR_MASK) ? TX : RX;
  939. num &= USB_ENDPOINT_NUMBER_MASK;
  940. if (dir == TX)
  941. num += ci->hw_ep_max / 2;
  942. spin_unlock(&ci->lock);
  943. err = _ep_set_halt(&ci->ci_hw_ep[num].ep, 1, false);
  944. spin_lock(&ci->lock);
  945. if (!err)
  946. isr_setup_status_phase(ci);
  947. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  948. if (req.wLength != 0)
  949. break;
  950. switch (le16_to_cpu(req.wValue)) {
  951. case USB_DEVICE_REMOTE_WAKEUP:
  952. ci->remote_wakeup = 1;
  953. err = isr_setup_status_phase(ci);
  954. break;
  955. case USB_DEVICE_TEST_MODE:
  956. tmode = le16_to_cpu(req.wIndex) >> 8;
  957. switch (tmode) {
  958. case TEST_J:
  959. case TEST_K:
  960. case TEST_SE0_NAK:
  961. case TEST_PACKET:
  962. case TEST_FORCE_EN:
  963. ci->test_mode = tmode;
  964. err = isr_setup_status_phase(
  965. ci);
  966. break;
  967. default:
  968. break;
  969. }
  970. break;
  971. case USB_DEVICE_B_HNP_ENABLE:
  972. if (ci_otg_is_fsm_mode(ci)) {
  973. ci->gadget.b_hnp_enable = 1;
  974. err = isr_setup_status_phase(
  975. ci);
  976. }
  977. break;
  978. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  979. if (ci_otg_is_fsm_mode(ci))
  980. err = otg_a_alt_hnp_support(ci);
  981. break;
  982. case USB_DEVICE_A_HNP_SUPPORT:
  983. if (ci_otg_is_fsm_mode(ci)) {
  984. ci->gadget.a_hnp_support = 1;
  985. err = isr_setup_status_phase(
  986. ci);
  987. }
  988. break;
  989. default:
  990. goto delegate;
  991. }
  992. } else {
  993. goto delegate;
  994. }
  995. break;
  996. default:
  997. delegate:
  998. if (req.wLength == 0) /* no data phase */
  999. ci->ep0_dir = TX;
  1000. spin_unlock(&ci->lock);
  1001. err = ci->driver->setup(&ci->gadget, &req);
  1002. spin_lock(&ci->lock);
  1003. break;
  1004. }
  1005. if (err < 0) {
  1006. spin_unlock(&ci->lock);
  1007. if (_ep_set_halt(&hwep->ep, 1, false))
  1008. dev_err(ci->dev, "error: _ep_set_halt\n");
  1009. spin_lock(&ci->lock);
  1010. }
  1011. }
  1012. /**
  1013. * isr_tr_complete_handler: transaction complete interrupt handler
  1014. * @ci: UDC descriptor
  1015. *
  1016. * This function handles traffic events
  1017. */
  1018. static void isr_tr_complete_handler(struct ci_hdrc *ci)
  1019. __releases(ci->lock)
  1020. __acquires(ci->lock)
  1021. {
  1022. unsigned i;
  1023. int err;
  1024. for (i = 0; i < ci->hw_ep_max; i++) {
  1025. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1026. if (hwep->ep.desc == NULL)
  1027. continue; /* not configured */
  1028. if (hw_test_and_clear_complete(ci, i)) {
  1029. err = isr_tr_complete_low(hwep);
  1030. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1031. if (err > 0) /* needs status phase */
  1032. err = isr_setup_status_phase(ci);
  1033. if (err < 0) {
  1034. spin_unlock(&ci->lock);
  1035. if (_ep_set_halt(&hwep->ep, 1, false))
  1036. dev_err(ci->dev,
  1037. "error: _ep_set_halt\n");
  1038. spin_lock(&ci->lock);
  1039. }
  1040. }
  1041. }
  1042. /* Only handle setup packet below */
  1043. if (i == 0 &&
  1044. hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0)))
  1045. isr_setup_packet_handler(ci);
  1046. }
  1047. }
  1048. /******************************************************************************
  1049. * ENDPT block
  1050. *****************************************************************************/
  1051. /**
  1052. * ep_enable: configure endpoint, making it usable
  1053. *
  1054. * Check usb_ep_enable() at "usb_gadget.h" for details
  1055. */
  1056. static int ep_enable(struct usb_ep *ep,
  1057. const struct usb_endpoint_descriptor *desc)
  1058. {
  1059. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1060. int retval = 0;
  1061. unsigned long flags;
  1062. u32 cap = 0;
  1063. if (ep == NULL || desc == NULL)
  1064. return -EINVAL;
  1065. spin_lock_irqsave(hwep->lock, flags);
  1066. /* only internal SW should enable ctrl endpts */
  1067. if (!list_empty(&hwep->qh.queue)) {
  1068. dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
  1069. spin_unlock_irqrestore(hwep->lock, flags);
  1070. return -EBUSY;
  1071. }
  1072. hwep->ep.desc = desc;
  1073. hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1074. hwep->num = usb_endpoint_num(desc);
  1075. hwep->type = usb_endpoint_type(desc);
  1076. hwep->ep.maxpacket = usb_endpoint_maxp(desc);
  1077. hwep->ep.mult = usb_endpoint_maxp_mult(desc);
  1078. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1079. cap |= QH_IOS;
  1080. cap |= QH_ZLT;
  1081. cap |= (hwep->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
  1082. /*
  1083. * For ISO-TX, we set mult at QH as the largest value, and use
  1084. * MultO at TD as real mult value.
  1085. */
  1086. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX)
  1087. cap |= 3 << __ffs(QH_MULT);
  1088. hwep->qh.ptr->cap = cpu_to_le32(cap);
  1089. hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
  1090. if (hwep->num != 0 && hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1091. dev_err(hwep->ci->dev, "Set control xfer at non-ep0\n");
  1092. retval = -EINVAL;
  1093. }
  1094. /*
  1095. * Enable endpoints in the HW other than ep0 as ep0
  1096. * is always enabled
  1097. */
  1098. if (hwep->num)
  1099. retval |= hw_ep_enable(hwep->ci, hwep->num, hwep->dir,
  1100. hwep->type);
  1101. spin_unlock_irqrestore(hwep->lock, flags);
  1102. return retval;
  1103. }
  1104. /**
  1105. * ep_disable: endpoint is no longer usable
  1106. *
  1107. * Check usb_ep_disable() at "usb_gadget.h" for details
  1108. */
  1109. static int ep_disable(struct usb_ep *ep)
  1110. {
  1111. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1112. int direction, retval = 0;
  1113. unsigned long flags;
  1114. if (ep == NULL)
  1115. return -EINVAL;
  1116. else if (hwep->ep.desc == NULL)
  1117. return -EBUSY;
  1118. spin_lock_irqsave(hwep->lock, flags);
  1119. /* only internal SW should disable ctrl endpts */
  1120. direction = hwep->dir;
  1121. do {
  1122. retval |= _ep_nuke(hwep);
  1123. retval |= hw_ep_disable(hwep->ci, hwep->num, hwep->dir);
  1124. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1125. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1126. } while (hwep->dir != direction);
  1127. hwep->ep.desc = NULL;
  1128. spin_unlock_irqrestore(hwep->lock, flags);
  1129. return retval;
  1130. }
  1131. /**
  1132. * ep_alloc_request: allocate a request object to use with this endpoint
  1133. *
  1134. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1135. */
  1136. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1137. {
  1138. struct ci_hw_req *hwreq = NULL;
  1139. if (ep == NULL)
  1140. return NULL;
  1141. hwreq = kzalloc(sizeof(struct ci_hw_req), gfp_flags);
  1142. if (hwreq != NULL) {
  1143. INIT_LIST_HEAD(&hwreq->queue);
  1144. INIT_LIST_HEAD(&hwreq->tds);
  1145. }
  1146. return (hwreq == NULL) ? NULL : &hwreq->req;
  1147. }
  1148. /**
  1149. * ep_free_request: frees a request object
  1150. *
  1151. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1152. */
  1153. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1154. {
  1155. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1156. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1157. struct td_node *node, *tmpnode;
  1158. unsigned long flags;
  1159. if (ep == NULL || req == NULL) {
  1160. return;
  1161. } else if (!list_empty(&hwreq->queue)) {
  1162. dev_err(hwep->ci->dev, "freeing queued request\n");
  1163. return;
  1164. }
  1165. spin_lock_irqsave(hwep->lock, flags);
  1166. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1167. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1168. list_del_init(&node->td);
  1169. node->ptr = NULL;
  1170. kfree(node);
  1171. }
  1172. kfree(hwreq);
  1173. spin_unlock_irqrestore(hwep->lock, flags);
  1174. }
  1175. /**
  1176. * ep_queue: queues (submits) an I/O request to an endpoint
  1177. *
  1178. * Check usb_ep_queue()* at usb_gadget.h" for details
  1179. */
  1180. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1181. gfp_t __maybe_unused gfp_flags)
  1182. {
  1183. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1184. int retval = 0;
  1185. unsigned long flags;
  1186. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  1187. return -EINVAL;
  1188. spin_lock_irqsave(hwep->lock, flags);
  1189. retval = _ep_queue(ep, req, gfp_flags);
  1190. spin_unlock_irqrestore(hwep->lock, flags);
  1191. return retval;
  1192. }
  1193. /**
  1194. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1195. *
  1196. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1197. */
  1198. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1199. {
  1200. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1201. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1202. unsigned long flags;
  1203. struct td_node *node, *tmpnode;
  1204. if (ep == NULL || req == NULL || hwreq->req.status != -EALREADY ||
  1205. hwep->ep.desc == NULL || list_empty(&hwreq->queue) ||
  1206. list_empty(&hwep->qh.queue))
  1207. return -EINVAL;
  1208. spin_lock_irqsave(hwep->lock, flags);
  1209. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1210. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1211. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1212. list_del(&node->td);
  1213. kfree(node);
  1214. }
  1215. /* pop request */
  1216. list_del_init(&hwreq->queue);
  1217. usb_gadget_unmap_request(&hwep->ci->gadget, req, hwep->dir);
  1218. req->status = -ECONNRESET;
  1219. if (hwreq->req.complete != NULL) {
  1220. spin_unlock(hwep->lock);
  1221. usb_gadget_giveback_request(&hwep->ep, &hwreq->req);
  1222. spin_lock(hwep->lock);
  1223. }
  1224. spin_unlock_irqrestore(hwep->lock, flags);
  1225. return 0;
  1226. }
  1227. /**
  1228. * ep_set_halt: sets the endpoint halt feature
  1229. *
  1230. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1231. */
  1232. static int ep_set_halt(struct usb_ep *ep, int value)
  1233. {
  1234. return _ep_set_halt(ep, value, true);
  1235. }
  1236. /**
  1237. * ep_set_wedge: sets the halt feature and ignores clear requests
  1238. *
  1239. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1240. */
  1241. static int ep_set_wedge(struct usb_ep *ep)
  1242. {
  1243. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1244. unsigned long flags;
  1245. if (ep == NULL || hwep->ep.desc == NULL)
  1246. return -EINVAL;
  1247. spin_lock_irqsave(hwep->lock, flags);
  1248. hwep->wedge = 1;
  1249. spin_unlock_irqrestore(hwep->lock, flags);
  1250. return usb_ep_set_halt(ep);
  1251. }
  1252. /**
  1253. * ep_fifo_flush: flushes contents of a fifo
  1254. *
  1255. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1256. */
  1257. static void ep_fifo_flush(struct usb_ep *ep)
  1258. {
  1259. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1260. unsigned long flags;
  1261. if (ep == NULL) {
  1262. dev_err(hwep->ci->dev, "%02X: -EINVAL\n", _usb_addr(hwep));
  1263. return;
  1264. }
  1265. spin_lock_irqsave(hwep->lock, flags);
  1266. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1267. spin_unlock_irqrestore(hwep->lock, flags);
  1268. }
  1269. /**
  1270. * Endpoint-specific part of the API to the USB controller hardware
  1271. * Check "usb_gadget.h" for details
  1272. */
  1273. static const struct usb_ep_ops usb_ep_ops = {
  1274. .enable = ep_enable,
  1275. .disable = ep_disable,
  1276. .alloc_request = ep_alloc_request,
  1277. .free_request = ep_free_request,
  1278. .queue = ep_queue,
  1279. .dequeue = ep_dequeue,
  1280. .set_halt = ep_set_halt,
  1281. .set_wedge = ep_set_wedge,
  1282. .fifo_flush = ep_fifo_flush,
  1283. };
  1284. /******************************************************************************
  1285. * GADGET block
  1286. *****************************************************************************/
  1287. static int ci_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
  1288. {
  1289. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1290. unsigned long flags;
  1291. int gadget_ready = 0;
  1292. spin_lock_irqsave(&ci->lock, flags);
  1293. ci->vbus_active = is_active;
  1294. if (ci->driver)
  1295. gadget_ready = 1;
  1296. spin_unlock_irqrestore(&ci->lock, flags);
  1297. if (ci->usb_phy)
  1298. usb_phy_set_charger_state(ci->usb_phy, is_active ?
  1299. USB_CHARGER_PRESENT : USB_CHARGER_ABSENT);
  1300. if (gadget_ready) {
  1301. if (is_active) {
  1302. pm_runtime_get_sync(&_gadget->dev);
  1303. hw_device_reset(ci);
  1304. hw_device_state(ci, ci->ep0out->qh.dma);
  1305. usb_gadget_set_state(_gadget, USB_STATE_POWERED);
  1306. usb_udc_vbus_handler(_gadget, true);
  1307. } else {
  1308. usb_udc_vbus_handler(_gadget, false);
  1309. if (ci->driver)
  1310. ci->driver->disconnect(&ci->gadget);
  1311. hw_device_state(ci, 0);
  1312. if (ci->platdata->notify_event)
  1313. ci->platdata->notify_event(ci,
  1314. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1315. _gadget_stop_activity(&ci->gadget);
  1316. pm_runtime_put_sync(&_gadget->dev);
  1317. usb_gadget_set_state(_gadget, USB_STATE_NOTATTACHED);
  1318. }
  1319. }
  1320. return 0;
  1321. }
  1322. static int ci_udc_wakeup(struct usb_gadget *_gadget)
  1323. {
  1324. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1325. unsigned long flags;
  1326. int ret = 0;
  1327. spin_lock_irqsave(&ci->lock, flags);
  1328. if (!ci->remote_wakeup) {
  1329. ret = -EOPNOTSUPP;
  1330. goto out;
  1331. }
  1332. if (!hw_read(ci, OP_PORTSC, PORTSC_SUSP)) {
  1333. ret = -EINVAL;
  1334. goto out;
  1335. }
  1336. hw_write(ci, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  1337. out:
  1338. spin_unlock_irqrestore(&ci->lock, flags);
  1339. return ret;
  1340. }
  1341. static int ci_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1342. {
  1343. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1344. if (ci->usb_phy)
  1345. return usb_phy_set_power(ci->usb_phy, ma);
  1346. return -ENOTSUPP;
  1347. }
  1348. static int ci_udc_selfpowered(struct usb_gadget *_gadget, int is_on)
  1349. {
  1350. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1351. struct ci_hw_ep *hwep = ci->ep0in;
  1352. unsigned long flags;
  1353. spin_lock_irqsave(hwep->lock, flags);
  1354. _gadget->is_selfpowered = (is_on != 0);
  1355. spin_unlock_irqrestore(hwep->lock, flags);
  1356. return 0;
  1357. }
  1358. /* Change Data+ pullup status
  1359. * this func is used by usb_gadget_connect/disconnet
  1360. */
  1361. static int ci_udc_pullup(struct usb_gadget *_gadget, int is_on)
  1362. {
  1363. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1364. /*
  1365. * Data+ pullup controlled by OTG state machine in OTG fsm mode;
  1366. * and don't touch Data+ in host mode for dual role config.
  1367. */
  1368. if (ci_otg_is_fsm_mode(ci) || ci->role == CI_ROLE_HOST)
  1369. return 0;
  1370. pm_runtime_get_sync(&ci->gadget.dev);
  1371. if (is_on)
  1372. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  1373. else
  1374. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  1375. pm_runtime_put_sync(&ci->gadget.dev);
  1376. return 0;
  1377. }
  1378. static int ci_udc_start(struct usb_gadget *gadget,
  1379. struct usb_gadget_driver *driver);
  1380. static int ci_udc_stop(struct usb_gadget *gadget);
  1381. /**
  1382. * Device operations part of the API to the USB controller hardware,
  1383. * which don't involve endpoints (or i/o)
  1384. * Check "usb_gadget.h" for details
  1385. */
  1386. static const struct usb_gadget_ops usb_gadget_ops = {
  1387. .vbus_session = ci_udc_vbus_session,
  1388. .wakeup = ci_udc_wakeup,
  1389. .set_selfpowered = ci_udc_selfpowered,
  1390. .pullup = ci_udc_pullup,
  1391. .vbus_draw = ci_udc_vbus_draw,
  1392. .udc_start = ci_udc_start,
  1393. .udc_stop = ci_udc_stop,
  1394. };
  1395. static int init_eps(struct ci_hdrc *ci)
  1396. {
  1397. int retval = 0, i, j;
  1398. for (i = 0; i < ci->hw_ep_max/2; i++)
  1399. for (j = RX; j <= TX; j++) {
  1400. int k = i + j * ci->hw_ep_max/2;
  1401. struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
  1402. scnprintf(hwep->name, sizeof(hwep->name), "ep%i%s", i,
  1403. (j == TX) ? "in" : "out");
  1404. hwep->ci = ci;
  1405. hwep->lock = &ci->lock;
  1406. hwep->td_pool = ci->td_pool;
  1407. hwep->ep.name = hwep->name;
  1408. hwep->ep.ops = &usb_ep_ops;
  1409. if (i == 0) {
  1410. hwep->ep.caps.type_control = true;
  1411. } else {
  1412. hwep->ep.caps.type_iso = true;
  1413. hwep->ep.caps.type_bulk = true;
  1414. hwep->ep.caps.type_int = true;
  1415. }
  1416. if (j == TX)
  1417. hwep->ep.caps.dir_in = true;
  1418. else
  1419. hwep->ep.caps.dir_out = true;
  1420. /*
  1421. * for ep0: maxP defined in desc, for other
  1422. * eps, maxP is set by epautoconfig() called
  1423. * by gadget layer
  1424. */
  1425. usb_ep_set_maxpacket_limit(&hwep->ep, (unsigned short)~0);
  1426. INIT_LIST_HEAD(&hwep->qh.queue);
  1427. hwep->qh.ptr = dma_pool_zalloc(ci->qh_pool, GFP_KERNEL,
  1428. &hwep->qh.dma);
  1429. if (hwep->qh.ptr == NULL)
  1430. retval = -ENOMEM;
  1431. /*
  1432. * set up shorthands for ep0 out and in endpoints,
  1433. * don't add to gadget's ep_list
  1434. */
  1435. if (i == 0) {
  1436. if (j == RX)
  1437. ci->ep0out = hwep;
  1438. else
  1439. ci->ep0in = hwep;
  1440. usb_ep_set_maxpacket_limit(&hwep->ep, CTRL_PAYLOAD_MAX);
  1441. continue;
  1442. }
  1443. list_add_tail(&hwep->ep.ep_list, &ci->gadget.ep_list);
  1444. }
  1445. return retval;
  1446. }
  1447. static void destroy_eps(struct ci_hdrc *ci)
  1448. {
  1449. int i;
  1450. for (i = 0; i < ci->hw_ep_max; i++) {
  1451. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1452. if (hwep->pending_td)
  1453. free_pending_td(hwep);
  1454. dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
  1455. }
  1456. }
  1457. /**
  1458. * ci_udc_start: register a gadget driver
  1459. * @gadget: our gadget
  1460. * @driver: the driver being registered
  1461. *
  1462. * Interrupts are enabled here.
  1463. */
  1464. static int ci_udc_start(struct usb_gadget *gadget,
  1465. struct usb_gadget_driver *driver)
  1466. {
  1467. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1468. int retval = -ENOMEM;
  1469. if (driver->disconnect == NULL)
  1470. return -EINVAL;
  1471. ci->ep0out->ep.desc = &ctrl_endpt_out_desc;
  1472. retval = usb_ep_enable(&ci->ep0out->ep);
  1473. if (retval)
  1474. return retval;
  1475. ci->ep0in->ep.desc = &ctrl_endpt_in_desc;
  1476. retval = usb_ep_enable(&ci->ep0in->ep);
  1477. if (retval)
  1478. return retval;
  1479. ci->driver = driver;
  1480. /* Start otg fsm for B-device */
  1481. if (ci_otg_is_fsm_mode(ci) && ci->fsm.id) {
  1482. ci_hdrc_otg_fsm_start(ci);
  1483. return retval;
  1484. }
  1485. pm_runtime_get_sync(&ci->gadget.dev);
  1486. if (ci->vbus_active) {
  1487. hw_device_reset(ci);
  1488. } else {
  1489. usb_udc_vbus_handler(&ci->gadget, false);
  1490. pm_runtime_put_sync(&ci->gadget.dev);
  1491. return retval;
  1492. }
  1493. retval = hw_device_state(ci, ci->ep0out->qh.dma);
  1494. if (retval)
  1495. pm_runtime_put_sync(&ci->gadget.dev);
  1496. return retval;
  1497. }
  1498. static void ci_udc_stop_for_otg_fsm(struct ci_hdrc *ci)
  1499. {
  1500. if (!ci_otg_is_fsm_mode(ci))
  1501. return;
  1502. mutex_lock(&ci->fsm.lock);
  1503. if (ci->fsm.otg->state == OTG_STATE_A_PERIPHERAL) {
  1504. ci->fsm.a_bidl_adis_tmout = 1;
  1505. ci_hdrc_otg_fsm_start(ci);
  1506. } else if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) {
  1507. ci->fsm.protocol = PROTO_UNDEF;
  1508. ci->fsm.otg->state = OTG_STATE_UNDEFINED;
  1509. }
  1510. mutex_unlock(&ci->fsm.lock);
  1511. }
  1512. /**
  1513. * ci_udc_stop: unregister a gadget driver
  1514. */
  1515. static int ci_udc_stop(struct usb_gadget *gadget)
  1516. {
  1517. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1518. unsigned long flags;
  1519. spin_lock_irqsave(&ci->lock, flags);
  1520. if (ci->vbus_active) {
  1521. hw_device_state(ci, 0);
  1522. spin_unlock_irqrestore(&ci->lock, flags);
  1523. if (ci->platdata->notify_event)
  1524. ci->platdata->notify_event(ci,
  1525. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1526. _gadget_stop_activity(&ci->gadget);
  1527. spin_lock_irqsave(&ci->lock, flags);
  1528. pm_runtime_put(&ci->gadget.dev);
  1529. }
  1530. ci->driver = NULL;
  1531. spin_unlock_irqrestore(&ci->lock, flags);
  1532. ci_udc_stop_for_otg_fsm(ci);
  1533. return 0;
  1534. }
  1535. /******************************************************************************
  1536. * BUS block
  1537. *****************************************************************************/
  1538. /**
  1539. * udc_irq: ci interrupt handler
  1540. *
  1541. * This function returns IRQ_HANDLED if the IRQ has been handled
  1542. * It locks access to registers
  1543. */
  1544. static irqreturn_t udc_irq(struct ci_hdrc *ci)
  1545. {
  1546. irqreturn_t retval;
  1547. u32 intr;
  1548. if (ci == NULL)
  1549. return IRQ_HANDLED;
  1550. spin_lock(&ci->lock);
  1551. if (ci->platdata->flags & CI_HDRC_REGS_SHARED) {
  1552. if (hw_read(ci, OP_USBMODE, USBMODE_CM) !=
  1553. USBMODE_CM_DC) {
  1554. spin_unlock(&ci->lock);
  1555. return IRQ_NONE;
  1556. }
  1557. }
  1558. intr = hw_test_and_clear_intr_active(ci);
  1559. if (intr) {
  1560. /* order defines priority - do NOT change it */
  1561. if (USBi_URI & intr)
  1562. isr_reset_handler(ci);
  1563. if (USBi_PCI & intr) {
  1564. ci->gadget.speed = hw_port_is_high_speed(ci) ?
  1565. USB_SPEED_HIGH : USB_SPEED_FULL;
  1566. if (ci->suspended) {
  1567. if (ci->driver->resume) {
  1568. spin_unlock(&ci->lock);
  1569. ci->driver->resume(&ci->gadget);
  1570. spin_lock(&ci->lock);
  1571. }
  1572. ci->suspended = 0;
  1573. usb_gadget_set_state(&ci->gadget,
  1574. ci->resume_state);
  1575. }
  1576. }
  1577. if (USBi_UI & intr)
  1578. isr_tr_complete_handler(ci);
  1579. if ((USBi_SLI & intr) && !(ci->suspended)) {
  1580. ci->suspended = 1;
  1581. ci->resume_state = ci->gadget.state;
  1582. if (ci->gadget.speed != USB_SPEED_UNKNOWN &&
  1583. ci->driver->suspend) {
  1584. spin_unlock(&ci->lock);
  1585. ci->driver->suspend(&ci->gadget);
  1586. spin_lock(&ci->lock);
  1587. }
  1588. usb_gadget_set_state(&ci->gadget,
  1589. USB_STATE_SUSPENDED);
  1590. }
  1591. retval = IRQ_HANDLED;
  1592. } else {
  1593. retval = IRQ_NONE;
  1594. }
  1595. spin_unlock(&ci->lock);
  1596. return retval;
  1597. }
  1598. /**
  1599. * udc_start: initialize gadget role
  1600. * @ci: chipidea controller
  1601. */
  1602. static int udc_start(struct ci_hdrc *ci)
  1603. {
  1604. struct device *dev = ci->dev;
  1605. struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
  1606. int retval = 0;
  1607. ci->gadget.ops = &usb_gadget_ops;
  1608. ci->gadget.speed = USB_SPEED_UNKNOWN;
  1609. ci->gadget.max_speed = USB_SPEED_HIGH;
  1610. ci->gadget.name = ci->platdata->name;
  1611. ci->gadget.otg_caps = otg_caps;
  1612. if (ci->platdata->flags & CI_HDRC_REQUIRES_ALIGNED_DMA)
  1613. ci->gadget.quirk_avoids_skb_reserve = 1;
  1614. if (ci->is_otg && (otg_caps->hnp_support || otg_caps->srp_support ||
  1615. otg_caps->adp_support))
  1616. ci->gadget.is_otg = 1;
  1617. INIT_LIST_HEAD(&ci->gadget.ep_list);
  1618. /* alloc resources */
  1619. ci->qh_pool = dma_pool_create("ci_hw_qh", dev->parent,
  1620. sizeof(struct ci_hw_qh),
  1621. 64, CI_HDRC_PAGE_SIZE);
  1622. if (ci->qh_pool == NULL)
  1623. return -ENOMEM;
  1624. ci->td_pool = dma_pool_create("ci_hw_td", dev->parent,
  1625. sizeof(struct ci_hw_td),
  1626. 64, CI_HDRC_PAGE_SIZE);
  1627. if (ci->td_pool == NULL) {
  1628. retval = -ENOMEM;
  1629. goto free_qh_pool;
  1630. }
  1631. retval = init_eps(ci);
  1632. if (retval)
  1633. goto free_pools;
  1634. ci->gadget.ep0 = &ci->ep0in->ep;
  1635. retval = usb_add_gadget_udc(dev, &ci->gadget);
  1636. if (retval)
  1637. goto destroy_eps;
  1638. pm_runtime_no_callbacks(&ci->gadget.dev);
  1639. pm_runtime_enable(&ci->gadget.dev);
  1640. return retval;
  1641. destroy_eps:
  1642. destroy_eps(ci);
  1643. free_pools:
  1644. dma_pool_destroy(ci->td_pool);
  1645. free_qh_pool:
  1646. dma_pool_destroy(ci->qh_pool);
  1647. return retval;
  1648. }
  1649. /**
  1650. * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
  1651. *
  1652. * No interrupts active, the IRQ has been released
  1653. */
  1654. void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
  1655. {
  1656. if (!ci->roles[CI_ROLE_GADGET])
  1657. return;
  1658. usb_del_gadget_udc(&ci->gadget);
  1659. destroy_eps(ci);
  1660. dma_pool_destroy(ci->td_pool);
  1661. dma_pool_destroy(ci->qh_pool);
  1662. }
  1663. static int udc_id_switch_for_device(struct ci_hdrc *ci)
  1664. {
  1665. if (ci->is_otg)
  1666. /* Clear and enable BSV irq */
  1667. hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
  1668. OTGSC_BSVIS | OTGSC_BSVIE);
  1669. return 0;
  1670. }
  1671. static void udc_id_switch_for_host(struct ci_hdrc *ci)
  1672. {
  1673. /*
  1674. * host doesn't care B_SESSION_VALID event
  1675. * so clear and disbale BSV irq
  1676. */
  1677. if (ci->is_otg)
  1678. hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
  1679. ci->vbus_active = 0;
  1680. }
  1681. /**
  1682. * ci_hdrc_gadget_init - initialize device related bits
  1683. * ci: the controller
  1684. *
  1685. * This function initializes the gadget, if the device is "device capable".
  1686. */
  1687. int ci_hdrc_gadget_init(struct ci_hdrc *ci)
  1688. {
  1689. struct ci_role_driver *rdrv;
  1690. int ret;
  1691. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
  1692. return -ENXIO;
  1693. rdrv = devm_kzalloc(ci->dev, sizeof(*rdrv), GFP_KERNEL);
  1694. if (!rdrv)
  1695. return -ENOMEM;
  1696. rdrv->start = udc_id_switch_for_device;
  1697. rdrv->stop = udc_id_switch_for_host;
  1698. rdrv->irq = udc_irq;
  1699. rdrv->name = "gadget";
  1700. ret = udc_start(ci);
  1701. if (!ret)
  1702. ci->roles[CI_ROLE_GADGET] = rdrv;
  1703. return ret;
  1704. }