rs.h 20 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2017 Intel Deutschland GmbH
  10. * Copyright(c) 2018 Intel Corporation
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called COPYING.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <linuxwifi@intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. * BSD LICENSE
  29. *
  30. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  31. * Copyright(c) 2017 Intel Deutschland GmbH
  32. * Copyright(c) 2018 Intel Corporation
  33. * All rights reserved.
  34. *
  35. * Redistribution and use in source and binary forms, with or without
  36. * modification, are permitted provided that the following conditions
  37. * are met:
  38. *
  39. * * Redistributions of source code must retain the above copyright
  40. * notice, this list of conditions and the following disclaimer.
  41. * * Redistributions in binary form must reproduce the above copyright
  42. * notice, this list of conditions and the following disclaimer in
  43. * the documentation and/or other materials provided with the
  44. * distribution.
  45. * * Neither the name Intel Corporation nor the names of its
  46. * contributors may be used to endorse or promote products derived
  47. * from this software without specific prior written permission.
  48. *
  49. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  50. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  51. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  52. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  53. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  54. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  55. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  56. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  57. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  58. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  59. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  60. *****************************************************************************/
  61. #ifndef __iwl_fw_api_rs_h__
  62. #define __iwl_fw_api_rs_h__
  63. #include "mac.h"
  64. /**
  65. * enum iwl_tlc_mng_cfg_flags_enum - options for TLC config flags
  66. * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for
  67. * bandwidths <= 80MHz
  68. * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
  69. * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
  70. * bandwidth
  71. * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation
  72. * for BPSK (MCS 0) with 1 spatial
  73. * stream
  74. * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
  75. * for BPSK (MCS 0) with 2 spatial
  76. * streams
  77. */
  78. enum iwl_tlc_mng_cfg_flags {
  79. IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
  80. IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
  81. IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
  82. IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
  83. IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
  84. };
  85. /**
  86. * enum iwl_tlc_mng_cfg_cw - channel width options
  87. * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
  88. * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
  89. * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
  90. * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
  91. * @IWL_TLC_MNG_CH_WIDTH_LAST: maximum value
  92. */
  93. enum iwl_tlc_mng_cfg_cw {
  94. IWL_TLC_MNG_CH_WIDTH_20MHZ,
  95. IWL_TLC_MNG_CH_WIDTH_40MHZ,
  96. IWL_TLC_MNG_CH_WIDTH_80MHZ,
  97. IWL_TLC_MNG_CH_WIDTH_160MHZ,
  98. IWL_TLC_MNG_CH_WIDTH_LAST = IWL_TLC_MNG_CH_WIDTH_160MHZ,
  99. };
  100. /**
  101. * enum iwl_tlc_mng_cfg_chains - possible chains
  102. * @IWL_TLC_MNG_CHAIN_A_MSK: chain A
  103. * @IWL_TLC_MNG_CHAIN_B_MSK: chain B
  104. */
  105. enum iwl_tlc_mng_cfg_chains {
  106. IWL_TLC_MNG_CHAIN_A_MSK = BIT(0),
  107. IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
  108. };
  109. /**
  110. * enum iwl_tlc_mng_cfg_mode - supported modes
  111. * @IWL_TLC_MNG_MODE_CCK: enable CCK
  112. * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT)
  113. * @IWL_TLC_MNG_MODE_NON_HT: enable non HT
  114. * @IWL_TLC_MNG_MODE_HT: enable HT
  115. * @IWL_TLC_MNG_MODE_VHT: enable VHT
  116. * @IWL_TLC_MNG_MODE_HE: enable HE
  117. * @IWL_TLC_MNG_MODE_INVALID: invalid value
  118. * @IWL_TLC_MNG_MODE_NUM: a count of possible modes
  119. */
  120. enum iwl_tlc_mng_cfg_mode {
  121. IWL_TLC_MNG_MODE_CCK = 0,
  122. IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK,
  123. IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK,
  124. IWL_TLC_MNG_MODE_HT,
  125. IWL_TLC_MNG_MODE_VHT,
  126. IWL_TLC_MNG_MODE_HE,
  127. IWL_TLC_MNG_MODE_INVALID,
  128. IWL_TLC_MNG_MODE_NUM = IWL_TLC_MNG_MODE_INVALID,
  129. };
  130. /**
  131. * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates
  132. * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0
  133. * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1
  134. * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2
  135. * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3
  136. * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4
  137. * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5
  138. * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6
  139. * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7
  140. * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8
  141. * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9
  142. * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10
  143. * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11
  144. * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
  145. */
  146. enum iwl_tlc_mng_ht_rates {
  147. IWL_TLC_MNG_HT_RATE_MCS0 = 0,
  148. IWL_TLC_MNG_HT_RATE_MCS1,
  149. IWL_TLC_MNG_HT_RATE_MCS2,
  150. IWL_TLC_MNG_HT_RATE_MCS3,
  151. IWL_TLC_MNG_HT_RATE_MCS4,
  152. IWL_TLC_MNG_HT_RATE_MCS5,
  153. IWL_TLC_MNG_HT_RATE_MCS6,
  154. IWL_TLC_MNG_HT_RATE_MCS7,
  155. IWL_TLC_MNG_HT_RATE_MCS8,
  156. IWL_TLC_MNG_HT_RATE_MCS9,
  157. IWL_TLC_MNG_HT_RATE_MCS10,
  158. IWL_TLC_MNG_HT_RATE_MCS11,
  159. IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11,
  160. };
  161. /* Maximum supported tx antennas number */
  162. #define MAX_NSS 2
  163. /**
  164. * struct tlc_config_cmd - TLC configuration
  165. * @sta_id: station id
  166. * @reserved1: reserved
  167. * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw
  168. * @mode: &enum iwl_tlc_mng_cfg_mode
  169. * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
  170. * @amsdu: TX amsdu is supported
  171. * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
  172. * @non_ht_rates: bitmap of supported legacy rates
  173. * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width>
  174. * pair (0 - 80mhz width and below, 1 - 160mhz).
  175. * @max_mpdu_len: max MPDU length, in bytes
  176. * @sgi_ch_width_supp: bitmap of SGI support per channel width
  177. * use BIT(@enum iwl_tlc_mng_cfg_cw)
  178. * @reserved2: reserved
  179. */
  180. struct iwl_tlc_config_cmd {
  181. u8 sta_id;
  182. u8 reserved1[3];
  183. u8 max_ch_width;
  184. u8 mode;
  185. u8 chains;
  186. u8 amsdu;
  187. __le16 flags;
  188. __le16 non_ht_rates;
  189. __le16 ht_rates[MAX_NSS][2];
  190. __le16 max_mpdu_len;
  191. u8 sgi_ch_width_supp;
  192. u8 reserved2[1];
  193. } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_2 */
  194. /**
  195. * enum iwl_tlc_update_flags - updated fields
  196. * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update
  197. * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
  198. */
  199. enum iwl_tlc_update_flags {
  200. IWL_TLC_NOTIF_FLAG_RATE = BIT(0),
  201. IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1),
  202. };
  203. /**
  204. * struct iwl_tlc_update_notif - TLC notification from FW
  205. * @sta_id: station id
  206. * @reserved: reserved
  207. * @flags: bitmap of notifications reported
  208. * @rate: current initial rate
  209. * @amsdu_size: Max AMSDU size, in bytes
  210. * @amsdu_enabled: bitmap for per-TID AMSDU enablement
  211. */
  212. struct iwl_tlc_update_notif {
  213. u8 sta_id;
  214. u8 reserved[3];
  215. __le32 flags;
  216. __le32 rate;
  217. __le32 amsdu_size;
  218. __le32 amsdu_enabled;
  219. } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */
  220. /*
  221. * These serve as indexes into
  222. * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT];
  223. * TODO: avoid overlap between legacy and HT rates
  224. */
  225. enum {
  226. IWL_RATE_1M_INDEX = 0,
  227. IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX,
  228. IWL_RATE_2M_INDEX,
  229. IWL_RATE_5M_INDEX,
  230. IWL_RATE_11M_INDEX,
  231. IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX,
  232. IWL_RATE_6M_INDEX,
  233. IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX,
  234. IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX,
  235. IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX,
  236. IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX,
  237. IWL_RATE_9M_INDEX,
  238. IWL_RATE_12M_INDEX,
  239. IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX,
  240. IWL_RATE_18M_INDEX,
  241. IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX,
  242. IWL_RATE_24M_INDEX,
  243. IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX,
  244. IWL_RATE_36M_INDEX,
  245. IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX,
  246. IWL_RATE_48M_INDEX,
  247. IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX,
  248. IWL_RATE_54M_INDEX,
  249. IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX,
  250. IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX,
  251. IWL_RATE_60M_INDEX,
  252. IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX,
  253. IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX,
  254. IWL_RATE_MCS_8_INDEX,
  255. IWL_RATE_MCS_9_INDEX,
  256. IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX,
  257. IWL_RATE_MCS_10_INDEX,
  258. IWL_RATE_MCS_11_INDEX,
  259. IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX,
  260. IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1,
  261. IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1,
  262. };
  263. #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX)
  264. /* fw API values for legacy bit rates, both OFDM and CCK */
  265. enum {
  266. IWL_RATE_6M_PLCP = 13,
  267. IWL_RATE_9M_PLCP = 15,
  268. IWL_RATE_12M_PLCP = 5,
  269. IWL_RATE_18M_PLCP = 7,
  270. IWL_RATE_24M_PLCP = 9,
  271. IWL_RATE_36M_PLCP = 11,
  272. IWL_RATE_48M_PLCP = 1,
  273. IWL_RATE_54M_PLCP = 3,
  274. IWL_RATE_1M_PLCP = 10,
  275. IWL_RATE_2M_PLCP = 20,
  276. IWL_RATE_5M_PLCP = 55,
  277. IWL_RATE_11M_PLCP = 110,
  278. IWL_RATE_INVM_PLCP = -1,
  279. };
  280. /*
  281. * rate_n_flags bit fields
  282. *
  283. * The 32-bit value has different layouts in the low 8 bites depending on the
  284. * format. There are three formats, HT, VHT and legacy (11abg, with subformats
  285. * for CCK and OFDM).
  286. *
  287. * High-throughput (HT) rate format
  288. * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
  289. * Very High-throughput (VHT) rate format
  290. * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
  291. * Legacy OFDM rate format for bits 7:0
  292. * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
  293. * Legacy CCK rate format for bits 7:0:
  294. * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
  295. */
  296. /* Bit 8: (1) HT format, (0) legacy or VHT format */
  297. #define RATE_MCS_HT_POS 8
  298. #define RATE_MCS_HT_MSK (1 << RATE_MCS_HT_POS)
  299. /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
  300. #define RATE_MCS_CCK_POS 9
  301. #define RATE_MCS_CCK_MSK (1 << RATE_MCS_CCK_POS)
  302. /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
  303. #define RATE_MCS_VHT_POS 26
  304. #define RATE_MCS_VHT_MSK (1 << RATE_MCS_VHT_POS)
  305. /*
  306. * High-throughput (HT) rate format for bits 7:0
  307. *
  308. * 2-0: MCS rate base
  309. * 0) 6 Mbps
  310. * 1) 12 Mbps
  311. * 2) 18 Mbps
  312. * 3) 24 Mbps
  313. * 4) 36 Mbps
  314. * 5) 48 Mbps
  315. * 6) 54 Mbps
  316. * 7) 60 Mbps
  317. * 4-3: 0) Single stream (SISO)
  318. * 1) Dual stream (MIMO)
  319. * 2) Triple stream (MIMO)
  320. * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
  321. * (bits 7-6 are zero)
  322. *
  323. * Together the low 5 bits work out to the MCS index because we don't
  324. * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
  325. * streams and 16-23 have three streams. We could also support MCS 32
  326. * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
  327. */
  328. #define RATE_HT_MCS_RATE_CODE_MSK 0x7
  329. #define RATE_HT_MCS_NSS_POS 3
  330. #define RATE_HT_MCS_NSS_MSK (3 << RATE_HT_MCS_NSS_POS)
  331. /* Bit 10: (1) Use Green Field preamble */
  332. #define RATE_HT_MCS_GF_POS 10
  333. #define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS)
  334. #define RATE_HT_MCS_INDEX_MSK 0x3f
  335. /*
  336. * Very High-throughput (VHT) rate format for bits 7:0
  337. *
  338. * 3-0: VHT MCS (0-9)
  339. * 5-4: number of streams - 1:
  340. * 0) Single stream (SISO)
  341. * 1) Dual stream (MIMO)
  342. * 2) Triple stream (MIMO)
  343. */
  344. /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
  345. #define RATE_VHT_MCS_RATE_CODE_MSK 0xf
  346. #define RATE_VHT_MCS_NSS_POS 4
  347. #define RATE_VHT_MCS_NSS_MSK (3 << RATE_VHT_MCS_NSS_POS)
  348. /*
  349. * Legacy OFDM rate format for bits 7:0
  350. *
  351. * 3-0: 0xD) 6 Mbps
  352. * 0xF) 9 Mbps
  353. * 0x5) 12 Mbps
  354. * 0x7) 18 Mbps
  355. * 0x9) 24 Mbps
  356. * 0xB) 36 Mbps
  357. * 0x1) 48 Mbps
  358. * 0x3) 54 Mbps
  359. * (bits 7-4 are 0)
  360. *
  361. * Legacy CCK rate format for bits 7:0:
  362. * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
  363. *
  364. * 6-0: 10) 1 Mbps
  365. * 20) 2 Mbps
  366. * 55) 5.5 Mbps
  367. * 110) 11 Mbps
  368. * (bit 7 is 0)
  369. */
  370. #define RATE_LEGACY_RATE_MSK 0xff
  371. /* Bit 10 - OFDM HE */
  372. #define RATE_MCS_HE_POS 10
  373. #define RATE_MCS_HE_MSK BIT(RATE_MCS_HE_POS)
  374. /*
  375. * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
  376. * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
  377. */
  378. #define RATE_MCS_CHAN_WIDTH_POS 11
  379. #define RATE_MCS_CHAN_WIDTH_MSK (3 << RATE_MCS_CHAN_WIDTH_POS)
  380. #define RATE_MCS_CHAN_WIDTH_20 (0 << RATE_MCS_CHAN_WIDTH_POS)
  381. #define RATE_MCS_CHAN_WIDTH_40 (1 << RATE_MCS_CHAN_WIDTH_POS)
  382. #define RATE_MCS_CHAN_WIDTH_80 (2 << RATE_MCS_CHAN_WIDTH_POS)
  383. #define RATE_MCS_CHAN_WIDTH_160 (3 << RATE_MCS_CHAN_WIDTH_POS)
  384. /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
  385. #define RATE_MCS_SGI_POS 13
  386. #define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS)
  387. /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
  388. #define RATE_MCS_ANT_POS 14
  389. #define RATE_MCS_ANT_A_MSK (1 << RATE_MCS_ANT_POS)
  390. #define RATE_MCS_ANT_B_MSK (2 << RATE_MCS_ANT_POS)
  391. #define RATE_MCS_ANT_C_MSK (4 << RATE_MCS_ANT_POS)
  392. #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | \
  393. RATE_MCS_ANT_B_MSK)
  394. #define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | \
  395. RATE_MCS_ANT_C_MSK)
  396. #define RATE_MCS_ANT_MSK RATE_MCS_ANT_ABC_MSK
  397. /* Bit 17: (0) SS, (1) SS*2 */
  398. #define RATE_MCS_STBC_POS 17
  399. #define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS)
  400. /* Bit 18: OFDM-HE dual carrier mode */
  401. #define RATE_HE_DUAL_CARRIER_MODE 18
  402. #define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE)
  403. /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
  404. #define RATE_MCS_BF_POS 19
  405. #define RATE_MCS_BF_MSK (1 << RATE_MCS_BF_POS)
  406. /*
  407. * Bit 20-21: HE LTF type and guard interval
  408. * HE (ext) SU:
  409. * 0 1xLTF+0.8us
  410. * 1 2xLTF+0.8us
  411. * 2 2xLTF+1.6us
  412. * 3 & SGI (bit 13) clear 4xLTF+3.2us
  413. * 3 & SGI (bit 13) set 4xLTF+0.8us
  414. * HE MU:
  415. * 0 4xLTF+0.8us
  416. * 1 2xLTF+0.8us
  417. * 2 2xLTF+1.6us
  418. * 3 4xLTF+3.2us
  419. * HE TRIG:
  420. * 0 1xLTF+1.6us
  421. * 1 2xLTF+1.6us
  422. * 2 4xLTF+3.2us
  423. * 3 (does not occur)
  424. */
  425. #define RATE_MCS_HE_GI_LTF_POS 20
  426. #define RATE_MCS_HE_GI_LTF_MSK (3 << RATE_MCS_HE_GI_LTF_POS)
  427. /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
  428. #define RATE_MCS_HE_TYPE_POS 22
  429. #define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS)
  430. #define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS)
  431. #define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS)
  432. #define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS)
  433. #define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS)
  434. /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
  435. #define RATE_MCS_DUP_POS 24
  436. #define RATE_MCS_DUP_MSK (3 << RATE_MCS_DUP_POS)
  437. /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
  438. #define RATE_MCS_LDPC_POS 27
  439. #define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS)
  440. /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
  441. #define RATE_MCS_HE_106T_POS 28
  442. #define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS)
  443. /* Link Quality definitions */
  444. /* # entries in rate scale table to support Tx retries */
  445. #define LQ_MAX_RETRY_NUM 16
  446. /* Link quality command flags bit fields */
  447. /* Bit 0: (0) Don't use RTS (1) Use RTS */
  448. #define LQ_FLAG_USE_RTS_POS 0
  449. #define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS)
  450. /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
  451. #define LQ_FLAG_COLOR_POS 1
  452. #define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS)
  453. #define LQ_FLAG_COLOR_GET(_f) (((_f) & LQ_FLAG_COLOR_MSK) >>\
  454. LQ_FLAG_COLOR_POS)
  455. #define LQ_FLAGS_COLOR_INC(_c) ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\
  456. LQ_FLAG_COLOR_MSK)
  457. #define LQ_FLAG_COLOR_SET(_f, _c) ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK))
  458. /* Bit 4-5: Tx RTS BW Signalling
  459. * (0) No RTS BW signalling
  460. * (1) Static BW signalling
  461. * (2) Dynamic BW signalling
  462. */
  463. #define LQ_FLAG_RTS_BW_SIG_POS 4
  464. #define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS)
  465. #define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS)
  466. #define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS)
  467. /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
  468. * Dyanmic BW selection allows Tx with narrower BW then requested in rates
  469. */
  470. #define LQ_FLAG_DYNAMIC_BW_POS 6
  471. #define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS)
  472. /* Single Stream Tx Parameters (lq_cmd->ss_params)
  473. * Flags to control a smart FW decision about whether BFER/STBC/SISO will be
  474. * used for single stream Tx.
  475. */
  476. /* Bit 0-1: Max STBC streams allowed. Can be 0-3.
  477. * (0) - No STBC allowed
  478. * (1) - 2x1 STBC allowed (HT/VHT)
  479. * (2) - 4x2 STBC allowed (HT/VHT)
  480. * (3) - 3x2 STBC allowed (HT only)
  481. * All our chips are at most 2 antennas so only (1) is valid for now.
  482. */
  483. #define LQ_SS_STBC_ALLOWED_POS 0
  484. #define LQ_SS_STBC_ALLOWED_MSK (3 << LQ_SS_STBC_ALLOWED_MSK)
  485. /* 2x1 STBC is allowed */
  486. #define LQ_SS_STBC_1SS_ALLOWED (1 << LQ_SS_STBC_ALLOWED_POS)
  487. /* Bit 2: Beamformer (VHT only) is allowed */
  488. #define LQ_SS_BFER_ALLOWED_POS 2
  489. #define LQ_SS_BFER_ALLOWED (1 << LQ_SS_BFER_ALLOWED_POS)
  490. /* Bit 3: Force BFER or STBC for testing
  491. * If this is set:
  492. * If BFER is allowed then force the ucode to choose BFER else
  493. * If STBC is allowed then force the ucode to choose STBC over SISO
  494. */
  495. #define LQ_SS_FORCE_POS 3
  496. #define LQ_SS_FORCE (1 << LQ_SS_FORCE_POS)
  497. /* Bit 31: ss_params field is valid. Used for FW backward compatibility
  498. * with other drivers which don't support the ss_params API yet
  499. */
  500. #define LQ_SS_PARAMS_VALID_POS 31
  501. #define LQ_SS_PARAMS_VALID (1 << LQ_SS_PARAMS_VALID_POS)
  502. /**
  503. * struct iwl_lq_cmd - link quality command
  504. * @sta_id: station to update
  505. * @reduced_tpc: reduced transmit power control value
  506. * @control: not used
  507. * @flags: combination of LQ_FLAG_*
  508. * @mimo_delim: the first SISO index in rs_table, which separates MIMO
  509. * and SISO rates
  510. * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
  511. * Should be ANT_[ABC]
  512. * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
  513. * @initial_rate_index: first index from rs_table per AC category
  514. * @agg_time_limit: aggregation max time threshold in usec/100, meaning
  515. * value of 100 is one usec. Range is 100 to 8000
  516. * @agg_disable_start_th: try-count threshold for starting aggregation.
  517. * If a frame has higher try-count, it should not be selected for
  518. * starting an aggregation sequence.
  519. * @agg_frame_cnt_limit: max frame count in an aggregation.
  520. * 0: no limit
  521. * 1: no aggregation (one frame per aggregation)
  522. * 2 - 0x3f: maximal number of frames (up to 3f == 63)
  523. * @reserved2: reserved
  524. * @rs_table: array of rates for each TX try, each is rate_n_flags,
  525. * meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP
  526. * @ss_params: single stream features. declare whether STBC or BFER are allowed.
  527. */
  528. struct iwl_lq_cmd {
  529. u8 sta_id;
  530. u8 reduced_tpc;
  531. __le16 control;
  532. /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
  533. u8 flags;
  534. u8 mimo_delim;
  535. u8 single_stream_ant_msk;
  536. u8 dual_stream_ant_msk;
  537. u8 initial_rate_index[AC_NUM];
  538. /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
  539. __le16 agg_time_limit;
  540. u8 agg_disable_start_th;
  541. u8 agg_frame_cnt_limit;
  542. __le32 reserved2;
  543. __le32 rs_table[LQ_MAX_RETRY_NUM];
  544. __le32 ss_params;
  545. }; /* LINK_QUALITY_CMD_API_S_VER_1 */
  546. #endif /* __iwl_fw_api_rs_h__ */