base.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164
  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "priv.h"
  25. #include <core/client.h>
  26. #include <core/device.h>
  27. #include <subdev/fb.h>
  28. #include <subdev/instmem.h>
  29. #include <nvif/class.h>
  30. #include <nvif/unpack.h>
  31. static int
  32. nvkm_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
  33. struct nvkm_gpuobj **pgpuobj)
  34. {
  35. const struct nvkm_dmaeng_impl *impl = (void *)
  36. nv_oclass(nv_object(dmaobj)->engine);
  37. int ret = 0;
  38. if (nv_object(dmaobj) == parent) { /* ctor bind */
  39. if (nv_mclass(parent->parent) == NV_DEVICE) {
  40. /* delayed, or no, binding */
  41. return 0;
  42. }
  43. ret = impl->bind(dmaobj, parent, pgpuobj);
  44. if (ret == 0)
  45. nvkm_object_ref(NULL, &parent);
  46. return ret;
  47. }
  48. return impl->bind(dmaobj, parent, pgpuobj);
  49. }
  50. int
  51. nvkm_dmaobj_create_(struct nvkm_object *parent,
  52. struct nvkm_object *engine,
  53. struct nvkm_oclass *oclass, void **pdata, u32 *psize,
  54. int length, void **pobject)
  55. {
  56. union {
  57. struct nv_dma_v0 v0;
  58. } *args = *pdata;
  59. struct nvkm_instmem *instmem = nvkm_instmem(parent);
  60. struct nvkm_client *client = nvkm_client(parent);
  61. struct nvkm_device *device = nv_device(parent);
  62. struct nvkm_fb *pfb = nvkm_fb(parent);
  63. struct nvkm_dmaobj *dmaobj;
  64. void *data = *pdata;
  65. u32 size = *psize;
  66. int ret;
  67. ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
  68. dmaobj = *pobject;
  69. if (ret)
  70. return ret;
  71. nv_ioctl(parent, "create dma size %d\n", *psize);
  72. if (nvif_unpack(args->v0, 0, 0, true)) {
  73. nv_ioctl(parent, "create dma vers %d target %d access %d "
  74. "start %016llx limit %016llx\n",
  75. args->v0.version, args->v0.target, args->v0.access,
  76. args->v0.start, args->v0.limit);
  77. dmaobj->target = args->v0.target;
  78. dmaobj->access = args->v0.access;
  79. dmaobj->start = args->v0.start;
  80. dmaobj->limit = args->v0.limit;
  81. } else
  82. return ret;
  83. *pdata = data;
  84. *psize = size;
  85. if (dmaobj->start > dmaobj->limit)
  86. return -EINVAL;
  87. switch (dmaobj->target) {
  88. case NV_DMA_V0_TARGET_VM:
  89. dmaobj->target = NV_MEM_TARGET_VM;
  90. break;
  91. case NV_DMA_V0_TARGET_VRAM:
  92. if (!client->super) {
  93. if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
  94. return -EACCES;
  95. if (device->card_type >= NV_50)
  96. return -EACCES;
  97. }
  98. dmaobj->target = NV_MEM_TARGET_VRAM;
  99. break;
  100. case NV_DMA_V0_TARGET_PCI:
  101. if (!client->super)
  102. return -EACCES;
  103. dmaobj->target = NV_MEM_TARGET_PCI;
  104. break;
  105. case NV_DMA_V0_TARGET_PCI_US:
  106. case NV_DMA_V0_TARGET_AGP:
  107. if (!client->super)
  108. return -EACCES;
  109. dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP;
  110. break;
  111. default:
  112. return -EINVAL;
  113. }
  114. switch (dmaobj->access) {
  115. case NV_DMA_V0_ACCESS_VM:
  116. dmaobj->access = NV_MEM_ACCESS_VM;
  117. break;
  118. case NV_DMA_V0_ACCESS_RD:
  119. dmaobj->access = NV_MEM_ACCESS_RO;
  120. break;
  121. case NV_DMA_V0_ACCESS_WR:
  122. dmaobj->access = NV_MEM_ACCESS_WO;
  123. break;
  124. case NV_DMA_V0_ACCESS_RDWR:
  125. dmaobj->access = NV_MEM_ACCESS_RW;
  126. break;
  127. default:
  128. return -EINVAL;
  129. }
  130. return ret;
  131. }
  132. int
  133. _nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  134. struct nvkm_oclass *oclass, void *data, u32 size,
  135. struct nvkm_object **pobject)
  136. {
  137. const struct nvkm_dmaeng_impl *impl = (void *)oclass;
  138. struct nvkm_dmaeng *dmaeng;
  139. int ret;
  140. ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ",
  141. "dmaobj", &dmaeng);
  142. *pobject = nv_object(dmaeng);
  143. if (ret)
  144. return ret;
  145. nv_engine(dmaeng)->sclass = impl->sclass;
  146. dmaeng->bind = nvkm_dmaobj_bind;
  147. return 0;
  148. }