nicstar.c 76 KB

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  1. /*
  2. * nicstar.c
  3. *
  4. * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
  5. *
  6. * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
  7. * It was taken from the frle-0.22 device driver.
  8. * As the file doesn't have a copyright notice, in the file
  9. * nicstarmac.copyright I put the copyright notice from the
  10. * frle-0.22 device driver.
  11. * Some code is based on the nicstar driver by M. Welsh.
  12. *
  13. * Author: Rui Prior (rprior@inescn.pt)
  14. * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
  15. *
  16. *
  17. * (C) INESC 1999
  18. */
  19. /*
  20. * IMPORTANT INFORMATION
  21. *
  22. * There are currently three types of spinlocks:
  23. *
  24. * 1 - Per card interrupt spinlock (to protect structures and such)
  25. * 2 - Per SCQ scq spinlock
  26. * 3 - Per card resource spinlock (to access registers, etc.)
  27. *
  28. * These must NEVER be grabbed in reverse order.
  29. *
  30. */
  31. /* Header files */
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/atmdev.h>
  36. #include <linux/atm.h>
  37. #include <linux/pci.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/types.h>
  40. #include <linux/string.h>
  41. #include <linux/delay.h>
  42. #include <linux/init.h>
  43. #include <linux/sched.h>
  44. #include <linux/timer.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/bitops.h>
  47. #include <linux/slab.h>
  48. #include <linux/idr.h>
  49. #include <asm/io.h>
  50. #include <asm/uaccess.h>
  51. #include <asm/atomic.h>
  52. #include "nicstar.h"
  53. #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
  54. #include "suni.h"
  55. #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
  56. #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
  57. #include "idt77105.h"
  58. #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
  59. /* Additional code */
  60. #include "nicstarmac.c"
  61. /* Configurable parameters */
  62. #undef PHY_LOOPBACK
  63. #undef TX_DEBUG
  64. #undef RX_DEBUG
  65. #undef GENERAL_DEBUG
  66. #undef EXTRA_DEBUG
  67. #undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know
  68. you're going to use only raw ATM */
  69. /* Do not touch these */
  70. #ifdef TX_DEBUG
  71. #define TXPRINTK(args...) printk(args)
  72. #else
  73. #define TXPRINTK(args...)
  74. #endif /* TX_DEBUG */
  75. #ifdef RX_DEBUG
  76. #define RXPRINTK(args...) printk(args)
  77. #else
  78. #define RXPRINTK(args...)
  79. #endif /* RX_DEBUG */
  80. #ifdef GENERAL_DEBUG
  81. #define PRINTK(args...) printk(args)
  82. #else
  83. #define PRINTK(args...)
  84. #endif /* GENERAL_DEBUG */
  85. #ifdef EXTRA_DEBUG
  86. #define XPRINTK(args...) printk(args)
  87. #else
  88. #define XPRINTK(args...)
  89. #endif /* EXTRA_DEBUG */
  90. /* Macros */
  91. #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
  92. #define NS_DELAY mdelay(1)
  93. #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
  94. #ifndef ATM_SKB
  95. #define ATM_SKB(s) (&(s)->atm)
  96. #endif
  97. #define scq_virt_to_bus(scq, p) \
  98. (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
  99. /* Function declarations */
  100. static u32 ns_read_sram(ns_dev * card, u32 sram_address);
  101. static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
  102. int count);
  103. static int __devinit ns_init_card(int i, struct pci_dev *pcidev);
  104. static void __devinit ns_init_card_error(ns_dev * card, int error);
  105. static scq_info *get_scq(ns_dev *card, int size, u32 scd);
  106. static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
  107. static void push_rxbufs(ns_dev *, struct sk_buff *);
  108. static irqreturn_t ns_irq_handler(int irq, void *dev_id);
  109. static int ns_open(struct atm_vcc *vcc);
  110. static void ns_close(struct atm_vcc *vcc);
  111. static void fill_tst(ns_dev * card, int n, vc_map * vc);
  112. static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
  113. static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
  114. struct sk_buff *skb);
  115. static void process_tsq(ns_dev * card);
  116. static void drain_scq(ns_dev * card, scq_info * scq, int pos);
  117. static void process_rsq(ns_dev * card);
  118. static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
  119. #ifdef NS_USE_DESTRUCTORS
  120. static void ns_sb_destructor(struct sk_buff *sb);
  121. static void ns_lb_destructor(struct sk_buff *lb);
  122. static void ns_hb_destructor(struct sk_buff *hb);
  123. #endif /* NS_USE_DESTRUCTORS */
  124. static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
  125. static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
  126. static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
  127. static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
  128. static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
  129. static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
  130. static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
  131. #ifdef EXTRA_DEBUG
  132. static void which_list(ns_dev * card, struct sk_buff *skb);
  133. #endif
  134. static void ns_poll(unsigned long arg);
  135. static int ns_parse_mac(char *mac, unsigned char *esi);
  136. static short ns_h2i(char c);
  137. static void ns_phy_put(struct atm_dev *dev, unsigned char value,
  138. unsigned long addr);
  139. static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
  140. /* Global variables */
  141. static struct ns_dev *cards[NS_MAX_CARDS];
  142. static unsigned num_cards;
  143. static struct atmdev_ops atm_ops = {
  144. .open = ns_open,
  145. .close = ns_close,
  146. .ioctl = ns_ioctl,
  147. .send = ns_send,
  148. .phy_put = ns_phy_put,
  149. .phy_get = ns_phy_get,
  150. .proc_read = ns_proc_read,
  151. .owner = THIS_MODULE,
  152. };
  153. static struct timer_list ns_timer;
  154. static char *mac[NS_MAX_CARDS];
  155. module_param_array(mac, charp, NULL, 0);
  156. MODULE_LICENSE("GPL");
  157. /* Functions */
  158. static int __devinit nicstar_init_one(struct pci_dev *pcidev,
  159. const struct pci_device_id *ent)
  160. {
  161. static int index = -1;
  162. unsigned int error;
  163. index++;
  164. cards[index] = NULL;
  165. error = ns_init_card(index, pcidev);
  166. if (error) {
  167. cards[index--] = NULL; /* don't increment index */
  168. goto err_out;
  169. }
  170. return 0;
  171. err_out:
  172. return -ENODEV;
  173. }
  174. static void __devexit nicstar_remove_one(struct pci_dev *pcidev)
  175. {
  176. int i, j;
  177. ns_dev *card = pci_get_drvdata(pcidev);
  178. struct sk_buff *hb;
  179. struct sk_buff *iovb;
  180. struct sk_buff *lb;
  181. struct sk_buff *sb;
  182. i = card->index;
  183. if (cards[i] == NULL)
  184. return;
  185. if (card->atmdev->phy && card->atmdev->phy->stop)
  186. card->atmdev->phy->stop(card->atmdev);
  187. /* Stop everything */
  188. writel(0x00000000, card->membase + CFG);
  189. /* De-register device */
  190. atm_dev_deregister(card->atmdev);
  191. /* Disable PCI device */
  192. pci_disable_device(pcidev);
  193. /* Free up resources */
  194. j = 0;
  195. PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
  196. while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
  197. dev_kfree_skb_any(hb);
  198. j++;
  199. }
  200. PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
  201. j = 0;
  202. PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
  203. card->iovpool.count);
  204. while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
  205. dev_kfree_skb_any(iovb);
  206. j++;
  207. }
  208. PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
  209. while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
  210. dev_kfree_skb_any(lb);
  211. while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
  212. dev_kfree_skb_any(sb);
  213. free_scq(card, card->scq0, NULL);
  214. for (j = 0; j < NS_FRSCD_NUM; j++) {
  215. if (card->scd2vc[j] != NULL)
  216. free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
  217. }
  218. idr_remove_all(&card->idr);
  219. idr_destroy(&card->idr);
  220. pci_free_consistent(card->pcidev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
  221. card->rsq.org, card->rsq.dma);
  222. pci_free_consistent(card->pcidev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
  223. card->tsq.org, card->tsq.dma);
  224. free_irq(card->pcidev->irq, card);
  225. iounmap(card->membase);
  226. kfree(card);
  227. }
  228. static struct pci_device_id nicstar_pci_tbl[] __devinitdata = {
  229. {PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77201,
  230. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  231. {0,} /* terminate list */
  232. };
  233. MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
  234. static struct pci_driver nicstar_driver = {
  235. .name = "nicstar",
  236. .id_table = nicstar_pci_tbl,
  237. .probe = nicstar_init_one,
  238. .remove = __devexit_p(nicstar_remove_one),
  239. };
  240. static int __init nicstar_init(void)
  241. {
  242. unsigned error = 0; /* Initialized to remove compile warning */
  243. XPRINTK("nicstar: nicstar_init() called.\n");
  244. error = pci_register_driver(&nicstar_driver);
  245. TXPRINTK("nicstar: TX debug enabled.\n");
  246. RXPRINTK("nicstar: RX debug enabled.\n");
  247. PRINTK("nicstar: General debug enabled.\n");
  248. #ifdef PHY_LOOPBACK
  249. printk("nicstar: using PHY loopback.\n");
  250. #endif /* PHY_LOOPBACK */
  251. XPRINTK("nicstar: nicstar_init() returned.\n");
  252. if (!error) {
  253. init_timer(&ns_timer);
  254. ns_timer.expires = jiffies + NS_POLL_PERIOD;
  255. ns_timer.data = 0UL;
  256. ns_timer.function = ns_poll;
  257. add_timer(&ns_timer);
  258. }
  259. return error;
  260. }
  261. static void __exit nicstar_cleanup(void)
  262. {
  263. XPRINTK("nicstar: nicstar_cleanup() called.\n");
  264. del_timer(&ns_timer);
  265. pci_unregister_driver(&nicstar_driver);
  266. XPRINTK("nicstar: nicstar_cleanup() returned.\n");
  267. }
  268. static u32 ns_read_sram(ns_dev * card, u32 sram_address)
  269. {
  270. unsigned long flags;
  271. u32 data;
  272. sram_address <<= 2;
  273. sram_address &= 0x0007FFFC; /* address must be dword aligned */
  274. sram_address |= 0x50000000; /* SRAM read command */
  275. spin_lock_irqsave(&card->res_lock, flags);
  276. while (CMD_BUSY(card)) ;
  277. writel(sram_address, card->membase + CMD);
  278. while (CMD_BUSY(card)) ;
  279. data = readl(card->membase + DR0);
  280. spin_unlock_irqrestore(&card->res_lock, flags);
  281. return data;
  282. }
  283. static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
  284. int count)
  285. {
  286. unsigned long flags;
  287. int i, c;
  288. count--; /* count range now is 0..3 instead of 1..4 */
  289. c = count;
  290. c <<= 2; /* to use increments of 4 */
  291. spin_lock_irqsave(&card->res_lock, flags);
  292. while (CMD_BUSY(card)) ;
  293. for (i = 0; i <= c; i += 4)
  294. writel(*(value++), card->membase + i);
  295. /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
  296. so card->membase + DR0 == card->membase */
  297. sram_address <<= 2;
  298. sram_address &= 0x0007FFFC;
  299. sram_address |= (0x40000000 | count);
  300. writel(sram_address, card->membase + CMD);
  301. spin_unlock_irqrestore(&card->res_lock, flags);
  302. }
  303. static int __devinit ns_init_card(int i, struct pci_dev *pcidev)
  304. {
  305. int j;
  306. struct ns_dev *card = NULL;
  307. unsigned char pci_latency;
  308. unsigned error;
  309. u32 data;
  310. u32 u32d[4];
  311. u32 ns_cfg_rctsize;
  312. int bcount;
  313. unsigned long membase;
  314. error = 0;
  315. if (pci_enable_device(pcidev)) {
  316. printk("nicstar%d: can't enable PCI device\n", i);
  317. error = 2;
  318. ns_init_card_error(card, error);
  319. return error;
  320. }
  321. if ((pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0) ||
  322. (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0)) {
  323. printk(KERN_WARNING
  324. "nicstar%d: No suitable DMA available.\n", i);
  325. error = 2;
  326. ns_init_card_error(card, error);
  327. return error;
  328. }
  329. if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) {
  330. printk
  331. ("nicstar%d: can't allocate memory for device structure.\n",
  332. i);
  333. error = 2;
  334. ns_init_card_error(card, error);
  335. return error;
  336. }
  337. cards[i] = card;
  338. spin_lock_init(&card->int_lock);
  339. spin_lock_init(&card->res_lock);
  340. pci_set_drvdata(pcidev, card);
  341. card->index = i;
  342. card->atmdev = NULL;
  343. card->pcidev = pcidev;
  344. membase = pci_resource_start(pcidev, 1);
  345. card->membase = ioremap(membase, NS_IOREMAP_SIZE);
  346. if (!card->membase) {
  347. printk("nicstar%d: can't ioremap() membase.\n", i);
  348. error = 3;
  349. ns_init_card_error(card, error);
  350. return error;
  351. }
  352. PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
  353. pci_set_master(pcidev);
  354. if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
  355. printk("nicstar%d: can't read PCI latency timer.\n", i);
  356. error = 6;
  357. ns_init_card_error(card, error);
  358. return error;
  359. }
  360. #ifdef NS_PCI_LATENCY
  361. if (pci_latency < NS_PCI_LATENCY) {
  362. PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
  363. NS_PCI_LATENCY);
  364. for (j = 1; j < 4; j++) {
  365. if (pci_write_config_byte
  366. (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
  367. break;
  368. }
  369. if (j == 4) {
  370. printk
  371. ("nicstar%d: can't set PCI latency timer to %d.\n",
  372. i, NS_PCI_LATENCY);
  373. error = 7;
  374. ns_init_card_error(card, error);
  375. return error;
  376. }
  377. }
  378. #endif /* NS_PCI_LATENCY */
  379. /* Clear timer overflow */
  380. data = readl(card->membase + STAT);
  381. if (data & NS_STAT_TMROF)
  382. writel(NS_STAT_TMROF, card->membase + STAT);
  383. /* Software reset */
  384. writel(NS_CFG_SWRST, card->membase + CFG);
  385. NS_DELAY;
  386. writel(0x00000000, card->membase + CFG);
  387. /* PHY reset */
  388. writel(0x00000008, card->membase + GP);
  389. NS_DELAY;
  390. writel(0x00000001, card->membase + GP);
  391. NS_DELAY;
  392. while (CMD_BUSY(card)) ;
  393. writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
  394. NS_DELAY;
  395. /* Detect PHY type */
  396. while (CMD_BUSY(card)) ;
  397. writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
  398. while (CMD_BUSY(card)) ;
  399. data = readl(card->membase + DR0);
  400. switch (data) {
  401. case 0x00000009:
  402. printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
  403. card->max_pcr = ATM_25_PCR;
  404. while (CMD_BUSY(card)) ;
  405. writel(0x00000008, card->membase + DR0);
  406. writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
  407. /* Clear an eventual pending interrupt */
  408. writel(NS_STAT_SFBQF, card->membase + STAT);
  409. #ifdef PHY_LOOPBACK
  410. while (CMD_BUSY(card)) ;
  411. writel(0x00000022, card->membase + DR0);
  412. writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
  413. #endif /* PHY_LOOPBACK */
  414. break;
  415. case 0x00000030:
  416. case 0x00000031:
  417. printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
  418. card->max_pcr = ATM_OC3_PCR;
  419. #ifdef PHY_LOOPBACK
  420. while (CMD_BUSY(card)) ;
  421. writel(0x00000002, card->membase + DR0);
  422. writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
  423. #endif /* PHY_LOOPBACK */
  424. break;
  425. default:
  426. printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
  427. error = 8;
  428. ns_init_card_error(card, error);
  429. return error;
  430. }
  431. writel(0x00000000, card->membase + GP);
  432. /* Determine SRAM size */
  433. data = 0x76543210;
  434. ns_write_sram(card, 0x1C003, &data, 1);
  435. data = 0x89ABCDEF;
  436. ns_write_sram(card, 0x14003, &data, 1);
  437. if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
  438. ns_read_sram(card, 0x1C003) == 0x76543210)
  439. card->sram_size = 128;
  440. else
  441. card->sram_size = 32;
  442. PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
  443. card->rct_size = NS_MAX_RCTSIZE;
  444. #if (NS_MAX_RCTSIZE == 4096)
  445. if (card->sram_size == 128)
  446. printk
  447. ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
  448. i);
  449. #elif (NS_MAX_RCTSIZE == 16384)
  450. if (card->sram_size == 32) {
  451. printk
  452. ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
  453. i);
  454. card->rct_size = 4096;
  455. }
  456. #else
  457. #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
  458. #endif
  459. card->vpibits = NS_VPIBITS;
  460. if (card->rct_size == 4096)
  461. card->vcibits = 12 - NS_VPIBITS;
  462. else /* card->rct_size == 16384 */
  463. card->vcibits = 14 - NS_VPIBITS;
  464. /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
  465. if (mac[i] == NULL)
  466. nicstar_init_eprom(card->membase);
  467. /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
  468. writel(0x00000000, card->membase + VPM);
  469. /* Initialize TSQ */
  470. card->tsq.org = pci_alloc_consistent(card->pcidev,
  471. NS_TSQSIZE + NS_TSQ_ALIGNMENT,
  472. &card->tsq.dma);
  473. if (card->tsq.org == NULL) {
  474. printk("nicstar%d: can't allocate TSQ.\n", i);
  475. error = 10;
  476. ns_init_card_error(card, error);
  477. return error;
  478. }
  479. card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
  480. card->tsq.next = card->tsq.base;
  481. card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
  482. for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
  483. ns_tsi_init(card->tsq.base + j);
  484. writel(0x00000000, card->membase + TSQH);
  485. writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
  486. PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
  487. /* Initialize RSQ */
  488. card->rsq.org = pci_alloc_consistent(card->pcidev,
  489. NS_RSQSIZE + NS_RSQ_ALIGNMENT,
  490. &card->rsq.dma);
  491. if (card->rsq.org == NULL) {
  492. printk("nicstar%d: can't allocate RSQ.\n", i);
  493. error = 11;
  494. ns_init_card_error(card, error);
  495. return error;
  496. }
  497. card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
  498. card->rsq.next = card->rsq.base;
  499. card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
  500. for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
  501. ns_rsqe_init(card->rsq.base + j);
  502. writel(0x00000000, card->membase + RSQH);
  503. writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
  504. PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
  505. /* Initialize SCQ0, the only VBR SCQ used */
  506. card->scq1 = NULL;
  507. card->scq2 = NULL;
  508. card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
  509. if (card->scq0 == NULL) {
  510. printk("nicstar%d: can't get SCQ0.\n", i);
  511. error = 12;
  512. ns_init_card_error(card, error);
  513. return error;
  514. }
  515. u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
  516. u32d[1] = (u32) 0x00000000;
  517. u32d[2] = (u32) 0xffffffff;
  518. u32d[3] = (u32) 0x00000000;
  519. ns_write_sram(card, NS_VRSCD0, u32d, 4);
  520. ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
  521. ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
  522. card->scq0->scd = NS_VRSCD0;
  523. PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
  524. /* Initialize TSTs */
  525. card->tst_addr = NS_TST0;
  526. card->tst_free_entries = NS_TST_NUM_ENTRIES;
  527. data = NS_TST_OPCODE_VARIABLE;
  528. for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
  529. ns_write_sram(card, NS_TST0 + j, &data, 1);
  530. data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
  531. ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
  532. for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
  533. ns_write_sram(card, NS_TST1 + j, &data, 1);
  534. data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
  535. ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
  536. for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
  537. card->tste2vc[j] = NULL;
  538. writel(NS_TST0 << 2, card->membase + TSTB);
  539. /* Initialize RCT. AAL type is set on opening the VC. */
  540. #ifdef RCQ_SUPPORT
  541. u32d[0] = NS_RCTE_RAWCELLINTEN;
  542. #else
  543. u32d[0] = 0x00000000;
  544. #endif /* RCQ_SUPPORT */
  545. u32d[1] = 0x00000000;
  546. u32d[2] = 0x00000000;
  547. u32d[3] = 0xFFFFFFFF;
  548. for (j = 0; j < card->rct_size; j++)
  549. ns_write_sram(card, j * 4, u32d, 4);
  550. memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map));
  551. for (j = 0; j < NS_FRSCD_NUM; j++)
  552. card->scd2vc[j] = NULL;
  553. /* Initialize buffer levels */
  554. card->sbnr.min = MIN_SB;
  555. card->sbnr.init = NUM_SB;
  556. card->sbnr.max = MAX_SB;
  557. card->lbnr.min = MIN_LB;
  558. card->lbnr.init = NUM_LB;
  559. card->lbnr.max = MAX_LB;
  560. card->iovnr.min = MIN_IOVB;
  561. card->iovnr.init = NUM_IOVB;
  562. card->iovnr.max = MAX_IOVB;
  563. card->hbnr.min = MIN_HB;
  564. card->hbnr.init = NUM_HB;
  565. card->hbnr.max = MAX_HB;
  566. card->sm_handle = 0x00000000;
  567. card->sm_addr = 0x00000000;
  568. card->lg_handle = 0x00000000;
  569. card->lg_addr = 0x00000000;
  570. card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
  571. idr_init(&card->idr);
  572. /* Pre-allocate some huge buffers */
  573. skb_queue_head_init(&card->hbpool.queue);
  574. card->hbpool.count = 0;
  575. for (j = 0; j < NUM_HB; j++) {
  576. struct sk_buff *hb;
  577. hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
  578. if (hb == NULL) {
  579. printk
  580. ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
  581. i, j, NUM_HB);
  582. error = 13;
  583. ns_init_card_error(card, error);
  584. return error;
  585. }
  586. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  587. skb_queue_tail(&card->hbpool.queue, hb);
  588. card->hbpool.count++;
  589. }
  590. /* Allocate large buffers */
  591. skb_queue_head_init(&card->lbpool.queue);
  592. card->lbpool.count = 0; /* Not used */
  593. for (j = 0; j < NUM_LB; j++) {
  594. struct sk_buff *lb;
  595. lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
  596. if (lb == NULL) {
  597. printk
  598. ("nicstar%d: can't allocate %dth of %d large buffers.\n",
  599. i, j, NUM_LB);
  600. error = 14;
  601. ns_init_card_error(card, error);
  602. return error;
  603. }
  604. NS_PRV_BUFTYPE(lb) = BUF_LG;
  605. skb_queue_tail(&card->lbpool.queue, lb);
  606. skb_reserve(lb, NS_SMBUFSIZE);
  607. push_rxbufs(card, lb);
  608. /* Due to the implementation of push_rxbufs() this is 1, not 0 */
  609. if (j == 1) {
  610. card->rcbuf = lb;
  611. card->rawcell = (struct ns_rcqe *) lb->data;
  612. card->rawch = NS_PRV_DMA(lb);
  613. }
  614. }
  615. /* Test for strange behaviour which leads to crashes */
  616. if ((bcount =
  617. ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
  618. printk
  619. ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
  620. i, j, bcount);
  621. error = 14;
  622. ns_init_card_error(card, error);
  623. return error;
  624. }
  625. /* Allocate small buffers */
  626. skb_queue_head_init(&card->sbpool.queue);
  627. card->sbpool.count = 0; /* Not used */
  628. for (j = 0; j < NUM_SB; j++) {
  629. struct sk_buff *sb;
  630. sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
  631. if (sb == NULL) {
  632. printk
  633. ("nicstar%d: can't allocate %dth of %d small buffers.\n",
  634. i, j, NUM_SB);
  635. error = 15;
  636. ns_init_card_error(card, error);
  637. return error;
  638. }
  639. NS_PRV_BUFTYPE(sb) = BUF_SM;
  640. skb_queue_tail(&card->sbpool.queue, sb);
  641. skb_reserve(sb, NS_AAL0_HEADER);
  642. push_rxbufs(card, sb);
  643. }
  644. /* Test for strange behaviour which leads to crashes */
  645. if ((bcount =
  646. ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
  647. printk
  648. ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
  649. i, j, bcount);
  650. error = 15;
  651. ns_init_card_error(card, error);
  652. return error;
  653. }
  654. /* Allocate iovec buffers */
  655. skb_queue_head_init(&card->iovpool.queue);
  656. card->iovpool.count = 0;
  657. for (j = 0; j < NUM_IOVB; j++) {
  658. struct sk_buff *iovb;
  659. iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
  660. if (iovb == NULL) {
  661. printk
  662. ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
  663. i, j, NUM_IOVB);
  664. error = 16;
  665. ns_init_card_error(card, error);
  666. return error;
  667. }
  668. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  669. skb_queue_tail(&card->iovpool.queue, iovb);
  670. card->iovpool.count++;
  671. }
  672. /* Configure NICStAR */
  673. if (card->rct_size == 4096)
  674. ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
  675. else /* (card->rct_size == 16384) */
  676. ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
  677. card->efbie = 1;
  678. card->intcnt = 0;
  679. if (request_irq
  680. (pcidev->irq, &ns_irq_handler, IRQF_DISABLED | IRQF_SHARED,
  681. "nicstar", card) != 0) {
  682. printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
  683. error = 9;
  684. ns_init_card_error(card, error);
  685. return error;
  686. }
  687. /* Register device */
  688. card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL);
  689. if (card->atmdev == NULL) {
  690. printk("nicstar%d: can't register device.\n", i);
  691. error = 17;
  692. ns_init_card_error(card, error);
  693. return error;
  694. }
  695. if (ns_parse_mac(mac[i], card->atmdev->esi)) {
  696. nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
  697. card->atmdev->esi, 6);
  698. if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) ==
  699. 0) {
  700. nicstar_read_eprom(card->membase,
  701. NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
  702. card->atmdev->esi, 6);
  703. }
  704. }
  705. printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
  706. card->atmdev->dev_data = card;
  707. card->atmdev->ci_range.vpi_bits = card->vpibits;
  708. card->atmdev->ci_range.vci_bits = card->vcibits;
  709. card->atmdev->link_rate = card->max_pcr;
  710. card->atmdev->phy = NULL;
  711. #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
  712. if (card->max_pcr == ATM_OC3_PCR)
  713. suni_init(card->atmdev);
  714. #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
  715. #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
  716. if (card->max_pcr == ATM_25_PCR)
  717. idt77105_init(card->atmdev);
  718. #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
  719. if (card->atmdev->phy && card->atmdev->phy->start)
  720. card->atmdev->phy->start(card->atmdev);
  721. writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
  722. NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
  723. NS_CFG_PHYIE, card->membase + CFG);
  724. num_cards++;
  725. return error;
  726. }
  727. static void __devinit ns_init_card_error(ns_dev * card, int error)
  728. {
  729. if (error >= 17) {
  730. writel(0x00000000, card->membase + CFG);
  731. }
  732. if (error >= 16) {
  733. struct sk_buff *iovb;
  734. while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
  735. dev_kfree_skb_any(iovb);
  736. }
  737. if (error >= 15) {
  738. struct sk_buff *sb;
  739. while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
  740. dev_kfree_skb_any(sb);
  741. free_scq(card, card->scq0, NULL);
  742. }
  743. if (error >= 14) {
  744. struct sk_buff *lb;
  745. while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
  746. dev_kfree_skb_any(lb);
  747. }
  748. if (error >= 13) {
  749. struct sk_buff *hb;
  750. while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
  751. dev_kfree_skb_any(hb);
  752. }
  753. if (error >= 12) {
  754. kfree(card->rsq.org);
  755. }
  756. if (error >= 11) {
  757. kfree(card->tsq.org);
  758. }
  759. if (error >= 10) {
  760. free_irq(card->pcidev->irq, card);
  761. }
  762. if (error >= 4) {
  763. iounmap(card->membase);
  764. }
  765. if (error >= 3) {
  766. pci_disable_device(card->pcidev);
  767. kfree(card);
  768. }
  769. }
  770. static scq_info *get_scq(ns_dev *card, int size, u32 scd)
  771. {
  772. scq_info *scq;
  773. int i;
  774. if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
  775. return NULL;
  776. scq = kmalloc(sizeof(scq_info), GFP_KERNEL);
  777. if (!scq)
  778. return NULL;
  779. scq->org = pci_alloc_consistent(card->pcidev, 2 * size, &scq->dma);
  780. if (!scq->org) {
  781. kfree(scq);
  782. return NULL;
  783. }
  784. scq->skb = kmalloc(sizeof(struct sk_buff *) *
  785. (size / NS_SCQE_SIZE), GFP_KERNEL);
  786. if (!scq->skb) {
  787. kfree(scq->org);
  788. kfree(scq);
  789. return NULL;
  790. }
  791. scq->num_entries = size / NS_SCQE_SIZE;
  792. scq->base = PTR_ALIGN(scq->org, size);
  793. scq->next = scq->base;
  794. scq->last = scq->base + (scq->num_entries - 1);
  795. scq->tail = scq->last;
  796. scq->scd = scd;
  797. scq->num_entries = size / NS_SCQE_SIZE;
  798. scq->tbd_count = 0;
  799. init_waitqueue_head(&scq->scqfull_waitq);
  800. scq->full = 0;
  801. spin_lock_init(&scq->lock);
  802. for (i = 0; i < scq->num_entries; i++)
  803. scq->skb[i] = NULL;
  804. return scq;
  805. }
  806. /* For variable rate SCQ vcc must be NULL */
  807. static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
  808. {
  809. int i;
  810. if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
  811. for (i = 0; i < scq->num_entries; i++) {
  812. if (scq->skb[i] != NULL) {
  813. vcc = ATM_SKB(scq->skb[i])->vcc;
  814. if (vcc->pop != NULL)
  815. vcc->pop(vcc, scq->skb[i]);
  816. else
  817. dev_kfree_skb_any(scq->skb[i]);
  818. }
  819. } else { /* vcc must be != NULL */
  820. if (vcc == NULL) {
  821. printk
  822. ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
  823. for (i = 0; i < scq->num_entries; i++)
  824. dev_kfree_skb_any(scq->skb[i]);
  825. } else
  826. for (i = 0; i < scq->num_entries; i++) {
  827. if (scq->skb[i] != NULL) {
  828. if (vcc->pop != NULL)
  829. vcc->pop(vcc, scq->skb[i]);
  830. else
  831. dev_kfree_skb_any(scq->skb[i]);
  832. }
  833. }
  834. }
  835. kfree(scq->skb);
  836. pci_free_consistent(card->pcidev,
  837. 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
  838. VBR_SCQSIZE : CBR_SCQSIZE),
  839. scq->org, scq->dma);
  840. kfree(scq);
  841. }
  842. /* The handles passed must be pointers to the sk_buff containing the small
  843. or large buffer(s) cast to u32. */
  844. static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
  845. {
  846. struct sk_buff *handle1, *handle2;
  847. u32 id1 = 0, id2 = 0;
  848. u32 addr1, addr2;
  849. u32 stat;
  850. unsigned long flags;
  851. int err;
  852. /* *BARF* */
  853. handle2 = NULL;
  854. addr2 = 0;
  855. handle1 = skb;
  856. addr1 = pci_map_single(card->pcidev,
  857. skb->data,
  858. (NS_PRV_BUFTYPE(skb) == BUF_SM
  859. ? NS_SMSKBSIZE : NS_LGSKBSIZE),
  860. PCI_DMA_TODEVICE);
  861. NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
  862. #ifdef GENERAL_DEBUG
  863. if (!addr1)
  864. printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
  865. card->index);
  866. #endif /* GENERAL_DEBUG */
  867. stat = readl(card->membase + STAT);
  868. card->sbfqc = ns_stat_sfbqc_get(stat);
  869. card->lbfqc = ns_stat_lfbqc_get(stat);
  870. if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
  871. if (!addr2) {
  872. if (card->sm_addr) {
  873. addr2 = card->sm_addr;
  874. handle2 = card->sm_handle;
  875. card->sm_addr = 0x00000000;
  876. card->sm_handle = 0x00000000;
  877. } else { /* (!sm_addr) */
  878. card->sm_addr = addr1;
  879. card->sm_handle = handle1;
  880. }
  881. }
  882. } else { /* buf_type == BUF_LG */
  883. if (!addr2) {
  884. if (card->lg_addr) {
  885. addr2 = card->lg_addr;
  886. handle2 = card->lg_handle;
  887. card->lg_addr = 0x00000000;
  888. card->lg_handle = 0x00000000;
  889. } else { /* (!lg_addr) */
  890. card->lg_addr = addr1;
  891. card->lg_handle = handle1;
  892. }
  893. }
  894. }
  895. if (addr2) {
  896. if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
  897. if (card->sbfqc >= card->sbnr.max) {
  898. skb_unlink(handle1, &card->sbpool.queue);
  899. dev_kfree_skb_any(handle1);
  900. skb_unlink(handle2, &card->sbpool.queue);
  901. dev_kfree_skb_any(handle2);
  902. return;
  903. } else
  904. card->sbfqc += 2;
  905. } else { /* (buf_type == BUF_LG) */
  906. if (card->lbfqc >= card->lbnr.max) {
  907. skb_unlink(handle1, &card->lbpool.queue);
  908. dev_kfree_skb_any(handle1);
  909. skb_unlink(handle2, &card->lbpool.queue);
  910. dev_kfree_skb_any(handle2);
  911. return;
  912. } else
  913. card->lbfqc += 2;
  914. }
  915. do {
  916. if (!idr_pre_get(&card->idr, GFP_ATOMIC)) {
  917. printk(KERN_ERR
  918. "nicstar%d: no free memory for idr\n",
  919. card->index);
  920. goto out;
  921. }
  922. if (!id1)
  923. err = idr_get_new_above(&card->idr, handle1, 0, &id1);
  924. if (!id2 && err == 0)
  925. err = idr_get_new_above(&card->idr, handle2, 0, &id2);
  926. } while (err == -EAGAIN);
  927. if (err)
  928. goto out;
  929. spin_lock_irqsave(&card->res_lock, flags);
  930. while (CMD_BUSY(card)) ;
  931. writel(addr2, card->membase + DR3);
  932. writel(id2, card->membase + DR2);
  933. writel(addr1, card->membase + DR1);
  934. writel(id1, card->membase + DR0);
  935. writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
  936. card->membase + CMD);
  937. spin_unlock_irqrestore(&card->res_lock, flags);
  938. XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
  939. card->index,
  940. (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
  941. addr1, addr2);
  942. }
  943. if (!card->efbie && card->sbfqc >= card->sbnr.min &&
  944. card->lbfqc >= card->lbnr.min) {
  945. card->efbie = 1;
  946. writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
  947. card->membase + CFG);
  948. }
  949. out:
  950. return;
  951. }
  952. static irqreturn_t ns_irq_handler(int irq, void *dev_id)
  953. {
  954. u32 stat_r;
  955. ns_dev *card;
  956. struct atm_dev *dev;
  957. unsigned long flags;
  958. card = (ns_dev *) dev_id;
  959. dev = card->atmdev;
  960. card->intcnt++;
  961. PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
  962. spin_lock_irqsave(&card->int_lock, flags);
  963. stat_r = readl(card->membase + STAT);
  964. /* Transmit Status Indicator has been written to T. S. Queue */
  965. if (stat_r & NS_STAT_TSIF) {
  966. TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
  967. process_tsq(card);
  968. writel(NS_STAT_TSIF, card->membase + STAT);
  969. }
  970. /* Incomplete CS-PDU has been transmitted */
  971. if (stat_r & NS_STAT_TXICP) {
  972. writel(NS_STAT_TXICP, card->membase + STAT);
  973. TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
  974. card->index);
  975. }
  976. /* Transmit Status Queue 7/8 full */
  977. if (stat_r & NS_STAT_TSQF) {
  978. writel(NS_STAT_TSQF, card->membase + STAT);
  979. PRINTK("nicstar%d: TSQ full.\n", card->index);
  980. process_tsq(card);
  981. }
  982. /* Timer overflow */
  983. if (stat_r & NS_STAT_TMROF) {
  984. writel(NS_STAT_TMROF, card->membase + STAT);
  985. PRINTK("nicstar%d: Timer overflow.\n", card->index);
  986. }
  987. /* PHY device interrupt signal active */
  988. if (stat_r & NS_STAT_PHYI) {
  989. writel(NS_STAT_PHYI, card->membase + STAT);
  990. PRINTK("nicstar%d: PHY interrupt.\n", card->index);
  991. if (dev->phy && dev->phy->interrupt) {
  992. dev->phy->interrupt(dev);
  993. }
  994. }
  995. /* Small Buffer Queue is full */
  996. if (stat_r & NS_STAT_SFBQF) {
  997. writel(NS_STAT_SFBQF, card->membase + STAT);
  998. printk("nicstar%d: Small free buffer queue is full.\n",
  999. card->index);
  1000. }
  1001. /* Large Buffer Queue is full */
  1002. if (stat_r & NS_STAT_LFBQF) {
  1003. writel(NS_STAT_LFBQF, card->membase + STAT);
  1004. printk("nicstar%d: Large free buffer queue is full.\n",
  1005. card->index);
  1006. }
  1007. /* Receive Status Queue is full */
  1008. if (stat_r & NS_STAT_RSQF) {
  1009. writel(NS_STAT_RSQF, card->membase + STAT);
  1010. printk("nicstar%d: RSQ full.\n", card->index);
  1011. process_rsq(card);
  1012. }
  1013. /* Complete CS-PDU received */
  1014. if (stat_r & NS_STAT_EOPDU) {
  1015. RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
  1016. process_rsq(card);
  1017. writel(NS_STAT_EOPDU, card->membase + STAT);
  1018. }
  1019. /* Raw cell received */
  1020. if (stat_r & NS_STAT_RAWCF) {
  1021. writel(NS_STAT_RAWCF, card->membase + STAT);
  1022. #ifndef RCQ_SUPPORT
  1023. printk("nicstar%d: Raw cell received and no support yet...\n",
  1024. card->index);
  1025. #endif /* RCQ_SUPPORT */
  1026. /* NOTE: the following procedure may keep a raw cell pending until the
  1027. next interrupt. As this preliminary support is only meant to
  1028. avoid buffer leakage, this is not an issue. */
  1029. while (readl(card->membase + RAWCT) != card->rawch) {
  1030. if (ns_rcqe_islast(card->rawcell)) {
  1031. struct sk_buff *oldbuf;
  1032. oldbuf = card->rcbuf;
  1033. card->rcbuf = idr_find(&card->idr,
  1034. ns_rcqe_nextbufhandle(card->rawcell));
  1035. card->rawch = NS_PRV_DMA(card->rcbuf);
  1036. card->rawcell = (struct ns_rcqe *)
  1037. card->rcbuf->data;
  1038. recycle_rx_buf(card, oldbuf);
  1039. } else {
  1040. card->rawch += NS_RCQE_SIZE;
  1041. card->rawcell++;
  1042. }
  1043. }
  1044. }
  1045. /* Small buffer queue is empty */
  1046. if (stat_r & NS_STAT_SFBQE) {
  1047. int i;
  1048. struct sk_buff *sb;
  1049. writel(NS_STAT_SFBQE, card->membase + STAT);
  1050. printk("nicstar%d: Small free buffer queue empty.\n",
  1051. card->index);
  1052. for (i = 0; i < card->sbnr.min; i++) {
  1053. sb = dev_alloc_skb(NS_SMSKBSIZE);
  1054. if (sb == NULL) {
  1055. writel(readl(card->membase + CFG) &
  1056. ~NS_CFG_EFBIE, card->membase + CFG);
  1057. card->efbie = 0;
  1058. break;
  1059. }
  1060. NS_PRV_BUFTYPE(sb) = BUF_SM;
  1061. skb_queue_tail(&card->sbpool.queue, sb);
  1062. skb_reserve(sb, NS_AAL0_HEADER);
  1063. push_rxbufs(card, sb);
  1064. }
  1065. card->sbfqc = i;
  1066. process_rsq(card);
  1067. }
  1068. /* Large buffer queue empty */
  1069. if (stat_r & NS_STAT_LFBQE) {
  1070. int i;
  1071. struct sk_buff *lb;
  1072. writel(NS_STAT_LFBQE, card->membase + STAT);
  1073. printk("nicstar%d: Large free buffer queue empty.\n",
  1074. card->index);
  1075. for (i = 0; i < card->lbnr.min; i++) {
  1076. lb = dev_alloc_skb(NS_LGSKBSIZE);
  1077. if (lb == NULL) {
  1078. writel(readl(card->membase + CFG) &
  1079. ~NS_CFG_EFBIE, card->membase + CFG);
  1080. card->efbie = 0;
  1081. break;
  1082. }
  1083. NS_PRV_BUFTYPE(lb) = BUF_LG;
  1084. skb_queue_tail(&card->lbpool.queue, lb);
  1085. skb_reserve(lb, NS_SMBUFSIZE);
  1086. push_rxbufs(card, lb);
  1087. }
  1088. card->lbfqc = i;
  1089. process_rsq(card);
  1090. }
  1091. /* Receive Status Queue is 7/8 full */
  1092. if (stat_r & NS_STAT_RSQAF) {
  1093. writel(NS_STAT_RSQAF, card->membase + STAT);
  1094. RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
  1095. process_rsq(card);
  1096. }
  1097. spin_unlock_irqrestore(&card->int_lock, flags);
  1098. PRINTK("nicstar%d: end of interrupt service\n", card->index);
  1099. return IRQ_HANDLED;
  1100. }
  1101. static int ns_open(struct atm_vcc *vcc)
  1102. {
  1103. ns_dev *card;
  1104. vc_map *vc;
  1105. unsigned long tmpl, modl;
  1106. int tcr, tcra; /* target cell rate, and absolute value */
  1107. int n = 0; /* Number of entries in the TST. Initialized to remove
  1108. the compiler warning. */
  1109. u32 u32d[4];
  1110. int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
  1111. warning. How I wish compilers were clever enough to
  1112. tell which variables can truly be used
  1113. uninitialized... */
  1114. int inuse; /* tx or rx vc already in use by another vcc */
  1115. short vpi = vcc->vpi;
  1116. int vci = vcc->vci;
  1117. card = (ns_dev *) vcc->dev->dev_data;
  1118. PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
  1119. vci);
  1120. if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
  1121. PRINTK("nicstar%d: unsupported AAL.\n", card->index);
  1122. return -EINVAL;
  1123. }
  1124. vc = &(card->vcmap[vpi << card->vcibits | vci]);
  1125. vcc->dev_data = vc;
  1126. inuse = 0;
  1127. if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
  1128. inuse = 1;
  1129. if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
  1130. inuse += 2;
  1131. if (inuse) {
  1132. printk("nicstar%d: %s vci already in use.\n", card->index,
  1133. inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
  1134. return -EINVAL;
  1135. }
  1136. set_bit(ATM_VF_ADDR, &vcc->flags);
  1137. /* NOTE: You are not allowed to modify an open connection's QOS. To change
  1138. that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
  1139. needed to do that. */
  1140. if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
  1141. scq_info *scq;
  1142. set_bit(ATM_VF_PARTIAL, &vcc->flags);
  1143. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1144. /* Check requested cell rate and availability of SCD */
  1145. if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
  1146. && vcc->qos.txtp.min_pcr == 0) {
  1147. PRINTK
  1148. ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
  1149. card->index);
  1150. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1151. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1152. return -EINVAL;
  1153. }
  1154. tcr = atm_pcr_goal(&(vcc->qos.txtp));
  1155. tcra = tcr >= 0 ? tcr : -tcr;
  1156. PRINTK("nicstar%d: target cell rate = %d.\n",
  1157. card->index, vcc->qos.txtp.max_pcr);
  1158. tmpl =
  1159. (unsigned long)tcra *(unsigned long)
  1160. NS_TST_NUM_ENTRIES;
  1161. modl = tmpl % card->max_pcr;
  1162. n = (int)(tmpl / card->max_pcr);
  1163. if (tcr > 0) {
  1164. if (modl > 0)
  1165. n++;
  1166. } else if (tcr == 0) {
  1167. if ((n =
  1168. (card->tst_free_entries -
  1169. NS_TST_RESERVED)) <= 0) {
  1170. PRINTK
  1171. ("nicstar%d: no CBR bandwidth free.\n",
  1172. card->index);
  1173. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1174. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1175. return -EINVAL;
  1176. }
  1177. }
  1178. if (n == 0) {
  1179. printk
  1180. ("nicstar%d: selected bandwidth < granularity.\n",
  1181. card->index);
  1182. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1183. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1184. return -EINVAL;
  1185. }
  1186. if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
  1187. PRINTK
  1188. ("nicstar%d: not enough free CBR bandwidth.\n",
  1189. card->index);
  1190. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1191. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1192. return -EINVAL;
  1193. } else
  1194. card->tst_free_entries -= n;
  1195. XPRINTK("nicstar%d: writing %d tst entries.\n",
  1196. card->index, n);
  1197. for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
  1198. if (card->scd2vc[frscdi] == NULL) {
  1199. card->scd2vc[frscdi] = vc;
  1200. break;
  1201. }
  1202. }
  1203. if (frscdi == NS_FRSCD_NUM) {
  1204. PRINTK
  1205. ("nicstar%d: no SCD available for CBR channel.\n",
  1206. card->index);
  1207. card->tst_free_entries += n;
  1208. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1209. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1210. return -EBUSY;
  1211. }
  1212. vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
  1213. scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
  1214. if (scq == NULL) {
  1215. PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
  1216. card->index);
  1217. card->scd2vc[frscdi] = NULL;
  1218. card->tst_free_entries += n;
  1219. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1220. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1221. return -ENOMEM;
  1222. }
  1223. vc->scq = scq;
  1224. u32d[0] = scq_virt_to_bus(scq, scq->base);
  1225. u32d[1] = (u32) 0x00000000;
  1226. u32d[2] = (u32) 0xffffffff;
  1227. u32d[3] = (u32) 0x00000000;
  1228. ns_write_sram(card, vc->cbr_scd, u32d, 4);
  1229. fill_tst(card, n, vc);
  1230. } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
  1231. vc->cbr_scd = 0x00000000;
  1232. vc->scq = card->scq0;
  1233. }
  1234. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1235. vc->tx = 1;
  1236. vc->tx_vcc = vcc;
  1237. vc->tbd_count = 0;
  1238. }
  1239. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1240. u32 status;
  1241. vc->rx = 1;
  1242. vc->rx_vcc = vcc;
  1243. vc->rx_iov = NULL;
  1244. /* Open the connection in hardware */
  1245. if (vcc->qos.aal == ATM_AAL5)
  1246. status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
  1247. else /* vcc->qos.aal == ATM_AAL0 */
  1248. status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
  1249. #ifdef RCQ_SUPPORT
  1250. status |= NS_RCTE_RAWCELLINTEN;
  1251. #endif /* RCQ_SUPPORT */
  1252. ns_write_sram(card,
  1253. NS_RCT +
  1254. (vpi << card->vcibits | vci) *
  1255. NS_RCT_ENTRY_SIZE, &status, 1);
  1256. }
  1257. }
  1258. set_bit(ATM_VF_READY, &vcc->flags);
  1259. return 0;
  1260. }
  1261. static void ns_close(struct atm_vcc *vcc)
  1262. {
  1263. vc_map *vc;
  1264. ns_dev *card;
  1265. u32 data;
  1266. int i;
  1267. vc = vcc->dev_data;
  1268. card = vcc->dev->dev_data;
  1269. PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
  1270. (int)vcc->vpi, vcc->vci);
  1271. clear_bit(ATM_VF_READY, &vcc->flags);
  1272. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1273. u32 addr;
  1274. unsigned long flags;
  1275. addr =
  1276. NS_RCT +
  1277. (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
  1278. spin_lock_irqsave(&card->res_lock, flags);
  1279. while (CMD_BUSY(card)) ;
  1280. writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
  1281. card->membase + CMD);
  1282. spin_unlock_irqrestore(&card->res_lock, flags);
  1283. vc->rx = 0;
  1284. if (vc->rx_iov != NULL) {
  1285. struct sk_buff *iovb;
  1286. u32 stat;
  1287. stat = readl(card->membase + STAT);
  1288. card->sbfqc = ns_stat_sfbqc_get(stat);
  1289. card->lbfqc = ns_stat_lfbqc_get(stat);
  1290. PRINTK
  1291. ("nicstar%d: closing a VC with pending rx buffers.\n",
  1292. card->index);
  1293. iovb = vc->rx_iov;
  1294. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1295. NS_PRV_IOVCNT(iovb));
  1296. NS_PRV_IOVCNT(iovb) = 0;
  1297. spin_lock_irqsave(&card->int_lock, flags);
  1298. recycle_iov_buf(card, iovb);
  1299. spin_unlock_irqrestore(&card->int_lock, flags);
  1300. vc->rx_iov = NULL;
  1301. }
  1302. }
  1303. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1304. vc->tx = 0;
  1305. }
  1306. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1307. unsigned long flags;
  1308. ns_scqe *scqep;
  1309. scq_info *scq;
  1310. scq = vc->scq;
  1311. for (;;) {
  1312. spin_lock_irqsave(&scq->lock, flags);
  1313. scqep = scq->next;
  1314. if (scqep == scq->base)
  1315. scqep = scq->last;
  1316. else
  1317. scqep--;
  1318. if (scqep == scq->tail) {
  1319. spin_unlock_irqrestore(&scq->lock, flags);
  1320. break;
  1321. }
  1322. /* If the last entry is not a TSR, place one in the SCQ in order to
  1323. be able to completely drain it and then close. */
  1324. if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
  1325. ns_scqe tsr;
  1326. u32 scdi, scqi;
  1327. u32 data;
  1328. int index;
  1329. tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
  1330. scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
  1331. scqi = scq->next - scq->base;
  1332. tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
  1333. tsr.word_3 = 0x00000000;
  1334. tsr.word_4 = 0x00000000;
  1335. *scq->next = tsr;
  1336. index = (int)scqi;
  1337. scq->skb[index] = NULL;
  1338. if (scq->next == scq->last)
  1339. scq->next = scq->base;
  1340. else
  1341. scq->next++;
  1342. data = scq_virt_to_bus(scq, scq->next);
  1343. ns_write_sram(card, scq->scd, &data, 1);
  1344. }
  1345. spin_unlock_irqrestore(&scq->lock, flags);
  1346. schedule();
  1347. }
  1348. /* Free all TST entries */
  1349. data = NS_TST_OPCODE_VARIABLE;
  1350. for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
  1351. if (card->tste2vc[i] == vc) {
  1352. ns_write_sram(card, card->tst_addr + i, &data,
  1353. 1);
  1354. card->tste2vc[i] = NULL;
  1355. card->tst_free_entries++;
  1356. }
  1357. }
  1358. card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
  1359. free_scq(card, vc->scq, vcc);
  1360. }
  1361. /* remove all references to vcc before deleting it */
  1362. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1363. unsigned long flags;
  1364. scq_info *scq = card->scq0;
  1365. spin_lock_irqsave(&scq->lock, flags);
  1366. for (i = 0; i < scq->num_entries; i++) {
  1367. if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
  1368. ATM_SKB(scq->skb[i])->vcc = NULL;
  1369. atm_return(vcc, scq->skb[i]->truesize);
  1370. PRINTK
  1371. ("nicstar: deleted pending vcc mapping\n");
  1372. }
  1373. }
  1374. spin_unlock_irqrestore(&scq->lock, flags);
  1375. }
  1376. vcc->dev_data = NULL;
  1377. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1378. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1379. #ifdef RX_DEBUG
  1380. {
  1381. u32 stat, cfg;
  1382. stat = readl(card->membase + STAT);
  1383. cfg = readl(card->membase + CFG);
  1384. printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
  1385. printk
  1386. ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
  1387. card->tsq.base, card->tsq.next,
  1388. card->tsq.last, readl(card->membase + TSQT));
  1389. printk
  1390. ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
  1391. card->rsq.base, card->rsq.next,
  1392. card->rsq.last, readl(card->membase + RSQT));
  1393. printk("Empty free buffer queue interrupt %s \n",
  1394. card->efbie ? "enabled" : "disabled");
  1395. printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
  1396. ns_stat_sfbqc_get(stat), card->sbpool.count,
  1397. ns_stat_lfbqc_get(stat), card->lbpool.count);
  1398. printk("hbpool.count = %d iovpool.count = %d \n",
  1399. card->hbpool.count, card->iovpool.count);
  1400. }
  1401. #endif /* RX_DEBUG */
  1402. }
  1403. static void fill_tst(ns_dev * card, int n, vc_map * vc)
  1404. {
  1405. u32 new_tst;
  1406. unsigned long cl;
  1407. int e, r;
  1408. u32 data;
  1409. /* It would be very complicated to keep the two TSTs synchronized while
  1410. assuring that writes are only made to the inactive TST. So, for now I
  1411. will use only one TST. If problems occur, I will change this again */
  1412. new_tst = card->tst_addr;
  1413. /* Fill procedure */
  1414. for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
  1415. if (card->tste2vc[e] == NULL)
  1416. break;
  1417. }
  1418. if (e == NS_TST_NUM_ENTRIES) {
  1419. printk("nicstar%d: No free TST entries found. \n", card->index);
  1420. return;
  1421. }
  1422. r = n;
  1423. cl = NS_TST_NUM_ENTRIES;
  1424. data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
  1425. while (r > 0) {
  1426. if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
  1427. card->tste2vc[e] = vc;
  1428. ns_write_sram(card, new_tst + e, &data, 1);
  1429. cl -= NS_TST_NUM_ENTRIES;
  1430. r--;
  1431. }
  1432. if (++e == NS_TST_NUM_ENTRIES) {
  1433. e = 0;
  1434. }
  1435. cl += n;
  1436. }
  1437. /* End of fill procedure */
  1438. data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
  1439. ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
  1440. ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
  1441. card->tst_addr = new_tst;
  1442. }
  1443. static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
  1444. {
  1445. ns_dev *card;
  1446. vc_map *vc;
  1447. scq_info *scq;
  1448. unsigned long buflen;
  1449. ns_scqe scqe;
  1450. u32 flags; /* TBD flags, not CPU flags */
  1451. card = vcc->dev->dev_data;
  1452. TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
  1453. if ((vc = (vc_map *) vcc->dev_data) == NULL) {
  1454. printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
  1455. card->index);
  1456. atomic_inc(&vcc->stats->tx_err);
  1457. dev_kfree_skb_any(skb);
  1458. return -EINVAL;
  1459. }
  1460. if (!vc->tx) {
  1461. printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
  1462. card->index);
  1463. atomic_inc(&vcc->stats->tx_err);
  1464. dev_kfree_skb_any(skb);
  1465. return -EINVAL;
  1466. }
  1467. if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
  1468. printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
  1469. card->index);
  1470. atomic_inc(&vcc->stats->tx_err);
  1471. dev_kfree_skb_any(skb);
  1472. return -EINVAL;
  1473. }
  1474. if (skb_shinfo(skb)->nr_frags != 0) {
  1475. printk("nicstar%d: No scatter-gather yet.\n", card->index);
  1476. atomic_inc(&vcc->stats->tx_err);
  1477. dev_kfree_skb_any(skb);
  1478. return -EINVAL;
  1479. }
  1480. ATM_SKB(skb)->vcc = vcc;
  1481. NS_PRV_DMA(skb) = pci_map_single(card->pcidev, skb->data,
  1482. skb->len, PCI_DMA_TODEVICE);
  1483. if (vcc->qos.aal == ATM_AAL5) {
  1484. buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
  1485. flags = NS_TBD_AAL5;
  1486. scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
  1487. scqe.word_3 = cpu_to_le32(skb->len);
  1488. scqe.word_4 =
  1489. ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
  1490. ATM_SKB(skb)->
  1491. atm_options & ATM_ATMOPT_CLP ? 1 : 0);
  1492. flags |= NS_TBD_EOPDU;
  1493. } else { /* (vcc->qos.aal == ATM_AAL0) */
  1494. buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
  1495. flags = NS_TBD_AAL0;
  1496. scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
  1497. scqe.word_3 = cpu_to_le32(0x00000000);
  1498. if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
  1499. flags |= NS_TBD_EOPDU;
  1500. scqe.word_4 =
  1501. cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
  1502. /* Force the VPI/VCI to be the same as in VCC struct */
  1503. scqe.word_4 |=
  1504. cpu_to_le32((((u32) vcc->
  1505. vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
  1506. vci) <<
  1507. NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
  1508. }
  1509. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1510. scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
  1511. scq = ((vc_map *) vcc->dev_data)->scq;
  1512. } else {
  1513. scqe.word_1 =
  1514. ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
  1515. scq = card->scq0;
  1516. }
  1517. if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
  1518. atomic_inc(&vcc->stats->tx_err);
  1519. dev_kfree_skb_any(skb);
  1520. return -EIO;
  1521. }
  1522. atomic_inc(&vcc->stats->tx);
  1523. return 0;
  1524. }
  1525. static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
  1526. struct sk_buff *skb)
  1527. {
  1528. unsigned long flags;
  1529. ns_scqe tsr;
  1530. u32 scdi, scqi;
  1531. int scq_is_vbr;
  1532. u32 data;
  1533. int index;
  1534. spin_lock_irqsave(&scq->lock, flags);
  1535. while (scq->tail == scq->next) {
  1536. if (in_interrupt()) {
  1537. spin_unlock_irqrestore(&scq->lock, flags);
  1538. printk("nicstar%d: Error pushing TBD.\n", card->index);
  1539. return 1;
  1540. }
  1541. scq->full = 1;
  1542. spin_unlock_irqrestore(&scq->lock, flags);
  1543. interruptible_sleep_on_timeout(&scq->scqfull_waitq,
  1544. SCQFULL_TIMEOUT);
  1545. spin_lock_irqsave(&scq->lock, flags);
  1546. if (scq->full) {
  1547. spin_unlock_irqrestore(&scq->lock, flags);
  1548. printk("nicstar%d: Timeout pushing TBD.\n",
  1549. card->index);
  1550. return 1;
  1551. }
  1552. }
  1553. *scq->next = *tbd;
  1554. index = (int)(scq->next - scq->base);
  1555. scq->skb[index] = skb;
  1556. XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
  1557. card->index, skb, index);
  1558. XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
  1559. card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
  1560. le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
  1561. scq->next);
  1562. if (scq->next == scq->last)
  1563. scq->next = scq->base;
  1564. else
  1565. scq->next++;
  1566. vc->tbd_count++;
  1567. if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
  1568. scq->tbd_count++;
  1569. scq_is_vbr = 1;
  1570. } else
  1571. scq_is_vbr = 0;
  1572. if (vc->tbd_count >= MAX_TBD_PER_VC
  1573. || scq->tbd_count >= MAX_TBD_PER_SCQ) {
  1574. int has_run = 0;
  1575. while (scq->tail == scq->next) {
  1576. if (in_interrupt()) {
  1577. data = scq_virt_to_bus(scq, scq->next);
  1578. ns_write_sram(card, scq->scd, &data, 1);
  1579. spin_unlock_irqrestore(&scq->lock, flags);
  1580. printk("nicstar%d: Error pushing TSR.\n",
  1581. card->index);
  1582. return 0;
  1583. }
  1584. scq->full = 1;
  1585. if (has_run++)
  1586. break;
  1587. spin_unlock_irqrestore(&scq->lock, flags);
  1588. interruptible_sleep_on_timeout(&scq->scqfull_waitq,
  1589. SCQFULL_TIMEOUT);
  1590. spin_lock_irqsave(&scq->lock, flags);
  1591. }
  1592. if (!scq->full) {
  1593. tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
  1594. if (scq_is_vbr)
  1595. scdi = NS_TSR_SCDISVBR;
  1596. else
  1597. scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
  1598. scqi = scq->next - scq->base;
  1599. tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
  1600. tsr.word_3 = 0x00000000;
  1601. tsr.word_4 = 0x00000000;
  1602. *scq->next = tsr;
  1603. index = (int)scqi;
  1604. scq->skb[index] = NULL;
  1605. XPRINTK
  1606. ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
  1607. card->index, le32_to_cpu(tsr.word_1),
  1608. le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
  1609. le32_to_cpu(tsr.word_4), scq->next);
  1610. if (scq->next == scq->last)
  1611. scq->next = scq->base;
  1612. else
  1613. scq->next++;
  1614. vc->tbd_count = 0;
  1615. scq->tbd_count = 0;
  1616. } else
  1617. PRINTK("nicstar%d: Timeout pushing TSR.\n",
  1618. card->index);
  1619. }
  1620. data = scq_virt_to_bus(scq, scq->next);
  1621. ns_write_sram(card, scq->scd, &data, 1);
  1622. spin_unlock_irqrestore(&scq->lock, flags);
  1623. return 0;
  1624. }
  1625. static void process_tsq(ns_dev * card)
  1626. {
  1627. u32 scdi;
  1628. scq_info *scq;
  1629. ns_tsi *previous = NULL, *one_ahead, *two_ahead;
  1630. int serviced_entries; /* flag indicating at least on entry was serviced */
  1631. serviced_entries = 0;
  1632. if (card->tsq.next == card->tsq.last)
  1633. one_ahead = card->tsq.base;
  1634. else
  1635. one_ahead = card->tsq.next + 1;
  1636. if (one_ahead == card->tsq.last)
  1637. two_ahead = card->tsq.base;
  1638. else
  1639. two_ahead = one_ahead + 1;
  1640. while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
  1641. !ns_tsi_isempty(two_ahead))
  1642. /* At most two empty, as stated in the 77201 errata */
  1643. {
  1644. serviced_entries = 1;
  1645. /* Skip the one or two possible empty entries */
  1646. while (ns_tsi_isempty(card->tsq.next)) {
  1647. if (card->tsq.next == card->tsq.last)
  1648. card->tsq.next = card->tsq.base;
  1649. else
  1650. card->tsq.next++;
  1651. }
  1652. if (!ns_tsi_tmrof(card->tsq.next)) {
  1653. scdi = ns_tsi_getscdindex(card->tsq.next);
  1654. if (scdi == NS_TSI_SCDISVBR)
  1655. scq = card->scq0;
  1656. else {
  1657. if (card->scd2vc[scdi] == NULL) {
  1658. printk
  1659. ("nicstar%d: could not find VC from SCD index.\n",
  1660. card->index);
  1661. ns_tsi_init(card->tsq.next);
  1662. return;
  1663. }
  1664. scq = card->scd2vc[scdi]->scq;
  1665. }
  1666. drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
  1667. scq->full = 0;
  1668. wake_up_interruptible(&(scq->scqfull_waitq));
  1669. }
  1670. ns_tsi_init(card->tsq.next);
  1671. previous = card->tsq.next;
  1672. if (card->tsq.next == card->tsq.last)
  1673. card->tsq.next = card->tsq.base;
  1674. else
  1675. card->tsq.next++;
  1676. if (card->tsq.next == card->tsq.last)
  1677. one_ahead = card->tsq.base;
  1678. else
  1679. one_ahead = card->tsq.next + 1;
  1680. if (one_ahead == card->tsq.last)
  1681. two_ahead = card->tsq.base;
  1682. else
  1683. two_ahead = one_ahead + 1;
  1684. }
  1685. if (serviced_entries)
  1686. writel(PTR_DIFF(previous, card->tsq.base),
  1687. card->membase + TSQH);
  1688. }
  1689. static void drain_scq(ns_dev * card, scq_info * scq, int pos)
  1690. {
  1691. struct atm_vcc *vcc;
  1692. struct sk_buff *skb;
  1693. int i;
  1694. unsigned long flags;
  1695. XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
  1696. card->index, scq, pos);
  1697. if (pos >= scq->num_entries) {
  1698. printk("nicstar%d: Bad index on drain_scq().\n", card->index);
  1699. return;
  1700. }
  1701. spin_lock_irqsave(&scq->lock, flags);
  1702. i = (int)(scq->tail - scq->base);
  1703. if (++i == scq->num_entries)
  1704. i = 0;
  1705. while (i != pos) {
  1706. skb = scq->skb[i];
  1707. XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
  1708. card->index, skb, i);
  1709. if (skb != NULL) {
  1710. pci_unmap_single(card->pcidev,
  1711. NS_PRV_DMA(skb),
  1712. skb->len,
  1713. PCI_DMA_TODEVICE);
  1714. vcc = ATM_SKB(skb)->vcc;
  1715. if (vcc && vcc->pop != NULL) {
  1716. vcc->pop(vcc, skb);
  1717. } else {
  1718. dev_kfree_skb_irq(skb);
  1719. }
  1720. scq->skb[i] = NULL;
  1721. }
  1722. if (++i == scq->num_entries)
  1723. i = 0;
  1724. }
  1725. scq->tail = scq->base + pos;
  1726. spin_unlock_irqrestore(&scq->lock, flags);
  1727. }
  1728. static void process_rsq(ns_dev * card)
  1729. {
  1730. ns_rsqe *previous;
  1731. if (!ns_rsqe_valid(card->rsq.next))
  1732. return;
  1733. do {
  1734. dequeue_rx(card, card->rsq.next);
  1735. ns_rsqe_init(card->rsq.next);
  1736. previous = card->rsq.next;
  1737. if (card->rsq.next == card->rsq.last)
  1738. card->rsq.next = card->rsq.base;
  1739. else
  1740. card->rsq.next++;
  1741. } while (ns_rsqe_valid(card->rsq.next));
  1742. writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
  1743. }
  1744. static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
  1745. {
  1746. u32 vpi, vci;
  1747. vc_map *vc;
  1748. struct sk_buff *iovb;
  1749. struct iovec *iov;
  1750. struct atm_vcc *vcc;
  1751. struct sk_buff *skb;
  1752. unsigned short aal5_len;
  1753. int len;
  1754. u32 stat;
  1755. u32 id;
  1756. stat = readl(card->membase + STAT);
  1757. card->sbfqc = ns_stat_sfbqc_get(stat);
  1758. card->lbfqc = ns_stat_lfbqc_get(stat);
  1759. id = le32_to_cpu(rsqe->buffer_handle);
  1760. skb = idr_find(&card->idr, id);
  1761. if (!skb) {
  1762. RXPRINTK(KERN_ERR
  1763. "nicstar%d: idr_find() failed!\n", card->index);
  1764. return;
  1765. }
  1766. idr_remove(&card->idr, id);
  1767. pci_dma_sync_single_for_cpu(card->pcidev,
  1768. NS_PRV_DMA(skb),
  1769. (NS_PRV_BUFTYPE(skb) == BUF_SM
  1770. ? NS_SMSKBSIZE : NS_LGSKBSIZE),
  1771. PCI_DMA_FROMDEVICE);
  1772. pci_unmap_single(card->pcidev,
  1773. NS_PRV_DMA(skb),
  1774. (NS_PRV_BUFTYPE(skb) == BUF_SM
  1775. ? NS_SMSKBSIZE : NS_LGSKBSIZE),
  1776. PCI_DMA_FROMDEVICE);
  1777. vpi = ns_rsqe_vpi(rsqe);
  1778. vci = ns_rsqe_vci(rsqe);
  1779. if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
  1780. printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
  1781. card->index, vpi, vci);
  1782. recycle_rx_buf(card, skb);
  1783. return;
  1784. }
  1785. vc = &(card->vcmap[vpi << card->vcibits | vci]);
  1786. if (!vc->rx) {
  1787. RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
  1788. card->index, vpi, vci);
  1789. recycle_rx_buf(card, skb);
  1790. return;
  1791. }
  1792. vcc = vc->rx_vcc;
  1793. if (vcc->qos.aal == ATM_AAL0) {
  1794. struct sk_buff *sb;
  1795. unsigned char *cell;
  1796. int i;
  1797. cell = skb->data;
  1798. for (i = ns_rsqe_cellcount(rsqe); i; i--) {
  1799. if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) {
  1800. printk
  1801. ("nicstar%d: Can't allocate buffers for aal0.\n",
  1802. card->index);
  1803. atomic_add(i, &vcc->stats->rx_drop);
  1804. break;
  1805. }
  1806. if (!atm_charge(vcc, sb->truesize)) {
  1807. RXPRINTK
  1808. ("nicstar%d: atm_charge() dropped aal0 packets.\n",
  1809. card->index);
  1810. atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
  1811. dev_kfree_skb_any(sb);
  1812. break;
  1813. }
  1814. /* Rebuild the header */
  1815. *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
  1816. (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
  1817. if (i == 1 && ns_rsqe_eopdu(rsqe))
  1818. *((u32 *) sb->data) |= 0x00000002;
  1819. skb_put(sb, NS_AAL0_HEADER);
  1820. memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
  1821. skb_put(sb, ATM_CELL_PAYLOAD);
  1822. ATM_SKB(sb)->vcc = vcc;
  1823. __net_timestamp(sb);
  1824. vcc->push(vcc, sb);
  1825. atomic_inc(&vcc->stats->rx);
  1826. cell += ATM_CELL_PAYLOAD;
  1827. }
  1828. recycle_rx_buf(card, skb);
  1829. return;
  1830. }
  1831. /* To reach this point, the AAL layer can only be AAL5 */
  1832. if ((iovb = vc->rx_iov) == NULL) {
  1833. iovb = skb_dequeue(&(card->iovpool.queue));
  1834. if (iovb == NULL) { /* No buffers in the queue */
  1835. iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
  1836. if (iovb == NULL) {
  1837. printk("nicstar%d: Out of iovec buffers.\n",
  1838. card->index);
  1839. atomic_inc(&vcc->stats->rx_drop);
  1840. recycle_rx_buf(card, skb);
  1841. return;
  1842. }
  1843. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  1844. } else if (--card->iovpool.count < card->iovnr.min) {
  1845. struct sk_buff *new_iovb;
  1846. if ((new_iovb =
  1847. alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
  1848. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  1849. skb_queue_tail(&card->iovpool.queue, new_iovb);
  1850. card->iovpool.count++;
  1851. }
  1852. }
  1853. vc->rx_iov = iovb;
  1854. NS_PRV_IOVCNT(iovb) = 0;
  1855. iovb->len = 0;
  1856. iovb->data = iovb->head;
  1857. skb_reset_tail_pointer(iovb);
  1858. /* IMPORTANT: a pointer to the sk_buff containing the small or large
  1859. buffer is stored as iovec base, NOT a pointer to the
  1860. small or large buffer itself. */
  1861. } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
  1862. printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
  1863. atomic_inc(&vcc->stats->rx_err);
  1864. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1865. NS_MAX_IOVECS);
  1866. NS_PRV_IOVCNT(iovb) = 0;
  1867. iovb->len = 0;
  1868. iovb->data = iovb->head;
  1869. skb_reset_tail_pointer(iovb);
  1870. }
  1871. iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
  1872. iov->iov_base = (void *)skb;
  1873. iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
  1874. iovb->len += iov->iov_len;
  1875. #ifdef EXTRA_DEBUG
  1876. if (NS_PRV_IOVCNT(iovb) == 1) {
  1877. if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
  1878. printk
  1879. ("nicstar%d: Expected a small buffer, and this is not one.\n",
  1880. card->index);
  1881. which_list(card, skb);
  1882. atomic_inc(&vcc->stats->rx_err);
  1883. recycle_rx_buf(card, skb);
  1884. vc->rx_iov = NULL;
  1885. recycle_iov_buf(card, iovb);
  1886. return;
  1887. }
  1888. } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
  1889. if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
  1890. printk
  1891. ("nicstar%d: Expected a large buffer, and this is not one.\n",
  1892. card->index);
  1893. which_list(card, skb);
  1894. atomic_inc(&vcc->stats->rx_err);
  1895. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1896. NS_PRV_IOVCNT(iovb));
  1897. vc->rx_iov = NULL;
  1898. recycle_iov_buf(card, iovb);
  1899. return;
  1900. }
  1901. }
  1902. #endif /* EXTRA_DEBUG */
  1903. if (ns_rsqe_eopdu(rsqe)) {
  1904. /* This works correctly regardless of the endianness of the host */
  1905. unsigned char *L1L2 = (unsigned char *)
  1906. (skb->data + iov->iov_len - 6);
  1907. aal5_len = L1L2[0] << 8 | L1L2[1];
  1908. len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
  1909. if (ns_rsqe_crcerr(rsqe) ||
  1910. len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
  1911. printk("nicstar%d: AAL5 CRC error", card->index);
  1912. if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
  1913. printk(" - PDU size mismatch.\n");
  1914. else
  1915. printk(".\n");
  1916. atomic_inc(&vcc->stats->rx_err);
  1917. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1918. NS_PRV_IOVCNT(iovb));
  1919. vc->rx_iov = NULL;
  1920. recycle_iov_buf(card, iovb);
  1921. return;
  1922. }
  1923. /* By this point we (hopefully) have a complete SDU without errors. */
  1924. if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
  1925. /* skb points to a small buffer */
  1926. if (!atm_charge(vcc, skb->truesize)) {
  1927. push_rxbufs(card, skb);
  1928. atomic_inc(&vcc->stats->rx_drop);
  1929. } else {
  1930. skb_put(skb, len);
  1931. dequeue_sm_buf(card, skb);
  1932. #ifdef NS_USE_DESTRUCTORS
  1933. skb->destructor = ns_sb_destructor;
  1934. #endif /* NS_USE_DESTRUCTORS */
  1935. ATM_SKB(skb)->vcc = vcc;
  1936. __net_timestamp(skb);
  1937. vcc->push(vcc, skb);
  1938. atomic_inc(&vcc->stats->rx);
  1939. }
  1940. } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
  1941. struct sk_buff *sb;
  1942. sb = (struct sk_buff *)(iov - 1)->iov_base;
  1943. /* skb points to a large buffer */
  1944. if (len <= NS_SMBUFSIZE) {
  1945. if (!atm_charge(vcc, sb->truesize)) {
  1946. push_rxbufs(card, sb);
  1947. atomic_inc(&vcc->stats->rx_drop);
  1948. } else {
  1949. skb_put(sb, len);
  1950. dequeue_sm_buf(card, sb);
  1951. #ifdef NS_USE_DESTRUCTORS
  1952. sb->destructor = ns_sb_destructor;
  1953. #endif /* NS_USE_DESTRUCTORS */
  1954. ATM_SKB(sb)->vcc = vcc;
  1955. __net_timestamp(sb);
  1956. vcc->push(vcc, sb);
  1957. atomic_inc(&vcc->stats->rx);
  1958. }
  1959. push_rxbufs(card, skb);
  1960. } else { /* len > NS_SMBUFSIZE, the usual case */
  1961. if (!atm_charge(vcc, skb->truesize)) {
  1962. push_rxbufs(card, skb);
  1963. atomic_inc(&vcc->stats->rx_drop);
  1964. } else {
  1965. dequeue_lg_buf(card, skb);
  1966. #ifdef NS_USE_DESTRUCTORS
  1967. skb->destructor = ns_lb_destructor;
  1968. #endif /* NS_USE_DESTRUCTORS */
  1969. skb_push(skb, NS_SMBUFSIZE);
  1970. skb_copy_from_linear_data(sb, skb->data,
  1971. NS_SMBUFSIZE);
  1972. skb_put(skb, len - NS_SMBUFSIZE);
  1973. ATM_SKB(skb)->vcc = vcc;
  1974. __net_timestamp(skb);
  1975. vcc->push(vcc, skb);
  1976. atomic_inc(&vcc->stats->rx);
  1977. }
  1978. push_rxbufs(card, sb);
  1979. }
  1980. } else { /* Must push a huge buffer */
  1981. struct sk_buff *hb, *sb, *lb;
  1982. int remaining, tocopy;
  1983. int j;
  1984. hb = skb_dequeue(&(card->hbpool.queue));
  1985. if (hb == NULL) { /* No buffers in the queue */
  1986. hb = dev_alloc_skb(NS_HBUFSIZE);
  1987. if (hb == NULL) {
  1988. printk
  1989. ("nicstar%d: Out of huge buffers.\n",
  1990. card->index);
  1991. atomic_inc(&vcc->stats->rx_drop);
  1992. recycle_iovec_rx_bufs(card,
  1993. (struct iovec *)
  1994. iovb->data,
  1995. NS_PRV_IOVCNT(iovb));
  1996. vc->rx_iov = NULL;
  1997. recycle_iov_buf(card, iovb);
  1998. return;
  1999. } else if (card->hbpool.count < card->hbnr.min) {
  2000. struct sk_buff *new_hb;
  2001. if ((new_hb =
  2002. dev_alloc_skb(NS_HBUFSIZE)) !=
  2003. NULL) {
  2004. skb_queue_tail(&card->hbpool.
  2005. queue, new_hb);
  2006. card->hbpool.count++;
  2007. }
  2008. }
  2009. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  2010. } else if (--card->hbpool.count < card->hbnr.min) {
  2011. struct sk_buff *new_hb;
  2012. if ((new_hb =
  2013. dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
  2014. NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
  2015. skb_queue_tail(&card->hbpool.queue,
  2016. new_hb);
  2017. card->hbpool.count++;
  2018. }
  2019. if (card->hbpool.count < card->hbnr.min) {
  2020. if ((new_hb =
  2021. dev_alloc_skb(NS_HBUFSIZE)) !=
  2022. NULL) {
  2023. NS_PRV_BUFTYPE(new_hb) =
  2024. BUF_NONE;
  2025. skb_queue_tail(&card->hbpool.
  2026. queue, new_hb);
  2027. card->hbpool.count++;
  2028. }
  2029. }
  2030. }
  2031. iov = (struct iovec *)iovb->data;
  2032. if (!atm_charge(vcc, hb->truesize)) {
  2033. recycle_iovec_rx_bufs(card, iov,
  2034. NS_PRV_IOVCNT(iovb));
  2035. if (card->hbpool.count < card->hbnr.max) {
  2036. skb_queue_tail(&card->hbpool.queue, hb);
  2037. card->hbpool.count++;
  2038. } else
  2039. dev_kfree_skb_any(hb);
  2040. atomic_inc(&vcc->stats->rx_drop);
  2041. } else {
  2042. /* Copy the small buffer to the huge buffer */
  2043. sb = (struct sk_buff *)iov->iov_base;
  2044. skb_copy_from_linear_data(sb, hb->data,
  2045. iov->iov_len);
  2046. skb_put(hb, iov->iov_len);
  2047. remaining = len - iov->iov_len;
  2048. iov++;
  2049. /* Free the small buffer */
  2050. push_rxbufs(card, sb);
  2051. /* Copy all large buffers to the huge buffer and free them */
  2052. for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
  2053. lb = (struct sk_buff *)iov->iov_base;
  2054. tocopy =
  2055. min_t(int, remaining, iov->iov_len);
  2056. skb_copy_from_linear_data(lb,
  2057. skb_tail_pointer
  2058. (hb), tocopy);
  2059. skb_put(hb, tocopy);
  2060. iov++;
  2061. remaining -= tocopy;
  2062. push_rxbufs(card, lb);
  2063. }
  2064. #ifdef EXTRA_DEBUG
  2065. if (remaining != 0 || hb->len != len)
  2066. printk
  2067. ("nicstar%d: Huge buffer len mismatch.\n",
  2068. card->index);
  2069. #endif /* EXTRA_DEBUG */
  2070. ATM_SKB(hb)->vcc = vcc;
  2071. #ifdef NS_USE_DESTRUCTORS
  2072. hb->destructor = ns_hb_destructor;
  2073. #endif /* NS_USE_DESTRUCTORS */
  2074. __net_timestamp(hb);
  2075. vcc->push(vcc, hb);
  2076. atomic_inc(&vcc->stats->rx);
  2077. }
  2078. }
  2079. vc->rx_iov = NULL;
  2080. recycle_iov_buf(card, iovb);
  2081. }
  2082. }
  2083. #ifdef NS_USE_DESTRUCTORS
  2084. static void ns_sb_destructor(struct sk_buff *sb)
  2085. {
  2086. ns_dev *card;
  2087. u32 stat;
  2088. card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data;
  2089. stat = readl(card->membase + STAT);
  2090. card->sbfqc = ns_stat_sfbqc_get(stat);
  2091. card->lbfqc = ns_stat_lfbqc_get(stat);
  2092. do {
  2093. sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
  2094. if (sb == NULL)
  2095. break;
  2096. NS_PRV_BUFTYPE(sb) = BUF_SM;
  2097. skb_queue_tail(&card->sbpool.queue, sb);
  2098. skb_reserve(sb, NS_AAL0_HEADER);
  2099. push_rxbufs(card, sb);
  2100. } while (card->sbfqc < card->sbnr.min);
  2101. }
  2102. static void ns_lb_destructor(struct sk_buff *lb)
  2103. {
  2104. ns_dev *card;
  2105. u32 stat;
  2106. card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data;
  2107. stat = readl(card->membase + STAT);
  2108. card->sbfqc = ns_stat_sfbqc_get(stat);
  2109. card->lbfqc = ns_stat_lfbqc_get(stat);
  2110. do {
  2111. lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
  2112. if (lb == NULL)
  2113. break;
  2114. NS_PRV_BUFTYPE(lb) = BUF_LG;
  2115. skb_queue_tail(&card->lbpool.queue, lb);
  2116. skb_reserve(lb, NS_SMBUFSIZE);
  2117. push_rxbufs(card, lb);
  2118. } while (card->lbfqc < card->lbnr.min);
  2119. }
  2120. static void ns_hb_destructor(struct sk_buff *hb)
  2121. {
  2122. ns_dev *card;
  2123. card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data;
  2124. while (card->hbpool.count < card->hbnr.init) {
  2125. hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
  2126. if (hb == NULL)
  2127. break;
  2128. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  2129. skb_queue_tail(&card->hbpool.queue, hb);
  2130. card->hbpool.count++;
  2131. }
  2132. }
  2133. #endif /* NS_USE_DESTRUCTORS */
  2134. static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
  2135. {
  2136. if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
  2137. printk("nicstar%d: What kind of rx buffer is this?\n",
  2138. card->index);
  2139. dev_kfree_skb_any(skb);
  2140. } else
  2141. push_rxbufs(card, skb);
  2142. }
  2143. static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
  2144. {
  2145. while (count-- > 0)
  2146. recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
  2147. }
  2148. static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
  2149. {
  2150. if (card->iovpool.count < card->iovnr.max) {
  2151. skb_queue_tail(&card->iovpool.queue, iovb);
  2152. card->iovpool.count++;
  2153. } else
  2154. dev_kfree_skb_any(iovb);
  2155. }
  2156. static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
  2157. {
  2158. skb_unlink(sb, &card->sbpool.queue);
  2159. #ifdef NS_USE_DESTRUCTORS
  2160. if (card->sbfqc < card->sbnr.min)
  2161. #else
  2162. if (card->sbfqc < card->sbnr.init) {
  2163. struct sk_buff *new_sb;
  2164. if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
  2165. NS_PRV_BUFTYPE(new_sb) = BUF_SM;
  2166. skb_queue_tail(&card->sbpool.queue, new_sb);
  2167. skb_reserve(new_sb, NS_AAL0_HEADER);
  2168. push_rxbufs(card, new_sb);
  2169. }
  2170. }
  2171. if (card->sbfqc < card->sbnr.init)
  2172. #endif /* NS_USE_DESTRUCTORS */
  2173. {
  2174. struct sk_buff *new_sb;
  2175. if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
  2176. NS_PRV_BUFTYPE(new_sb) = BUF_SM;
  2177. skb_queue_tail(&card->sbpool.queue, new_sb);
  2178. skb_reserve(new_sb, NS_AAL0_HEADER);
  2179. push_rxbufs(card, new_sb);
  2180. }
  2181. }
  2182. }
  2183. static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
  2184. {
  2185. skb_unlink(lb, &card->lbpool.queue);
  2186. #ifdef NS_USE_DESTRUCTORS
  2187. if (card->lbfqc < card->lbnr.min)
  2188. #else
  2189. if (card->lbfqc < card->lbnr.init) {
  2190. struct sk_buff *new_lb;
  2191. if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
  2192. NS_PRV_BUFTYPE(new_lb) = BUF_LG;
  2193. skb_queue_tail(&card->lbpool.queue, new_lb);
  2194. skb_reserve(new_lb, NS_SMBUFSIZE);
  2195. push_rxbufs(card, new_lb);
  2196. }
  2197. }
  2198. if (card->lbfqc < card->lbnr.init)
  2199. #endif /* NS_USE_DESTRUCTORS */
  2200. {
  2201. struct sk_buff *new_lb;
  2202. if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
  2203. NS_PRV_BUFTYPE(new_lb) = BUF_LG;
  2204. skb_queue_tail(&card->lbpool.queue, new_lb);
  2205. skb_reserve(new_lb, NS_SMBUFSIZE);
  2206. push_rxbufs(card, new_lb);
  2207. }
  2208. }
  2209. }
  2210. static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
  2211. {
  2212. u32 stat;
  2213. ns_dev *card;
  2214. int left;
  2215. left = (int)*pos;
  2216. card = (ns_dev *) dev->dev_data;
  2217. stat = readl(card->membase + STAT);
  2218. if (!left--)
  2219. return sprintf(page, "Pool count min init max \n");
  2220. if (!left--)
  2221. return sprintf(page, "Small %5d %5d %5d %5d \n",
  2222. ns_stat_sfbqc_get(stat), card->sbnr.min,
  2223. card->sbnr.init, card->sbnr.max);
  2224. if (!left--)
  2225. return sprintf(page, "Large %5d %5d %5d %5d \n",
  2226. ns_stat_lfbqc_get(stat), card->lbnr.min,
  2227. card->lbnr.init, card->lbnr.max);
  2228. if (!left--)
  2229. return sprintf(page, "Huge %5d %5d %5d %5d \n",
  2230. card->hbpool.count, card->hbnr.min,
  2231. card->hbnr.init, card->hbnr.max);
  2232. if (!left--)
  2233. return sprintf(page, "Iovec %5d %5d %5d %5d \n",
  2234. card->iovpool.count, card->iovnr.min,
  2235. card->iovnr.init, card->iovnr.max);
  2236. if (!left--) {
  2237. int retval;
  2238. retval =
  2239. sprintf(page, "Interrupt counter: %u \n", card->intcnt);
  2240. card->intcnt = 0;
  2241. return retval;
  2242. }
  2243. #if 0
  2244. /* Dump 25.6 Mbps PHY registers */
  2245. /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
  2246. here just in case it's needed for debugging. */
  2247. if (card->max_pcr == ATM_25_PCR && !left--) {
  2248. u32 phy_regs[4];
  2249. u32 i;
  2250. for (i = 0; i < 4; i++) {
  2251. while (CMD_BUSY(card)) ;
  2252. writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
  2253. card->membase + CMD);
  2254. while (CMD_BUSY(card)) ;
  2255. phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
  2256. }
  2257. return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
  2258. phy_regs[0], phy_regs[1], phy_regs[2],
  2259. phy_regs[3]);
  2260. }
  2261. #endif /* 0 - Dump 25.6 Mbps PHY registers */
  2262. #if 0
  2263. /* Dump TST */
  2264. if (left-- < NS_TST_NUM_ENTRIES) {
  2265. if (card->tste2vc[left + 1] == NULL)
  2266. return sprintf(page, "%5d - VBR/UBR \n", left + 1);
  2267. else
  2268. return sprintf(page, "%5d - %d %d \n", left + 1,
  2269. card->tste2vc[left + 1]->tx_vcc->vpi,
  2270. card->tste2vc[left + 1]->tx_vcc->vci);
  2271. }
  2272. #endif /* 0 */
  2273. return 0;
  2274. }
  2275. static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
  2276. {
  2277. ns_dev *card;
  2278. pool_levels pl;
  2279. long btype;
  2280. unsigned long flags;
  2281. card = dev->dev_data;
  2282. switch (cmd) {
  2283. case NS_GETPSTAT:
  2284. if (get_user
  2285. (pl.buftype, &((pool_levels __user *) arg)->buftype))
  2286. return -EFAULT;
  2287. switch (pl.buftype) {
  2288. case NS_BUFTYPE_SMALL:
  2289. pl.count =
  2290. ns_stat_sfbqc_get(readl(card->membase + STAT));
  2291. pl.level.min = card->sbnr.min;
  2292. pl.level.init = card->sbnr.init;
  2293. pl.level.max = card->sbnr.max;
  2294. break;
  2295. case NS_BUFTYPE_LARGE:
  2296. pl.count =
  2297. ns_stat_lfbqc_get(readl(card->membase + STAT));
  2298. pl.level.min = card->lbnr.min;
  2299. pl.level.init = card->lbnr.init;
  2300. pl.level.max = card->lbnr.max;
  2301. break;
  2302. case NS_BUFTYPE_HUGE:
  2303. pl.count = card->hbpool.count;
  2304. pl.level.min = card->hbnr.min;
  2305. pl.level.init = card->hbnr.init;
  2306. pl.level.max = card->hbnr.max;
  2307. break;
  2308. case NS_BUFTYPE_IOVEC:
  2309. pl.count = card->iovpool.count;
  2310. pl.level.min = card->iovnr.min;
  2311. pl.level.init = card->iovnr.init;
  2312. pl.level.max = card->iovnr.max;
  2313. break;
  2314. default:
  2315. return -ENOIOCTLCMD;
  2316. }
  2317. if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
  2318. return (sizeof(pl));
  2319. else
  2320. return -EFAULT;
  2321. case NS_SETBUFLEV:
  2322. if (!capable(CAP_NET_ADMIN))
  2323. return -EPERM;
  2324. if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
  2325. return -EFAULT;
  2326. if (pl.level.min >= pl.level.init
  2327. || pl.level.init >= pl.level.max)
  2328. return -EINVAL;
  2329. if (pl.level.min == 0)
  2330. return -EINVAL;
  2331. switch (pl.buftype) {
  2332. case NS_BUFTYPE_SMALL:
  2333. if (pl.level.max > TOP_SB)
  2334. return -EINVAL;
  2335. card->sbnr.min = pl.level.min;
  2336. card->sbnr.init = pl.level.init;
  2337. card->sbnr.max = pl.level.max;
  2338. break;
  2339. case NS_BUFTYPE_LARGE:
  2340. if (pl.level.max > TOP_LB)
  2341. return -EINVAL;
  2342. card->lbnr.min = pl.level.min;
  2343. card->lbnr.init = pl.level.init;
  2344. card->lbnr.max = pl.level.max;
  2345. break;
  2346. case NS_BUFTYPE_HUGE:
  2347. if (pl.level.max > TOP_HB)
  2348. return -EINVAL;
  2349. card->hbnr.min = pl.level.min;
  2350. card->hbnr.init = pl.level.init;
  2351. card->hbnr.max = pl.level.max;
  2352. break;
  2353. case NS_BUFTYPE_IOVEC:
  2354. if (pl.level.max > TOP_IOVB)
  2355. return -EINVAL;
  2356. card->iovnr.min = pl.level.min;
  2357. card->iovnr.init = pl.level.init;
  2358. card->iovnr.max = pl.level.max;
  2359. break;
  2360. default:
  2361. return -EINVAL;
  2362. }
  2363. return 0;
  2364. case NS_ADJBUFLEV:
  2365. if (!capable(CAP_NET_ADMIN))
  2366. return -EPERM;
  2367. btype = (long)arg; /* a long is the same size as a pointer or bigger */
  2368. switch (btype) {
  2369. case NS_BUFTYPE_SMALL:
  2370. while (card->sbfqc < card->sbnr.init) {
  2371. struct sk_buff *sb;
  2372. sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
  2373. if (sb == NULL)
  2374. return -ENOMEM;
  2375. NS_PRV_BUFTYPE(sb) = BUF_SM;
  2376. skb_queue_tail(&card->sbpool.queue, sb);
  2377. skb_reserve(sb, NS_AAL0_HEADER);
  2378. push_rxbufs(card, sb);
  2379. }
  2380. break;
  2381. case NS_BUFTYPE_LARGE:
  2382. while (card->lbfqc < card->lbnr.init) {
  2383. struct sk_buff *lb;
  2384. lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
  2385. if (lb == NULL)
  2386. return -ENOMEM;
  2387. NS_PRV_BUFTYPE(lb) = BUF_LG;
  2388. skb_queue_tail(&card->lbpool.queue, lb);
  2389. skb_reserve(lb, NS_SMBUFSIZE);
  2390. push_rxbufs(card, lb);
  2391. }
  2392. break;
  2393. case NS_BUFTYPE_HUGE:
  2394. while (card->hbpool.count > card->hbnr.init) {
  2395. struct sk_buff *hb;
  2396. spin_lock_irqsave(&card->int_lock, flags);
  2397. hb = skb_dequeue(&card->hbpool.queue);
  2398. card->hbpool.count--;
  2399. spin_unlock_irqrestore(&card->int_lock, flags);
  2400. if (hb == NULL)
  2401. printk
  2402. ("nicstar%d: huge buffer count inconsistent.\n",
  2403. card->index);
  2404. else
  2405. dev_kfree_skb_any(hb);
  2406. }
  2407. while (card->hbpool.count < card->hbnr.init) {
  2408. struct sk_buff *hb;
  2409. hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
  2410. if (hb == NULL)
  2411. return -ENOMEM;
  2412. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  2413. spin_lock_irqsave(&card->int_lock, flags);
  2414. skb_queue_tail(&card->hbpool.queue, hb);
  2415. card->hbpool.count++;
  2416. spin_unlock_irqrestore(&card->int_lock, flags);
  2417. }
  2418. break;
  2419. case NS_BUFTYPE_IOVEC:
  2420. while (card->iovpool.count > card->iovnr.init) {
  2421. struct sk_buff *iovb;
  2422. spin_lock_irqsave(&card->int_lock, flags);
  2423. iovb = skb_dequeue(&card->iovpool.queue);
  2424. card->iovpool.count--;
  2425. spin_unlock_irqrestore(&card->int_lock, flags);
  2426. if (iovb == NULL)
  2427. printk
  2428. ("nicstar%d: iovec buffer count inconsistent.\n",
  2429. card->index);
  2430. else
  2431. dev_kfree_skb_any(iovb);
  2432. }
  2433. while (card->iovpool.count < card->iovnr.init) {
  2434. struct sk_buff *iovb;
  2435. iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
  2436. if (iovb == NULL)
  2437. return -ENOMEM;
  2438. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  2439. spin_lock_irqsave(&card->int_lock, flags);
  2440. skb_queue_tail(&card->iovpool.queue, iovb);
  2441. card->iovpool.count++;
  2442. spin_unlock_irqrestore(&card->int_lock, flags);
  2443. }
  2444. break;
  2445. default:
  2446. return -EINVAL;
  2447. }
  2448. return 0;
  2449. default:
  2450. if (dev->phy && dev->phy->ioctl) {
  2451. return dev->phy->ioctl(dev, cmd, arg);
  2452. } else {
  2453. printk("nicstar%d: %s == NULL \n", card->index,
  2454. dev->phy ? "dev->phy->ioctl" : "dev->phy");
  2455. return -ENOIOCTLCMD;
  2456. }
  2457. }
  2458. }
  2459. #ifdef EXTRA_DEBUG
  2460. static void which_list(ns_dev * card, struct sk_buff *skb)
  2461. {
  2462. printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
  2463. }
  2464. #endif /* EXTRA_DEBUG */
  2465. static void ns_poll(unsigned long arg)
  2466. {
  2467. int i;
  2468. ns_dev *card;
  2469. unsigned long flags;
  2470. u32 stat_r, stat_w;
  2471. PRINTK("nicstar: Entering ns_poll().\n");
  2472. for (i = 0; i < num_cards; i++) {
  2473. card = cards[i];
  2474. if (spin_is_locked(&card->int_lock)) {
  2475. /* Probably it isn't worth spinning */
  2476. continue;
  2477. }
  2478. spin_lock_irqsave(&card->int_lock, flags);
  2479. stat_w = 0;
  2480. stat_r = readl(card->membase + STAT);
  2481. if (stat_r & NS_STAT_TSIF)
  2482. stat_w |= NS_STAT_TSIF;
  2483. if (stat_r & NS_STAT_EOPDU)
  2484. stat_w |= NS_STAT_EOPDU;
  2485. process_tsq(card);
  2486. process_rsq(card);
  2487. writel(stat_w, card->membase + STAT);
  2488. spin_unlock_irqrestore(&card->int_lock, flags);
  2489. }
  2490. mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
  2491. PRINTK("nicstar: Leaving ns_poll().\n");
  2492. }
  2493. static int ns_parse_mac(char *mac, unsigned char *esi)
  2494. {
  2495. int i, j;
  2496. short byte1, byte0;
  2497. if (mac == NULL || esi == NULL)
  2498. return -1;
  2499. j = 0;
  2500. for (i = 0; i < 6; i++) {
  2501. if ((byte1 = ns_h2i(mac[j++])) < 0)
  2502. return -1;
  2503. if ((byte0 = ns_h2i(mac[j++])) < 0)
  2504. return -1;
  2505. esi[i] = (unsigned char)(byte1 * 16 + byte0);
  2506. if (i < 5) {
  2507. if (mac[j++] != ':')
  2508. return -1;
  2509. }
  2510. }
  2511. return 0;
  2512. }
  2513. static short ns_h2i(char c)
  2514. {
  2515. if (c >= '0' && c <= '9')
  2516. return (short)(c - '0');
  2517. if (c >= 'A' && c <= 'F')
  2518. return (short)(c - 'A' + 10);
  2519. if (c >= 'a' && c <= 'f')
  2520. return (short)(c - 'a' + 10);
  2521. return -1;
  2522. }
  2523. static void ns_phy_put(struct atm_dev *dev, unsigned char value,
  2524. unsigned long addr)
  2525. {
  2526. ns_dev *card;
  2527. unsigned long flags;
  2528. card = dev->dev_data;
  2529. spin_lock_irqsave(&card->res_lock, flags);
  2530. while (CMD_BUSY(card)) ;
  2531. writel((u32) value, card->membase + DR0);
  2532. writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
  2533. card->membase + CMD);
  2534. spin_unlock_irqrestore(&card->res_lock, flags);
  2535. }
  2536. static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
  2537. {
  2538. ns_dev *card;
  2539. unsigned long flags;
  2540. u32 data;
  2541. card = dev->dev_data;
  2542. spin_lock_irqsave(&card->res_lock, flags);
  2543. while (CMD_BUSY(card)) ;
  2544. writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
  2545. card->membase + CMD);
  2546. while (CMD_BUSY(card)) ;
  2547. data = readl(card->membase + DR0) & 0x000000FF;
  2548. spin_unlock_irqrestore(&card->res_lock, flags);
  2549. return (unsigned char)data;
  2550. }
  2551. module_init(nicstar_init);
  2552. module_exit(nicstar_cleanup);